1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file performs vector type splitting and scalarization for LegalizeTypes.
10 // Scalarization is the act of changing a computation in an illegal one-element
11 // vector type to be a computation in its scalar element type. For example,
12 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
13 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
14 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
16 // Splitting is the act of changing a computation in an invalid vector type to
17 // be a computation in two vectors of half the size. For example, implementing
18 // <128 x f32> operations in terms of two <64 x f32> operations.
20 //===----------------------------------------------------------------------===//
22 #include "LegalizeTypes.h"
23 #include "llvm/Analysis/MemoryLocation.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TypeSize.h"
27 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "legalize-types"
32 //===----------------------------------------------------------------------===//
33 // Result Vector Scalarization: <1 x ty> -> ty.
34 //===----------------------------------------------------------------------===//
36 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
37 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND_VECTOR_INREG:
68 case ISD::SIGN_EXTEND_VECTOR_INREG:
69 case ISD::ZERO_EXTEND_VECTOR_INREG:
70 R = ScalarizeVecRes_VecInregOp(N);
77 case ISD::CTLZ_ZERO_UNDEF:
80 case ISD::CTTZ_ZERO_UNDEF:
102 case ISD::SIGN_EXTEND:
103 case ISD::SINT_TO_FP:
105 case ISD::UINT_TO_FP:
106 case ISD::ZERO_EXTEND:
107 case ISD::FCANONICALIZE:
108 R = ScalarizeVecRes_UnaryOp(N);
119 case ISD::FMINNUM_IEEE:
120 case ISD::FMAXNUM_IEEE:
147 R = ScalarizeVecRes_BinOp(N);
150 R = ScalarizeVecRes_TernaryOp(N);
153 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
154 case ISD::STRICT_##DAGN:
155 #include "llvm/IR/ConstrainedOps.def"
156 R = ScalarizeVecRes_StrictFPOp(N);
165 R = ScalarizeVecRes_OverflowOp(N, ResNo);
168 case ISD::SMULFIXSAT:
170 case ISD::UMULFIXSAT:
172 case ISD::SDIVFIXSAT:
174 case ISD::UDIVFIXSAT:
175 R = ScalarizeVecRes_FIX(N);
179 // If R is null, the sub-method took care of registering the result.
181 SetScalarizedVector(SDValue(N, ResNo), R);
184 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
185 SDValue LHS = GetScalarizedVector(N->getOperand(0));
186 SDValue RHS = GetScalarizedVector(N->getOperand(1));
187 return DAG.getNode(N->getOpcode(), SDLoc(N),
188 LHS.getValueType(), LHS, RHS, N->getFlags());
191 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
192 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
193 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
194 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
195 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FIX(SDNode *N) {
200 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
201 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
202 SDValue Op2 = N->getOperand(2);
203 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
207 SDValue DAGTypeLegalizer::ScalarizeVecRes_StrictFPOp(SDNode *N) {
208 EVT VT = N->getValueType(0).getVectorElementType();
209 unsigned NumOpers = N->getNumOperands();
210 SDValue Chain = N->getOperand(0);
211 EVT ValueVTs[] = {VT, MVT::Other};
214 SmallVector<SDValue, 4> Opers(NumOpers);
216 // The Chain is the first operand.
219 // Now process the remaining operands.
220 for (unsigned i = 1; i < NumOpers; ++i) {
221 SDValue Oper = N->getOperand(i);
223 if (Oper.getValueType().isVector())
224 Oper = GetScalarizedVector(Oper);
229 SDValue Result = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(ValueVTs),
230 Opers, N->getFlags());
232 // Legalize the chain result - switch anything that used the old chain to
234 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
238 SDValue DAGTypeLegalizer::ScalarizeVecRes_OverflowOp(SDNode *N,
241 EVT ResVT = N->getValueType(0);
242 EVT OvVT = N->getValueType(1);
244 SDValue ScalarLHS, ScalarRHS;
245 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) {
246 ScalarLHS = GetScalarizedVector(N->getOperand(0));
247 ScalarRHS = GetScalarizedVector(N->getOperand(1));
249 SmallVector<SDValue, 1> ElemsLHS, ElemsRHS;
250 DAG.ExtractVectorElements(N->getOperand(0), ElemsLHS);
251 DAG.ExtractVectorElements(N->getOperand(1), ElemsRHS);
252 ScalarLHS = ElemsLHS[0];
253 ScalarRHS = ElemsRHS[0];
256 SDVTList ScalarVTs = DAG.getVTList(
257 ResVT.getVectorElementType(), OvVT.getVectorElementType());
258 SDNode *ScalarNode = DAG.getNode(
259 N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
260 ScalarNode->setFlags(N->getFlags());
262 // Replace the other vector result not being explicitly scalarized here.
263 unsigned OtherNo = 1 - ResNo;
264 EVT OtherVT = N->getValueType(OtherNo);
265 if (getTypeAction(OtherVT) == TargetLowering::TypeScalarizeVector) {
266 SetScalarizedVector(SDValue(N, OtherNo), SDValue(ScalarNode, OtherNo));
268 SDValue OtherVal = DAG.getNode(
269 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo));
270 ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
273 return SDValue(ScalarNode, ResNo);
276 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
278 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
279 return GetScalarizedVector(Op);
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
283 SDValue Op = N->getOperand(0);
284 if (Op.getValueType().isVector()
285 && Op.getValueType().getVectorNumElements() == 1
286 && !isSimpleLegalType(Op.getValueType()))
287 Op = GetScalarizedVector(Op);
288 EVT NewVT = N->getValueType(0).getVectorElementType();
289 return DAG.getNode(ISD::BITCAST, SDLoc(N),
293 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
294 EVT EltVT = N->getValueType(0).getVectorElementType();
295 SDValue InOp = N->getOperand(0);
296 // The BUILD_VECTOR operands may be of wider element types and
297 // we may need to truncate them back to the requested return type.
298 if (EltVT.isInteger())
299 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
303 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
304 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
305 N->getValueType(0).getVectorElementType(),
306 N->getOperand(0), N->getOperand(1));
309 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
310 EVT NewVT = N->getValueType(0).getVectorElementType();
311 SDValue Op = GetScalarizedVector(N->getOperand(0));
312 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
313 NewVT, Op, N->getOperand(1));
316 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
317 SDValue Op = GetScalarizedVector(N->getOperand(0));
318 return DAG.getNode(ISD::FPOWI, SDLoc(N),
319 Op.getValueType(), Op, N->getOperand(1));
322 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
323 // The value to insert may have a wider type than the vector element type,
324 // so be sure to truncate it to the element type if necessary.
325 SDValue Op = N->getOperand(1);
326 EVT EltVT = N->getValueType(0).getVectorElementType();
327 if (Op.getValueType() != EltVT)
328 // FIXME: Can this happen for floating point types?
329 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
333 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
334 assert(N->isUnindexed() && "Indexed vector load?");
336 SDValue Result = DAG.getLoad(
337 ISD::UNINDEXED, N->getExtensionType(),
338 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
339 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
340 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
341 N->getOriginalAlign(), N->getMemOperand()->getFlags(), N->getAAInfo());
343 // Legalize the chain result - switch anything that used the old chain to
345 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
349 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
350 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
351 EVT DestVT = N->getValueType(0).getVectorElementType();
352 SDValue Op = N->getOperand(0);
353 EVT OpVT = Op.getValueType();
355 // The result needs scalarizing, but it's not a given that the source does.
356 // This is a workaround for targets where it's impossible to scalarize the
357 // result of a conversion, because the source type is legal.
358 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
359 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
360 // legal and was not scalarized.
361 // See the similar logic in ScalarizeVecRes_SETCC
362 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
363 Op = GetScalarizedVector(Op);
365 EVT VT = OpVT.getVectorElementType();
366 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
367 DAG.getVectorIdxConstant(0, DL));
369 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags());
372 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
373 EVT EltVT = N->getValueType(0).getVectorElementType();
374 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
375 SDValue LHS = GetScalarizedVector(N->getOperand(0));
376 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
377 LHS, DAG.getValueType(ExtVT));
380 SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
382 SDValue Op = N->getOperand(0);
384 EVT OpVT = Op.getValueType();
385 EVT OpEltVT = OpVT.getVectorElementType();
386 EVT EltVT = N->getValueType(0).getVectorElementType();
388 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
389 Op = GetScalarizedVector(Op);
391 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
392 DAG.getVectorIdxConstant(0, DL));
395 switch (N->getOpcode()) {
396 case ISD::ANY_EXTEND_VECTOR_INREG:
397 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
398 case ISD::SIGN_EXTEND_VECTOR_INREG:
399 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
400 case ISD::ZERO_EXTEND_VECTOR_INREG:
401 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
404 llvm_unreachable("Illegal extend_vector_inreg opcode");
407 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
408 // If the operand is wider than the vector element type then it is implicitly
409 // truncated. Make that explicit here.
410 EVT EltVT = N->getValueType(0).getVectorElementType();
411 SDValue InOp = N->getOperand(0);
412 if (InOp.getValueType() != EltVT)
413 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
417 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
418 SDValue Cond = N->getOperand(0);
419 EVT OpVT = Cond.getValueType();
421 // The vselect result and true/value operands needs scalarizing, but it's
422 // not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
423 // See the similar logic in ScalarizeVecRes_SETCC
424 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
425 Cond = GetScalarizedVector(Cond);
427 EVT VT = OpVT.getVectorElementType();
428 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
429 DAG.getVectorIdxConstant(0, DL));
432 SDValue LHS = GetScalarizedVector(N->getOperand(1));
433 TargetLowering::BooleanContent ScalarBool =
434 TLI.getBooleanContents(false, false);
435 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
437 // If integer and float booleans have different contents then we can't
438 // reliably optimize in all cases. There is a full explanation for this in
439 // DAGCombiner::visitSELECT() where the same issue affects folding
440 // (select C, 0, 1) to (xor C, 1).
441 if (TLI.getBooleanContents(false, false) !=
442 TLI.getBooleanContents(false, true)) {
443 // At least try the common case where the boolean is generated by a
445 if (Cond->getOpcode() == ISD::SETCC) {
446 EVT OpVT = Cond->getOperand(0).getValueType();
447 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
448 VecBool = TLI.getBooleanContents(OpVT);
450 ScalarBool = TargetLowering::UndefinedBooleanContent;
453 EVT CondVT = Cond.getValueType();
454 if (ScalarBool != VecBool) {
455 switch (ScalarBool) {
456 case TargetLowering::UndefinedBooleanContent:
458 case TargetLowering::ZeroOrOneBooleanContent:
459 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
460 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
461 // Vector read from all ones, scalar expects a single 1 so mask.
462 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
463 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
465 case TargetLowering::ZeroOrNegativeOneBooleanContent:
466 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
467 VecBool == TargetLowering::ZeroOrOneBooleanContent);
468 // Vector reads from a one, scalar from all ones so sign extend.
469 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
470 Cond, DAG.getValueType(MVT::i1));
475 // Truncate the condition if needed
476 auto BoolVT = getSetCCResultType(CondVT);
477 if (BoolVT.bitsLT(CondVT))
478 Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
480 return DAG.getSelect(SDLoc(N),
481 LHS.getValueType(), Cond, LHS,
482 GetScalarizedVector(N->getOperand(2)));
485 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
486 SDValue LHS = GetScalarizedVector(N->getOperand(1));
487 return DAG.getSelect(SDLoc(N),
488 LHS.getValueType(), N->getOperand(0), LHS,
489 GetScalarizedVector(N->getOperand(2)));
492 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
493 SDValue LHS = GetScalarizedVector(N->getOperand(2));
494 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
495 N->getOperand(0), N->getOperand(1),
496 LHS, GetScalarizedVector(N->getOperand(3)),
500 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
501 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
504 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
505 // Figure out if the scalar is the LHS or RHS and return it.
506 SDValue Arg = N->getOperand(2).getOperand(0);
508 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
509 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
510 return GetScalarizedVector(N->getOperand(Op));
513 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
514 assert(N->getValueType(0).isVector() &&
515 N->getOperand(0).getValueType().isVector() &&
516 "Operand types must be vectors");
517 SDValue LHS = N->getOperand(0);
518 SDValue RHS = N->getOperand(1);
519 EVT OpVT = LHS.getValueType();
520 EVT NVT = N->getValueType(0).getVectorElementType();
523 // The result needs scalarizing, but it's not a given that the source does.
524 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
525 LHS = GetScalarizedVector(LHS);
526 RHS = GetScalarizedVector(RHS);
528 EVT VT = OpVT.getVectorElementType();
529 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
530 DAG.getVectorIdxConstant(0, DL));
531 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
532 DAG.getVectorIdxConstant(0, DL));
535 // Turn it into a scalar SETCC.
536 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
538 // Vectors may have a different boolean contents to scalars. Promote the
539 // value appropriately.
540 ISD::NodeType ExtendCode =
541 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
542 return DAG.getNode(ExtendCode, DL, NVT, Res);
546 //===----------------------------------------------------------------------===//
547 // Operand Vector Scalarization <1 x ty> -> ty.
548 //===----------------------------------------------------------------------===//
550 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
551 LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
553 SDValue Res = SDValue();
555 if (!Res.getNode()) {
556 switch (N->getOpcode()) {
559 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
563 report_fatal_error("Do not know how to scalarize this operator's "
566 Res = ScalarizeVecOp_BITCAST(N);
568 case ISD::ANY_EXTEND:
569 case ISD::ZERO_EXTEND:
570 case ISD::SIGN_EXTEND:
572 case ISD::FP_TO_SINT:
573 case ISD::FP_TO_UINT:
574 case ISD::SINT_TO_FP:
575 case ISD::UINT_TO_FP:
576 Res = ScalarizeVecOp_UnaryOp(N);
578 case ISD::STRICT_SINT_TO_FP:
579 case ISD::STRICT_UINT_TO_FP:
580 case ISD::STRICT_FP_TO_SINT:
581 case ISD::STRICT_FP_TO_UINT:
582 Res = ScalarizeVecOp_UnaryOp_StrictFP(N);
584 case ISD::CONCAT_VECTORS:
585 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
587 case ISD::EXTRACT_VECTOR_ELT:
588 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
591 Res = ScalarizeVecOp_VSELECT(N);
594 Res = ScalarizeVecOp_VSETCC(N);
597 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
599 case ISD::STRICT_FP_ROUND:
600 Res = ScalarizeVecOp_STRICT_FP_ROUND(N, OpNo);
603 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
605 case ISD::VECREDUCE_FADD:
606 case ISD::VECREDUCE_FMUL:
607 case ISD::VECREDUCE_ADD:
608 case ISD::VECREDUCE_MUL:
609 case ISD::VECREDUCE_AND:
610 case ISD::VECREDUCE_OR:
611 case ISD::VECREDUCE_XOR:
612 case ISD::VECREDUCE_SMAX:
613 case ISD::VECREDUCE_SMIN:
614 case ISD::VECREDUCE_UMAX:
615 case ISD::VECREDUCE_UMIN:
616 case ISD::VECREDUCE_FMAX:
617 case ISD::VECREDUCE_FMIN:
618 Res = ScalarizeVecOp_VECREDUCE(N);
623 // If the result is null, the sub-method took care of registering results etc.
624 if (!Res.getNode()) return false;
626 // If the result is N, the sub-method updated N in place. Tell the legalizer
628 if (Res.getNode() == N)
631 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
632 "Invalid operand expansion");
634 ReplaceValueWith(SDValue(N, 0), Res);
638 /// If the value to convert is a vector that needs to be scalarized, it must be
639 /// <1 x ty>. Convert the element instead.
640 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
641 SDValue Elt = GetScalarizedVector(N->getOperand(0));
642 return DAG.getNode(ISD::BITCAST, SDLoc(N),
643 N->getValueType(0), Elt);
646 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
647 /// Do the operation on the element instead.
648 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
649 assert(N->getValueType(0).getVectorNumElements() == 1 &&
650 "Unexpected vector type!");
651 SDValue Elt = GetScalarizedVector(N->getOperand(0));
652 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
653 N->getValueType(0).getScalarType(), Elt);
654 // Revectorize the result so the types line up with what the uses of this
655 // expression expect.
656 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
659 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
660 /// Do the strict FP operation on the element instead.
661 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N) {
662 assert(N->getValueType(0).getVectorNumElements() == 1 &&
663 "Unexpected vector type!");
664 SDValue Elt = GetScalarizedVector(N->getOperand(1));
665 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
666 { N->getValueType(0).getScalarType(), MVT::Other },
667 { N->getOperand(0), Elt });
668 // Legalize the chain result - switch anything that used the old chain to
670 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
671 // Revectorize the result so the types line up with what the uses of this
672 // expression expect.
673 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
675 // Do our own replacement and return SDValue() to tell the caller that we
676 // handled all replacements since caller can only handle a single result.
677 ReplaceValueWith(SDValue(N, 0), Res);
681 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
682 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
683 SmallVector<SDValue, 8> Ops(N->getNumOperands());
684 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
685 Ops[i] = GetScalarizedVector(N->getOperand(i));
686 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
689 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
690 /// so just return the element, ignoring the index.
691 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
692 EVT VT = N->getValueType(0);
693 SDValue Res = GetScalarizedVector(N->getOperand(0));
694 if (Res.getValueType() != VT)
695 Res = VT.isFloatingPoint()
696 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
697 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
701 /// If the input condition is a vector that needs to be scalarized, it must be
702 /// <1 x i1>, so just convert to a normal ISD::SELECT
703 /// (still with vector output type since that was acceptable if we got here).
704 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
705 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
706 EVT VT = N->getValueType(0);
708 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
712 /// If the operand is a vector that needs to be scalarized then the
713 /// result must be v1i1, so just convert to a scalar SETCC and wrap
714 /// with a scalar_to_vector since the res type is legal if we got here
715 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) {
716 assert(N->getValueType(0).isVector() &&
717 N->getOperand(0).getValueType().isVector() &&
718 "Operand types must be vectors");
719 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type");
721 EVT VT = N->getValueType(0);
722 SDValue LHS = GetScalarizedVector(N->getOperand(0));
723 SDValue RHS = GetScalarizedVector(N->getOperand(1));
725 EVT OpVT = N->getOperand(0).getValueType();
726 EVT NVT = VT.getVectorElementType();
728 // Turn it into a scalar SETCC.
729 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
732 // Vectors may have a different boolean contents to scalars. Promote the
733 // value appropriately.
734 ISD::NodeType ExtendCode =
735 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
737 Res = DAG.getNode(ExtendCode, DL, NVT, Res);
739 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
742 /// If the value to store is a vector that needs to be scalarized, it must be
743 /// <1 x ty>. Just store the element.
744 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
745 assert(N->isUnindexed() && "Indexed store of one-element vector?");
746 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
749 if (N->isTruncatingStore())
750 return DAG.getTruncStore(
751 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
752 N->getBasePtr(), N->getPointerInfo(),
753 N->getMemoryVT().getVectorElementType(), N->getOriginalAlign(),
754 N->getMemOperand()->getFlags(), N->getAAInfo());
756 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
757 N->getBasePtr(), N->getPointerInfo(),
758 N->getOriginalAlign(), N->getMemOperand()->getFlags(),
762 /// If the value to round is a vector that needs to be scalarized, it must be
763 /// <1 x ty>. Convert the element instead.
764 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
765 SDValue Elt = GetScalarizedVector(N->getOperand(0));
766 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
767 N->getValueType(0).getVectorElementType(), Elt,
769 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
772 SDValue DAGTypeLegalizer::ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N,
774 assert(OpNo == 1 && "Wrong operand for scalarization!");
775 SDValue Elt = GetScalarizedVector(N->getOperand(1));
776 SDValue Res = DAG.getNode(ISD::STRICT_FP_ROUND, SDLoc(N),
777 { N->getValueType(0).getVectorElementType(),
779 { N->getOperand(0), Elt, N->getOperand(2) });
780 // Legalize the chain result - switch anything that used the old chain to
782 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
784 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
786 // Do our own replacement and return SDValue() to tell the caller that we
787 // handled all replacements since caller can only handle a single result.
788 ReplaceValueWith(SDValue(N, 0), Res);
792 SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE(SDNode *N) {
793 SDValue Res = GetScalarizedVector(N->getOperand(0));
794 // Result type may be wider than element type.
795 if (Res.getValueType() != N->getValueType(0))
796 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res);
800 //===----------------------------------------------------------------------===//
801 // Result Vector Splitting
802 //===----------------------------------------------------------------------===//
804 /// This method is called when the specified result of the specified node is
805 /// found to need vector splitting. At this point, the node may also have
806 /// invalid operands or may have other results that need legalization, we just
807 /// know that (at least) one result needs vector splitting.
808 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
809 LLVM_DEBUG(dbgs() << "Split node result: "; N->dump(&DAG); dbgs() << "\n");
812 // See if the target wants to custom expand this node.
813 if (CustomLowerNode(N, N->getValueType(ResNo), true))
816 switch (N->getOpcode()) {
819 dbgs() << "SplitVectorResult #" << ResNo << ": ";
823 report_fatal_error("Do not know how to split the result of this "
826 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
828 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
829 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
830 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
831 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
832 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
833 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
834 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
835 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
836 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
837 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
838 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
839 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
840 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
842 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
845 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
848 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
851 SplitVecRes_SETCC(N, Lo, Hi);
853 case ISD::VECTOR_SHUFFLE:
854 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
857 SplitVecRes_VAARG(N, Lo, Hi);
860 case ISD::ANY_EXTEND_VECTOR_INREG:
861 case ISD::SIGN_EXTEND_VECTOR_INREG:
862 case ISD::ZERO_EXTEND_VECTOR_INREG:
863 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
867 case ISD::BITREVERSE:
871 case ISD::CTLZ_ZERO_UNDEF:
872 case ISD::CTTZ_ZERO_UNDEF:
883 case ISD::FNEARBYINT:
888 case ISD::FP_TO_SINT:
889 case ISD::FP_TO_UINT:
892 case ISD::FROUNDEVEN:
896 case ISD::SINT_TO_FP:
898 case ISD::UINT_TO_FP:
899 case ISD::FCANONICALIZE:
900 SplitVecRes_UnaryOp(N, Lo, Hi);
903 case ISD::ANY_EXTEND:
904 case ISD::SIGN_EXTEND:
905 case ISD::ZERO_EXTEND:
906 SplitVecRes_ExtendOp(N, Lo, Hi);
942 SplitVecRes_BinOp(N, Lo, Hi);
945 SplitVecRes_TernaryOp(N, Lo, Hi);
948 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
949 case ISD::STRICT_##DAGN:
950 #include "llvm/IR/ConstrainedOps.def"
951 SplitVecRes_StrictFPOp(N, Lo, Hi);
960 SplitVecRes_OverflowOp(N, ResNo, Lo, Hi);
963 case ISD::SMULFIXSAT:
965 case ISD::UMULFIXSAT:
967 case ISD::SDIVFIXSAT:
969 case ISD::UDIVFIXSAT:
970 SplitVecRes_FIX(N, Lo, Hi);
974 // If Lo/Hi is null, the sub-method took care of registering results etc.
976 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
979 void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT,
980 MachinePointerInfo &MPI,
983 unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinSize() / 8;
985 if (MemVT.isScalableVector()) {
986 SDValue BytesIncrement = DAG.getVScale(
987 DL, Ptr.getValueType(),
988 APInt(Ptr.getValueSizeInBits().getFixedSize(), IncrementSize));
989 MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace());
990 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement);
992 MPI = N->getPointerInfo().getWithOffset(IncrementSize);
993 // Increment the pointer to the other half.
994 Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
998 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
1000 SDValue LHSLo, LHSHi;
1001 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1002 SDValue RHSLo, RHSHi;
1003 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
1006 const SDNodeFlags Flags = N->getFlags();
1007 unsigned Opcode = N->getOpcode();
1008 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
1009 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
1012 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
1014 SDValue Op0Lo, Op0Hi;
1015 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
1016 SDValue Op1Lo, Op1Hi;
1017 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
1018 SDValue Op2Lo, Op2Hi;
1019 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
1022 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(), Op0Lo, Op1Lo,
1023 Op2Lo, N->getFlags());
1024 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(), Op0Hi, Op1Hi,
1025 Op2Hi, N->getFlags());
1028 void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
1029 SDValue LHSLo, LHSHi;
1030 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1031 SDValue RHSLo, RHSHi;
1032 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
1034 SDValue Op2 = N->getOperand(2);
1036 unsigned Opcode = N->getOpcode();
1037 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Op2,
1039 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Op2,
1043 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
1045 // We know the result is a vector. The input may be either a vector or a
1048 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1051 SDValue InOp = N->getOperand(0);
1052 EVT InVT = InOp.getValueType();
1054 // Handle some special cases efficiently.
1055 switch (getTypeAction(InVT)) {
1056 case TargetLowering::TypeLegal:
1057 case TargetLowering::TypePromoteInteger:
1058 case TargetLowering::TypePromoteFloat:
1059 case TargetLowering::TypeSoftPromoteHalf:
1060 case TargetLowering::TypeSoftenFloat:
1061 case TargetLowering::TypeScalarizeVector:
1062 case TargetLowering::TypeWidenVector:
1064 case TargetLowering::TypeExpandInteger:
1065 case TargetLowering::TypeExpandFloat:
1066 // A scalar to vector conversion, where the scalar needs expansion.
1067 // If the vector is being split in two then we can just convert the
1070 GetExpandedOp(InOp, Lo, Hi);
1071 if (DAG.getDataLayout().isBigEndian())
1073 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1074 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1078 case TargetLowering::TypeSplitVector:
1079 // If the input is a vector that needs to be split, convert each split
1080 // piece of the input now.
1081 GetSplitVector(InOp, Lo, Hi);
1082 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1083 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1085 case TargetLowering::TypeScalarizeScalableVector:
1086 report_fatal_error("Scalarization of scalable vectors is not supported.");
1089 // In the general case, convert the input to an integer and split it by hand.
1090 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
1091 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
1092 if (DAG.getDataLayout().isBigEndian())
1093 std::swap(LoIntVT, HiIntVT);
1095 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
1097 if (DAG.getDataLayout().isBigEndian())
1099 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
1100 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
1103 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
1107 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1108 unsigned LoNumElts = LoVT.getVectorNumElements();
1109 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
1110 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
1112 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
1113 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
1116 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
1118 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
1120 unsigned NumSubvectors = N->getNumOperands() / 2;
1121 if (NumSubvectors == 1) {
1122 Lo = N->getOperand(0);
1123 Hi = N->getOperand(1);
1128 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1130 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
1131 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
1133 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
1134 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
1137 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
1139 SDValue Vec = N->getOperand(0);
1140 SDValue Idx = N->getOperand(1);
1144 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1146 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
1147 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1149 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
1150 DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorNumElements(), dl));
1153 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
1155 SDValue Vec = N->getOperand(0);
1156 SDValue SubVec = N->getOperand(1);
1157 SDValue Idx = N->getOperand(2);
1159 GetSplitVector(Vec, Lo, Hi);
1161 EVT VecVT = Vec.getValueType();
1162 unsigned VecElems = VecVT.getVectorNumElements();
1163 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
1165 // If we know the index is 0, and we know the subvector doesn't cross the
1166 // boundary between the halves, we can avoid spilling the vector, and insert
1167 // into the lower half of the split vector directly.
1168 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
1169 // there is no boundary crossing. But those cases don't seem to get hit in
1171 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1172 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
1174 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1175 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
1179 // Spill the vector to the stack.
1180 // In cases where the vector is illegal it will be broken down into parts
1181 // and stored in parts - we should use the alignment for the smallest part.
1182 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false);
1184 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign);
1185 auto &MF = DAG.getMachineFunction();
1186 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1187 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1189 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1192 // Store the new subvector into the specified index.
1193 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1194 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr,
1195 MachinePointerInfo::getUnknownStack(MF));
1197 // Load the Lo part from the stack slot.
1198 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, PtrInfo,
1201 // Increment the pointer to the other part.
1202 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1203 StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
1205 // Load the Hi part from the stack slot.
1206 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr,
1207 PtrInfo.getWithOffset(IncrementSize), SmallestAlign);
1210 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
1213 GetSplitVector(N->getOperand(0), Lo, Hi);
1214 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
1215 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
1218 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
1220 SDValue LHSLo, LHSHi;
1221 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1224 SDValue RHSLo, RHSHi;
1225 SDValue RHS = N->getOperand(1);
1226 EVT RHSVT = RHS.getValueType();
1227 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
1228 GetSplitVector(RHS, RHSLo, RHSHi);
1230 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
1233 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
1234 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
1237 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
1239 SDValue LHSLo, LHSHi;
1240 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1244 std::tie(LoVT, HiVT) =
1245 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
1247 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
1248 DAG.getValueType(LoVT));
1249 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
1250 DAG.getValueType(HiVT));
1253 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
1255 unsigned Opcode = N->getOpcode();
1256 SDValue N0 = N->getOperand(0);
1261 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1262 GetSplitVector(N0, InLo, InHi);
1264 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
1266 EVT InLoVT = InLo.getValueType();
1267 unsigned InNumElements = InLoVT.getVectorNumElements();
1269 EVT OutLoVT, OutHiVT;
1270 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1271 unsigned OutNumElements = OutLoVT.getVectorNumElements();
1272 assert((2 * OutNumElements) <= InNumElements &&
1273 "Illegal extend vector in reg split");
1275 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
1276 // input vector (i.e. we only use InLo):
1277 // OutLo will extend the first OutNumElements from InLo.
1278 // OutHi will extend the next OutNumElements from InLo.
1280 // Shuffle the elements from InLo for OutHi into the bottom elements to
1281 // create a 'fake' InHi.
1282 SmallVector<int, 8> SplitHi(InNumElements, -1);
1283 for (unsigned i = 0; i != OutNumElements; ++i)
1284 SplitHi[i] = i + OutNumElements;
1285 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
1287 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
1288 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
1291 void DAGTypeLegalizer::SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo,
1293 unsigned NumOps = N->getNumOperands();
1294 SDValue Chain = N->getOperand(0);
1297 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1299 SmallVector<SDValue, 4> OpsLo(NumOps);
1300 SmallVector<SDValue, 4> OpsHi(NumOps);
1302 // The Chain is the first operand.
1306 // Now process the remaining operands.
1307 for (unsigned i = 1; i < NumOps; ++i) {
1308 SDValue Op = N->getOperand(i);
1312 EVT InVT = Op.getValueType();
1313 if (InVT.isVector()) {
1314 // If the input also splits, handle it directly for a
1315 // compile time speedup. Otherwise split it by hand.
1316 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1317 GetSplitVector(Op, OpLo, OpHi);
1319 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1326 EVT LoValueVTs[] = {LoVT, MVT::Other};
1327 EVT HiValueVTs[] = {HiVT, MVT::Other};
1328 Lo = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(LoValueVTs), OpsLo,
1330 Hi = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(HiValueVTs), OpsHi,
1333 // Build a factor node to remember that this Op is independent of the
1335 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1336 Lo.getValue(1), Hi.getValue(1));
1338 // Legalize the chain result - switch anything that used the old chain to
1340 ReplaceValueWith(SDValue(N, 1), Chain);
1343 SDValue DAGTypeLegalizer::UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE) {
1344 SDValue Chain = N->getOperand(0);
1345 EVT VT = N->getValueType(0);
1346 unsigned NE = VT.getVectorNumElements();
1347 EVT EltVT = VT.getVectorElementType();
1350 SmallVector<SDValue, 8> Scalars;
1351 SmallVector<SDValue, 4> Operands(N->getNumOperands());
1353 // If ResNE is 0, fully unroll the vector op.
1356 else if (NE > ResNE)
1359 //The results of each unrolled operation, including the chain.
1360 EVT ChainVTs[] = {EltVT, MVT::Other};
1361 SmallVector<SDValue, 8> Chains;
1364 for (i = 0; i != NE; ++i) {
1365 Operands[0] = Chain;
1366 for (unsigned j = 1, e = N->getNumOperands(); j != e; ++j) {
1367 SDValue Operand = N->getOperand(j);
1368 EVT OperandVT = Operand.getValueType();
1369 if (OperandVT.isVector()) {
1370 EVT OperandEltVT = OperandVT.getVectorElementType();
1371 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT,
1372 Operand, DAG.getVectorIdxConstant(i, dl));
1374 Operands[j] = Operand;
1377 SDValue Scalar = DAG.getNode(N->getOpcode(), dl, ChainVTs, Operands);
1378 Scalar.getNode()->setFlags(N->getFlags());
1380 //Add in the scalar as well as its chain value to the
1382 Scalars.push_back(Scalar);
1383 Chains.push_back(Scalar.getValue(1));
1386 for (; i < ResNE; ++i)
1387 Scalars.push_back(DAG.getUNDEF(EltVT));
1389 // Build a new factor node to connect the chain back together.
1390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
1391 ReplaceValueWith(SDValue(N, 1), Chain);
1393 // Create a new BUILD_VECTOR node
1394 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, ResNE);
1395 return DAG.getBuildVector(VecVT, dl, Scalars);
1398 void DAGTypeLegalizer::SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
1399 SDValue &Lo, SDValue &Hi) {
1401 EVT ResVT = N->getValueType(0);
1402 EVT OvVT = N->getValueType(1);
1403 EVT LoResVT, HiResVT, LoOvVT, HiOvVT;
1404 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT);
1405 std::tie(LoOvVT, HiOvVT) = DAG.GetSplitDestVTs(OvVT);
1407 SDValue LoLHS, HiLHS, LoRHS, HiRHS;
1408 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) {
1409 GetSplitVector(N->getOperand(0), LoLHS, HiLHS);
1410 GetSplitVector(N->getOperand(1), LoRHS, HiRHS);
1412 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0);
1413 std::tie(LoRHS, HiRHS) = DAG.SplitVectorOperand(N, 1);
1416 unsigned Opcode = N->getOpcode();
1417 SDVTList LoVTs = DAG.getVTList(LoResVT, LoOvVT);
1418 SDVTList HiVTs = DAG.getVTList(HiResVT, HiOvVT);
1419 SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode();
1420 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode();
1421 LoNode->setFlags(N->getFlags());
1422 HiNode->setFlags(N->getFlags());
1424 Lo = SDValue(LoNode, ResNo);
1425 Hi = SDValue(HiNode, ResNo);
1427 // Replace the other vector result not being explicitly split here.
1428 unsigned OtherNo = 1 - ResNo;
1429 EVT OtherVT = N->getValueType(OtherNo);
1430 if (getTypeAction(OtherVT) == TargetLowering::TypeSplitVector) {
1431 SetSplitVector(SDValue(N, OtherNo),
1432 SDValue(LoNode, OtherNo), SDValue(HiNode, OtherNo));
1434 SDValue OtherVal = DAG.getNode(
1435 ISD::CONCAT_VECTORS, dl, OtherVT,
1436 SDValue(LoNode, OtherNo), SDValue(HiNode, OtherNo));
1437 ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
1441 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
1443 SDValue Vec = N->getOperand(0);
1444 SDValue Elt = N->getOperand(1);
1445 SDValue Idx = N->getOperand(2);
1447 GetSplitVector(Vec, Lo, Hi);
1449 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1450 unsigned IdxVal = CIdx->getZExtValue();
1451 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1452 if (IdxVal < LoNumElts)
1453 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1454 Lo.getValueType(), Lo, Elt, Idx);
1456 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1457 DAG.getVectorIdxConstant(IdxVal - LoNumElts, dl));
1461 // See if the target wants to custom expand this node.
1462 if (CustomLowerNode(N, N->getValueType(0), true))
1465 // Make the vector elements byte-addressable if they aren't already.
1466 EVT VecVT = Vec.getValueType();
1467 EVT EltVT = VecVT.getVectorElementType();
1468 if (VecVT.getScalarSizeInBits() < 8) {
1470 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1471 VecVT.getVectorNumElements());
1472 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1473 // Extend the element type to match if needed.
1474 if (EltVT.bitsGT(Elt.getValueType()))
1475 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt);
1478 // Spill the vector to the stack.
1479 // In cases where the vector is illegal it will be broken down into parts
1480 // and stored in parts - we should use the alignment for the smallest part.
1481 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false);
1483 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign);
1484 auto &MF = DAG.getMachineFunction();
1485 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1486 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1488 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1491 // Store the new element. This may be larger than the vector element type,
1492 // so use a truncating store.
1493 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1494 Store = DAG.getTruncStore(
1495 Store, dl, Elt, EltPtr, MachinePointerInfo::getUnknownStack(MF), EltVT,
1496 commonAlignment(SmallestAlign, EltVT.getSizeInBits() / 8));
1499 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
1501 // Load the Lo part from the stack slot.
1502 Lo = DAG.getLoad(LoVT, dl, Store, StackPtr, PtrInfo, SmallestAlign);
1504 // Increment the pointer to the other part.
1505 unsigned IncrementSize = LoVT.getSizeInBits() / 8;
1506 StackPtr = DAG.getMemBasePlusOffset(StackPtr, IncrementSize, dl);
1508 // Load the Hi part from the stack slot.
1509 Hi = DAG.getLoad(HiVT, dl, Store, StackPtr,
1510 PtrInfo.getWithOffset(IncrementSize), SmallestAlign);
1512 // If we adjusted the original type, we need to truncate the results.
1513 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1514 if (LoVT != Lo.getValueType())
1515 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo);
1516 if (HiVT != Hi.getValueType())
1517 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
1520 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1524 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1525 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1526 Hi = DAG.getUNDEF(HiVT);
1529 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1531 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1534 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1536 ISD::LoadExtType ExtType = LD->getExtensionType();
1537 SDValue Ch = LD->getChain();
1538 SDValue Ptr = LD->getBasePtr();
1539 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1540 EVT MemoryVT = LD->getMemoryVT();
1541 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1542 AAMDNodes AAInfo = LD->getAAInfo();
1544 EVT LoMemVT, HiMemVT;
1545 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1547 if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized()) {
1548 SDValue Value, NewChain;
1549 std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
1550 std::tie(Lo, Hi) = DAG.SplitVector(Value, dl);
1551 ReplaceValueWith(SDValue(LD, 1), NewChain);
1555 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1556 LD->getPointerInfo(), LoMemVT, LD->getOriginalAlign(),
1559 MachinePointerInfo MPI;
1560 IncrementPointer(LD, LoMemVT, MPI, Ptr);
1562 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI,
1563 HiMemVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
1565 // Build a factor node to remember that this load is independent of the
1567 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1570 // Legalize the chain result - switch anything that used the old chain to
1572 ReplaceValueWith(SDValue(LD, 1), Ch);
1575 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1576 SDValue &Lo, SDValue &Hi) {
1577 assert(MLD->isUnindexed() && "Indexed masked load during type legalization!");
1580 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1582 SDValue Ch = MLD->getChain();
1583 SDValue Ptr = MLD->getBasePtr();
1584 SDValue Offset = MLD->getOffset();
1585 assert(Offset.isUndef() && "Unexpected indexed masked load offset");
1586 SDValue Mask = MLD->getMask();
1587 SDValue PassThru = MLD->getPassThru();
1588 Align Alignment = MLD->getOriginalAlign();
1589 ISD::LoadExtType ExtType = MLD->getExtensionType();
1591 // Split Mask operand
1592 SDValue MaskLo, MaskHi;
1593 if (Mask.getOpcode() == ISD::SETCC) {
1594 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
1596 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1597 GetSplitVector(Mask, MaskLo, MaskHi);
1599 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1602 EVT MemoryVT = MLD->getMemoryVT();
1603 EVT LoMemVT, HiMemVT;
1604 bool HiIsEmpty = false;
1605 std::tie(LoMemVT, HiMemVT) =
1606 DAG.GetDependentSplitDestVTs(MemoryVT, LoVT, &HiIsEmpty);
1608 SDValue PassThruLo, PassThruHi;
1609 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1610 GetSplitVector(PassThru, PassThruLo, PassThruHi);
1612 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1614 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
1615 MLD->getPointerInfo(), MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1616 Alignment, MLD->getAAInfo(), MLD->getRanges());
1618 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, Offset, MaskLo, PassThruLo, LoMemVT,
1619 MMO, MLD->getAddressingMode(), ExtType,
1620 MLD->isExpandingLoad());
1623 // The hi masked load has zero storage size. We therefore simply set it to
1624 // the low masked load and rely on subsequent removal from the chain.
1627 // Generate hi masked load.
1628 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1629 MLD->isExpandingLoad());
1630 unsigned HiOffset = LoMemVT.getStoreSize();
1632 MMO = DAG.getMachineFunction().getMachineMemOperand(
1633 MLD->getPointerInfo().getWithOffset(HiOffset),
1634 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(), Alignment,
1635 MLD->getAAInfo(), MLD->getRanges());
1637 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, Offset, MaskHi, PassThruHi,
1638 HiMemVT, MMO, MLD->getAddressingMode(), ExtType,
1639 MLD->isExpandingLoad());
1642 // Build a factor node to remember that this load is independent of the
1644 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1647 // Legalize the chain result - switch anything that used the old chain to
1649 ReplaceValueWith(SDValue(MLD, 1), Ch);
1653 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1654 SDValue &Lo, SDValue &Hi) {
1657 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1659 SDValue Ch = MGT->getChain();
1660 SDValue Ptr = MGT->getBasePtr();
1661 SDValue Mask = MGT->getMask();
1662 SDValue PassThru = MGT->getPassThru();
1663 SDValue Index = MGT->getIndex();
1664 SDValue Scale = MGT->getScale();
1665 Align Alignment = MGT->getOriginalAlign();
1667 // Split Mask operand
1668 SDValue MaskLo, MaskHi;
1669 if (Mask.getOpcode() == ISD::SETCC) {
1670 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
1672 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1673 GetSplitVector(Mask, MaskLo, MaskHi);
1675 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1678 SDValue PassThruLo, PassThruHi;
1679 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1680 GetSplitVector(PassThru, PassThruLo, PassThruHi);
1682 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1684 SDValue IndexHi, IndexLo;
1685 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1686 GetSplitVector(Index, IndexLo, IndexHi);
1688 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1690 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
1691 MGT->getPointerInfo(), MachineMemOperand::MOLoad,
1692 MemoryLocation::UnknownSize, Alignment, MGT->getAAInfo(),
1695 SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
1696 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1697 MMO, MGT->getIndexType());
1699 SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
1700 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1701 MMO, MGT->getIndexType());
1703 // Build a factor node to remember that this load is independent of the
1705 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1708 // Legalize the chain result - switch anything that used the old chain to
1710 ReplaceValueWith(SDValue(MGT, 1), Ch);
1714 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1715 assert(N->getValueType(0).isVector() &&
1716 N->getOperand(0).getValueType().isVector() &&
1717 "Operand types must be vectors");
1721 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1723 // If the input also splits, handle it directly. Otherwise split it by hand.
1724 SDValue LL, LH, RL, RH;
1725 if (getTypeAction(N->getOperand(0).getValueType()) ==
1726 TargetLowering::TypeSplitVector)
1727 GetSplitVector(N->getOperand(0), LL, LH);
1729 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1731 if (getTypeAction(N->getOperand(1).getValueType()) ==
1732 TargetLowering::TypeSplitVector)
1733 GetSplitVector(N->getOperand(1), RL, RH);
1735 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1737 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1738 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1741 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1743 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1746 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1748 // If the input also splits, handle it directly for a compile time speedup.
1749 // Otherwise split it by hand.
1750 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1751 EVT InVT = N->getOperand(OpNo).getValueType();
1752 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1753 GetSplitVector(N->getOperand(OpNo), Lo, Hi);
1755 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, OpNo);
1757 if (N->getOpcode() == ISD::FP_ROUND) {
1758 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1),
1760 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1),
1763 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getFlags());
1764 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getFlags());
1768 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1771 EVT SrcVT = N->getOperand(0).getValueType();
1772 EVT DestVT = N->getValueType(0);
1774 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1776 // We can do better than a generic split operation if the extend is doing
1777 // more than just doubling the width of the elements and the following are
1779 // - The number of vector elements is even,
1780 // - the source type is legal,
1781 // - the type of a split source is illegal,
1782 // - the type of an extended (by doubling element size) source is legal, and
1783 // - the type of that extended source when split is legal.
1785 // This won't necessarily completely legalize the operation, but it will
1786 // more effectively move in the right direction and prevent falling down
1787 // to scalarization in many cases due to the input vector being split too
1789 if ((SrcVT.getVectorMinNumElements() & 1) == 0 &&
1790 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1791 LLVMContext &Ctx = *DAG.getContext();
1792 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
1793 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
1795 EVT SplitLoVT, SplitHiVT;
1796 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1797 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1798 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1799 LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";
1800 N->dump(&DAG); dbgs() << "\n");
1801 // Extend the source vector by one step.
1803 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1804 // Get the low and high halves of the new, extended one step, vector.
1805 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1806 // Extend those vector halves the rest of the way.
1807 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1808 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1812 // Fall back to the generic unary operator splitting otherwise.
1813 SplitVecRes_UnaryOp(N, Lo, Hi);
1816 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1817 SDValue &Lo, SDValue &Hi) {
1818 // The low and high parts of the original input give four input vectors.
1821 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1822 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1823 EVT NewVT = Inputs[0].getValueType();
1824 unsigned NewElts = NewVT.getVectorNumElements();
1826 // If Lo or Hi uses elements from at most two of the four input vectors, then
1827 // express it as a vector shuffle of those two inputs. Otherwise extract the
1828 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1829 SmallVector<int, 16> Ops;
1830 for (unsigned High = 0; High < 2; ++High) {
1831 SDValue &Output = High ? Hi : Lo;
1833 // Build a shuffle mask for the output, discovering on the fly which
1834 // input vectors to use as shuffle operands (recorded in InputUsed).
1835 // If building a suitable shuffle vector proves too hard, then bail
1836 // out with useBuildVector set.
1837 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1838 unsigned FirstMaskIdx = High * NewElts;
1839 bool useBuildVector = false;
1840 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1841 // The mask element. This indexes into the input.
1842 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1844 // The input vector this mask element indexes into.
1845 unsigned Input = (unsigned)Idx / NewElts;
1847 if (Input >= array_lengthof(Inputs)) {
1848 // The mask element does not index into any input vector.
1853 // Turn the index into an offset from the start of the input vector.
1854 Idx -= Input * NewElts;
1856 // Find or create a shuffle vector operand to hold this input.
1858 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1859 if (InputUsed[OpNo] == Input) {
1860 // This input vector is already an operand.
1862 } else if (InputUsed[OpNo] == -1U) {
1863 // Create a new operand for this input vector.
1864 InputUsed[OpNo] = Input;
1869 if (OpNo >= array_lengthof(InputUsed)) {
1870 // More than two input vectors used! Give up on trying to create a
1871 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1872 useBuildVector = true;
1876 // Add the mask index for the new shuffle vector.
1877 Ops.push_back(Idx + OpNo * NewElts);
1880 if (useBuildVector) {
1881 EVT EltVT = NewVT.getVectorElementType();
1882 SmallVector<SDValue, 16> SVOps;
1884 // Extract the input elements by hand.
1885 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1886 // The mask element. This indexes into the input.
1887 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1889 // The input vector this mask element indexes into.
1890 unsigned Input = (unsigned)Idx / NewElts;
1892 if (Input >= array_lengthof(Inputs)) {
1893 // The mask element is "undef" or indexes off the end of the input.
1894 SVOps.push_back(DAG.getUNDEF(EltVT));
1898 // Turn the index into an offset from the start of the input vector.
1899 Idx -= Input * NewElts;
1901 // Extract the vector element by hand.
1902 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1904 DAG.getVectorIdxConstant(Idx, dl)));
1907 // Construct the Lo/Hi output using a BUILD_VECTOR.
1908 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1909 } else if (InputUsed[0] == -1U) {
1910 // No input vectors were used! The result is undefined.
1911 Output = DAG.getUNDEF(NewVT);
1913 SDValue Op0 = Inputs[InputUsed[0]];
1914 // If only one input was used, use an undefined vector for the other.
1915 SDValue Op1 = InputUsed[1] == -1U ?
1916 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1917 // At least one input vector was used. Create a new shuffle vector.
1918 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1925 void DAGTypeLegalizer::SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1926 EVT OVT = N->getValueType(0);
1927 EVT NVT = OVT.getHalfNumVectorElementsVT(*DAG.getContext());
1928 SDValue Chain = N->getOperand(0);
1929 SDValue Ptr = N->getOperand(1);
1930 SDValue SV = N->getOperand(2);
1933 const Align Alignment =
1934 DAG.getDataLayout().getABITypeAlign(NVT.getTypeForEVT(*DAG.getContext()));
1936 Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, SV, Alignment.value());
1937 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, SV, Alignment.value());
1938 Chain = Hi.getValue(1);
1940 // Modified the chain - switch anything that used the old chain to use
1942 ReplaceValueWith(SDValue(N, 1), Chain);
1946 //===----------------------------------------------------------------------===//
1947 // Operand Vector Splitting
1948 //===----------------------------------------------------------------------===//
1950 /// This method is called when the specified operand of the specified node is
1951 /// found to need vector splitting. At this point, all of the result types of
1952 /// the node are known to be legal, but other operands of the node may need
1953 /// legalization as well as the specified one.
1954 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1955 LLVM_DEBUG(dbgs() << "Split node operand: "; N->dump(&DAG); dbgs() << "\n");
1956 SDValue Res = SDValue();
1958 // See if the target wants to custom split this node.
1959 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1962 if (!Res.getNode()) {
1963 switch (N->getOpcode()) {
1966 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1970 report_fatal_error("Do not know how to split this operator's "
1973 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1974 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1975 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1976 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1977 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1979 Res = SplitVecOp_TruncateHelper(N);
1981 case ISD::STRICT_FP_ROUND:
1982 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1983 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1985 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1988 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1991 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1994 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1997 Res = SplitVecOp_VSELECT(N, OpNo);
1999 case ISD::STRICT_SINT_TO_FP:
2000 case ISD::STRICT_UINT_TO_FP:
2001 case ISD::SINT_TO_FP:
2002 case ISD::UINT_TO_FP:
2003 if (N->getValueType(0).bitsLT(
2004 N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType()))
2005 Res = SplitVecOp_TruncateHelper(N);
2007 Res = SplitVecOp_UnaryOp(N);
2009 case ISD::FP_TO_SINT:
2010 case ISD::FP_TO_UINT:
2011 case ISD::STRICT_FP_TO_SINT:
2012 case ISD::STRICT_FP_TO_UINT:
2016 case ISD::STRICT_FP_EXTEND:
2017 case ISD::FP_EXTEND:
2018 case ISD::SIGN_EXTEND:
2019 case ISD::ZERO_EXTEND:
2020 case ISD::ANY_EXTEND:
2022 case ISD::FCANONICALIZE:
2023 Res = SplitVecOp_UnaryOp(N);
2026 case ISD::ANY_EXTEND_VECTOR_INREG:
2027 case ISD::SIGN_EXTEND_VECTOR_INREG:
2028 case ISD::ZERO_EXTEND_VECTOR_INREG:
2029 Res = SplitVecOp_ExtVecInRegOp(N);
2032 case ISD::VECREDUCE_FADD:
2033 case ISD::VECREDUCE_FMUL:
2034 case ISD::VECREDUCE_ADD:
2035 case ISD::VECREDUCE_MUL:
2036 case ISD::VECREDUCE_AND:
2037 case ISD::VECREDUCE_OR:
2038 case ISD::VECREDUCE_XOR:
2039 case ISD::VECREDUCE_SMAX:
2040 case ISD::VECREDUCE_SMIN:
2041 case ISD::VECREDUCE_UMAX:
2042 case ISD::VECREDUCE_UMIN:
2043 case ISD::VECREDUCE_FMAX:
2044 case ISD::VECREDUCE_FMIN:
2045 Res = SplitVecOp_VECREDUCE(N, OpNo);
2050 // If the result is null, the sub-method took care of registering results etc.
2051 if (!Res.getNode()) return false;
2053 // If the result is N, the sub-method updated N in place. Tell the legalizer
2055 if (Res.getNode() == N)
2058 if (N->isStrictFPOpcode())
2059 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 2 &&
2060 "Invalid operand expansion");
2062 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2063 "Invalid operand expansion");
2065 ReplaceValueWith(SDValue(N, 0), Res);
2069 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
2070 // The only possibility for an illegal operand is the mask, since result type
2071 // legalization would have handled this node already otherwise.
2072 assert(OpNo == 0 && "Illegal operand must be mask");
2074 SDValue Mask = N->getOperand(0);
2075 SDValue Src0 = N->getOperand(1);
2076 SDValue Src1 = N->getOperand(2);
2077 EVT Src0VT = Src0.getValueType();
2079 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
2082 GetSplitVector(N->getOperand(0), Lo, Hi);
2083 assert(Lo.getValueType() == Hi.getValueType() &&
2084 "Lo and Hi have differing types");
2087 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
2088 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
2090 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
2091 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
2092 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
2093 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
2096 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
2098 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
2100 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
2103 SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
2104 EVT ResVT = N->getValueType(0);
2108 SDValue VecOp = N->getOperand(OpNo);
2109 EVT VecVT = VecOp.getValueType();
2110 assert(VecVT.isVector() && "Can only split reduce vector operand");
2111 GetSplitVector(VecOp, Lo, Hi);
2113 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
2115 bool NoNaN = N->getFlags().hasNoNaNs();
2116 unsigned CombineOpc = 0;
2117 switch (N->getOpcode()) {
2118 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
2119 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
2120 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
2121 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
2122 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
2123 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
2124 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
2125 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
2126 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
2127 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
2128 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
2129 case ISD::VECREDUCE_FMAX:
2130 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
2132 case ISD::VECREDUCE_FMIN:
2133 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
2136 llvm_unreachable("Unexpected reduce ISD node");
2139 // Use the appropriate scalar instruction on the split subvectors before
2140 // reducing the now partially reduced smaller vector.
2141 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
2142 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
2145 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
2146 // The result has a legal vector type, but the input needs splitting.
2147 EVT ResVT = N->getValueType(0);
2150 GetSplitVector(N->getOperand(N->isStrictFPOpcode() ? 1 : 0), Lo, Hi);
2151 EVT InVT = Lo.getValueType();
2153 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2154 InVT.getVectorElementCount());
2156 if (N->isStrictFPOpcode()) {
2157 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other },
2158 { N->getOperand(0), Lo });
2159 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other },
2160 { N->getOperand(0), Hi });
2162 // Build a factor node to remember that this operation is independent
2163 // of the other one.
2164 SDValue Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2167 // Legalize the chain result - switch anything that used the old chain to
2169 ReplaceValueWith(SDValue(N, 1), Ch);
2171 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
2172 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
2175 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
2178 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
2179 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
2180 // end up being split all the way down to individual components. Convert the
2181 // split pieces into integers and reassemble.
2183 GetSplitVector(N->getOperand(0), Lo, Hi);
2184 Lo = BitConvertToInteger(Lo);
2185 Hi = BitConvertToInteger(Hi);
2187 if (DAG.getDataLayout().isBigEndian())
2190 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
2191 JoinIntegers(Lo, Hi));
2194 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2195 // We know that the extracted result type is legal.
2196 EVT SubVT = N->getValueType(0);
2197 SDValue Idx = N->getOperand(1);
2201 if (SubVT.isScalableVector() !=
2202 N->getOperand(0).getValueType().isScalableVector())
2203 report_fatal_error("Extracting a fixed-length vector from an illegal "
2204 "scalable vector is not yet supported");
2206 GetSplitVector(N->getOperand(0), Lo, Hi);
2208 uint64_t LoElts = Lo.getValueType().getVectorMinNumElements();
2209 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2211 if (IdxVal < LoElts) {
2212 assert(IdxVal + SubVT.getVectorMinNumElements() <= LoElts &&
2213 "Extracted subvector crosses vector split!");
2214 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
2216 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
2217 DAG.getVectorIdxConstant(IdxVal - LoElts, dl));
2221 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2222 SDValue Vec = N->getOperand(0);
2223 SDValue Idx = N->getOperand(1);
2224 EVT VecVT = Vec.getValueType();
2226 if (isa<ConstantSDNode>(Idx)) {
2227 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2230 GetSplitVector(Vec, Lo, Hi);
2232 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2234 if (IdxVal < LoElts)
2235 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
2236 return SDValue(DAG.UpdateNodeOperands(N, Hi,
2237 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
2238 Idx.getValueType())), 0);
2241 // See if the target wants to custom expand this node.
2242 if (CustomLowerNode(N, N->getValueType(0), true))
2245 // Make the vector elements byte-addressable if they aren't already.
2247 EVT EltVT = VecVT.getVectorElementType();
2248 if (VecVT.getScalarSizeInBits() < 8) {
2250 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
2251 VecVT.getVectorNumElements());
2252 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
2255 // Store the vector to the stack.
2256 // In cases where the vector is illegal it will be broken down into parts
2257 // and stored in parts - we should use the alignment for the smallest part.
2258 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false);
2260 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign);
2261 auto &MF = DAG.getMachineFunction();
2262 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
2263 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
2264 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
2267 // Load back the required element.
2268 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
2270 // FIXME: This is to handle i1 vectors with elements promoted to i8.
2271 // i1 vector handling needs general improvement.
2272 if (N->getValueType(0).bitsLT(EltVT)) {
2273 SDValue Load = DAG.getLoad(EltVT, dl, Store, StackPtr,
2274 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
2275 return DAG.getZExtOrTrunc(Load, dl, N->getValueType(0));
2278 return DAG.getExtLoad(
2279 ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
2280 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT,
2281 commonAlignment(SmallestAlign, EltVT.getSizeInBits() / 8));
2284 SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
2287 // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
2288 // splitting the result has the same effect as splitting the input operand.
2289 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
2291 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
2294 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
2298 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
2300 SDValue Ch = MGT->getChain();
2301 SDValue Ptr = MGT->getBasePtr();
2302 SDValue Index = MGT->getIndex();
2303 SDValue Scale = MGT->getScale();
2304 SDValue Mask = MGT->getMask();
2305 SDValue PassThru = MGT->getPassThru();
2306 Align Alignment = MGT->getOriginalAlign();
2308 SDValue MaskLo, MaskHi;
2309 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2310 // Split Mask operand
2311 GetSplitVector(Mask, MaskLo, MaskHi);
2313 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
2315 EVT MemoryVT = MGT->getMemoryVT();
2316 EVT LoMemVT, HiMemVT;
2317 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2319 SDValue PassThruLo, PassThruHi;
2320 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
2321 GetSplitVector(PassThru, PassThruLo, PassThruHi);
2323 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
2325 SDValue IndexHi, IndexLo;
2326 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2327 GetSplitVector(Index, IndexLo, IndexHi);
2329 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
2331 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
2332 MGT->getPointerInfo(), MachineMemOperand::MOLoad,
2333 MemoryLocation::UnknownSize, Alignment, MGT->getAAInfo(),
2336 SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
2337 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
2338 OpsLo, MMO, MGT->getIndexType());
2340 SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
2341 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
2342 OpsHi, MMO, MGT->getIndexType());
2344 // Build a factor node to remember that this load is independent of the
2346 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2349 // Legalize the chain result - switch anything that used the old chain to
2351 ReplaceValueWith(SDValue(MGT, 1), Ch);
2353 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
2355 ReplaceValueWith(SDValue(MGT, 0), Res);
2359 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
2361 assert(N->isUnindexed() && "Indexed masked store of vector?");
2362 SDValue Ch = N->getChain();
2363 SDValue Ptr = N->getBasePtr();
2364 SDValue Offset = N->getOffset();
2365 assert(Offset.isUndef() && "Unexpected indexed masked store offset");
2366 SDValue Mask = N->getMask();
2367 SDValue Data = N->getValue();
2368 Align Alignment = N->getOriginalAlign();
2371 SDValue DataLo, DataHi;
2372 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2373 // Split Data operand
2374 GetSplitVector(Data, DataLo, DataHi);
2376 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2378 // Split Mask operand
2379 SDValue MaskLo, MaskHi;
2380 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
2381 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
2383 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2384 GetSplitVector(Mask, MaskLo, MaskHi);
2386 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2389 EVT MemoryVT = N->getMemoryVT();
2390 EVT LoMemVT, HiMemVT;
2391 bool HiIsEmpty = false;
2392 std::tie(LoMemVT, HiMemVT) =
2393 DAG.GetDependentSplitDestVTs(MemoryVT, DataLo.getValueType(), &HiIsEmpty);
2395 SDValue Lo, Hi, Res;
2396 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
2397 N->getPointerInfo(), MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
2398 Alignment, N->getAAInfo(), N->getRanges());
2400 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, Offset, MaskLo, LoMemVT, MMO,
2401 N->getAddressingMode(), N->isTruncatingStore(),
2402 N->isCompressingStore());
2405 // The hi masked store has zero storage size.
2406 // Only the lo masked store is needed.
2410 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
2411 N->isCompressingStore());
2412 unsigned HiOffset = LoMemVT.getStoreSize();
2414 MMO = DAG.getMachineFunction().getMachineMemOperand(
2415 N->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOStore,
2416 HiMemVT.getStoreSize(), Alignment, N->getAAInfo(), N->getRanges());
2418 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, Offset, MaskHi, HiMemVT, MMO,
2419 N->getAddressingMode(), N->isTruncatingStore(),
2420 N->isCompressingStore());
2422 // Build a factor node to remember that this store is independent of the
2424 Res = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2430 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
2432 SDValue Ch = N->getChain();
2433 SDValue Ptr = N->getBasePtr();
2434 SDValue Mask = N->getMask();
2435 SDValue Index = N->getIndex();
2436 SDValue Scale = N->getScale();
2437 SDValue Data = N->getValue();
2438 Align Alignment = N->getOriginalAlign();
2441 // Split all operands
2443 SDValue DataLo, DataHi;
2444 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2445 // Split Data operand
2446 GetSplitVector(Data, DataLo, DataHi);
2448 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2450 // Split Mask operand
2451 SDValue MaskLo, MaskHi;
2452 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) {
2453 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi);
2455 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2456 GetSplitVector(Mask, MaskLo, MaskHi);
2458 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2461 SDValue IndexHi, IndexLo;
2462 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2463 GetSplitVector(Index, IndexLo, IndexHi);
2465 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
2468 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
2469 N->getPointerInfo(), MachineMemOperand::MOStore,
2470 MemoryLocation::UnknownSize, Alignment, N->getAAInfo(), N->getRanges());
2472 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo, Scale};
2473 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
2474 DL, OpsLo, MMO, N->getIndexType());
2476 // The order of the Scatter operation after split is well defined. The "Hi"
2477 // part comes after the "Lo". So these two operations should be chained one
2479 SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi, Scale};
2480 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
2481 DL, OpsHi, MMO, N->getIndexType());
2484 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
2485 assert(N->isUnindexed() && "Indexed store of vector?");
2486 assert(OpNo == 1 && "Can only split the stored value");
2489 bool isTruncating = N->isTruncatingStore();
2490 SDValue Ch = N->getChain();
2491 SDValue Ptr = N->getBasePtr();
2492 EVT MemoryVT = N->getMemoryVT();
2493 Align Alignment = N->getOriginalAlign();
2494 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2495 AAMDNodes AAInfo = N->getAAInfo();
2497 GetSplitVector(N->getOperand(1), Lo, Hi);
2499 EVT LoMemVT, HiMemVT;
2500 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2502 // Scalarize if the split halves are not byte-sized.
2503 if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized())
2504 return TLI.scalarizeVectorStore(N, DAG);
2507 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
2508 Alignment, MMOFlags, AAInfo);
2510 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2513 MachinePointerInfo MPI;
2514 IncrementPointer(N, LoMemVT, MPI, Ptr);
2517 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, MPI,
2518 HiMemVT, Alignment, MMOFlags, AAInfo);
2520 Hi = DAG.getStore(Ch, DL, Hi, Ptr, MPI, Alignment, MMOFlags, AAInfo);
2522 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2525 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
2528 // The input operands all must have the same type, and we know the result
2529 // type is valid. Convert this to a buildvector which extracts all the
2531 // TODO: If the input elements are power-two vectors, we could convert this to
2532 // a new CONCAT_VECTORS node with elements that are half-wide.
2533 SmallVector<SDValue, 32> Elts;
2534 EVT EltVT = N->getValueType(0).getVectorElementType();
2535 for (const SDValue &Op : N->op_values()) {
2536 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
2538 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
2539 DAG.getVectorIdxConstant(i, DL)));
2543 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
2546 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
2547 // The result type is legal, but the input type is illegal. If splitting
2548 // ends up with the result type of each half still being legal, just
2549 // do that. If, however, that would result in an illegal result type,
2550 // we can try to get more clever with power-two vectors. Specifically,
2551 // split the input type, but also widen the result element size, then
2552 // concatenate the halves and truncate again. For example, consider a target
2553 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
2554 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
2555 // %inlo = v4i32 extract_subvector %in, 0
2556 // %inhi = v4i32 extract_subvector %in, 4
2557 // %lo16 = v4i16 trunc v4i32 %inlo
2558 // %hi16 = v4i16 trunc v4i32 %inhi
2559 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
2560 // %res = v8i8 trunc v8i16 %in16
2562 // Without this transform, the original truncate would end up being
2563 // scalarized, which is pretty much always a last resort.
2564 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
2565 SDValue InVec = N->getOperand(OpNo);
2566 EVT InVT = InVec->getValueType(0);
2567 EVT OutVT = N->getValueType(0);
2568 ElementCount NumElements = OutVT.getVectorElementCount();
2569 bool IsFloat = OutVT.isFloatingPoint();
2571 unsigned InElementSize = InVT.getScalarSizeInBits();
2572 unsigned OutElementSize = OutVT.getScalarSizeInBits();
2574 // Determine the split output VT. If its legal we can just split dirctly.
2575 EVT LoOutVT, HiOutVT;
2576 std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT);
2577 assert(LoOutVT == HiOutVT && "Unequal split?");
2579 // If the input elements are only 1/2 the width of the result elements,
2580 // just use the normal splitting. Our trick only work if there's room
2581 // to split more than once.
2582 if (isTypeLegal(LoOutVT) ||
2583 InElementSize <= OutElementSize * 2)
2584 return SplitVecOp_UnaryOp(N);
2587 // Don't touch if this will be scalarized.
2589 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
2590 FinalVT = FinalVT.getHalfNumVectorElementsVT(*DAG.getContext());
2592 if (getTypeAction(FinalVT) == TargetLowering::TypeScalarizeVector)
2593 return SplitVecOp_UnaryOp(N);
2595 // Get the split input vector.
2596 SDValue InLoVec, InHiVec;
2597 GetSplitVector(InVec, InLoVec, InHiVec);
2599 // Truncate them to 1/2 the element size.
2601 // This assumes the number of elements is a power of two; any vector that
2602 // isn't should be widened, not split.
2603 EVT HalfElementVT = IsFloat ?
2604 EVT::getFloatingPointVT(InElementSize/2) :
2605 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
2606 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
2612 if (N->isStrictFPOpcode()) {
2613 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
2614 {N->getOperand(0), InLoVec});
2615 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other},
2616 {N->getOperand(0), InHiVec});
2617 // Legalize the chain result - switch anything that used the old chain to
2619 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, HalfLo.getValue(1),
2620 HalfHi.getValue(1));
2622 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2623 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2625 // Concatenate them to get the full intermediate truncation result.
2626 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
2627 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2629 // Now finish up by truncating all the way down to the original result
2630 // type. This should normally be something that ends up being legal directly,
2631 // but in theory if a target has very wide vectors and an annoyingly
2632 // restricted set of legal types, this split can chain to build things up.
2634 if (N->isStrictFPOpcode()) {
2635 SDValue Res = DAG.getNode(
2636 ISD::STRICT_FP_ROUND, DL, {OutVT, MVT::Other},
2638 DAG.getTargetConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout()))});
2640 ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
2645 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2646 DAG.getTargetConstant(
2647 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2648 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2651 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2652 assert(N->getValueType(0).isVector() &&
2653 N->getOperand(0).getValueType().isVector() &&
2654 "Operand types must be vectors");
2655 // The result has a legal vector type, but the input needs splitting.
2656 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2658 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2659 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2660 auto PartEltCnt = Lo0.getValueType().getVectorElementCount();
2662 LLVMContext &Context = *DAG.getContext();
2663 EVT PartResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt);
2664 EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt*2);
2666 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2667 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2668 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2670 EVT OpVT = N->getOperand(0).getValueType();
2671 ISD::NodeType ExtendCode =
2672 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
2673 return DAG.getNode(ExtendCode, DL, N->getValueType(0), Con);
2677 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2678 // The result has a legal vector type, but the input needs splitting.
2679 EVT ResVT = N->getValueType(0);
2682 GetSplitVector(N->getOperand(N->isStrictFPOpcode() ? 1 : 0), Lo, Hi);
2683 EVT InVT = Lo.getValueType();
2685 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2686 InVT.getVectorNumElements());
2688 if (N->isStrictFPOpcode()) {
2689 Lo = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other },
2690 { N->getOperand(0), Lo, N->getOperand(2) });
2691 Hi = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other },
2692 { N->getOperand(0), Hi, N->getOperand(2) });
2693 // Legalize the chain result - switch anything that used the old chain to
2695 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2696 Lo.getValue(1), Hi.getValue(1));
2697 ReplaceValueWith(SDValue(N, 1), NewChain);
2699 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2700 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2703 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2706 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2707 // The result (and the first input) has a legal vector type, but the second
2708 // input needs splitting.
2709 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2713 //===----------------------------------------------------------------------===//
2714 // Result Vector Widening
2715 //===----------------------------------------------------------------------===//
2717 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2718 LLVM_DEBUG(dbgs() << "Widen node result " << ResNo << ": "; N->dump(&DAG);
2721 // See if the target wants to custom widen this node.
2722 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2725 SDValue Res = SDValue();
2726 switch (N->getOpcode()) {
2729 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2733 llvm_unreachable("Do not know how to widen the result of this operator!");
2735 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2736 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2737 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2738 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2739 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2740 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2741 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2742 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2743 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2745 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2746 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2747 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2748 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2749 case ISD::VECTOR_SHUFFLE:
2750 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2753 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2756 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2779 Res = WidenVecRes_Binary(N);
2792 Res = WidenVecRes_BinaryCanTrap(N);
2796 case ISD::SMULFIXSAT:
2798 case ISD::UMULFIXSAT:
2799 // These are binary operations, but with an extra operand that shouldn't
2800 // be widened (the scale).
2801 Res = WidenVecRes_BinaryWithExtraScalarOp(N);
2804 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
2805 case ISD::STRICT_##DAGN:
2806 #include "llvm/IR/ConstrainedOps.def"
2807 Res = WidenVecRes_StrictFP(N);
2816 Res = WidenVecRes_OverflowOp(N, ResNo);
2819 case ISD::FCOPYSIGN:
2820 Res = WidenVecRes_FCOPYSIGN(N);
2824 Res = WidenVecRes_POWI(N);
2830 Res = WidenVecRes_Shift(N);
2833 case ISD::ANY_EXTEND_VECTOR_INREG:
2834 case ISD::SIGN_EXTEND_VECTOR_INREG:
2835 case ISD::ZERO_EXTEND_VECTOR_INREG:
2836 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2839 case ISD::ANY_EXTEND:
2840 case ISD::FP_EXTEND:
2842 case ISD::FP_TO_SINT:
2843 case ISD::FP_TO_UINT:
2844 case ISD::SIGN_EXTEND:
2845 case ISD::SINT_TO_FP:
2847 case ISD::UINT_TO_FP:
2848 case ISD::ZERO_EXTEND:
2849 Res = WidenVecRes_Convert(N);
2861 case ISD::FNEARBYINT:
2864 case ISD::FROUNDEVEN:
2868 // We're going to widen this vector op to a legal type by padding with undef
2869 // elements. If the wide vector op is eventually going to be expanded to
2870 // scalar libcalls, then unroll into scalar ops now to avoid unnecessary
2871 // libcalls on the undef elements.
2872 EVT VT = N->getValueType(0);
2873 EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2874 if (!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
2875 TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
2876 Res = DAG.UnrollVectorOp(N, WideVecVT.getVectorNumElements());
2880 // If the target has custom/legal support for the scalar FP intrinsic ops
2881 // (they are probably not destined to become libcalls), then widen those like
2882 // any other unary ops.
2886 case ISD::BITREVERSE:
2889 case ISD::CTLZ_ZERO_UNDEF:
2892 case ISD::CTTZ_ZERO_UNDEF:
2895 case ISD::FCANONICALIZE:
2896 Res = WidenVecRes_Unary(N);
2899 Res = WidenVecRes_Ternary(N);
2903 // If Res is null, the sub-method took care of registering the result.
2905 SetWidenedVector(SDValue(N, ResNo), Res);
2908 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2909 // Ternary op widening.
2911 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2912 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2913 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2914 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2915 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2918 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2919 // Binary op widening.
2921 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2922 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2923 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2924 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2927 SDValue DAGTypeLegalizer::WidenVecRes_BinaryWithExtraScalarOp(SDNode *N) {
2928 // Binary op widening, but with an extra operand that shouldn't be widened.
2930 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2931 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2932 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2933 SDValue InOp3 = N->getOperand(2);
2934 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3,
2938 // Given a vector of operations that have been broken up to widen, see
2939 // if we can collect them together into the next widest legal VT. This
2940 // implementation is trap-safe.
2941 static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI,
2942 SmallVectorImpl<SDValue> &ConcatOps,
2943 unsigned ConcatEnd, EVT VT, EVT MaxVT,
2945 // Check to see if we have a single operation with the widen type.
2946 if (ConcatEnd == 1) {
2947 VT = ConcatOps[0].getValueType();
2949 return ConcatOps[0];
2952 SDLoc dl(ConcatOps[0]);
2953 EVT WidenEltVT = WidenVT.getVectorElementType();
2955 // while (Some element of ConcatOps is not of type MaxVT) {
2956 // From the end of ConcatOps, collect elements of the same type and put
2957 // them into an op of the next larger supported type
2959 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2960 int Idx = ConcatEnd - 1;
2961 VT = ConcatOps[Idx--].getValueType();
2962 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2965 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2969 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2970 } while (!TLI.isTypeLegal(NextVT));
2972 if (!VT.isVector()) {
2973 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2974 SDValue VecOp = DAG.getUNDEF(NextVT);
2975 unsigned NumToInsert = ConcatEnd - Idx - 1;
2976 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2977 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
2978 ConcatOps[OpIdx], DAG.getVectorIdxConstant(i, dl));
2980 ConcatOps[Idx+1] = VecOp;
2981 ConcatEnd = Idx + 2;
2983 // Vector type, create a CONCAT_VECTORS of type NextVT
2984 SDValue undefVec = DAG.getUNDEF(VT);
2985 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2986 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2987 unsigned RealVals = ConcatEnd - Idx - 1;
2988 unsigned SubConcatEnd = 0;
2989 unsigned SubConcatIdx = Idx + 1;
2990 while (SubConcatEnd < RealVals)
2991 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2992 while (SubConcatEnd < OpsToConcat)
2993 SubConcatOps[SubConcatEnd++] = undefVec;
2994 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2995 NextVT, SubConcatOps);
2996 ConcatEnd = SubConcatIdx + 1;
3000 // Check to see if we have a single operation with the widen type.
3001 if (ConcatEnd == 1) {
3002 VT = ConcatOps[0].getValueType();
3004 return ConcatOps[0];
3007 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
3008 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
3009 if (NumOps != ConcatEnd ) {
3010 SDValue UndefVal = DAG.getUNDEF(MaxVT);
3011 for (unsigned j = ConcatEnd; j < NumOps; ++j)
3012 ConcatOps[j] = UndefVal;
3014 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3015 makeArrayRef(ConcatOps.data(), NumOps));
3018 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
3019 // Binary op widening for operations that can trap.
3020 unsigned Opcode = N->getOpcode();
3022 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3023 EVT WidenEltVT = WidenVT.getVectorElementType();
3025 unsigned NumElts = VT.getVectorNumElements();
3026 const SDNodeFlags Flags = N->getFlags();
3027 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
3028 NumElts = NumElts / 2;
3029 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
3032 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
3033 // Operation doesn't trap so just widen as normal.
3034 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3035 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3036 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
3039 // No legal vector version so unroll the vector operation and then widen.
3041 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
3043 // Since the operation can trap, apply operation on the original vector.
3045 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3046 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3047 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
3049 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
3050 unsigned ConcatEnd = 0; // Current ConcatOps index.
3051 int Idx = 0; // Current Idx into input vectors.
3053 // NumElts := greatest legal vector size (at most WidenVT)
3054 // while (orig. vector has unhandled elements) {
3055 // take munches of size NumElts from the beginning and add to ConcatOps
3056 // NumElts := next smaller supported vector size or 1
3058 while (CurNumElts != 0) {
3059 while (CurNumElts >= NumElts) {
3060 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
3061 DAG.getVectorIdxConstant(Idx, dl));
3062 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
3063 DAG.getVectorIdxConstant(Idx, dl));
3064 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
3066 CurNumElts -= NumElts;
3069 NumElts = NumElts / 2;
3070 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
3071 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
3074 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
3075 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
3076 InOp1, DAG.getVectorIdxConstant(Idx, dl));
3077 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
3078 InOp2, DAG.getVectorIdxConstant(Idx, dl));
3079 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
3086 return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
3089 SDValue DAGTypeLegalizer::WidenVecRes_StrictFP(SDNode *N) {
3090 switch (N->getOpcode()) {
3091 case ISD::STRICT_FSETCC:
3092 case ISD::STRICT_FSETCCS:
3093 return WidenVecRes_STRICT_FSETCC(N);
3094 case ISD::STRICT_FP_EXTEND:
3095 case ISD::STRICT_FP_ROUND:
3096 case ISD::STRICT_FP_TO_SINT:
3097 case ISD::STRICT_FP_TO_UINT:
3098 case ISD::STRICT_SINT_TO_FP:
3099 case ISD::STRICT_UINT_TO_FP:
3100 return WidenVecRes_Convert_StrictFP(N);
3105 // StrictFP op widening for operations that can trap.
3106 unsigned NumOpers = N->getNumOperands();
3107 unsigned Opcode = N->getOpcode();
3109 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3110 EVT WidenEltVT = WidenVT.getVectorElementType();
3112 unsigned NumElts = VT.getVectorNumElements();
3113 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
3114 NumElts = NumElts / 2;
3115 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
3118 // No legal vector version so unroll the vector operation and then widen.
3120 return UnrollVectorOp_StrictFP(N, WidenVT.getVectorNumElements());
3122 // Since the operation can trap, apply operation on the original vector.
3124 SmallVector<SDValue, 4> InOps;
3125 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
3127 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
3128 SmallVector<SDValue, 16> Chains;
3129 unsigned ConcatEnd = 0; // Current ConcatOps index.
3130 int Idx = 0; // Current Idx into input vectors.
3132 // The Chain is the first operand.
3133 InOps.push_back(N->getOperand(0));
3135 // Now process the remaining operands.
3136 for (unsigned i = 1; i < NumOpers; ++i) {
3137 SDValue Oper = N->getOperand(i);
3139 if (Oper.getValueType().isVector()) {
3140 assert(Oper.getValueType() == N->getValueType(0) &&
3141 "Invalid operand type to widen!");
3142 Oper = GetWidenedVector(Oper);
3145 InOps.push_back(Oper);
3148 // NumElts := greatest legal vector size (at most WidenVT)
3149 // while (orig. vector has unhandled elements) {
3150 // take munches of size NumElts from the beginning and add to ConcatOps
3151 // NumElts := next smaller supported vector size or 1
3153 while (CurNumElts != 0) {
3154 while (CurNumElts >= NumElts) {
3155 SmallVector<SDValue, 4> EOps;
3157 for (unsigned i = 0; i < NumOpers; ++i) {
3158 SDValue Op = InOps[i];
3160 if (Op.getValueType().isVector())
3161 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
3162 DAG.getVectorIdxConstant(Idx, dl));
3167 EVT OperVT[] = {VT, MVT::Other};
3168 SDValue Oper = DAG.getNode(Opcode, dl, OperVT, EOps);
3169 ConcatOps[ConcatEnd++] = Oper;
3170 Chains.push_back(Oper.getValue(1));
3172 CurNumElts -= NumElts;
3175 NumElts = NumElts / 2;
3176 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
3177 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
3180 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
3181 SmallVector<SDValue, 4> EOps;
3183 for (unsigned i = 0; i < NumOpers; ++i) {
3184 SDValue Op = InOps[i];
3186 if (Op.getValueType().isVector())
3187 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, Op,
3188 DAG.getVectorIdxConstant(Idx, dl));
3193 EVT WidenVT[] = {WidenEltVT, MVT::Other};
3194 SDValue Oper = DAG.getNode(Opcode, dl, WidenVT, EOps);
3195 ConcatOps[ConcatEnd++] = Oper;
3196 Chains.push_back(Oper.getValue(1));
3202 // Build a factor node to remember all the Ops that have been created.
3204 if (Chains.size() == 1)
3205 NewChain = Chains[0];
3207 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
3208 ReplaceValueWith(SDValue(N, 1), NewChain);
3210 return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
3213 SDValue DAGTypeLegalizer::WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo) {
3215 EVT ResVT = N->getValueType(0);
3216 EVT OvVT = N->getValueType(1);
3217 EVT WideResVT, WideOvVT;
3218 SDValue WideLHS, WideRHS;
3220 // TODO: This might result in a widen/split loop.
3222 WideResVT = TLI.getTypeToTransformTo(*DAG.getContext(), ResVT);
3223 WideOvVT = EVT::getVectorVT(
3224 *DAG.getContext(), OvVT.getVectorElementType(),
3225 WideResVT.getVectorNumElements());
3227 WideLHS = GetWidenedVector(N->getOperand(0));
3228 WideRHS = GetWidenedVector(N->getOperand(1));
3230 WideOvVT = TLI.getTypeToTransformTo(*DAG.getContext(), OvVT);
3231 WideResVT = EVT::getVectorVT(
3232 *DAG.getContext(), ResVT.getVectorElementType(),
3233 WideOvVT.getVectorNumElements());
3235 SDValue Zero = DAG.getVectorIdxConstant(0, DL);
3236 WideLHS = DAG.getNode(
3237 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3238 N->getOperand(0), Zero);
3239 WideRHS = DAG.getNode(
3240 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3241 N->getOperand(1), Zero);
3244 SDVTList WideVTs = DAG.getVTList(WideResVT, WideOvVT);
3245 SDNode *WideNode = DAG.getNode(
3246 N->getOpcode(), DL, WideVTs, WideLHS, WideRHS).getNode();
3248 // Replace the other vector result not being explicitly widened here.
3249 unsigned OtherNo = 1 - ResNo;
3250 EVT OtherVT = N->getValueType(OtherNo);
3251 if (getTypeAction(OtherVT) == TargetLowering::TypeWidenVector) {
3252 SetWidenedVector(SDValue(N, OtherNo), SDValue(WideNode, OtherNo));
3254 SDValue Zero = DAG.getVectorIdxConstant(0, DL);
3255 SDValue OtherVal = DAG.getNode(
3256 ISD::EXTRACT_SUBVECTOR, DL, OtherVT, SDValue(WideNode, OtherNo), Zero);
3257 ReplaceValueWith(SDValue(N, OtherNo), OtherVal);
3260 return SDValue(WideNode, ResNo);
3263 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
3264 SDValue InOp = N->getOperand(0);
3267 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3268 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3270 EVT InVT = InOp.getValueType();
3271 EVT InEltVT = InVT.getVectorElementType();
3272 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
3274 unsigned Opcode = N->getOpcode();
3275 unsigned InVTNumElts = InVT.getVectorNumElements();
3276 const SDNodeFlags Flags = N->getFlags();
3277 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
3278 InOp = GetWidenedVector(N->getOperand(0));
3279 InVT = InOp.getValueType();
3280 InVTNumElts = InVT.getVectorNumElements();
3281 if (InVTNumElts == WidenNumElts) {
3282 if (N->getNumOperands() == 1)
3283 return DAG.getNode(Opcode, DL, WidenVT, InOp);
3284 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
3286 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
3287 // If both input and result vector types are of same width, extend
3288 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
3289 // accepts fewer elements in the result than in the input.
3290 if (Opcode == ISD::ANY_EXTEND)
3291 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3292 if (Opcode == ISD::SIGN_EXTEND)
3293 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3294 if (Opcode == ISD::ZERO_EXTEND)
3295 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3299 if (TLI.isTypeLegal(InWidenVT)) {
3300 // Because the result and the input are different vector types, widening
3301 // the result could create a legal type but widening the input might make
3302 // it an illegal type that might lead to repeatedly splitting the input
3303 // and then widening it. To avoid this, we widen the input only if
3304 // it results in a legal type.
3305 if (WidenNumElts % InVTNumElts == 0) {
3306 // Widen the input and call convert on the widened input vector.
3307 unsigned NumConcat = WidenNumElts/InVTNumElts;
3308 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
3310 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
3311 if (N->getNumOperands() == 1)
3312 return DAG.getNode(Opcode, DL, WidenVT, InVec);
3313 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
3316 if (InVTNumElts % WidenNumElts == 0) {
3317 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
3318 DAG.getVectorIdxConstant(0, DL));
3319 // Extract the input and convert the shorten input vector.
3320 if (N->getNumOperands() == 1)
3321 return DAG.getNode(Opcode, DL, WidenVT, InVal);
3322 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
3326 // Otherwise unroll into some nasty scalar code and rebuild the vector.
3327 EVT EltVT = WidenVT.getVectorElementType();
3328 SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
3329 // Use the original element count so we don't do more scalar opts than
3331 unsigned MinElts = N->getValueType(0).getVectorNumElements();
3332 for (unsigned i=0; i < MinElts; ++i) {
3333 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
3334 DAG.getVectorIdxConstant(i, DL));
3335 if (N->getNumOperands() == 1)
3336 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
3338 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
3341 return DAG.getBuildVector(WidenVT, DL, Ops);
3344 SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
3345 SDValue InOp = N->getOperand(1);
3347 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
3349 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3350 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3352 EVT InVT = InOp.getValueType();
3353 EVT InEltVT = InVT.getVectorElementType();
3355 unsigned Opcode = N->getOpcode();
3357 // FIXME: Optimizations need to be implemented here.
3359 // Otherwise unroll into some nasty scalar code and rebuild the vector.
3360 EVT EltVT = WidenVT.getVectorElementType();
3361 std::array<EVT, 2> EltVTs = {{EltVT, MVT::Other}};
3362 SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
3363 SmallVector<SDValue, 32> OpChains;
3364 // Use the original element count so we don't do more scalar opts than
3366 unsigned MinElts = N->getValueType(0).getVectorNumElements();
3367 for (unsigned i=0; i < MinElts; ++i) {
3368 NewOps[1] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
3369 DAG.getVectorIdxConstant(i, DL));
3370 Ops[i] = DAG.getNode(Opcode, DL, EltVTs, NewOps);
3371 OpChains.push_back(Ops[i].getValue(1));
3373 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OpChains);
3374 ReplaceValueWith(SDValue(N, 1), NewChain);
3376 return DAG.getBuildVector(WidenVT, DL, Ops);
3379 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
3380 unsigned Opcode = N->getOpcode();
3381 SDValue InOp = N->getOperand(0);
3384 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3385 EVT WidenSVT = WidenVT.getVectorElementType();
3386 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3388 EVT InVT = InOp.getValueType();
3389 EVT InSVT = InVT.getVectorElementType();
3390 unsigned InVTNumElts = InVT.getVectorNumElements();
3392 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
3393 InOp = GetWidenedVector(InOp);
3394 InVT = InOp.getValueType();
3395 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
3397 case ISD::ANY_EXTEND_VECTOR_INREG:
3398 case ISD::SIGN_EXTEND_VECTOR_INREG:
3399 case ISD::ZERO_EXTEND_VECTOR_INREG:
3400 return DAG.getNode(Opcode, DL, WidenVT, InOp);
3405 // Unroll, extend the scalars and rebuild the vector.
3406 SmallVector<SDValue, 16> Ops;
3407 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
3408 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
3409 DAG.getVectorIdxConstant(i, DL));
3411 case ISD::ANY_EXTEND_VECTOR_INREG:
3412 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
3414 case ISD::SIGN_EXTEND_VECTOR_INREG:
3415 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
3417 case ISD::ZERO_EXTEND_VECTOR_INREG:
3418 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
3421 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
3426 while (Ops.size() != WidenNumElts)
3427 Ops.push_back(DAG.getUNDEF(WidenSVT));
3429 return DAG.getBuildVector(WidenVT, DL, Ops);
3432 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
3433 // If this is an FCOPYSIGN with same input types, we can treat it as a
3434 // normal (can trap) binary op.
3435 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
3436 return WidenVecRes_BinaryCanTrap(N);
3438 // If the types are different, fall back to unrolling.
3439 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3440 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
3443 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
3444 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3445 SDValue InOp = GetWidenedVector(N->getOperand(0));
3446 SDValue ShOp = N->getOperand(1);
3447 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3450 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
3451 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3452 SDValue InOp = GetWidenedVector(N->getOperand(0));
3453 SDValue ShOp = N->getOperand(1);
3455 EVT ShVT = ShOp.getValueType();
3456 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
3457 ShOp = GetWidenedVector(ShOp);
3458 ShVT = ShOp.getValueType();
3460 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
3461 ShVT.getVectorElementType(),
3462 WidenVT.getVectorNumElements());
3463 if (ShVT != ShWidenVT)
3464 ShOp = ModifyToType(ShOp, ShWidenVT);
3466 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
3469 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
3470 // Unary op widening.
3471 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3472 SDValue InOp = GetWidenedVector(N->getOperand(0));
3473 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
3476 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
3477 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3478 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
3479 cast<VTSDNode>(N->getOperand(1))->getVT()
3480 .getVectorElementType(),
3481 WidenVT.getVectorNumElements());
3482 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
3483 return DAG.getNode(N->getOpcode(), SDLoc(N),
3484 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
3487 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
3488 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
3489 return GetWidenedVector(WidenVec);
3492 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
3493 SDValue InOp = N->getOperand(0);
3494 EVT InVT = InOp.getValueType();
3495 EVT VT = N->getValueType(0);
3496 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3499 switch (getTypeAction(InVT)) {
3500 case TargetLowering::TypeLegal:
3502 case TargetLowering::TypeScalarizeScalableVector:
3503 report_fatal_error("Scalarization of scalable vectors is not supported.");
3504 case TargetLowering::TypePromoteInteger: {
3505 // If the incoming type is a vector that is being promoted, then
3506 // we know that the elements are arranged differently and that we
3507 // must perform the conversion using a stack slot.
3508 if (InVT.isVector())
3511 // If the InOp is promoted to the same size, convert it. Otherwise,
3512 // fall out of the switch and widen the promoted input.
3513 SDValue NInOp = GetPromotedInteger(InOp);
3514 EVT NInVT = NInOp.getValueType();
3515 if (WidenVT.bitsEq(NInVT)) {
3516 // For big endian targets we need to shift the input integer or the
3517 // interesting bits will end up at the wrong place.
3518 if (DAG.getDataLayout().isBigEndian()) {
3519 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
3520 EVT ShiftAmtTy = TLI.getShiftAmountTy(NInVT, DAG.getDataLayout());
3521 assert(ShiftAmt < WidenVT.getSizeInBits() && "Too large shift amount!");
3522 NInOp = DAG.getNode(ISD::SHL, dl, NInVT, NInOp,
3523 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
3525 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NInOp);
3531 case TargetLowering::TypeSoftenFloat:
3532 case TargetLowering::TypePromoteFloat:
3533 case TargetLowering::TypeSoftPromoteHalf:
3534 case TargetLowering::TypeExpandInteger:
3535 case TargetLowering::TypeExpandFloat:
3536 case TargetLowering::TypeScalarizeVector:
3537 case TargetLowering::TypeSplitVector:
3539 case TargetLowering::TypeWidenVector:
3540 // If the InOp is widened to the same size, convert it. Otherwise, fall
3541 // out of the switch and widen the widened input.
3542 InOp = GetWidenedVector(InOp);
3543 InVT = InOp.getValueType();
3544 if (WidenVT.bitsEq(InVT))
3545 // The input widens to the same size. Convert to the widen value.
3546 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
3550 unsigned WidenSize = WidenVT.getSizeInBits();
3551 unsigned InSize = InVT.getSizeInBits();
3552 // x86mmx is not an acceptable vector element type, so don't try.
3553 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
3554 // Determine new input vector type. The new input vector type will use
3555 // the same element type (if its a vector) or use the input type as a
3556 // vector. It is the same size as the type to widen to.
3558 unsigned NewNumElts = WidenSize / InSize;
3559 if (InVT.isVector()) {
3560 EVT InEltVT = InVT.getVectorElementType();
3561 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
3562 WidenSize / InEltVT.getSizeInBits());
3564 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
3567 if (TLI.isTypeLegal(NewInVT)) {
3569 if (InVT.isVector()) {
3570 // Because the result and the input are different vector types, widening
3571 // the result could create a legal type but widening the input might make
3572 // it an illegal type that might lead to repeatedly splitting the input
3573 // and then widening it. To avoid this, we widen the input only if
3574 // it results in a legal type.
3575 SmallVector<SDValue, 16> Ops(NewNumElts, DAG.getUNDEF(InVT));
3578 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
3580 NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
3582 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
3586 return CreateStackStoreLoad(InOp, WidenVT);
3589 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
3591 // Build a vector with undefined for the new nodes.
3592 EVT VT = N->getValueType(0);
3594 // Integer BUILD_VECTOR operands may be larger than the node's vector element
3595 // type. The UNDEFs need to have the same type as the existing operands.
3596 EVT EltVT = N->getOperand(0).getValueType();
3597 unsigned NumElts = VT.getVectorNumElements();
3599 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3600 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3602 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
3603 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
3604 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
3606 return DAG.getBuildVector(WidenVT, dl, NewOps);
3609 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
3610 EVT InVT = N->getOperand(0).getValueType();
3611 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3613 unsigned NumOperands = N->getNumOperands();
3615 bool InputWidened = false; // Indicates we need to widen the input.
3616 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
3617 unsigned WidenNumElts = WidenVT.getVectorMinNumElements();
3618 unsigned NumInElts = InVT.getVectorMinNumElements();
3619 if (WidenNumElts % NumInElts == 0) {
3620 // Add undef vectors to widen to correct length.
3621 unsigned NumConcat = WidenNumElts / NumInElts;
3622 SDValue UndefVal = DAG.getUNDEF(InVT);
3623 SmallVector<SDValue, 16> Ops(NumConcat);
3624 for (unsigned i=0; i < NumOperands; ++i)
3625 Ops[i] = N->getOperand(i);
3626 for (unsigned i = NumOperands; i != NumConcat; ++i)
3628 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
3631 InputWidened = true;
3632 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
3633 // The inputs and the result are widen to the same value.
3635 for (i=1; i < NumOperands; ++i)
3636 if (!N->getOperand(i).isUndef())
3639 if (i == NumOperands)
3640 // Everything but the first operand is an UNDEF so just return the
3641 // widened first operand.
3642 return GetWidenedVector(N->getOperand(0));
3644 if (NumOperands == 2) {
3645 assert(!WidenVT.isScalableVector() &&
3646 "Cannot use vector shuffles to widen CONCAT_VECTOR result");
3647 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3648 unsigned NumInElts = InVT.getVectorNumElements();
3650 // Replace concat of two operands with a shuffle.
3651 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
3652 for (unsigned i = 0; i < NumInElts; ++i) {
3654 MaskOps[i + NumInElts] = i + WidenNumElts;
3656 return DAG.getVectorShuffle(WidenVT, dl,
3657 GetWidenedVector(N->getOperand(0)),
3658 GetWidenedVector(N->getOperand(1)),
3664 assert(!WidenVT.isScalableVector() &&
3665 "Cannot use build vectors to widen CONCAT_VECTOR result");
3666 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3667 unsigned NumInElts = InVT.getVectorNumElements();
3669 // Fall back to use extracts and build vector.
3670 EVT EltVT = WidenVT.getVectorElementType();
3671 SmallVector<SDValue, 16> Ops(WidenNumElts);
3673 for (unsigned i=0; i < NumOperands; ++i) {
3674 SDValue InOp = N->getOperand(i);
3676 InOp = GetWidenedVector(InOp);
3677 for (unsigned j = 0; j < NumInElts; ++j)
3678 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3679 DAG.getVectorIdxConstant(j, dl));
3681 SDValue UndefVal = DAG.getUNDEF(EltVT);
3682 for (; Idx < WidenNumElts; ++Idx)
3683 Ops[Idx] = UndefVal;
3684 return DAG.getBuildVector(WidenVT, dl, Ops);
3687 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
3688 EVT VT = N->getValueType(0);
3689 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3690 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3691 SDValue InOp = N->getOperand(0);
3692 SDValue Idx = N->getOperand(1);
3695 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3696 InOp = GetWidenedVector(InOp);
3698 EVT InVT = InOp.getValueType();
3700 // Check if we can just return the input vector after widening.
3701 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3702 if (IdxVal == 0 && InVT == WidenVT)
3705 // Check if we can extract from the vector.
3706 unsigned InNumElts = InVT.getVectorNumElements();
3707 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
3708 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
3710 // We could try widening the input to the right length but for now, extract
3711 // the original elements, fill the rest with undefs and build a vector.
3712 SmallVector<SDValue, 16> Ops(WidenNumElts);
3713 EVT EltVT = VT.getVectorElementType();
3714 unsigned NumElts = VT.getVectorNumElements();
3716 for (i = 0; i < NumElts; ++i)
3717 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3718 DAG.getVectorIdxConstant(IdxVal + i, dl));
3720 SDValue UndefVal = DAG.getUNDEF(EltVT);
3721 for (; i < WidenNumElts; ++i)
3723 return DAG.getBuildVector(WidenVT, dl, Ops);
3726 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
3727 SDValue InOp = GetWidenedVector(N->getOperand(0));
3728 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
3729 InOp.getValueType(), InOp,
3730 N->getOperand(1), N->getOperand(2));
3733 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
3734 LoadSDNode *LD = cast<LoadSDNode>(N);
3735 ISD::LoadExtType ExtType = LD->getExtensionType();
3737 // A vector must always be stored in memory as-is, i.e. without any padding
3738 // between the elements, since various code depend on it, e.g. in the
3739 // handling of a bitcast of a vector type to int, which may be done with a
3740 // vector store followed by an integer load. A vector that does not have
3741 // elements that are byte-sized must therefore be stored as an integer
3742 // built out of the extracted vector elements.
3743 if (!LD->getMemoryVT().isByteSized()) {
3744 SDValue Value, NewChain;
3745 std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
3746 ReplaceValueWith(SDValue(LD, 0), Value);
3747 ReplaceValueWith(SDValue(LD, 1), NewChain);
3752 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
3753 if (ExtType != ISD::NON_EXTLOAD)
3754 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
3756 Result = GenWidenVectorLoads(LdChain, LD);
3758 // If we generate a single load, we can use that for the chain. Otherwise,
3759 // build a factor node to remember the multiple loads are independent and
3762 if (LdChain.size() == 1)
3763 NewChain = LdChain[0];
3765 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
3767 // Modified the chain - switch anything that used the old chain to use
3769 ReplaceValueWith(SDValue(N, 1), NewChain);
3774 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
3776 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
3777 SDValue Mask = N->getMask();
3778 EVT MaskVT = Mask.getValueType();
3779 SDValue PassThru = GetWidenedVector(N->getPassThru());
3780 ISD::LoadExtType ExtType = N->getExtensionType();
3783 // The mask should be widened as well
3784 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3785 MaskVT.getVectorElementType(),
3786 WidenVT.getVectorNumElements());
3787 Mask = ModifyToType(Mask, WideMaskVT, true);
3789 SDValue Res = DAG.getMaskedLoad(
3790 WidenVT, dl, N->getChain(), N->getBasePtr(), N->getOffset(), Mask,
3791 PassThru, N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
3792 ExtType, N->isExpandingLoad());
3793 // Legalize the chain result - switch anything that used the old chain to
3795 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3799 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
3801 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3802 SDValue Mask = N->getMask();
3803 EVT MaskVT = Mask.getValueType();
3804 SDValue PassThru = GetWidenedVector(N->getPassThru());
3805 SDValue Scale = N->getScale();
3806 unsigned NumElts = WideVT.getVectorNumElements();
3809 // The mask should be widened as well
3810 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3811 MaskVT.getVectorElementType(),
3812 WideVT.getVectorNumElements());
3813 Mask = ModifyToType(Mask, WideMaskVT, true);
3815 // Widen the Index operand
3816 SDValue Index = N->getIndex();
3817 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3818 Index.getValueType().getScalarType(),
3820 Index = ModifyToType(Index, WideIndexVT);
3821 SDValue Ops[] = { N->getChain(), PassThru, Mask, N->getBasePtr(), Index,
3823 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
3824 N->getMemoryVT(), dl, Ops,
3825 N->getMemOperand(), N->getIndexType());
3827 // Legalize the chain result - switch anything that used the old chain to
3829 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3833 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
3834 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3835 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
3836 WidenVT, N->getOperand(0));
3839 // Return true is this is a SETCC node or a strict version of it.
3840 static inline bool isSETCCOp(unsigned Opcode) {
3843 case ISD::STRICT_FSETCC:
3844 case ISD::STRICT_FSETCCS:
3850 // Return true if this is a node that could have two SETCCs as operands.
3851 static inline bool isLogicalMaskOp(unsigned Opcode) {
3861 // If N is a SETCC or a strict variant of it, return the type
3862 // of the compare operands.
3863 static inline EVT getSETCCOperandType(SDValue N) {
3864 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
3865 return N->getOperand(OpNo).getValueType();
3868 // This is used just for the assert in convertMask(). Check that this either
3869 // a SETCC or a previously handled SETCC by convertMask().
3871 static inline bool isSETCCorConvertedSETCC(SDValue N) {
3872 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
3873 N = N.getOperand(0);
3874 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3875 for (unsigned i = 1; i < N->getNumOperands(); ++i)
3876 if (!N->getOperand(i)->isUndef())
3878 N = N.getOperand(0);
3881 if (N.getOpcode() == ISD::TRUNCATE)
3882 N = N.getOperand(0);
3883 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3884 N = N.getOperand(0);
3886 if (isLogicalMaskOp(N.getOpcode()))
3887 return isSETCCorConvertedSETCC(N.getOperand(0)) &&
3888 isSETCCorConvertedSETCC(N.getOperand(1));
3890 return (isSETCCOp(N.getOpcode()) ||
3891 ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
3895 // Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
3896 // to ToMaskVT if needed with vector extension or truncation.
3897 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
3899 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3900 // FIXME: This code seems to be too restrictive, we might consider
3901 // generalizing it or dropping it.
3902 assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.");
3904 // Make a new Mask node, with a legal result VT.
3906 SmallVector<SDValue, 4> Ops;
3907 for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3908 Ops.push_back(InMask->getOperand(i));
3909 if (InMask->isStrictFPOpcode()) {
3910 Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask),
3911 { MaskVT, MVT::Other }, Ops);
3912 ReplaceValueWith(InMask.getValue(1), Mask.getValue(1));
3915 Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3917 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
3918 // extend or truncate is needed.
3919 LLVMContext &Ctx = *DAG.getContext();
3920 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
3921 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
3922 if (MaskScalarBits < ToMaskScalBits) {
3923 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3924 MaskVT.getVectorNumElements());
3925 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
3926 } else if (MaskScalarBits > ToMaskScalBits) {
3927 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3928 MaskVT.getVectorNumElements());
3929 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
3932 assert(Mask->getValueType(0).getScalarSizeInBits() ==
3933 ToMaskVT.getScalarSizeInBits() &&
3934 "Mask should have the right element size by now.");
3936 // Adjust Mask to the right number of elements.
3937 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3938 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
3939 SDValue ZeroIdx = DAG.getVectorIdxConstant(0, SDLoc(Mask));
3940 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
3942 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
3943 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
3944 EVT SubVT = Mask->getValueType(0);
3945 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
3947 Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
3950 assert((Mask->getValueType(0) == ToMaskVT) &&
3951 "A mask of ToMaskVT should have been produced by now.");
3956 // This method tries to handle VSELECT and its mask by legalizing operands
3957 // (which may require widening) and if needed adjusting the mask vector type
3958 // to match that of the VSELECT. Without it, many cases end up with
3959 // scalarization of the SETCC, with many unnecessary instructions.
3960 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
3961 LLVMContext &Ctx = *DAG.getContext();
3962 SDValue Cond = N->getOperand(0);
3964 if (N->getOpcode() != ISD::VSELECT)
3967 if (!isSETCCOp(Cond->getOpcode()) && !isLogicalMaskOp(Cond->getOpcode()))
3970 // If this is a splitted VSELECT that was previously already handled, do
3972 EVT CondVT = Cond->getValueType(0);
3973 if (CondVT.getScalarSizeInBits() != 1)
3976 EVT VSelVT = N->getValueType(0);
3977 // Only handle vector types which are a power of 2.
3978 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3981 // Don't touch if this will be scalarized.
3982 EVT FinalVT = VSelVT;
3983 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3984 FinalVT = FinalVT.getHalfNumVectorElementsVT(Ctx);
3986 if (FinalVT.getVectorNumElements() == 1)
3989 // If there is support for an i1 vector mask, don't touch.
3990 if (isSETCCOp(Cond.getOpcode())) {
3991 EVT SetCCOpVT = getSETCCOperandType(Cond);
3992 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3993 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3994 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3995 if (SetCCResVT.getScalarSizeInBits() == 1)
3997 } else if (CondVT.getScalarType() == MVT::i1) {
3998 // If there is support for an i1 vector mask (or only scalar i1 conditions),
4000 while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal)
4001 CondVT = TLI.getTypeToTransformTo(Ctx, CondVT);
4003 if (CondVT.getScalarType() == MVT::i1)
4007 // Get the VT and operands for VSELECT, and widen if needed.
4008 SDValue VSelOp1 = N->getOperand(1);
4009 SDValue VSelOp2 = N->getOperand(2);
4010 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
4011 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
4012 VSelOp1 = GetWidenedVector(VSelOp1);
4013 VSelOp2 = GetWidenedVector(VSelOp2);
4016 // The mask of the VSELECT should have integer elements.
4017 EVT ToMaskVT = VSelVT;
4018 if (!ToMaskVT.getScalarType().isInteger())
4019 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
4022 if (isSETCCOp(Cond->getOpcode())) {
4023 EVT MaskVT = getSetCCResultType(getSETCCOperandType(Cond));
4024 Mask = convertMask(Cond, MaskVT, ToMaskVT);
4025 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
4026 isSETCCOp(Cond->getOperand(0).getOpcode()) &&
4027 isSETCCOp(Cond->getOperand(1).getOpcode())) {
4028 // Cond is (AND/OR/XOR (SETCC, SETCC))
4029 SDValue SETCC0 = Cond->getOperand(0);
4030 SDValue SETCC1 = Cond->getOperand(1);
4031 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0));
4032 EVT VT1 = getSetCCResultType(getSETCCOperandType(SETCC1));
4033 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
4034 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
4035 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
4037 // If the two SETCCs have different VTs, either extend/truncate one of
4038 // them to the other "towards" ToMaskVT, or truncate one and extend the
4039 // other to ToMaskVT.
4040 if (ScalarBits0 != ScalarBits1) {
4041 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
4042 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
4043 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
4045 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
4050 // If the two SETCCs have the same VT, don't change it.
4053 // Make new SETCCs and logical nodes.
4054 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
4055 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
4056 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
4058 // Convert the logical op for VSELECT if needed.
4059 Mask = convertMask(Cond, MaskVT, ToMaskVT);
4063 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
4066 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
4067 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4068 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4070 SDValue Cond1 = N->getOperand(0);
4071 EVT CondVT = Cond1.getValueType();
4072 if (CondVT.isVector()) {
4073 if (SDValue Res = WidenVSELECTAndMask(N))
4076 EVT CondEltVT = CondVT.getVectorElementType();
4077 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
4078 CondEltVT, WidenNumElts);
4079 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
4080 Cond1 = GetWidenedVector(Cond1);
4082 // If we have to split the condition there is no point in widening the
4083 // select. This would result in an cycle of widening the select ->
4084 // widening the condition operand -> splitting the condition operand ->
4085 // splitting the select -> widening the select. Instead split this select
4086 // further and widen the resulting type.
4087 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
4088 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
4089 SDValue Res = ModifyToType(SplitSelect, WidenVT);
4093 if (Cond1.getValueType() != CondWidenVT)
4094 Cond1 = ModifyToType(Cond1, CondWidenVT);
4097 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
4098 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
4099 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
4100 return DAG.getNode(N->getOpcode(), SDLoc(N),
4101 WidenVT, Cond1, InOp1, InOp2);
4104 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
4105 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
4106 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
4107 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
4108 InOp1.getValueType(), N->getOperand(0),
4109 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
4112 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
4113 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4114 return DAG.getUNDEF(WidenVT);
4117 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
4118 EVT VT = N->getValueType(0);
4121 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4122 unsigned NumElts = VT.getVectorNumElements();
4123 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4125 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
4126 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
4128 // Adjust mask based on new input vector length.
4129 SmallVector<int, 16> NewMask;
4130 for (unsigned i = 0; i != NumElts; ++i) {
4131 int Idx = N->getMaskElt(i);
4132 if (Idx < (int)NumElts)
4133 NewMask.push_back(Idx);
4135 NewMask.push_back(Idx - NumElts + WidenNumElts);
4137 for (unsigned i = NumElts; i != WidenNumElts; ++i)
4138 NewMask.push_back(-1);
4139 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
4142 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
4143 assert(N->getValueType(0).isVector() &&
4144 N->getOperand(0).getValueType().isVector() &&
4145 "Operands must be vectors");
4146 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4147 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4149 SDValue InOp1 = N->getOperand(0);
4150 EVT InVT = InOp1.getValueType();
4151 assert(InVT.isVector() && "can not widen non-vector type");
4152 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
4153 InVT.getVectorElementType(), WidenNumElts);
4155 // The input and output types often differ here, and it could be that while
4156 // we'd prefer to widen the result type, the input operands have been split.
4157 // In this case, we also need to split the result of this node as well.
4158 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
4159 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
4160 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
4164 // If the inputs also widen, handle them directly. Otherwise widen by hand.
4165 SDValue InOp2 = N->getOperand(1);
4166 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
4167 InOp1 = GetWidenedVector(InOp1);
4168 InOp2 = GetWidenedVector(InOp2);
4170 InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
4171 InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
4174 // Assume that the input and output will be widen appropriately. If not,
4175 // we will have to unroll it at some point.
4176 assert(InOp1.getValueType() == WidenInVT &&
4177 InOp2.getValueType() == WidenInVT &&
4178 "Input not widened to expected type!");
4180 return DAG.getNode(ISD::SETCC, SDLoc(N),
4181 WidenVT, InOp1, InOp2, N->getOperand(2));
4184 SDValue DAGTypeLegalizer::WidenVecRes_STRICT_FSETCC(SDNode *N) {
4185 assert(N->getValueType(0).isVector() &&
4186 N->getOperand(1).getValueType().isVector() &&
4187 "Operands must be vectors");
4188 EVT VT = N->getValueType(0);
4189 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4190 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4191 unsigned NumElts = VT.getVectorNumElements();
4192 EVT EltVT = VT.getVectorElementType();
4195 SDValue Chain = N->getOperand(0);
4196 SDValue LHS = N->getOperand(1);
4197 SDValue RHS = N->getOperand(2);
4198 SDValue CC = N->getOperand(3);
4199 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
4201 // Fully unroll and reassemble.
4202 SmallVector<SDValue, 8> Scalars(WidenNumElts, DAG.getUNDEF(EltVT));
4203 SmallVector<SDValue, 8> Chains(NumElts);
4204 for (unsigned i = 0; i != NumElts; ++i) {
4205 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
4206 DAG.getVectorIdxConstant(i, dl));
4207 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
4208 DAG.getVectorIdxConstant(i, dl));
4210 Scalars[i] = DAG.getNode(N->getOpcode(), dl, {MVT::i1, MVT::Other},
4211 {Chain, LHSElem, RHSElem, CC});
4212 Chains[i] = Scalars[i].getValue(1);
4213 Scalars[i] = DAG.getSelect(dl, EltVT, Scalars[i],
4214 DAG.getBoolConstant(true, dl, EltVT, VT),
4215 DAG.getBoolConstant(false, dl, EltVT, VT));
4218 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
4219 ReplaceValueWith(SDValue(N, 1), NewChain);
4221 return DAG.getBuildVector(WidenVT, dl, Scalars);
4224 //===----------------------------------------------------------------------===//
4225 // Widen Vector Operand
4226 //===----------------------------------------------------------------------===//
4227 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
4228 LLVM_DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; N->dump(&DAG);
4230 SDValue Res = SDValue();
4232 // See if the target wants to custom widen this node.
4233 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
4236 switch (N->getOpcode()) {
4239 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
4243 llvm_unreachable("Do not know how to widen this operator's operand!");
4245 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
4246 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
4247 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
4248 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
4249 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
4250 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
4251 case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break;
4252 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
4253 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
4254 case ISD::STRICT_FSETCC:
4255 case ISD::STRICT_FSETCCS: Res = WidenVecOp_STRICT_FSETCC(N); break;
4256 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break;
4257 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
4259 case ISD::ANY_EXTEND:
4260 case ISD::SIGN_EXTEND:
4261 case ISD::ZERO_EXTEND:
4262 Res = WidenVecOp_EXTEND(N);
4265 case ISD::FP_EXTEND:
4266 case ISD::STRICT_FP_EXTEND:
4268 case ISD::STRICT_FP_ROUND:
4269 case ISD::FP_TO_SINT:
4270 case ISD::STRICT_FP_TO_SINT:
4271 case ISD::FP_TO_UINT:
4272 case ISD::STRICT_FP_TO_UINT:
4273 case ISD::SINT_TO_FP:
4274 case ISD::STRICT_SINT_TO_FP:
4275 case ISD::UINT_TO_FP:
4276 case ISD::STRICT_UINT_TO_FP:
4278 Res = WidenVecOp_Convert(N);
4281 case ISD::VECREDUCE_FADD:
4282 case ISD::VECREDUCE_FMUL:
4283 case ISD::VECREDUCE_ADD:
4284 case ISD::VECREDUCE_MUL:
4285 case ISD::VECREDUCE_AND:
4286 case ISD::VECREDUCE_OR:
4287 case ISD::VECREDUCE_XOR:
4288 case ISD::VECREDUCE_SMAX:
4289 case ISD::VECREDUCE_SMIN:
4290 case ISD::VECREDUCE_UMAX:
4291 case ISD::VECREDUCE_UMIN:
4292 case ISD::VECREDUCE_FMAX:
4293 case ISD::VECREDUCE_FMIN:
4294 Res = WidenVecOp_VECREDUCE(N);
4298 // If Res is null, the sub-method took care of registering the result.
4299 if (!Res.getNode()) return false;
4301 // If the result is N, the sub-method updated N in place. Tell the legalizer
4303 if (Res.getNode() == N)
4307 if (N->isStrictFPOpcode())
4308 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 2 &&
4309 "Invalid operand expansion");
4311 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
4312 "Invalid operand expansion");
4314 ReplaceValueWith(SDValue(N, 0), Res);
4318 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
4320 EVT VT = N->getValueType(0);
4322 SDValue InOp = N->getOperand(0);
4323 assert(getTypeAction(InOp.getValueType()) ==
4324 TargetLowering::TypeWidenVector &&
4325 "Unexpected type action");
4326 InOp = GetWidenedVector(InOp);
4327 assert(VT.getVectorNumElements() <
4328 InOp.getValueType().getVectorNumElements() &&
4329 "Input wasn't widened!");
4331 // We may need to further widen the operand until it has the same total
4332 // vector size as the result.
4333 EVT InVT = InOp.getValueType();
4334 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
4335 EVT InEltVT = InVT.getVectorElementType();
4336 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
4337 EVT FixedVT = (MVT::SimpleValueType)i;
4338 EVT FixedEltVT = FixedVT.getVectorElementType();
4339 if (TLI.isTypeLegal(FixedVT) &&
4340 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
4341 FixedEltVT == InEltVT) {
4342 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
4343 "Not enough elements in the fixed type for the operand!");
4344 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
4345 "We can't have the same type as we started with!");
4346 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
4347 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
4348 DAG.getUNDEF(FixedVT), InOp,
4349 DAG.getVectorIdxConstant(0, DL));
4351 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
4352 DAG.getVectorIdxConstant(0, DL));
4356 InVT = InOp.getValueType();
4357 if (InVT.getSizeInBits() != VT.getSizeInBits())
4358 // We couldn't find a legal vector type that was a widening of the input
4359 // and could be extended in-register to the result type, so we have to
4361 return WidenVecOp_Convert(N);
4364 // Use special DAG nodes to represent the operation of extending the
4366 switch (N->getOpcode()) {
4368 llvm_unreachable("Extend legalization on extend operation!");
4369 case ISD::ANY_EXTEND:
4370 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp);
4371 case ISD::SIGN_EXTEND:
4372 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp);
4373 case ISD::ZERO_EXTEND:
4374 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp);
4378 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
4379 // The result (and first input) is legal, but the second input is illegal.
4380 // We can't do much to fix that, so just unroll and let the extracts off of
4381 // the second input be widened as needed later.
4382 return DAG.UnrollVectorOp(N);
4385 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
4386 // Since the result is legal and the input is illegal.
4387 EVT VT = N->getValueType(0);
4388 EVT EltVT = VT.getVectorElementType();
4390 unsigned NumElts = VT.getVectorNumElements();
4391 SDValue InOp = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
4392 assert(getTypeAction(InOp.getValueType()) ==
4393 TargetLowering::TypeWidenVector &&
4394 "Unexpected type action");
4395 InOp = GetWidenedVector(InOp);
4396 EVT InVT = InOp.getValueType();
4397 unsigned Opcode = N->getOpcode();
4399 // See if a widened result type would be legal, if so widen the node.
4400 // FIXME: This isn't safe for StrictFP. Other optimization here is needed.
4401 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4402 InVT.getVectorNumElements());
4403 if (TLI.isTypeLegal(WideVT) && !N->isStrictFPOpcode()) {
4405 if (N->isStrictFPOpcode()) {
4406 if (Opcode == ISD::STRICT_FP_ROUND)
4407 Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
4408 { N->getOperand(0), InOp, N->getOperand(2) });
4410 Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
4411 { N->getOperand(0), InOp });
4412 // Legalize the chain result - switch anything that used the old chain to
4414 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
4416 if (Opcode == ISD::FP_ROUND)
4417 Res = DAG.getNode(Opcode, dl, WideVT, InOp, N->getOperand(1));
4419 Res = DAG.getNode(Opcode, dl, WideVT, InOp);
4421 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
4422 DAG.getVectorIdxConstant(0, dl));
4425 EVT InEltVT = InVT.getVectorElementType();
4427 // Unroll the convert into some scalar code and create a nasty build vector.
4428 SmallVector<SDValue, 16> Ops(NumElts);
4429 if (N->isStrictFPOpcode()) {
4430 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
4431 SmallVector<SDValue, 32> OpChains;
4432 for (unsigned i=0; i < NumElts; ++i) {
4433 NewOps[1] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
4434 DAG.getVectorIdxConstant(i, dl));
4435 Ops[i] = DAG.getNode(Opcode, dl, { EltVT, MVT::Other }, NewOps);
4436 OpChains.push_back(Ops[i].getValue(1));
4438 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
4439 ReplaceValueWith(SDValue(N, 1), NewChain);
4441 for (unsigned i = 0; i < NumElts; ++i)
4442 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
4443 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT,
4444 InOp, DAG.getVectorIdxConstant(i, dl)));
4447 return DAG.getBuildVector(VT, dl, Ops);
4450 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
4451 EVT VT = N->getValueType(0);
4452 SDValue InOp = GetWidenedVector(N->getOperand(0));
4453 EVT InWidenVT = InOp.getValueType();
4456 // Check if we can convert between two legal vector types and extract.
4457 unsigned InWidenSize = InWidenVT.getSizeInBits();
4458 unsigned Size = VT.getSizeInBits();
4459 // x86mmx is not an acceptable vector element type, so don't try.
4460 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
4461 unsigned NewNumElts = InWidenSize / Size;
4462 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
4463 if (TLI.isTypeLegal(NewVT)) {
4464 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
4465 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
4466 DAG.getVectorIdxConstant(0, dl));
4470 // Handle a case like bitcast v12i8 -> v3i32. Normally that would get widened
4471 // to v16i8 -> v4i32, but for a target where v3i32 is legal but v12i8 is not,
4472 // we end up here. Handling the case here with EXTRACT_SUBVECTOR avoids
4473 // having to copy via memory.
4474 if (VT.isVector()) {
4475 EVT EltVT = VT.getVectorElementType();
4476 unsigned EltSize = EltVT.getSizeInBits();
4477 if (InWidenSize % EltSize == 0) {
4478 unsigned NewNumElts = InWidenSize / EltSize;
4479 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NewNumElts);
4480 if (TLI.isTypeLegal(NewVT)) {
4481 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
4482 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, BitOp,
4483 DAG.getVectorIdxConstant(0, dl));
4488 return CreateStackStoreLoad(InOp, VT);
4491 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
4492 EVT VT = N->getValueType(0);
4493 EVT EltVT = VT.getVectorElementType();
4494 EVT InVT = N->getOperand(0).getValueType();
4497 // If the widen width for this operand is the same as the width of the concat
4498 // and all but the first operand is undef, just use the widened operand.
4499 unsigned NumOperands = N->getNumOperands();
4500 if (VT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
4502 for (i = 1; i < NumOperands; ++i)
4503 if (!N->getOperand(i).isUndef())
4506 if (i == NumOperands)
4507 return GetWidenedVector(N->getOperand(0));
4510 // Otherwise, fall back to a nasty build vector.
4511 unsigned NumElts = VT.getVectorNumElements();
4512 SmallVector<SDValue, 16> Ops(NumElts);
4514 unsigned NumInElts = InVT.getVectorNumElements();
4517 for (unsigned i=0; i < NumOperands; ++i) {
4518 SDValue InOp = N->getOperand(i);
4519 assert(getTypeAction(InOp.getValueType()) ==
4520 TargetLowering::TypeWidenVector &&
4521 "Unexpected type action");
4522 InOp = GetWidenedVector(InOp);
4523 for (unsigned j = 0; j < NumInElts; ++j)
4524 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4525 DAG.getVectorIdxConstant(j, dl));
4527 return DAG.getBuildVector(VT, dl, Ops);
4530 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
4531 SDValue InOp = GetWidenedVector(N->getOperand(0));
4532 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
4533 N->getValueType(0), InOp, N->getOperand(1));
4536 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4537 SDValue InOp = GetWidenedVector(N->getOperand(0));
4538 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4539 N->getValueType(0), InOp, N->getOperand(1));
4542 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
4543 // We have to widen the value, but we want only to store the original
4545 StoreSDNode *ST = cast<StoreSDNode>(N);
4547 if (!ST->getMemoryVT().getScalarType().isByteSized())
4548 return TLI.scalarizeVectorStore(ST, DAG);
4550 SmallVector<SDValue, 16> StChain;
4551 if (ST->isTruncatingStore())
4552 GenWidenVectorTruncStores(StChain, ST);
4554 GenWidenVectorStores(StChain, ST);
4556 if (StChain.size() == 1)
4559 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
4562 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
4563 assert((OpNo == 1 || OpNo == 3) &&
4564 "Can widen only data or mask operand of mstore");
4565 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
4566 SDValue Mask = MST->getMask();
4567 EVT MaskVT = Mask.getValueType();
4568 SDValue StVal = MST->getValue();
4573 StVal = GetWidenedVector(StVal);
4575 // The mask should be widened as well.
4576 EVT WideVT = StVal.getValueType();
4577 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
4578 MaskVT.getVectorElementType(),
4579 WideVT.getVectorNumElements());
4580 Mask = ModifyToType(Mask, WideMaskVT, true);
4583 EVT WideMaskVT = TLI.getTypeToTransformTo(*DAG.getContext(), MaskVT);
4584 Mask = ModifyToType(Mask, WideMaskVT, true);
4586 EVT ValueVT = StVal.getValueType();
4587 EVT WideVT = EVT::getVectorVT(*DAG.getContext(),
4588 ValueVT.getVectorElementType(),
4589 WideMaskVT.getVectorNumElements());
4590 StVal = ModifyToType(StVal, WideVT);
4593 assert(Mask.getValueType().getVectorNumElements() ==
4594 StVal.getValueType().getVectorNumElements() &&
4595 "Mask and data vectors should have the same number of elements");
4596 return DAG.getMaskedStore(MST->getChain(), dl, StVal, MST->getBasePtr(),
4597 MST->getOffset(), Mask, MST->getMemoryVT(),
4598 MST->getMemOperand(), MST->getAddressingMode(),
4599 false, MST->isCompressingStore());
4602 SDValue DAGTypeLegalizer::WidenVecOp_MGATHER(SDNode *N, unsigned OpNo) {
4603 assert(OpNo == 4 && "Can widen only the index of mgather");
4604 auto *MG = cast<MaskedGatherSDNode>(N);
4605 SDValue DataOp = MG->getPassThru();
4606 SDValue Mask = MG->getMask();
4607 SDValue Scale = MG->getScale();
4609 // Just widen the index. It's allowed to have extra elements.
4610 SDValue Index = GetWidenedVector(MG->getIndex());
4613 SDValue Ops[] = {MG->getChain(), DataOp, Mask, MG->getBasePtr(), Index,
4615 SDValue Res = DAG.getMaskedGather(MG->getVTList(), MG->getMemoryVT(), dl, Ops,
4616 MG->getMemOperand(), MG->getIndexType());
4617 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
4618 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
4622 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
4623 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
4624 SDValue DataOp = MSC->getValue();
4625 SDValue Mask = MSC->getMask();
4626 SDValue Index = MSC->getIndex();
4627 SDValue Scale = MSC->getScale();
4630 DataOp = GetWidenedVector(DataOp);
4631 unsigned NumElts = DataOp.getValueType().getVectorNumElements();
4634 EVT IndexVT = Index.getValueType();
4635 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
4636 IndexVT.getVectorElementType(), NumElts);
4637 Index = ModifyToType(Index, WideIndexVT);
4639 // The mask should be widened as well.
4640 EVT MaskVT = Mask.getValueType();
4641 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
4642 MaskVT.getVectorElementType(), NumElts);
4643 Mask = ModifyToType(Mask, WideMaskVT, true);
4644 } else if (OpNo == 4) {
4645 // Just widen the index. It's allowed to have extra elements.
4646 Index = GetWidenedVector(Index);
4648 llvm_unreachable("Can't widen this operand of mscatter");
4650 SDValue Ops[] = {MSC->getChain(), DataOp, Mask, MSC->getBasePtr(), Index,
4652 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
4653 MSC->getMemoryVT(), SDLoc(N), Ops,
4654 MSC->getMemOperand(), MSC->getIndexType());
4657 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
4658 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
4659 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
4661 EVT VT = N->getValueType(0);
4663 // WARNING: In this code we widen the compare instruction with garbage.
4664 // This garbage may contain denormal floats which may be slow. Is this a real
4665 // concern ? Should we zero the unused lanes if this is a float compare ?
4667 // Get a new SETCC node to compare the newly widened operands.
4668 // Only some of the compared elements are legal.
4669 EVT SVT = getSetCCResultType(InOp0.getValueType());
4670 // The result type is legal, if its vXi1, keep vXi1 for the new SETCC.
4671 if (VT.getScalarType() == MVT::i1)
4672 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
4673 SVT.getVectorNumElements());
4675 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
4676 SVT, InOp0, InOp1, N->getOperand(2));
4678 // Extract the needed results from the result vector.
4679 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
4680 SVT.getVectorElementType(),
4681 VT.getVectorNumElements());
4682 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
4683 DAG.getVectorIdxConstant(0, dl));
4685 EVT OpVT = N->getOperand(0).getValueType();
4686 ISD::NodeType ExtendCode =
4687 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
4688 return DAG.getNode(ExtendCode, dl, VT, CC);
4691 SDValue DAGTypeLegalizer::WidenVecOp_STRICT_FSETCC(SDNode *N) {
4692 SDValue Chain = N->getOperand(0);
4693 SDValue LHS = GetWidenedVector(N->getOperand(1));
4694 SDValue RHS = GetWidenedVector(N->getOperand(2));
4695 SDValue CC = N->getOperand(3);
4698 EVT VT = N->getValueType(0);
4699 EVT EltVT = VT.getVectorElementType();
4700 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
4701 unsigned NumElts = VT.getVectorNumElements();
4703 // Unroll into a build vector.
4704 SmallVector<SDValue, 8> Scalars(NumElts);
4705 SmallVector<SDValue, 8> Chains(NumElts);
4707 for (unsigned i = 0; i != NumElts; ++i) {
4708 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
4709 DAG.getVectorIdxConstant(i, dl));
4710 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
4711 DAG.getVectorIdxConstant(i, dl));
4713 Scalars[i] = DAG.getNode(N->getOpcode(), dl, {MVT::i1, MVT::Other},
4714 {Chain, LHSElem, RHSElem, CC});
4715 Chains[i] = Scalars[i].getValue(1);
4716 Scalars[i] = DAG.getSelect(dl, EltVT, Scalars[i],
4717 DAG.getBoolConstant(true, dl, EltVT, VT),
4718 DAG.getBoolConstant(false, dl, EltVT, VT));
4721 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
4722 ReplaceValueWith(SDValue(N, 1), NewChain);
4724 return DAG.getBuildVector(VT, dl, Scalars);
4727 SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE(SDNode *N) {
4729 SDValue Op = GetWidenedVector(N->getOperand(0));
4730 EVT OrigVT = N->getOperand(0).getValueType();
4731 EVT WideVT = Op.getValueType();
4732 EVT ElemVT = OrigVT.getVectorElementType();
4734 SDValue NeutralElem;
4735 switch (N->getOpcode()) {
4736 case ISD::VECREDUCE_ADD:
4737 case ISD::VECREDUCE_OR:
4738 case ISD::VECREDUCE_XOR:
4739 case ISD::VECREDUCE_UMAX:
4740 NeutralElem = DAG.getConstant(0, dl, ElemVT);
4742 case ISD::VECREDUCE_MUL:
4743 NeutralElem = DAG.getConstant(1, dl, ElemVT);
4745 case ISD::VECREDUCE_AND:
4746 case ISD::VECREDUCE_UMIN:
4747 NeutralElem = DAG.getAllOnesConstant(dl, ElemVT);
4749 case ISD::VECREDUCE_SMAX:
4750 NeutralElem = DAG.getConstant(
4751 APInt::getSignedMinValue(ElemVT.getSizeInBits()), dl, ElemVT);
4753 case ISD::VECREDUCE_SMIN:
4754 NeutralElem = DAG.getConstant(
4755 APInt::getSignedMaxValue(ElemVT.getSizeInBits()), dl, ElemVT);
4757 case ISD::VECREDUCE_FADD:
4758 NeutralElem = DAG.getConstantFP(0.0, dl, ElemVT);
4760 case ISD::VECREDUCE_FMUL:
4761 NeutralElem = DAG.getConstantFP(1.0, dl, ElemVT);
4763 case ISD::VECREDUCE_FMAX:
4764 NeutralElem = DAG.getConstantFP(
4765 -std::numeric_limits<double>::infinity(), dl, ElemVT);
4767 case ISD::VECREDUCE_FMIN:
4768 NeutralElem = DAG.getConstantFP(
4769 std::numeric_limits<double>::infinity(), dl, ElemVT);
4773 // Pad the vector with the neutral element.
4774 unsigned OrigElts = OrigVT.getVectorNumElements();
4775 unsigned WideElts = WideVT.getVectorNumElements();
4776 for (unsigned Idx = OrigElts; Idx < WideElts; Idx++)
4777 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem,
4778 DAG.getVectorIdxConstant(Idx, dl));
4780 return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Op, N->getFlags());
4783 SDValue DAGTypeLegalizer::WidenVecOp_VSELECT(SDNode *N) {
4784 // This only gets called in the case that the left and right inputs and
4785 // result are of a legal odd vector type, and the condition is illegal i1 of
4786 // the same odd width that needs widening.
4787 EVT VT = N->getValueType(0);
4788 assert(VT.isVector() && !VT.isPow2VectorType() && isTypeLegal(VT));
4790 SDValue Cond = GetWidenedVector(N->getOperand(0));
4791 SDValue LeftIn = DAG.WidenVector(N->getOperand(1), SDLoc(N));
4792 SDValue RightIn = DAG.WidenVector(N->getOperand(2), SDLoc(N));
4795 SDValue Select = DAG.getNode(N->getOpcode(), DL, LeftIn.getValueType(), Cond,
4797 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Select,
4798 DAG.getVectorIdxConstant(0, DL));
4801 //===----------------------------------------------------------------------===//
4802 // Vector Widening Utilities
4803 //===----------------------------------------------------------------------===//
4805 // Utility function to find the type to chop up a widen vector for load/store
4806 // TLI: Target lowering used to determine legal types.
4807 // Width: Width left need to load/store.
4808 // WidenVT: The widen vector type to load to/store from
4809 // Align: If 0, don't allow use of a wider type
4810 // WidenEx: If Align is not 0, the amount additional we can load/store from.
4812 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
4813 unsigned Width, EVT WidenVT,
4814 unsigned Align = 0, unsigned WidenEx = 0) {
4815 EVT WidenEltVT = WidenVT.getVectorElementType();
4816 const bool Scalable = WidenVT.isScalableVector();
4817 unsigned WidenWidth = WidenVT.getSizeInBits().getKnownMinSize();
4818 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
4819 unsigned AlignInBits = Align*8;
4821 // If we have one element to load/store, return it.
4822 EVT RetVT = WidenEltVT;
4823 if (Width == WidenEltWidth)
4826 // See if there is larger legal integer than the element type to load/store.
4828 // Don't bother looking for an integer type if the vector is scalable, skip
4831 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
4832 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
4833 EVT MemVT((MVT::SimpleValueType) VT);
4834 unsigned MemVTWidth = MemVT.getSizeInBits();
4835 if (MemVT.getSizeInBits() <= WidenEltWidth)
4837 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
4838 if ((Action == TargetLowering::TypeLegal ||
4839 Action == TargetLowering::TypePromoteInteger) &&
4840 (WidenWidth % MemVTWidth) == 0 &&
4841 isPowerOf2_32(WidenWidth / MemVTWidth) &&
4842 (MemVTWidth <= Width ||
4843 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4844 if (MemVTWidth == WidenWidth)
4852 // See if there is a larger vector type to load/store that has the same vector
4853 // element type and is evenly divisible with the WidenVT.
4854 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
4855 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
4856 EVT MemVT = (MVT::SimpleValueType) VT;
4857 // Skip vector MVTs which don't match the scalable property of WidenVT.
4858 if (Scalable != MemVT.isScalableVector())
4860 unsigned MemVTWidth = MemVT.getSizeInBits().getKnownMinSize();
4861 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
4862 if ((Action == TargetLowering::TypeLegal ||
4863 Action == TargetLowering::TypePromoteInteger) &&
4864 WidenEltVT == MemVT.getVectorElementType() &&
4865 (WidenWidth % MemVTWidth) == 0 &&
4866 isPowerOf2_32(WidenWidth / MemVTWidth) &&
4867 (MemVTWidth <= Width ||
4868 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4869 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
4877 // Builds a vector type from scalar loads
4878 // VecTy: Resulting Vector type
4879 // LDOps: Load operators to build a vector type
4880 // [Start,End) the list of loads to use.
4881 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
4882 SmallVectorImpl<SDValue> &LdOps,
4883 unsigned Start, unsigned End) {
4884 SDLoc dl(LdOps[Start]);
4885 EVT LdTy = LdOps[Start].getValueType();
4886 unsigned Width = VecTy.getSizeInBits();
4887 unsigned NumElts = Width / LdTy.getSizeInBits();
4888 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
4891 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
4893 for (unsigned i = Start + 1; i != End; ++i) {
4894 EVT NewLdTy = LdOps[i].getValueType();
4895 if (NewLdTy != LdTy) {
4896 NumElts = Width / NewLdTy.getSizeInBits();
4897 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
4898 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
4899 // Readjust position and vector position based on new load type.
4900 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
4903 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
4904 DAG.getVectorIdxConstant(Idx++, dl));
4906 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
4909 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
4911 // The strategy assumes that we can efficiently load power-of-two widths.
4912 // The routine chops the vector into the largest vector loads with the same
4913 // element type or scalar loads and then recombines it to the widen vector
4915 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
4916 unsigned WidenWidth = WidenVT.getSizeInBits();
4917 EVT LdVT = LD->getMemoryVT();
4919 assert(LdVT.isVector() && WidenVT.isVector());
4920 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
4923 SDValue Chain = LD->getChain();
4924 SDValue BasePtr = LD->getBasePtr();
4925 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4926 AAMDNodes AAInfo = LD->getAAInfo();
4928 int LdWidth = LdVT.getSizeInBits();
4929 int WidthDiff = WidenWidth - LdWidth;
4930 // Allow wider loads if they are sufficiently aligned to avoid memory faults
4931 // and if the original load is simple.
4932 unsigned LdAlign = (!LD->isSimple()) ? 0 : LD->getAlignment();
4934 // Find the vector type that can load from.
4935 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4936 int NewVTWidth = NewVT.getSizeInBits();
4937 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
4938 LD->getOriginalAlign(), MMOFlags, AAInfo);
4939 LdChain.push_back(LdOp.getValue(1));
4941 // Check if we can load the element with one instruction.
4942 if (LdWidth <= NewVTWidth) {
4943 if (!NewVT.isVector()) {
4944 unsigned NumElts = WidenWidth / NewVTWidth;
4945 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4946 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
4947 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
4949 if (NewVT == WidenVT)
4952 assert(WidenWidth % NewVTWidth == 0);
4953 unsigned NumConcat = WidenWidth / NewVTWidth;
4954 SmallVector<SDValue, 16> ConcatOps(NumConcat);
4955 SDValue UndefVal = DAG.getUNDEF(NewVT);
4956 ConcatOps[0] = LdOp;
4957 for (unsigned i = 1; i != NumConcat; ++i)
4958 ConcatOps[i] = UndefVal;
4959 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
4962 // Load vector by using multiple loads from largest vector to scalar.
4963 SmallVector<SDValue, 16> LdOps;
4964 LdOps.push_back(LdOp);
4966 LdWidth -= NewVTWidth;
4967 unsigned Offset = 0;
4969 while (LdWidth > 0) {
4970 unsigned Increment = NewVTWidth / 8;
4971 Offset += Increment;
4972 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4975 if (LdWidth < NewVTWidth) {
4976 // The current type we are using is too large. Find a better size.
4977 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4978 NewVTWidth = NewVT.getSizeInBits();
4979 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4980 LD->getPointerInfo().getWithOffset(Offset),
4981 LD->getOriginalAlign(), MMOFlags, AAInfo);
4982 LdChain.push_back(L.getValue(1));
4984 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4985 LD->getPointerInfo().getWithOffset(Offset),
4986 LD->getOriginalAlign(), MMOFlags, AAInfo);
4987 LdChain.push_back(L.getValue(1));
4993 LdWidth -= NewVTWidth;
4996 // Build the vector from the load operations.
4997 unsigned End = LdOps.size();
4998 if (!LdOps[0].getValueType().isVector())
4999 // All the loads are scalar loads.
5000 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
5002 // If the load contains vectors, build the vector using concat vector.
5003 // All of the vectors used to load are power-of-2, and the scalar loads can be
5004 // combined to make a power-of-2 vector.
5005 SmallVector<SDValue, 16> ConcatOps(End);
5008 EVT LdTy = LdOps[i].getValueType();
5009 // First, combine the scalar loads to a vector.
5010 if (!LdTy.isVector()) {
5011 for (--i; i >= 0; --i) {
5012 LdTy = LdOps[i].getValueType();
5013 if (LdTy.isVector())
5016 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
5018 ConcatOps[--Idx] = LdOps[i];
5019 for (--i; i >= 0; --i) {
5020 EVT NewLdTy = LdOps[i].getValueType();
5021 if (NewLdTy != LdTy) {
5022 // Create a larger vector.
5023 unsigned NumOps = NewLdTy.getSizeInBits() / LdTy.getSizeInBits();
5024 assert(NewLdTy.getSizeInBits() % LdTy.getSizeInBits() == 0);
5025 SmallVector<SDValue, 16> WidenOps(NumOps);
5027 for (; j != End-Idx; ++j)
5028 WidenOps[j] = ConcatOps[Idx+j];
5029 for (; j != NumOps; ++j)
5030 WidenOps[j] = DAG.getUNDEF(LdTy);
5032 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
5037 ConcatOps[--Idx] = LdOps[i];
5040 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
5041 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
5042 makeArrayRef(&ConcatOps[Idx], End - Idx));
5044 // We need to fill the rest with undefs to build the vector.
5045 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
5046 SmallVector<SDValue, 16> WidenOps(NumOps);
5047 SDValue UndefVal = DAG.getUNDEF(LdTy);
5050 for (; i != End-Idx; ++i)
5051 WidenOps[i] = ConcatOps[Idx+i];
5052 for (; i != NumOps; ++i)
5053 WidenOps[i] = UndefVal;
5055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
5059 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
5061 ISD::LoadExtType ExtType) {
5062 // For extension loads, it may not be more efficient to chop up the vector
5063 // and then extend it. Instead, we unroll the load and build a new vector.
5064 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
5065 EVT LdVT = LD->getMemoryVT();
5067 assert(LdVT.isVector() && WidenVT.isVector());
5070 SDValue Chain = LD->getChain();
5071 SDValue BasePtr = LD->getBasePtr();
5072 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
5073 AAMDNodes AAInfo = LD->getAAInfo();
5075 EVT EltVT = WidenVT.getVectorElementType();
5076 EVT LdEltVT = LdVT.getVectorElementType();
5077 unsigned NumElts = LdVT.getVectorNumElements();
5079 // Load each element and widen.
5080 unsigned WidenNumElts = WidenVT.getVectorNumElements();
5081 SmallVector<SDValue, 16> Ops(WidenNumElts);
5082 unsigned Increment = LdEltVT.getSizeInBits() / 8;
5084 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
5085 LdEltVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
5086 LdChain.push_back(Ops[0].getValue(1));
5087 unsigned i = 0, Offset = Increment;
5088 for (i=1; i < NumElts; ++i, Offset += Increment) {
5089 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
5090 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
5091 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
5092 LD->getOriginalAlign(), MMOFlags, AAInfo);
5093 LdChain.push_back(Ops[i].getValue(1));
5096 // Fill the rest with undefs.
5097 SDValue UndefVal = DAG.getUNDEF(EltVT);
5098 for (; i != WidenNumElts; ++i)
5101 return DAG.getBuildVector(WidenVT, dl, Ops);
5104 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
5106 // The strategy assumes that we can efficiently store power-of-two widths.
5107 // The routine chops the vector into the largest vector stores with the same
5108 // element type or scalar stores.
5109 SDValue Chain = ST->getChain();
5110 SDValue BasePtr = ST->getBasePtr();
5111 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
5112 AAMDNodes AAInfo = ST->getAAInfo();
5113 SDValue ValOp = GetWidenedVector(ST->getValue());
5116 EVT StVT = ST->getMemoryVT();
5117 unsigned StWidth = StVT.getSizeInBits();
5118 EVT ValVT = ValOp.getValueType();
5119 unsigned ValWidth = ValVT.getSizeInBits();
5120 EVT ValEltVT = ValVT.getVectorElementType();
5121 unsigned ValEltWidth = ValEltVT.getSizeInBits();
5122 assert(StVT.getVectorElementType() == ValEltVT);
5124 int Idx = 0; // current index to store
5125 unsigned Offset = 0; // offset from base to store
5126 while (StWidth != 0) {
5127 // Find the largest vector type we can store with.
5128 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
5129 unsigned NewVTWidth = NewVT.getSizeInBits();
5130 unsigned Increment = NewVTWidth / 8;
5131 if (NewVT.isVector()) {
5132 unsigned NumVTElts = NewVT.getVectorNumElements();
5134 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
5135 DAG.getVectorIdxConstant(Idx, dl));
5136 StChain.push_back(DAG.getStore(
5137 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
5138 ST->getOriginalAlign(), MMOFlags, AAInfo));
5139 StWidth -= NewVTWidth;
5140 Offset += Increment;
5143 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
5144 } while (StWidth != 0 && StWidth >= NewVTWidth);
5146 // Cast the vector to the scalar type we can store.
5147 unsigned NumElts = ValWidth / NewVTWidth;
5148 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
5149 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
5150 // Readjust index position based on new vector type.
5151 Idx = Idx * ValEltWidth / NewVTWidth;
5153 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
5154 DAG.getVectorIdxConstant(Idx++, dl));
5155 StChain.push_back(DAG.getStore(
5156 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
5157 ST->getOriginalAlign(), MMOFlags, AAInfo));
5158 StWidth -= NewVTWidth;
5159 Offset += Increment;
5160 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
5161 } while (StWidth != 0 && StWidth >= NewVTWidth);
5162 // Restore index back to be relative to the original widen element type.
5163 Idx = Idx * NewVTWidth / ValEltWidth;
5169 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
5171 // For extension loads, it may not be more efficient to truncate the vector
5172 // and then store it. Instead, we extract each element and then store it.
5173 SDValue Chain = ST->getChain();
5174 SDValue BasePtr = ST->getBasePtr();
5175 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
5176 AAMDNodes AAInfo = ST->getAAInfo();
5177 SDValue ValOp = GetWidenedVector(ST->getValue());
5180 EVT StVT = ST->getMemoryVT();
5181 EVT ValVT = ValOp.getValueType();
5183 // It must be true that the wide vector type is bigger than where we need to
5185 assert(StVT.isVector() && ValOp.getValueType().isVector());
5186 assert(StVT.bitsLT(ValOp.getValueType()));
5188 // For truncating stores, we can not play the tricks of chopping legal vector
5189 // types and bitcast it to the right type. Instead, we unroll the store.
5190 EVT StEltVT = StVT.getVectorElementType();
5191 EVT ValEltVT = ValVT.getVectorElementType();
5192 unsigned Increment = ValEltVT.getSizeInBits() / 8;
5193 unsigned NumElts = StVT.getVectorNumElements();
5194 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
5195 DAG.getVectorIdxConstant(0, dl));
5197 DAG.getTruncStore(Chain, dl, EOp, BasePtr, ST->getPointerInfo(), StEltVT,
5198 ST->getOriginalAlign(), MMOFlags, AAInfo));
5199 unsigned Offset = Increment;
5200 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
5201 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
5202 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
5203 DAG.getVectorIdxConstant(0, dl));
5204 StChain.push_back(DAG.getTruncStore(
5205 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
5206 StEltVT, ST->getOriginalAlign(), MMOFlags, AAInfo));
5210 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
5211 /// input vector must have the same element type as NVT.
5212 /// FillWithZeroes specifies that the vector should be widened with zeroes.
5213 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
5214 bool FillWithZeroes) {
5215 // Note that InOp might have been widened so it might already have
5216 // the right width or it might need be narrowed.
5217 EVT InVT = InOp.getValueType();
5218 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
5219 "input and widen element type must match");
5222 // Check if InOp already has the right width.
5226 unsigned InNumElts = InVT.getVectorNumElements();
5227 unsigned WidenNumElts = NVT.getVectorNumElements();
5228 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
5229 unsigned NumConcat = WidenNumElts / InNumElts;
5230 SmallVector<SDValue, 16> Ops(NumConcat);
5231 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
5234 for (unsigned i = 1; i != NumConcat; ++i)
5237 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
5240 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
5241 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
5242 DAG.getVectorIdxConstant(0, dl));
5244 // Fall back to extract and build.
5245 SmallVector<SDValue, 16> Ops(WidenNumElts);
5246 EVT EltVT = NVT.getVectorElementType();
5247 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
5249 for (Idx = 0; Idx < MinNumElts; ++Idx)
5250 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
5251 DAG.getVectorIdxConstant(Idx, dl));
5253 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
5254 DAG.getUNDEF(EltVT);
5255 for ( ; Idx < WidenNumElts; ++Idx)
5257 return DAG.getBuildVector(NVT, dl, Ops);