1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the AArch64 implementation of the MRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
16 #define GET_REGINFO_HEADER
17 #include "AArch64GenRegisterInfo.inc"
21 class MachineFunction;
23 class TargetRegisterClass;
26 class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
30 AArch64RegisterInfo(const Triple &TT);
32 // FIXME: This should be tablegen'd like getDwarfRegNum is
33 int getSEHRegNum(unsigned i) const {
34 return getEncodingValue(i);
37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
38 bool isAnyArgRegReserved(const MachineFunction &MF) const;
39 void emitReservedArgRegCallError(const MachineFunction &MF) const;
41 void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
42 void UpdateCustomCallPreservedMask(MachineFunction &MF,
43 const uint32_t **Mask) const;
45 static bool hasSVEArgsOrReturn(const MachineFunction *MF);
47 /// Code Generation virtual methods...
48 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
49 const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;
51 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
52 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
53 CallingConv::ID) const override;
54 const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
55 CallingConv::ID) const;
57 unsigned getCSRFirstUseCost() const override {
58 // The cost will be compared against BlockFrequency where entry has the
59 // value of 1 << 14. A value of 5 will choose to spill or split really
60 // cold path instead of using a callee-saved register.
64 const TargetRegisterClass *
65 getSubClassWithSubReg(const TargetRegisterClass *RC,
66 unsigned Idx) const override;
68 // Calls involved in thread-local variable lookup save more registers than
69 // normal calls, so they need a different mask to represent this.
70 const uint32_t *getTLSCallPreservedMask() const;
72 // Funclets on ARM64 Windows don't preserve any registers.
73 const uint32_t *getNoPreservedMask() const override;
75 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
76 /// case that 'returned' is on an i64 first argument if the calling convention
77 /// is one that can (partially) model this attribute with a preserved mask
78 /// (i.e. it is a calling convention that uses the same register for the first
79 /// i64 argument and an i64 return value)
81 /// Should return NULL in the case that the calling convention does not have
83 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
84 CallingConv::ID) const;
86 /// Stack probing calls preserve different CSRs to the normal CC.
87 const uint32_t *getWindowsStackProbePreservedMask() const;
89 BitVector getReservedRegs(const MachineFunction &MF) const override;
90 bool isAsmClobberable(const MachineFunction &MF,
91 MCRegister PhysReg) const override;
92 bool isConstantPhysReg(MCRegister PhysReg) const override;
93 const TargetRegisterClass *
94 getPointerRegClass(const MachineFunction &MF,
95 unsigned Kind = 0) const override;
96 const TargetRegisterClass *
97 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
99 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
100 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
101 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
103 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
104 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
105 int64_t Offset) const override;
106 void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg,
108 int64_t Offset) const override;
109 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
110 int64_t Offset) const override;
111 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
112 unsigned FIOperandNum,
113 RegScavenger *RS = nullptr) const override;
114 bool cannotEliminateFrame(const MachineFunction &MF) const;
116 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
117 bool hasBasePointer(const MachineFunction &MF) const;
118 unsigned getBaseRegister() const;
120 // Debug information queries.
121 Register getFrameRegister(const MachineFunction &MF) const override;
123 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
124 MachineFunction &MF) const override;
126 unsigned getLocalAddressRegister(const MachineFunction &MF) const;
127 bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
130 } // end namespace llvm