1 //=- AArch64RegisterInfo.td - Describe the AArch64 Registers -*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
13 class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],
14 list<string> altNames = []>
15 : Register<n, altNames> {
17 let Namespace = "AArch64";
18 let SubRegs = subregs;
21 let Namespace = "AArch64" in {
22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<32>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def qhisub : SubRegIndex<64>;
31 def qsub : SubRegIndex<64>;
32 def sube64 : SubRegIndex<64>;
33 def subo64 : SubRegIndex<64>;
35 def zsub : SubRegIndex<128>;
36 // Note: zsub_hi should never be used directly because it represents
37 // the scalable part of the SVE vector and cannot be manipulated as a
38 // subvector in the same way the lower 128bits can.
39 def zsub_hi : SubRegIndex<128>;
40 // Note: Code depends on these having consecutive numbers
41 def dsub0 : SubRegIndex<64>;
42 def dsub1 : SubRegIndex<64>;
43 def dsub2 : SubRegIndex<64>;
44 def dsub3 : SubRegIndex<64>;
45 // Note: Code depends on these having consecutive numbers
46 def qsub0 : SubRegIndex<128>;
47 def qsub1 : SubRegIndex<128>;
48 def qsub2 : SubRegIndex<128>;
49 def qsub3 : SubRegIndex<128>;
52 let Namespace = "AArch64" in {
53 def vreg : RegAltNameIndex;
54 def vlist1 : RegAltNameIndex;
57 //===----------------------------------------------------------------------===//
59 //===----------------------------------------------------------------------===//
60 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
61 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
62 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
63 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
64 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
65 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
66 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
67 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
68 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
69 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
70 def W10 : AArch64Reg<10, "w10">, DwarfRegNum<[10]>;
71 def W11 : AArch64Reg<11, "w11">, DwarfRegNum<[11]>;
72 def W12 : AArch64Reg<12, "w12">, DwarfRegNum<[12]>;
73 def W13 : AArch64Reg<13, "w13">, DwarfRegNum<[13]>;
74 def W14 : AArch64Reg<14, "w14">, DwarfRegNum<[14]>;
75 def W15 : AArch64Reg<15, "w15">, DwarfRegNum<[15]>;
76 def W16 : AArch64Reg<16, "w16">, DwarfRegNum<[16]>;
77 def W17 : AArch64Reg<17, "w17">, DwarfRegNum<[17]>;
78 def W18 : AArch64Reg<18, "w18">, DwarfRegNum<[18]>;
79 def W19 : AArch64Reg<19, "w19">, DwarfRegNum<[19]>;
80 def W20 : AArch64Reg<20, "w20">, DwarfRegNum<[20]>;
81 def W21 : AArch64Reg<21, "w21">, DwarfRegNum<[21]>;
82 def W22 : AArch64Reg<22, "w22">, DwarfRegNum<[22]>;
83 def W23 : AArch64Reg<23, "w23">, DwarfRegNum<[23]>;
84 def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>;
85 def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>;
86 def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>;
87 def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>;
88 def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;
89 def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;
90 def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;
91 def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
92 def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>;
94 let SubRegIndices = [sub_32] in {
95 def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>;
96 def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>;
97 def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>;
98 def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>;
99 def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>;
100 def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>;
101 def X6 : AArch64Reg<6, "x6", [W6]>, DwarfRegAlias<W6>;
102 def X7 : AArch64Reg<7, "x7", [W7]>, DwarfRegAlias<W7>;
103 def X8 : AArch64Reg<8, "x8", [W8]>, DwarfRegAlias<W8>;
104 def X9 : AArch64Reg<9, "x9", [W9]>, DwarfRegAlias<W9>;
105 def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>;
106 def X11 : AArch64Reg<11, "x11", [W11]>, DwarfRegAlias<W11>;
107 def X12 : AArch64Reg<12, "x12", [W12]>, DwarfRegAlias<W12>;
108 def X13 : AArch64Reg<13, "x13", [W13]>, DwarfRegAlias<W13>;
109 def X14 : AArch64Reg<14, "x14", [W14]>, DwarfRegAlias<W14>;
110 def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>;
111 def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>;
112 def X17 : AArch64Reg<17, "x17", [W17]>, DwarfRegAlias<W17>;
113 def X18 : AArch64Reg<18, "x18", [W18]>, DwarfRegAlias<W18>;
114 def X19 : AArch64Reg<19, "x19", [W19]>, DwarfRegAlias<W19>;
115 def X20 : AArch64Reg<20, "x20", [W20]>, DwarfRegAlias<W20>;
116 def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>;
117 def X22 : AArch64Reg<22, "x22", [W22]>, DwarfRegAlias<W22>;
118 def X23 : AArch64Reg<23, "x23", [W23]>, DwarfRegAlias<W23>;
119 def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
120 def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
121 def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
122 def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
123 def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
124 def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
125 def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
126 def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
127 def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
130 // Condition code register.
131 def NZCV : AArch64Reg<0, "nzcv">;
133 // First fault status register
134 def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
136 // Purely virtual Vector Granule (VG) Dwarf register
137 def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
139 // GPR register classes with the intersections of GPR32/GPR32sp and
140 // GPR64/GPR64sp for use by the coalescer.
141 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
142 let AltOrders = [(rotl GPR32common, 8)];
143 let AltOrderSelect = [{ return 1; }];
145 def GPR64common : RegisterClass<"AArch64", [i64], 64,
146 (add (sequence "X%u", 0, 28), FP, LR)> {
147 let AltOrders = [(rotl GPR64common, 8)];
148 let AltOrderSelect = [{ return 1; }];
150 // GPR register classes which exclude SP/WSP.
151 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
152 let AltOrders = [(rotl GPR32, 8)];
153 let AltOrderSelect = [{ return 1; }];
155 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
156 let AltOrders = [(rotl GPR64, 8)];
157 let AltOrderSelect = [{ return 1; }];
160 // GPR register classes which include SP/WSP.
161 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
162 let AltOrders = [(rotl GPR32sp, 8)];
163 let AltOrderSelect = [{ return 1; }];
165 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
166 let AltOrders = [(rotl GPR64sp, 8)];
167 let AltOrderSelect = [{ return 1; }];
170 def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
171 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
173 def GPR64spPlus0Operand : AsmOperandClass {
174 let Name = "GPR64sp0";
175 let RenderMethod = "addRegOperands";
176 let PredicateMethod = "isGPR64<AArch64::GPR64spRegClassID>";
177 let ParserMethod = "tryParseGPR64sp0Operand";
180 def GPR64sp0 : RegisterOperand<GPR64sp> {
181 let ParserMatchClass = GPR64spPlus0Operand;
184 // GPR32/GPR64 but with zero-register substitution enabled.
185 // TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all.
186 def GPR32z : RegisterOperand<GPR32> {
187 let GIZeroRegister = WZR;
189 def GPR64z : RegisterOperand<GPR64> {
190 let GIZeroRegister = XZR;
193 // GPR argument registers.
194 def GPR32arg : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 7)>;
195 def GPR64arg : RegisterClass<"AArch64", [i64], 64, (sequence "X%u", 0, 7)>;
197 // GPR register classes which include WZR/XZR AND SP/WSP. This is not a
198 // constraint used by any instructions, it is used as a common super-class.
199 def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>;
200 def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>;
202 // For tail calls, we can't use callee-saved registers, as they are restored
203 // to the saved value before the tail call, which would clobber a call address.
204 // This is for indirect tail calls to store the address of the destination.
205 def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21,
206 X22, X23, X24, X25, X26,
209 // Restricted set of tail call registers, for use when branch target
210 // enforcement is enabled. These are the only registers which can be used to
211 // indirectly branch (not call) to the "BTI c" instruction at the start of a
212 // BTI-protected function.
213 def rtcGPR64 : RegisterClass<"AArch64", [i64], 64, (add X16, X17)>;
215 // Register set that excludes registers that are reserved for procedure calls.
216 // This is used for pseudo-instructions that are actually implemented using a
218 def GPR64noip : RegisterClass<"AArch64", [i64], 64, (sub GPR64, X16, X17, LR)>;
220 // GPR register classes for post increment amount of vector load/store that
221 // has alternate printing when Rm=31 and prints a constant immediate value
222 // equal to the total number of bytes transferred.
224 // FIXME: TableGen *should* be able to do these itself now. There appears to be
225 // a bug in counting how many operands a Post-indexed MCInst should have which
226 // means the aliases don't trigger.
227 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
228 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
229 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
230 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
231 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
232 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
233 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
234 def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;
235 def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;
236 def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;
237 def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
238 def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
240 // Condition code regclass.
241 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
242 let CopyCost = -1; // Don't allow copying of status registers.
244 // CCR is not allocatable.
245 let isAllocatable = 0;
248 //===----------------------------------------------------------------------===//
249 // Floating Point Scalar Registers
250 //===----------------------------------------------------------------------===//
252 def B0 : AArch64Reg<0, "b0">, DwarfRegNum<[64]>;
253 def B1 : AArch64Reg<1, "b1">, DwarfRegNum<[65]>;
254 def B2 : AArch64Reg<2, "b2">, DwarfRegNum<[66]>;
255 def B3 : AArch64Reg<3, "b3">, DwarfRegNum<[67]>;
256 def B4 : AArch64Reg<4, "b4">, DwarfRegNum<[68]>;
257 def B5 : AArch64Reg<5, "b5">, DwarfRegNum<[69]>;
258 def B6 : AArch64Reg<6, "b6">, DwarfRegNum<[70]>;
259 def B7 : AArch64Reg<7, "b7">, DwarfRegNum<[71]>;
260 def B8 : AArch64Reg<8, "b8">, DwarfRegNum<[72]>;
261 def B9 : AArch64Reg<9, "b9">, DwarfRegNum<[73]>;
262 def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>;
263 def B11 : AArch64Reg<11, "b11">, DwarfRegNum<[75]>;
264 def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>;
265 def B13 : AArch64Reg<13, "b13">, DwarfRegNum<[77]>;
266 def B14 : AArch64Reg<14, "b14">, DwarfRegNum<[78]>;
267 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;
268 def B16 : AArch64Reg<16, "b16">, DwarfRegNum<[80]>;
269 def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>;
270 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;
271 def B19 : AArch64Reg<19, "b19">, DwarfRegNum<[83]>;
272 def B20 : AArch64Reg<20, "b20">, DwarfRegNum<[84]>;
273 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;
274 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;
275 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>;
276 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;
277 def B25 : AArch64Reg<25, "b25">, DwarfRegNum<[89]>;
278 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;
279 def B27 : AArch64Reg<27, "b27">, DwarfRegNum<[91]>;
280 def B28 : AArch64Reg<28, "b28">, DwarfRegNum<[92]>;
281 def B29 : AArch64Reg<29, "b29">, DwarfRegNum<[93]>;
282 def B30 : AArch64Reg<30, "b30">, DwarfRegNum<[94]>;
283 def B31 : AArch64Reg<31, "b31">, DwarfRegNum<[95]>;
285 let SubRegIndices = [bsub] in {
286 def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>;
287 def H1 : AArch64Reg<1, "h1", [B1]>, DwarfRegAlias<B1>;
288 def H2 : AArch64Reg<2, "h2", [B2]>, DwarfRegAlias<B2>;
289 def H3 : AArch64Reg<3, "h3", [B3]>, DwarfRegAlias<B3>;
290 def H4 : AArch64Reg<4, "h4", [B4]>, DwarfRegAlias<B4>;
291 def H5 : AArch64Reg<5, "h5", [B5]>, DwarfRegAlias<B5>;
292 def H6 : AArch64Reg<6, "h6", [B6]>, DwarfRegAlias<B6>;
293 def H7 : AArch64Reg<7, "h7", [B7]>, DwarfRegAlias<B7>;
294 def H8 : AArch64Reg<8, "h8", [B8]>, DwarfRegAlias<B8>;
295 def H9 : AArch64Reg<9, "h9", [B9]>, DwarfRegAlias<B9>;
296 def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
297 def H11 : AArch64Reg<11, "h11", [B11]>, DwarfRegAlias<B11>;
298 def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;
299 def H13 : AArch64Reg<13, "h13", [B13]>, DwarfRegAlias<B13>;
300 def H14 : AArch64Reg<14, "h14", [B14]>, DwarfRegAlias<B14>;
301 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
302 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
303 def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
304 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
305 def H19 : AArch64Reg<19, "h19", [B19]>, DwarfRegAlias<B19>;
306 def H20 : AArch64Reg<20, "h20", [B20]>, DwarfRegAlias<B20>;
307 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
308 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
309 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>;
310 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
311 def H25 : AArch64Reg<25, "h25", [B25]>, DwarfRegAlias<B25>;
312 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
313 def H27 : AArch64Reg<27, "h27", [B27]>, DwarfRegAlias<B27>;
314 def H28 : AArch64Reg<28, "h28", [B28]>, DwarfRegAlias<B28>;
315 def H29 : AArch64Reg<29, "h29", [B29]>, DwarfRegAlias<B29>;
316 def H30 : AArch64Reg<30, "h30", [B30]>, DwarfRegAlias<B30>;
317 def H31 : AArch64Reg<31, "h31", [B31]>, DwarfRegAlias<B31>;
320 let SubRegIndices = [hsub] in {
321 def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>;
322 def S1 : AArch64Reg<1, "s1", [H1]>, DwarfRegAlias<B1>;
323 def S2 : AArch64Reg<2, "s2", [H2]>, DwarfRegAlias<B2>;
324 def S3 : AArch64Reg<3, "s3", [H3]>, DwarfRegAlias<B3>;
325 def S4 : AArch64Reg<4, "s4", [H4]>, DwarfRegAlias<B4>;
326 def S5 : AArch64Reg<5, "s5", [H5]>, DwarfRegAlias<B5>;
327 def S6 : AArch64Reg<6, "s6", [H6]>, DwarfRegAlias<B6>;
328 def S7 : AArch64Reg<7, "s7", [H7]>, DwarfRegAlias<B7>;
329 def S8 : AArch64Reg<8, "s8", [H8]>, DwarfRegAlias<B8>;
330 def S9 : AArch64Reg<9, "s9", [H9]>, DwarfRegAlias<B9>;
331 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
332 def S11 : AArch64Reg<11, "s11", [H11]>, DwarfRegAlias<B11>;
333 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;
334 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
335 def S14 : AArch64Reg<14, "s14", [H14]>, DwarfRegAlias<B14>;
336 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
337 def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>;
338 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
339 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
340 def S19 : AArch64Reg<19, "s19", [H19]>, DwarfRegAlias<B19>;
341 def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>;
342 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
343 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
344 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
345 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
346 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
347 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
348 def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>;
349 def S28 : AArch64Reg<28, "s28", [H28]>, DwarfRegAlias<B28>;
350 def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>;
351 def S30 : AArch64Reg<30, "s30", [H30]>, DwarfRegAlias<B30>;
352 def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>;
355 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
356 def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>;
357 def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>;
358 def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>;
359 def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>;
360 def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>;
361 def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>;
362 def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>;
363 def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>;
364 def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>;
365 def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>;
366 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
367 def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>;
368 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
369 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
370 def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>;
371 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
372 def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
373 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
374 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
375 def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>;
376 def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
377 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
378 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
379 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
380 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
381 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
382 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
383 def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
384 def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>;
385 def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
386 def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
387 def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
390 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
391 def Q0 : AArch64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias<B0>;
392 def Q1 : AArch64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias<B1>;
393 def Q2 : AArch64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias<B2>;
394 def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>;
395 def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>;
396 def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
397 def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
398 def Q7 : AArch64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias<B7>;
399 def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>;
400 def Q9 : AArch64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias<B9>;
401 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
402 def Q11 : AArch64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias<B11>;
403 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
404 def Q13 : AArch64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias<B13>;
405 def Q14 : AArch64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias<B14>;
406 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
407 def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
408 def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
409 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
410 def Q19 : AArch64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias<B19>;
411 def Q20 : AArch64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias<B20>;
412 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
413 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
414 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
415 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
416 def Q25 : AArch64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias<B25>;
417 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
418 def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;
419 def Q28 : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>;
420 def Q29 : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>;
421 def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;
422 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
425 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
428 def FPR16 : RegisterClass<"AArch64", [f16, bf16], 16, (sequence "H%u", 0, 31)> {
432 def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {
435 def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
436 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
437 v1i64, v4f16, v4bf16],
438 64, (sequence "D%u", 0, 31)>;
439 def FPR64_lo : RegisterClass<"AArch64",
440 [v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,
442 64, (trunc FPR64, 16)>;
444 // We don't (yet) have an f128 legal type, so don't use that here. We
445 // normalize 128-bit vectors to v2f64 for arg passing and such, so use
447 def FPR128 : RegisterClass<"AArch64",
448 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128,
450 128, (sequence "Q%u", 0, 31)>;
452 // The lower 16 vector registers. Some instructions can only take registers
454 def FPR128_lo : RegisterClass<"AArch64",
455 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16,
457 128, (trunc FPR128, 16)>;
459 // Pairs, triples, and quads of 64-bit vector registers.
460 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
461 def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],
462 [(rotl FPR64, 0), (rotl FPR64, 1),
464 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
465 [(rotl FPR64, 0), (rotl FPR64, 1),
466 (rotl FPR64, 2), (rotl FPR64, 3)]>;
467 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
470 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
473 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
477 // Pairs, triples, and quads of 128-bit vector registers.
478 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
479 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],
480 [(rotl FPR128, 0), (rotl FPR128, 1),
482 def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],
483 [(rotl FPR128, 0), (rotl FPR128, 1),
484 (rotl FPR128, 2), (rotl FPR128, 3)]>;
485 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
488 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
491 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
496 // Vector operand versions of the FP registers. Alternate name printing and
497 // assembler matching.
498 def VectorReg64AsmOperand : AsmOperandClass {
499 let Name = "VectorReg64";
500 let PredicateMethod = "isNeonVectorReg";
502 def VectorReg128AsmOperand : AsmOperandClass {
503 let Name = "VectorReg128";
504 let PredicateMethod = "isNeonVectorReg";
507 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
508 let ParserMatchClass = VectorReg64AsmOperand;
511 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
512 let ParserMatchClass = VectorReg128AsmOperand;
515 def VectorRegLoAsmOperand : AsmOperandClass {
516 let Name = "VectorRegLo";
517 let PredicateMethod = "isNeonVectorRegLo";
519 def V64_lo : RegisterOperand<FPR64_lo, "printVRegOperand"> {
520 let ParserMatchClass = VectorRegLoAsmOperand;
522 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
523 let ParserMatchClass = VectorRegLoAsmOperand;
526 class TypedVecListAsmOperand<int count, string vecty, int lanes, int eltsize>
528 let Name = "TypedVectorList" # count # "_" # lanes # eltsize;
531 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
532 let RenderMethod = "addVectorListOperands<" # vecty # ", " # count # ">";
535 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
536 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
539 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
540 // With implicit types (probably on instruction instead). E.g. { v0, v1 }
541 def _64AsmOperand : AsmOperandClass {
542 let Name = NAME # "64";
543 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
544 let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_DReg, " # count # ">";
547 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
548 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_64AsmOperand");
551 def _128AsmOperand : AsmOperandClass {
552 let Name = NAME # "128";
553 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
554 let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ">";
557 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
558 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");
561 // 64-bit register lists with explicit type.
564 def _8bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 8, 8>;
565 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
566 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8bAsmOperand");
570 def _4hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 4, 16>;
571 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
572 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4hAsmOperand");
576 def _2sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 2, 32>;
577 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
578 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2sAsmOperand");
582 def _1dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 1, 64>;
583 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
584 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_1dAsmOperand");
587 // 128-bit register lists with explicit type
589 // { v0.16b, v1.16b }
590 def _16bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 16, 8>;
591 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
592 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_16bAsmOperand");
596 def _8hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 8, 16>;
597 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
598 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8hAsmOperand");
602 def _4sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 4, 32>;
603 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
604 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4sAsmOperand");
608 def _2dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 2, 64>;
609 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
610 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2dAsmOperand");
614 def _bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 8>;
615 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
616 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_bAsmOperand");
620 def _hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 16>;
621 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
622 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_hAsmOperand");
626 def _sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 32>;
627 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
628 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_sAsmOperand");
632 def _dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 64>;
633 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
634 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_dAsmOperand");
640 defm VecListOne : VectorList<1, FPR64, FPR128>;
641 defm VecListTwo : VectorList<2, DD, QQ>;
642 defm VecListThree : VectorList<3, DDD, QQQ>;
643 defm VecListFour : VectorList<4, DDDD, QQQQ>;
645 class FPRAsmOperand<string RC> : AsmOperandClass {
646 let Name = "FPRAsmOperand" # RC;
647 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
648 let RenderMethod = "addRegOperands";
651 // Register operand versions of the scalar FP registers.
652 def FPR8Op : RegisterOperand<FPR8, "printOperand"> {
653 let ParserMatchClass = FPRAsmOperand<"FPR8">;
656 def FPR16Op : RegisterOperand<FPR16, "printOperand"> {
657 let ParserMatchClass = FPRAsmOperand<"FPR16">;
660 def FPR16Op_lo : RegisterOperand<FPR16_lo, "printOperand"> {
661 let ParserMatchClass = FPRAsmOperand<"FPR16_lo">;
664 def FPR32Op : RegisterOperand<FPR32, "printOperand"> {
665 let ParserMatchClass = FPRAsmOperand<"FPR32">;
668 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
669 let ParserMatchClass = FPRAsmOperand<"FPR64">;
672 def FPR128Op : RegisterOperand<FPR128, "printOperand"> {
673 let ParserMatchClass = FPRAsmOperand<"FPR128">;
676 //===----------------------------------------------------------------------===//
677 // ARMv8.1a atomic CASP register operands
680 def WSeqPairs : RegisterTuples<[sube32, subo32],
681 [(decimate (rotl GPR32, 0), 2),
682 (decimate (rotl GPR32, 1), 2)]>;
683 def XSeqPairs : RegisterTuples<[sube64, subo64],
684 [(decimate (rotl GPR64, 0), 2),
685 (decimate (rotl GPR64, 1), 2)]>;
687 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
691 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
697 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
698 def WSeqPairsAsmOperandClass : AsmOperandClass { let Name = "WSeqPair"; }
699 def XSeqPairsAsmOperandClass : AsmOperandClass { let Name = "XSeqPair"; }
702 def WSeqPairClassOperand :
703 RegisterOperand<WSeqPairsClass, "printGPRSeqPairsClassOperand<32>"> {
704 let ParserMatchClass = WSeqPairsAsmOperandClass;
706 def XSeqPairClassOperand :
707 RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {
708 let ParserMatchClass = XSeqPairsAsmOperandClass;
712 //===----- END: v8.1a atomic CASP register operands -----------------------===//
714 // SVE predicate registers
715 def P0 : AArch64Reg<0, "p0">, DwarfRegNum<[48]>;
716 def P1 : AArch64Reg<1, "p1">, DwarfRegNum<[49]>;
717 def P2 : AArch64Reg<2, "p2">, DwarfRegNum<[50]>;
718 def P3 : AArch64Reg<3, "p3">, DwarfRegNum<[51]>;
719 def P4 : AArch64Reg<4, "p4">, DwarfRegNum<[52]>;
720 def P5 : AArch64Reg<5, "p5">, DwarfRegNum<[53]>;
721 def P6 : AArch64Reg<6, "p6">, DwarfRegNum<[54]>;
722 def P7 : AArch64Reg<7, "p7">, DwarfRegNum<[55]>;
723 def P8 : AArch64Reg<8, "p8">, DwarfRegNum<[56]>;
724 def P9 : AArch64Reg<9, "p9">, DwarfRegNum<[57]>;
725 def P10 : AArch64Reg<10, "p10">, DwarfRegNum<[58]>;
726 def P11 : AArch64Reg<11, "p11">, DwarfRegNum<[59]>;
727 def P12 : AArch64Reg<12, "p12">, DwarfRegNum<[60]>;
728 def P13 : AArch64Reg<13, "p13">, DwarfRegNum<[61]>;
729 def P14 : AArch64Reg<14, "p14">, DwarfRegNum<[62]>;
730 def P15 : AArch64Reg<15, "p15">, DwarfRegNum<[63]>;
732 // The part of SVE registers that don't overlap Neon registers.
733 // These are only used as part of clobber lists.
734 def Z0_HI : AArch64Reg<0, "z0_hi">;
735 def Z1_HI : AArch64Reg<1, "z1_hi">;
736 def Z2_HI : AArch64Reg<2, "z2_hi">;
737 def Z3_HI : AArch64Reg<3, "z3_hi">;
738 def Z4_HI : AArch64Reg<4, "z4_hi">;
739 def Z5_HI : AArch64Reg<5, "z5_hi">;
740 def Z6_HI : AArch64Reg<6, "z6_hi">;
741 def Z7_HI : AArch64Reg<7, "z7_hi">;
742 def Z8_HI : AArch64Reg<8, "z8_hi">;
743 def Z9_HI : AArch64Reg<9, "z9_hi">;
744 def Z10_HI : AArch64Reg<10, "z10_hi">;
745 def Z11_HI : AArch64Reg<11, "z11_hi">;
746 def Z12_HI : AArch64Reg<12, "z12_hi">;
747 def Z13_HI : AArch64Reg<13, "z13_hi">;
748 def Z14_HI : AArch64Reg<14, "z14_hi">;
749 def Z15_HI : AArch64Reg<15, "z15_hi">;
750 def Z16_HI : AArch64Reg<16, "z16_hi">;
751 def Z17_HI : AArch64Reg<17, "z17_hi">;
752 def Z18_HI : AArch64Reg<18, "z18_hi">;
753 def Z19_HI : AArch64Reg<19, "z19_hi">;
754 def Z20_HI : AArch64Reg<20, "z20_hi">;
755 def Z21_HI : AArch64Reg<21, "z21_hi">;
756 def Z22_HI : AArch64Reg<22, "z22_hi">;
757 def Z23_HI : AArch64Reg<23, "z23_hi">;
758 def Z24_HI : AArch64Reg<24, "z24_hi">;
759 def Z25_HI : AArch64Reg<25, "z25_hi">;
760 def Z26_HI : AArch64Reg<26, "z26_hi">;
761 def Z27_HI : AArch64Reg<27, "z27_hi">;
762 def Z28_HI : AArch64Reg<28, "z28_hi">;
763 def Z29_HI : AArch64Reg<29, "z29_hi">;
764 def Z30_HI : AArch64Reg<30, "z30_hi">;
765 def Z31_HI : AArch64Reg<31, "z31_hi">;
767 // SVE variable-size vector registers
768 let SubRegIndices = [zsub,zsub_hi] in {
769 def Z0 : AArch64Reg<0, "z0", [Q0, Z0_HI]>, DwarfRegNum<[96]>;
770 def Z1 : AArch64Reg<1, "z1", [Q1, Z1_HI]>, DwarfRegNum<[97]>;
771 def Z2 : AArch64Reg<2, "z2", [Q2, Z2_HI]>, DwarfRegNum<[98]>;
772 def Z3 : AArch64Reg<3, "z3", [Q3, Z3_HI]>, DwarfRegNum<[99]>;
773 def Z4 : AArch64Reg<4, "z4", [Q4, Z4_HI]>, DwarfRegNum<[100]>;
774 def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>;
775 def Z6 : AArch64Reg<6, "z6", [Q6, Z6_HI]>, DwarfRegNum<[102]>;
776 def Z7 : AArch64Reg<7, "z7", [Q7, Z7_HI]>, DwarfRegNum<[103]>;
777 def Z8 : AArch64Reg<8, "z8", [Q8, Z8_HI]>, DwarfRegNum<[104]>;
778 def Z9 : AArch64Reg<9, "z9", [Q9, Z9_HI]>, DwarfRegNum<[105]>;
779 def Z10 : AArch64Reg<10, "z10", [Q10, Z10_HI]>, DwarfRegNum<[106]>;
780 def Z11 : AArch64Reg<11, "z11", [Q11, Z11_HI]>, DwarfRegNum<[107]>;
781 def Z12 : AArch64Reg<12, "z12", [Q12, Z12_HI]>, DwarfRegNum<[108]>;
782 def Z13 : AArch64Reg<13, "z13", [Q13, Z13_HI]>, DwarfRegNum<[109]>;
783 def Z14 : AArch64Reg<14, "z14", [Q14, Z14_HI]>, DwarfRegNum<[110]>;
784 def Z15 : AArch64Reg<15, "z15", [Q15, Z15_HI]>, DwarfRegNum<[111]>;
785 def Z16 : AArch64Reg<16, "z16", [Q16, Z16_HI]>, DwarfRegNum<[112]>;
786 def Z17 : AArch64Reg<17, "z17", [Q17, Z17_HI]>, DwarfRegNum<[113]>;
787 def Z18 : AArch64Reg<18, "z18", [Q18, Z18_HI]>, DwarfRegNum<[114]>;
788 def Z19 : AArch64Reg<19, "z19", [Q19, Z19_HI]>, DwarfRegNum<[115]>;
789 def Z20 : AArch64Reg<20, "z20", [Q20, Z20_HI]>, DwarfRegNum<[116]>;
790 def Z21 : AArch64Reg<21, "z21", [Q21, Z21_HI]>, DwarfRegNum<[117]>;
791 def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
792 def Z23 : AArch64Reg<23, "z23", [Q23, Z23_HI]>, DwarfRegNum<[119]>;
793 def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
794 def Z25 : AArch64Reg<25, "z25", [Q25, Z25_HI]>, DwarfRegNum<[121]>;
795 def Z26 : AArch64Reg<26, "z26", [Q26, Z26_HI]>, DwarfRegNum<[122]>;
796 def Z27 : AArch64Reg<27, "z27", [Q27, Z27_HI]>, DwarfRegNum<[123]>;
797 def Z28 : AArch64Reg<28, "z28", [Q28, Z28_HI]>, DwarfRegNum<[124]>;
798 def Z29 : AArch64Reg<29, "z29", [Q29, Z29_HI]>, DwarfRegNum<[125]>;
799 def Z30 : AArch64Reg<30, "z30", [Q30, Z30_HI]>, DwarfRegNum<[126]>;
800 def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
803 // Enum describing the element size for destructive
805 class ElementSizeEnum<bits<3> val> {
809 def ElementSizeNone : ElementSizeEnum<0>;
810 def ElementSizeB : ElementSizeEnum<1>;
811 def ElementSizeH : ElementSizeEnum<2>;
812 def ElementSizeS : ElementSizeEnum<3>;
813 def ElementSizeD : ElementSizeEnum<4>;
814 def ElementSizeQ : ElementSizeEnum<5>; // Unused
816 class SVERegOp <string Suffix, AsmOperandClass C,
817 ElementSizeEnum Size,
818 RegisterClass RC> : RegisterOperand<RC> {
819 ElementSizeEnum ElementSize;
821 let ElementSize = Size;
822 let PrintMethod = !if(!eq(Suffix, ""),
824 "printSVERegOp<'" # Suffix # "'>");
825 let ParserMatchClass = C;
828 class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
829 RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
830 class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
831 RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
833 //******************************************************************************
835 // SVE predicate register classes.
836 class PPRClass<int lastreg> : RegisterClass<
838 [ nxv16i1, nxv8i1, nxv4i1, nxv2i1 ], 16,
839 (sequence "P%u", 0, lastreg)> {
843 def PPR : PPRClass<15>;
844 def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
846 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
847 let Name = "SVE" # name # "Reg";
848 let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
849 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
850 let DiagnosticType = "InvalidSVE" # name # "Reg";
851 let RenderMethod = "addRegOperands";
852 let ParserMethod = "tryParseSVEPredicateVector";
855 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
856 def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
857 def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
858 def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
859 def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
861 def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
862 def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
863 def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
864 def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
865 def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
867 def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>;
868 def PPRAsmOp3b8 : PPRAsmOperand<"Predicate3bB", "PPR_3b", 8>;
869 def PPRAsmOp3b16 : PPRAsmOperand<"Predicate3bH", "PPR_3b", 16>;
870 def PPRAsmOp3b32 : PPRAsmOperand<"Predicate3bS", "PPR_3b", 32>;
871 def PPRAsmOp3b64 : PPRAsmOperand<"Predicate3bD", "PPR_3b", 64>;
873 def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
874 def PPR3b8 : PPRRegOp<"b", PPRAsmOp3b8, ElementSizeB, PPR_3b>;
875 def PPR3b16 : PPRRegOp<"h", PPRAsmOp3b16, ElementSizeH, PPR_3b>;
876 def PPR3b32 : PPRRegOp<"s", PPRAsmOp3b32, ElementSizeS, PPR_3b>;
877 def PPR3b64 : PPRRegOp<"d", PPRAsmOp3b64, ElementSizeD, PPR_3b>;
879 //******************************************************************************
881 // SVE vector register classes
882 class ZPRClass<int lastreg> : RegisterClass<"AArch64",
883 [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
884 nxv2f16, nxv4f16, nxv8f16,
885 nxv2bf16, nxv4bf16, nxv8bf16,
888 128, (sequence "Z%u", 0, lastreg)> {
892 def ZPR : ZPRClass<31>;
893 def ZPR_4b : ZPRClass<15>; // Restricted 4 bit SVE vector register class.
894 def ZPR_3b : ZPRClass<7>; // Restricted 3 bit SVE vector register class.
896 class ZPRAsmOperand<string name, int Width, string RegClassSuffix = "">
898 let Name = "SVE" # name # "Reg";
899 let PredicateMethod = "isSVEDataVectorRegOfWidth<"
900 # Width # ", AArch64::ZPR"
901 # RegClassSuffix # "RegClassID>";
902 let RenderMethod = "addRegOperands";
903 let DiagnosticType = "InvalidZPR" # RegClassSuffix # Width;
904 let ParserMethod = "tryParseSVEDataVector<false, "
905 # !if(!eq(Width, 0), "false", "true") # ">";
908 def ZPRAsmOpAny : ZPRAsmOperand<"VectorAny", 0>;
909 def ZPRAsmOp8 : ZPRAsmOperand<"VectorB", 8>;
910 def ZPRAsmOp16 : ZPRAsmOperand<"VectorH", 16>;
911 def ZPRAsmOp32 : ZPRAsmOperand<"VectorS", 32>;
912 def ZPRAsmOp64 : ZPRAsmOperand<"VectorD", 64>;
913 def ZPRAsmOp128 : ZPRAsmOperand<"VectorQ", 128>;
915 def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>;
916 def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>;
917 def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>;
918 def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>;
919 def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>;
920 def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;
922 def ZPRAsmOp3b8 : ZPRAsmOperand<"Vector3bB", 8, "_3b">;
923 def ZPRAsmOp3b16 : ZPRAsmOperand<"Vector3bH", 16, "_3b">;
924 def ZPRAsmOp3b32 : ZPRAsmOperand<"Vector3bS", 32, "_3b">;
926 def ZPR3b8 : ZPRRegOp<"b", ZPRAsmOp3b8, ElementSizeB, ZPR_3b>;
927 def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ElementSizeH, ZPR_3b>;
928 def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ElementSizeS, ZPR_3b>;
930 def ZPRAsmOp4b16 : ZPRAsmOperand<"Vector4bH", 16, "_4b">;
931 def ZPRAsmOp4b32 : ZPRAsmOperand<"Vector4bS", 32, "_4b">;
932 def ZPRAsmOp4b64 : ZPRAsmOperand<"Vector4bD", 64, "_4b">;
934 def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ElementSizeH, ZPR_4b>;
935 def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ElementSizeS, ZPR_4b>;
936 def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ElementSizeD, ZPR_4b>;
938 class FPRasZPR<int Width> : AsmOperandClass{
939 let Name = "FPR" # Width # "asZPR";
940 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
941 let RenderMethod = "addFPRasZPRRegOperands<" # Width # ">";
944 class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {
945 let ParserMatchClass = FPRasZPR<Width>;
946 let PrintMethod = "printZPRasFPR<" # Width # ">";
949 def FPR8asZPR : FPRasZPROperand<8>;
950 def FPR16asZPR : FPRasZPROperand<16>;
951 def FPR32asZPR : FPRasZPROperand<32>;
952 def FPR64asZPR : FPRasZPROperand<64>;
953 def FPR128asZPR : FPRasZPROperand<128>;
955 let Namespace = "AArch64" in {
956 def zsub0 : SubRegIndex<128, -1>;
957 def zsub1 : SubRegIndex<128, -1>;
958 def zsub2 : SubRegIndex<128, -1>;
959 def zsub3 : SubRegIndex<128, -1>;
962 // Pairs, triples, and quads of SVE vector registers.
963 def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;
964 def ZSeqTriples : RegisterTuples<[zsub0, zsub1, zsub2], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2)]>;
965 def ZSeqQuads : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2), (rotl ZPR, 3)]>;
967 def ZPR2 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)> {
970 def ZPR3 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqTriples)> {
973 def ZPR4 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqQuads)> {
977 class ZPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
978 let Name = "SVEVectorList" # NumRegs # ElementWidth;
979 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
980 let PredicateMethod =
981 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
982 let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_ZReg, " # NumRegs # ">";
985 def Z_b : RegisterOperand<ZPR, "printTypedVectorList<0,'b'>"> {
986 let ParserMatchClass = ZPRVectorList<8, 1>;
989 def Z_h : RegisterOperand<ZPR, "printTypedVectorList<0,'h'>"> {
990 let ParserMatchClass = ZPRVectorList<16, 1>;
993 def Z_s : RegisterOperand<ZPR, "printTypedVectorList<0,'s'>"> {
994 let ParserMatchClass = ZPRVectorList<32, 1>;
997 def Z_d : RegisterOperand<ZPR, "printTypedVectorList<0,'d'>"> {
998 let ParserMatchClass = ZPRVectorList<64, 1>;
1001 def ZZ_b : RegisterOperand<ZPR2, "printTypedVectorList<0,'b'>"> {
1002 let ParserMatchClass = ZPRVectorList<8, 2>;
1005 def ZZ_h : RegisterOperand<ZPR2, "printTypedVectorList<0,'h'>"> {
1006 let ParserMatchClass = ZPRVectorList<16, 2>;
1009 def ZZ_s : RegisterOperand<ZPR2, "printTypedVectorList<0,'s'>"> {
1010 let ParserMatchClass = ZPRVectorList<32, 2>;
1013 def ZZ_d : RegisterOperand<ZPR2, "printTypedVectorList<0,'d'>"> {
1014 let ParserMatchClass = ZPRVectorList<64, 2>;
1017 def ZZZ_b : RegisterOperand<ZPR3, "printTypedVectorList<0,'b'>"> {
1018 let ParserMatchClass = ZPRVectorList<8, 3>;
1021 def ZZZ_h : RegisterOperand<ZPR3, "printTypedVectorList<0,'h'>"> {
1022 let ParserMatchClass = ZPRVectorList<16, 3>;
1025 def ZZZ_s : RegisterOperand<ZPR3, "printTypedVectorList<0,'s'>"> {
1026 let ParserMatchClass = ZPRVectorList<32, 3>;
1029 def ZZZ_d : RegisterOperand<ZPR3, "printTypedVectorList<0,'d'>"> {
1030 let ParserMatchClass = ZPRVectorList<64, 3>;
1033 def ZZZZ_b : RegisterOperand<ZPR4, "printTypedVectorList<0,'b'>"> {
1034 let ParserMatchClass = ZPRVectorList<8, 4>;
1037 def ZZZZ_h : RegisterOperand<ZPR4, "printTypedVectorList<0,'h'>"> {
1038 let ParserMatchClass = ZPRVectorList<16, 4>;
1041 def ZZZZ_s : RegisterOperand<ZPR4, "printTypedVectorList<0,'s'>"> {
1042 let ParserMatchClass = ZPRVectorList<32, 4>;
1045 def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
1046 let ParserMatchClass = ZPRVectorList<64, 4>;
1049 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
1050 bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
1051 let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
1052 # !if(ScaleAlwaysSame, "Only", "");
1054 let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"
1055 # RegWidth # ", AArch64::ZPRRegClassID, "
1056 # "AArch64_AM::" # ShiftExtend # ", "
1058 # !if(ScaleAlwaysSame, "true", "false")
1060 let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
1061 let RenderMethod = "addRegOperands";
1062 let ParserMethod = "tryParseSVEDataVector<true, true>";
1065 class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,
1066 int RegWidth, int Scale, string Suffix = "">
1067 : RegisterOperand<ZPR> {
1068 let ParserMatchClass =
1069 !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
1070 let PrintMethod = "printRegWithShiftExtend<"
1071 # !if(SignExtend, "true", "false") # ", "
1073 # !if(IsLSL, "'x'", "'w'") # ", "
1074 # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
1077 foreach RegWidth = [32, 64] in {
1079 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1080 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1081 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1082 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1083 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1085 def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">;
1086 def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
1087 def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
1088 def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
1089 def ZPR#RegWidth#ExtUXTW64 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>;
1092 def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;
1093 def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
1094 def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
1095 def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
1096 def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
1098 def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">;
1099 def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
1100 def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
1101 def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
1102 def ZPR#RegWidth#ExtSXTW64 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>;
1105 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1106 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1107 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1108 def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1109 def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1110 def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1111 def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1112 def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
1115 class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
1116 let Name = AsmOperandName # Scale;
1117 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1118 let DiagnosticType = "Invalid" # AsmOperandName # Scale;
1119 let RenderMethod = "addRegOperands";
1120 let ParserMethod = "tryParseGPROperand<true>";
1123 class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{
1124 let ParserMatchClass = !cast<AsmOperandClass>(Name);
1125 let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x', 0>";
1128 foreach Scale = [8, 16, 32, 64] in {
1129 def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">;
1130 def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>;
1132 def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">;
1133 def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>;