contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

   1 //=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M3 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM3Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  40; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  28                                                     PAUnsupported.F);
  29 }
  30
  31 //===----------------------------------------------------------------------===//
  32 // Define each kind of processor resource and number available on the Exynos-M3,
  33 // which has 12 pipelines, each with its own queue with out-of-order dispatch.
  34
  35 let SchedModel = ExynosM3Model in {
  36
  37 def M3UnitA  : ProcResource<2>; // Simple integer
  38 def M3UnitC  : ProcResource<2>; // Simple and complex integer
  39 def M3UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  40 def M3UnitB  : ProcResource<2>; // Branch
  41 def M3UnitL  : ProcResource<2>; // Load
  42 def M3UnitS  : ProcResource<1>; // Store
  43 def M3PipeF0 : ProcResource<1>; // FP #0
  44 let Super = M3PipeF0 in {
  45   def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
  46   def M3UnitFADD0 : ProcResource<1>; // Simple FP
  47   def M3UnitFCVT0 : ProcResource<1>; // FP conversion
  48   def M3UnitFSQR  : ProcResource<2>; // FP square root (serialized)
  49   def M3UnitNALU0 : ProcResource<1>; // Simple vector
  50   def M3UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  51   def M3UnitNSHT0 : ProcResource<1>; // Vector shifting
  52   def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling
  53 }
  54 def M3PipeF1 : ProcResource<1>; // FP #1
  55 let Super = M3PipeF1 in {
  56   def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
  57   def M3UnitFADD1 : ProcResource<1>; // Simple FP
  58   def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  59   def M3UnitFCVT1 : ProcResource<1>; // FP conversion
  60   def M3UnitFST0  : ProcResource<1>; // FP store
  61   def M3UnitNALU1 : ProcResource<1>; // Simple vector
  62   def M3UnitNCRY0 : ProcResource<1>; // Cryptographic
  63   def M3UnitNMUL  : ProcResource<1>; // Vector multiplication
  64   def M3UnitNSHT1 : ProcResource<1>; // Vector shifting
  65   def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling
  66 }
  67 def M3PipeF2 : ProcResource<1>; // FP #2
  68 let Super = M3PipeF2 in {
  69   def M3UnitFMAC2 : ProcResource<1>; // FP multiplication
  70   def M3UnitFADD2 : ProcResource<1>; // Simple FP
  71   def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  72   def M3UnitFST1  : ProcResource<1>; // FP store
  73   def M3UnitNALU2 : ProcResource<1>; // Simple vector
  74   def M3UnitNCRY1 : ProcResource<1>; // Cryptographic
  75   def M3UnitNSHT2 : ProcResource<1>; // Vector shifting
  76   def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
  77 }
  78
  79
  80 def M3UnitALU  : ProcResGroup<[M3UnitA,
  81                                M3UnitC]>;
  82 def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
  83                                M3UnitFMAC1,
  84                                M3UnitFMAC2]>;
  85 def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
  86                                M3UnitFADD1,
  87                                M3UnitFADD2]>;
  88 def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
  89                                M3UnitFDIV1]>;
  90 def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
  91                                M3UnitFCVT1]>;
  92 def M3UnitFST  : ProcResGroup<[M3UnitFST0,
  93                                M3UnitFST1]>;
  94 def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
  95                                M3UnitNALU1,
  96                                M3UnitNALU2]>;
  97 def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
  98                                M3UnitNCRY1]>;
  99 def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
 100                                M3UnitNSHT1,
 101                                M3UnitNSHT2]>;
 102 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
 103                                M3UnitNSHF1,
 104                                M3UnitNSHF2]>;
 105
 106 //===----------------------------------------------------------------------===//
 107 // Coarse scheduling model.
 108
 109 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
 110                                     let NumMicroOps = 1; }
 111 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 112                                     let NumMicroOps = 0; }
 113
 114 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
 115 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
 116                                              let ResourceCycles = [2]; }
 117 def M3WriteAB : SchedWriteRes<[M3UnitALU,
 118                                M3UnitC]>   { let Latency = 1;
 119                                              let NumMicroOps = 2; }
 120 def M3WriteAC : SchedWriteRes<[M3UnitALU,
 121                                M3UnitALU,
 122                                M3UnitC]>   { let Latency = 2;
 123                                              let NumMicroOps = 3; }
 124 def M3WriteAD : SchedWriteRes<[M3UnitALU,
 125                                M3UnitC]>   { let Latency = 2;
 126                                              let NumMicroOps = 2; }
 127 def M3WriteC1 : SchedWriteRes<[M3UnitC]>   { let Latency = 1; }
 128 def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
 129 def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 130                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
 131                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 132                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 133 def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 134                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
 135                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 136 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
 137                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 138                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 139 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
 140                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 141                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 142 def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
 143                                    SchedVar<NoSchedPred,              [M3WriteAA]>]>;
 144
 145 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 146 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
 147                                    SchedVar<NoSchedPred,            [M3WriteAB]>]>;
 148
 149 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
 150 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
 151 def M3WriteLA : SchedWriteRes<[M3UnitL,
 152                                M3UnitL]> { let Latency = 5;
 153                                            let NumMicroOps = 1; }
 154 def M3WriteLB : SchedWriteRes<[M3UnitA,
 155                                M3UnitL]> { let Latency = 5;
 156                                            let NumMicroOps = 2; }
 157 def M3WriteLC : SchedWriteRes<[M3UnitA,
 158                                M3UnitL,
 159                                M3UnitL]> { let Latency = 5;
 160                                            let NumMicroOps = 2; }
 161 def M3WriteLD : SchedWriteRes<[M3UnitA,
 162                                M3UnitL]> { let Latency = 4;
 163                                            let NumMicroOps = 2; }
 164 def M3WriteLE : SchedWriteRes<[M3UnitA,
 165                                M3UnitL]> { let Latency = 6;
 166                                            let NumMicroOps = 2; }
 167 def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 168                                            let NumMicroOps = 0; }
 169 def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
 170                                    SchedVar<NoSchedPred,         [M3WriteL4]>]>;
 171 def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>,
 172                                    SchedVar<NoSchedPred,         [M3WriteL5]>]>;
 173
 174 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 175 def M3WriteSA : SchedWriteRes<[M3UnitA,
 176                                M3UnitS,
 177                                M3UnitFST]> { let Latency = 3;
 178                                              let NumMicroOps = 2; }
 179 def M3WriteSB : SchedWriteRes<[M3UnitA,
 180                                M3UnitS]>   { let Latency = 2;
 181                                              let NumMicroOps = 2; }
 182 def M3WriteSC : SchedWriteRes<[M3UnitA,
 183                                M3UnitS,
 184                                M3UnitFST]> { let Latency = 1;
 185                                              let NumMicroOps = 2; }
 186 def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>,
 187                                    SchedVar<NoSchedPred,         [WriteVST]>]>;
 188
 189 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
 190                                       SchedVar<NoSchedPred,         [ReadDefault]>]>;
 191
 192 // Branch instructions.
 193 def : SchedAlias<WriteBr, M3WriteZ0>;
 194 def : SchedAlias<WriteBrReg, M3WriteC1>;
 195
 196 // Arithmetic and logical integer instructions.
 197 def : SchedAlias<WriteI,     M3WriteA1>;
 198 def : SchedAlias<WriteISReg, M3WriteA1>;
 199 def : SchedAlias<WriteIEReg, M3WriteA1>;
 200 def : SchedAlias<WriteIS,    M3WriteA1>;
 201
 202 // Move instructions.
 203 def : SchedAlias<WriteImm, M3WriteA1>;
 204
 205 // Divide and multiply instructions.
 206 def : WriteRes<WriteID32, [M3UnitC,
 207                            M3UnitD]>  { let Latency = 12;
 208                                         let ResourceCycles = [1, 12]; }
 209 def : WriteRes<WriteID64, [M3UnitC,
 210                            M3UnitD]>  { let Latency = 21;
 211                                         let ResourceCycles = [1, 21]; }
 212 def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
 213 def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
 214                                         let ResourceCycles = [2]; }
 215
 216 // Miscellaneous instructions.
 217 def : SchedAlias<WriteExtr, M3WriteAY>;
 218
 219 // Addressing modes.
 220 def : SchedAlias<WriteAdr,    M3WriteZ1>;
 221 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
 222
 223 // Load instructions.
 224 def : SchedAlias<WriteLD, M3WriteL4>;
 225 def : WriteRes<WriteLDHi, []> { let Latency = 4;
 226                                 let NumMicroOps = 0; }
 227 def : SchedAlias<WriteLDIdx, M3WriteLB>;
 228
 229 // Store instructions.
 230 def : SchedAlias<WriteST,    M3WriteS1>;
 231 def : SchedAlias<WriteSTP,   M3WriteS1>;
 232 def : SchedAlias<WriteSTX,   M3WriteS1>;
 233 def : SchedAlias<WriteSTIdx, M3WriteSB>;
 234
 235 // FP data instructions.
 236 def : WriteRes<WriteF,    [M3UnitFADD]>  { let Latency = 2; }
 237 def : WriteRes<WriteFCmp, [M3UnitNMSC]>  { let Latency = 2; }
 238 def : WriteRes<WriteFDiv, [M3UnitFDIV]>  { let Latency = 12;
 239                                            let ResourceCycles = [12]; }
 240 def : WriteRes<WriteFMul, [M3UnitFMAC]>  { let Latency = 4; }
 241
 242 // FP miscellaneous instructions.
 243 def : WriteRes<WriteFCvt,  [M3UnitFCVT]> { let Latency = 3; }
 244 def : WriteRes<WriteFImm,  [M3UnitNALU]> { let Latency = 1; }
 245 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
 246
 247 // FP load instructions.
 248 def : SchedAlias<WriteVLD, M3WriteL5>;
 249
 250 // FP store instructions.
 251 def : WriteRes<WriteVST, [M3UnitS,
 252                           M3UnitFST]> { let Latency = 1;
 253                                         let NumMicroOps = 1; }
 254
 255 // ASIMD FP instructions.
 256 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
 257
 258 // Other miscellaneous instructions.
 259 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 260 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 261 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 262 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 263
 264 //===----------------------------------------------------------------------===//
 265 // Generic fast forwarding.
 266
 267 // TODO: Add FP register forwarding rules.
 268
 269 def : ReadAdvance<ReadI,       0>;
 270 def : ReadAdvance<ReadISReg,   0>;
 271 def : ReadAdvance<ReadIEReg,   0>;
 272 def : ReadAdvance<ReadIM,      0>;
 273 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 274 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 275 def : ReadAdvance<ReadID,      0>;
 276 def : ReadAdvance<ReadExtrHi,  0>;
 277 def : ReadAdvance<ReadAdrBase, 0>;
 278 def : ReadAdvance<ReadVLD,     0>;
 279
 280 //===----------------------------------------------------------------------===//
 281 // Finer scheduling model.
 282
 283 def M3WriteNEONA   : SchedWriteRes<[M3UnitNSHF,
 284                                     M3UnitFADD]>  { let Latency = 3;
 285                                                     let NumMicroOps = 2; }
 286 def M3WriteNEONB   : SchedWriteRes<[M3UnitNALU,
 287                                     M3UnitFST]>   { let Latency = 10;
 288                                                     let NumMicroOps = 2; }
 289 def M3WriteNEOND   : SchedWriteRes<[M3UnitNSHF,
 290                                     M3UnitFST]>   { let Latency = 6;
 291                                                     let NumMicroOps = 2; }
 292 def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
 293                                     M3UnitS]>     { let Latency = 5;
 294                                                     let NumMicroOps = 2; }
 295 def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
 296                                     M3UnitS]>     { let Latency = 5;
 297                                                     let NumMicroOps = 2; }
 298 def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV0,
 299                                     M3UnitFDIV1]>  { let Latency = 7;
 300                                                      let NumMicroOps = 2;
 301                                                      let ResourceCycles = [8, 8]; }
 302 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV0,
 303                                     M3UnitFDIV1]>  { let Latency = 12;
 304                                                      let NumMicroOps = 2;
 305                                                      let ResourceCycles = [13, 13]; }
 306 def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
 307                                     M3UnitFSQR]>  { let Latency = 18;
 308                                                     let NumMicroOps = 2;
 309                                                     let ResourceCycles = [19, 19]; }
 310 def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
 311                                     M3UnitFSQR]>  { let Latency = 25;
 312                                                     let NumMicroOps = 2;
 313                                                     let ResourceCycles = [26, 26]; }
 314 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
 315                                     M3UnitNMSC]>  { let Latency = 5;
 316                                                     let NumMicroOps = 2; }
 317 def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
 318 def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
 319 def M3WriteFCVT3   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 3; }
 320 def M3WriteFCVT3A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
 321 def M3WriteFCVT4A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
 322 def M3WriteFCVT4   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 4; }
 323 def M3WriteFDIV10  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 7;
 324                                                     let ResourceCycles = [8]; }
 325 def M3WriteFDIV12  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 12;
 326                                                     let ResourceCycles = [13]; }
 327 def M3WriteFMAC3   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 3; }
 328 def M3WriteFMAC4   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 4; }
 329 def M3WriteFMAC5   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 5; }
 330 def M3WriteFSQR17  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 18;
 331                                                     let ResourceCycles = [19]; }
 332 def M3WriteFSQR25  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 25;
 333                                                     let ResourceCycles = [26]; }
 334 def M3WriteNALU1   : SchedWriteRes<[M3UnitNALU]>  { let Latency = 1; }
 335 def M3WriteNCRY1A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
 336 def M3WriteNCRY3A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
 337 def M3WriteNCRY5A  : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 5; }
 338 def M3WriteNMSC1   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 1; }
 339 def M3WriteNMSC2   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 2; }
 340 def M3WriteNMSC3   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 3; }
 341 def M3WriteNMUL3   : SchedWriteRes<[M3UnitNMUL]>  { let Latency = 3; }
 342 def M3WriteNSHF1   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 1; }
 343 def M3WriteNSHF3   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 3; }
 344 def M3WriteNSHT1   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 1; }
 345 def M3WriteNSHT2   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 2; }
 346 def M3WriteNSHT3   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 3; }
 347 def M3WriteVLDA    : SchedWriteRes<[M3UnitL,
 348                                     M3UnitL]>     { let Latency = 5;
 349                                                     let NumMicroOps = 2; }
 350 def M3WriteVLDB    : SchedWriteRes<[M3UnitL,
 351                                     M3UnitL,
 352                                     M3UnitL]>     { let Latency = 6;
 353                                                     let NumMicroOps = 3; }
 354 def M3WriteVLDC    : SchedWriteRes<[M3UnitL,
 355                                     M3UnitL,
 356                                     M3UnitL,
 357                                     M3UnitL]>     { let Latency = 6;
 358                                                     let NumMicroOps = 4; }
 359 def M3WriteVLDD    : SchedWriteRes<[M3UnitL,
 360                                     M3UnitNALU]>  { let Latency = 7;
 361                                                     let NumMicroOps = 2;
 362                                                     let ResourceCycles = [2, 1]; }
 363 def M3WriteVLDE    : SchedWriteRes<[M3UnitL,
 364                                     M3UnitNALU]>  { let Latency = 6;
 365                                                     let NumMicroOps = 2;
 366                                                     let ResourceCycles = [2, 1]; }
 367 def M3WriteVLDF    : SchedWriteRes<[M3UnitL,
 368                                     M3UnitL]>     { let Latency = 10;
 369                                                     let NumMicroOps = 2;
 370                                                     let ResourceCycles = [5, 5]; }
 371 def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
 372                                     M3UnitNALU,
 373                                     M3UnitNALU]>  { let Latency = 7;
 374                                                     let NumMicroOps = 3;
 375                                                     let ResourceCycles = [2, 1, 1]; }
 376 def M3WriteVLDH    : SchedWriteRes<[M3UnitL,
 377                                     M3UnitNALU,
 378                                     M3UnitNALU]>  { let Latency = 6;
 379                                                     let NumMicroOps = 3;
 380                                                     let ResourceCycles = [2, 1, 1]; }
 381 def M3WriteVLDI    : SchedWriteRes<[M3UnitL,
 382                                     M3UnitL,
 383                                     M3UnitL]>     { let Latency = 12;
 384                                                     let NumMicroOps = 3;
 385                                                     let ResourceCycles = [6, 6, 6]; }
 386 def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
 387                                     M3UnitNALU,
 388                                     M3UnitNALU,
 389                                     M3UnitNALU]>  { let Latency = 7;
 390                                                     let NumMicroOps = 4;
 391                                                     let ResourceCycles = [2, 1, 1, 1]; }
 392 def M3WriteVLDK    : SchedWriteRes<[M3UnitL,
 393                                     M3UnitNALU,
 394                                     M3UnitNALU,
 395                                     M3UnitNALU,
 396                                     M3UnitNALU]>  { let Latency = 9;
 397                                                     let NumMicroOps = 5;
 398                                                     let ResourceCycles = [4, 1, 1, 1, 1]; }
 399 def M3WriteVLDL    : SchedWriteRes<[M3UnitL,
 400                                     M3UnitNALU,
 401                                     M3UnitNALU,
 402                                     M3UnitL,
 403                                     M3UnitNALU]>  { let Latency = 6;
 404                                                     let NumMicroOps = 5;
 405                                                     let ResourceCycles = [6, 1, 1, 6, 1]; }
 406 def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
 407                                     M3UnitNALU,
 408                                     M3UnitNALU,
 409                                     M3UnitL,
 410                                     M3UnitNALU,
 411                                     M3UnitNALU]>  { let Latency = 7;
 412                                                     let NumMicroOps = 6;
 413                                                     let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
 414 def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
 415                                     M3UnitL,
 416                                     M3UnitL,
 417                                     M3UnitL]>     { let Latency = 14;
 418                                                     let NumMicroOps = 4;
 419                                                     let ResourceCycles = [6, 6, 6, 6]; }
 420 def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
 421 def M3WriteVSTB    : WriteSequence<[WriteVST], 3>;
 422 def M3WriteVSTC    : WriteSequence<[WriteVST], 4>;
 423 def M3WriteVSTD    : SchedWriteRes<[M3UnitS,
 424                                     M3UnitFST,
 425                                     M3UnitS,
 426                                     M3UnitFST]>   { let Latency = 7;
 427                                                     let NumMicroOps = 4;
 428                                                     let ResourceCycles = [1, 3, 1, 3]; }
 429 def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
 430                                     M3UnitFST,
 431                                     M3UnitS,
 432                                     M3UnitFST,
 433                                     M3UnitS,
 434                                     M3UnitFST]>   { let Latency = 8;
 435                                                     let NumMicroOps = 6;
 436                                                     let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
 437 def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
 438                                     M3UnitFST,
 439                                     M3UnitFST,
 440                                     M3UnitS,
 441                                     M3UnitFST,
 442                                     M3UnitS,
 443                                     M3UnitFST]>   { let Latency = 15;
 444                                                     let NumMicroOps = 7;
 445                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
 446 def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
 447                                     M3UnitFST,
 448                                     M3UnitFST,
 449                                     M3UnitS,
 450                                     M3UnitFST,
 451                                     M3UnitS,
 452                                     M3UnitFST,
 453                                     M3UnitS,
 454                                     M3UnitFST]>   { let Latency = 16;
 455                                                     let NumMicroOps = 9;
 456                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 457 def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
 458                                     M3UnitFST,
 459                                     M3UnitFST,
 460                                     M3UnitS,
 461                                     M3UnitFST]>   { let Latency = 14;
 462                                                     let NumMicroOps = 5;
 463                                                     let ResourceCycles = [1, 3, 3, 1, 3]; }
 464 def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
 465                                     M3UnitFST,
 466                                     M3UnitFST,
 467                                     M3UnitS,
 468                                     M3UnitFST,
 469                                     M3UnitS,
 470                                     M3UnitFST,
 471                                     M3UnitS,
 472                                     M3UnitFST]>   { let Latency = 17;
 473                                                     let NumMicroOps = 9;
 474                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 475
 476 // Special cases.
 477 def M3WriteAES     : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 1; }
 478 def M3WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
 479                                         SchedVar<NoSchedPred,  [M3WriteZ0]>]>;
 480 def M3WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
 481                                         SchedVar<NoSchedPred,       [M3WriteNALU1]>]>;
 482
 483 // Fast forwarding.
 484 def M3ReadAES      : SchedReadAdvance<1, [M3WriteAES]>;
 485 def M3ReadFMAC     : SchedReadAdvance<1, [M3WriteFMAC4,
 486                                           M3WriteFMAC5]>;
 487 def M3ReadNMUL     : SchedReadAdvance<1, [M3WriteNMUL3]>;
 488
 489 // Branch instructions
 490 def : InstRW<[M3WriteB1], (instrs Bcc)>;
 491 def : InstRW<[M3WriteA1], (instrs BL)>;
 492 def : InstRW<[M3WriteBX], (instrs BLR)>;
 493 def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
 494 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
 495
 496 // Arithmetic and logical integer instructions.
 497 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 498 def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
 499 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 500 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 501 def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
 502 def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
 503
 504 // Move instructions.
 505 def : InstRW<[M3WriteCOPY], (instrs COPY)>;
 506 def : InstRW<[M3WriteZ0],   (instrs ADR, ADRP)>;
 507 def : InstRW<[M3WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 508
 509 // Divide and multiply instructions.
 510
 511 // Miscellaneous instructions.
 512
 513 // Load instructions.
 514 def : InstRW<[M3WriteLD,
 515               WriteLDHi,
 516               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 517 def : InstRW<[M3WriteLB,
 518               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 519 def : InstRW<[M3WriteLX,
 520               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 521 def : InstRW<[M3WriteLB,
 522               ReadAdrBase], (instrs PRFMroW)>;
 523 def : InstRW<[M3WriteLX,
 524               ReadAdrBase], (instrs PRFMroX)>;
 525
 526 // Store instructions.
 527 def : InstRW<[M3WriteSB,
 528               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 529 def : InstRW<[WriteST,
 530               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 531
 532 // FP data instructions.
 533 def : InstRW<[M3WriteNSHF1],  (instregex "^FABS[DS]r")>;
 534 def : InstRW<[M3WriteFADD2],  (instregex "^F(ADD|SUB)[DS]rr")>;
 535 def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>;
 536 def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>;
 537 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN).+rr")>;
 538 def : InstRW<[M3WriteFMAC3],  (instregex "^FN?MUL[DS]rr")>;
 539 def : InstRW<[M3WriteFMAC4,
 540               M3ReadFMAC],    (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 541 def : InstRW<[M3WriteNALU1],  (instregex "^FNEG[DS]r")>;
 542 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
 543 def : InstRW<[M3WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 544 def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>;
 545 def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>;
 546
 547 // FP miscellaneous instructions.
 548 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT[DHS][DHS]r")>;
 549 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
 550 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
 551 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>;
 552 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 553 def : InstRW<[M3WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 554 def : InstRW<[M3WriteNMSC1],  (instregex "^FRECPXv1")>;
 555 def : InstRW<[M3WriteFMAC4,
 556               M3ReadFMAC],    (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 557 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS]r")>;
 558 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX]r")>;
 559 def : InstRW<[M3WriteNEONI],  (instregex "^FMOV(DX|XD)Highr")>;
 560
 561 // FP load instructions.
 562 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 563 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 564 def : InstRW<[WriteVLD,
 565               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 566 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 567 def : InstRW<[M3WriteLE,
 568               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 569 def : InstRW<[WriteVLD,
 570               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
 571 def : InstRW<[M3WriteLY,
 572               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 573 def : InstRW<[WriteVLD,
 574               M3WriteLH],   (instregex "^LDN?P[DS]i")>;
 575 def : InstRW<[M3WriteLA,
 576               M3WriteLH],   (instregex "^LDN?PQi")>;
 577 def : InstRW<[M3WriteLB,
 578               M3WriteLH,
 579               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 580 def : InstRW<[M3WriteLC,
 581               M3WriteLH,
 582               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 583
 584 // FP store instructions.
 585 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 586 def : InstRW<[WriteVST,
 587               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 588 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 589 def : InstRW<[M3WriteSA,
 590               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
 591 def : InstRW<[M3WriteSA,
 592               ReadAdrBase], (instregex "^STRQroW")>;
 593 def : InstRW<[WriteVST,
 594               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
 595 def : InstRW<[M3WriteSY,
 596               ReadAdrBase], (instregex "^STRQroX")>;
 597 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 598 def : InstRW<[WriteVST,
 599               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 600 def : InstRW<[M3WriteSC,
 601               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 602
 603 // ASIMD instructions.
 604 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>;
 605 def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>;
 606 def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>;
 607 def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
 608 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
 609 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>;
 610 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>;
 611 def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>;
 612 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>;
 613 def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>;
 614 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>;
 615 def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 616 def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>;
 617 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 618 def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
 619 def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
 620 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
 621 def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>;
 622 def : InstRW<[M3WriteNMUL3,
 623               M3ReadNMUL],   (instregex "^ML[AS]v")>;
 624 def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>;
 625 def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>;
 626 def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>;
 627 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>;
 628 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>;
 629 def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>;
 630 def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
 631 def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>;
 632 def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>;
 633 def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 634 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>;
 635 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 636
 637 // ASIMD FP instructions.
 638 def : InstRW<[M3WriteNSHF1],  (instregex "^FABSv")>;
 639 def : InstRW<[M3WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v")>;
 640 def : InstRW<[M3WriteNEONA],  (instregex "^FADDP")>;
 641 def : InstRW<[M3WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 642 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT(L|N|XN)v")>;
 643 def : InstRW<[M3WriteFCVT2],  (instregex "^FCVT[AMNPZ][SU]v")>;
 644 def : InstRW<[M3WriteFCVT2],  (instregex "^[SU]CVTFv")>;
 645 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
 646 def : InstRW<[M3WriteNEONV],  (instrs FDIVv4f32)>;
 647 def : InstRW<[M3WriteNEONW],  (instrs FDIVv2f64)>;
 648 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 649 def : InstRW<[M3WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 650 def : InstRW<[M3WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 651 def : InstRW<[M3WriteFMAC3],  (instregex "^FMULX?v.[fi]")>;
 652 def : InstRW<[M3WriteFMAC4,
 653               M3ReadFMAC],    (instregex "^FML[AS]v.f")>;
 654 def : InstRW<[M3WriteFMAC5,
 655               M3ReadFMAC],    (instregex "^FML[AS]v.i")>;
 656 def : InstRW<[M3WriteNALU1],  (instregex "^FNEGv")>;
 657 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 658 def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>;
 659 def : InstRW<[M3WriteNEONX],  (instrs FSQRTv4f32)>;
 660 def : InstRW<[M3WriteNEONY],  (instrs FSQRTv2f64)>;
 661
 662 // ASIMD miscellaneous instructions.
 663 def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
 664 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>;
 665 def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
 666 def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
 667 def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
 668 def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
 669 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
 670 def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
 671 def : InstRW<[M3WriteMOVI],  (instregex "^MOVI")>;
 672 def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
 673 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 674 def : InstRW<[M3WriteFMAC4,
 675               M3ReadFMAC],   (instregex "^F(RECP|RSQRT)Sv")>;
 676 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
 677 def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
 678 def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>;
 679 def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>;
 680 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
 681
 682 // ASIMD load instructions.
 683 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 684 def : InstRW<[M3WriteL5,
 685               M3WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST")>;
 686 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 687 def : InstRW<[M3WriteL5,
 688               M3WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST")>;
 689
 690 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 691 def : InstRW<[M3WriteVLDA,
 692               M3WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
 693 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 694 def : InstRW<[M3WriteVLDA,
 695               M3WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
 696
 697 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 698 def : InstRW<[M3WriteVLDB,
 699               M3WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
 700 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 701 def : InstRW<[M3WriteVLDB,
 702               M3WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
 703
 704 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 705 def : InstRW<[M3WriteVLDC,
 706               M3WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
 707 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 708 def : InstRW<[M3WriteVLDC,
 709               M3WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
 710
 711 def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>;
 712 def : InstRW<[M3WriteVLDD,
 713               M3WriteA1],   (instregex "LD1i(8|16|32)_POST")>;
 714 def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>;
 715 def : InstRW<[M3WriteVLDE,
 716               M3WriteA1],   (instregex "LD1i(64)_POST")>;
 717
 718 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 719 def : InstRW<[M3WriteL5,
 720               M3WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST")>;
 721 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 722 def : InstRW<[M3WriteL5,
 723               M3WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST")>;
 724
 725 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 726 def : InstRW<[M3WriteVLDF,
 727               M3WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST")>;
 728 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 729 def : InstRW<[M3WriteVLDF,
 730               M3WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
 731
 732 def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>;
 733 def : InstRW<[M3WriteVLDG,
 734               M3WriteA1],   (instregex "LD2i(8|16|32)_POST")>;
 735 def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>;
 736 def : InstRW<[M3WriteVLDH,
 737               M3WriteA1],   (instregex "LD2i(64)_POST")>;
 738
 739 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 740 def : InstRW<[M3WriteVLDA,
 741               M3WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST")>;
 742 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 743 def : InstRW<[M3WriteVLDA,
 744               M3WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST")>;
 745
 746 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 747 def : InstRW<[M3WriteVLDI,
 748               M3WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST")>;
 749 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 750 def : InstRW<[M3WriteVLDI,
 751               M3WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
 752
 753 def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 754 def : InstRW<[M3WriteVLDJ,
 755               M3WriteA1],   (instregex "LD3i(8|16|32)_POST")>;
 756 def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>;
 757 def : InstRW<[M3WriteVLDL,
 758               M3WriteA1],   (instregex "LD3i(64)_POST")>;
 759
 760 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 761 def : InstRW<[M3WriteVLDB,
 762               M3WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST")>;
 763 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 764 def : InstRW<[M3WriteVLDB,
 765               M3WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST")>;
 766
 767 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 768 def : InstRW<[M3WriteVLDN,
 769               M3WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST")>;
 770 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 771 def : InstRW<[M3WriteVLDN,
 772               M3WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
 773
 774 def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 775 def : InstRW<[M3WriteVLDK,
 776               M3WriteA1],   (instregex "LD4i(8|16|32)_POST")>;
 777 def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>;
 778 def : InstRW<[M3WriteVLDM,
 779               M3WriteA1],   (instregex "LD4i(64)_POST")>;
 780
 781 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 782 def : InstRW<[M3WriteVLDC,
 783               M3WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST")>;
 784 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 785 def : InstRW<[M3WriteVLDC,
 786               M3WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST")>;
 787
 788 // ASIMD store instructions.
 789 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 790 def : InstRW<[WriteVST,
 791               WriteAdr],    (instregex "ST1Onev(8b|4h|2s|1d)_POST")>;
 792 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 793 def : InstRW<[WriteVST,
 794               WriteAdr],    (instregex "ST1Onev(16b|8h|4s|2d)_POST")>;
 795
 796 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 797 def : InstRW<[M3WriteVSTA,
 798               WriteAdr],    (instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
 799 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 800 def : InstRW<[M3WriteVSTA,
 801               WriteAdr],    (instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
 802
 803 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 804 def : InstRW<[M3WriteVSTB,
 805               WriteAdr],    (instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
 806 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 807 def : InstRW<[M3WriteVSTB,
 808               WriteAdr],    (instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
 809
 810 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 811 def : InstRW<[M3WriteVSTC,
 812               WriteAdr],    (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
 813 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 814 def : InstRW<[M3WriteVSTC,
 815               WriteAdr],    (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
 816
 817 def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>;
 818 def : InstRW<[M3WriteVSTD,
 819               WriteAdr],    (instregex "ST1i(8|16|32|64)_POST")>;
 820
 821 def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 822 def : InstRW<[M3WriteVSTD,
 823               WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST")>;
 824 def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 825 def : InstRW<[M3WriteVSTE,
 826               WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
 827
 828 def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>;
 829 def : InstRW<[M3WriteVSTD,
 830               WriteAdr],    (instregex "ST2i(8|16|32)_POST")>;
 831 def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>;
 832 def : InstRW<[M3WriteVSTD,
 833               WriteAdr],    (instregex "ST2i(64)_POST")>;
 834
 835 def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 836 def : InstRW<[M3WriteVSTF,
 837               WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST")>;
 838 def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 839 def : InstRW<[M3WriteVSTG,
 840               WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
 841
 842 def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>;
 843 def : InstRW<[M3WriteVSTH,
 844               WriteAdr],    (instregex "ST3i(8|16|32)_POST")>;
 845 def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>;
 846 def : InstRW<[M3WriteVSTF,
 847               WriteAdr],    (instregex "ST3i(64)_POST")>;
 848
 849 def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
 850 def : InstRW<[M3WriteVSTF,
 851               WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST")>;
 852 def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 853 def : InstRW<[M3WriteVSTI,
 854               WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
 855
 856 def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>;
 857 def : InstRW<[M3WriteVSTF,
 858               WriteAdr],    (instregex "ST4i(8|16|32|64)_POST")>;
 859
 860 // Cryptography instructions.
 861 def : InstRW<[M3WriteAES],    (instregex "^AES[DE]")>;
 862 def : InstRW<[M3WriteAES,
 863               M3ReadAES],     (instregex "^AESI?MC")>;
 864
 865 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
 866
 867 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
 868 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>;
 869 def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>;
 870
 871 // CRC instructions.
 872 def : InstRW<[M3WriteC2], (instregex "^CRC32")>;
 873
 874 } // SchedModel = ExynosM3Model