1 //=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the Samsung Exynos M5 to support
10 // instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide
16 // in-order stage for decode and dispatch and a wider issue stage.
17 // The execution units and loads and stores are out-of-order.
19 def ExynosM5Model : SchedMachineModel {
20 let IssueWidth = 6; // Up to 6 uops per cycle.
21 let MicroOpBufferSize = 228; // ROB size.
22 let LoopMicroOpBufferSize = 60; // Based on the instruction queue size.
23 let LoadLatency = 4; // Optimistic load cases.
24 let MispredictPenalty = 15; // Minimum branch misprediction penalty.
25 let CompleteModel = 1; // Use the default model otherwise.
27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
31 //===----------------------------------------------------------------------===//
32 // Define each kind of processor resource and number available on the Exynos-M5.
34 let SchedModel = ExynosM5Model in {
36 def M5UnitA : ProcResource<2>; // Simple integer
37 def M5UnitC : ProcResource<2>; // Simple and complex integer
38 let Super = M5UnitC, BufferSize = 1 in
39 def M5UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M5UnitE : ProcResource<2>; // Simple 32-bit integer
41 let Super = M5UnitC in
42 def M5UnitF : ProcResource<2>; // CRC (inside C)
43 def M5UnitB : ProcResource<1>; // Branch
44 def M5UnitL0 : ProcResource<1>; // Load
45 def M5UnitS0 : ProcResource<1>; // Store
46 def M5PipeLS : ProcResource<1>; // Load/Store
47 let Super = M5PipeLS in {
48 def M5UnitL1 : ProcResource<1>;
49 def M5UnitS1 : ProcResource<1>;
51 def M5PipeF0 : ProcResource<1>; // FP #0
52 let Super = M5PipeF0 in {
53 def M5UnitFMAC0 : ProcResource<1>; // FP multiplication
54 def M5UnitFADD0 : ProcResource<1>; // Simple FP
55 def M5UnitNALU0 : ProcResource<1>; // Simple vector
56 def M5UnitNDOT0 : ProcResource<1>; // Dot product vector
57 def M5UnitNHAD : ProcResource<1>; // Horizontal vector
58 def M5UnitNMSC : ProcResource<1>; // FP and vector miscellanea
59 def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication
60 def M5UnitNSHT0 : ProcResource<1>; // Vector shifting
61 def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling
62 def M5UnitNCRY0 : ProcResource<1>; // Cryptographic
64 def M5PipeF1 : ProcResource<1>; // FP #1
65 let Super = M5PipeF1 in {
66 def M5UnitFMAC1 : ProcResource<1>; // FP multiplication
67 def M5UnitFADD1 : ProcResource<1>; // Simple FP
68 def M5UnitFCVT0 : ProcResource<1>; // FP conversion
69 def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized)
70 def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
71 def M5UnitFST0 : ProcResource<1>; // FP store
72 def M5UnitNALU1 : ProcResource<1>; // Simple vector
73 def M5UnitNDOT1 : ProcResource<1>; // Dot product vector
74 def M5UnitNSHT1 : ProcResource<1>; // Vector shifting
75 def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling
77 def M5PipeF2 : ProcResource<1>; // FP #2
78 let Super = M5PipeF2 in {
79 def M5UnitFMAC2 : ProcResource<1>; // FP multiplication
80 def M5UnitFADD2 : ProcResource<1>; // Simple FP
81 def M5UnitFCVT1 : ProcResource<1>; // FP conversion
82 def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized)
83 def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
84 def M5UnitFST1 : ProcResource<1>; // FP store
85 def M5UnitNALU2 : ProcResource<1>; // Simple vector
86 def M5UnitNDOT2 : ProcResource<1>; // Dot product vector
87 def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication
88 def M5UnitNSHT2 : ProcResource<1>; // Vector shifting
89 def M5UnitNCRY1 : ProcResource<1>; // Cryptographic
92 def M5UnitAX : ProcResGroup<[M5UnitA,
94 def M5UnitAW : ProcResGroup<[M5UnitA,
97 def M5UnitL : ProcResGroup<[M5UnitL0,
99 def M5UnitS : ProcResGroup<[M5UnitS0,
101 def M5UnitFMAC : ProcResGroup<[M5UnitFMAC0,
104 def M5UnitFADD : ProcResGroup<[M5UnitFADD0,
107 def M5UnitFCVT : ProcResGroup<[M5UnitFCVT0,
109 def M5UnitFDIV : ProcResGroup<[M5UnitFDIV0,
111 def M5UnitFSQR : ProcResGroup<[M5UnitFSQR0,
113 def M5UnitFST : ProcResGroup<[M5UnitFST0,
115 def M5UnitNALU : ProcResGroup<[M5UnitNALU0,
118 def M5UnitNDOT : ProcResGroup<[M5UnitNDOT0,
121 def M5UnitNMUL : ProcResGroup<[M5UnitNMUL0,
123 def M5UnitNSHT : ProcResGroup<[M5UnitNSHT0,
126 def M5UnitNSHF : ProcResGroup<[M5UnitNSHF0,
128 def M5UnitNCRY : ProcResGroup<[M5UnitNCRY0,
131 //===----------------------------------------------------------------------===//
132 // Resources details.
134 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
135 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
136 let NumMicroOps = 0; }
137 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
138 let NumMicroOps = 0; }
140 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
141 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
142 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
143 let ResourceCycles = [2]; }
144 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
145 let ResourceCycles = [2]; }
146 def M5WriteAB : SchedWriteRes<[M5UnitAX,
148 M5UnitE]> { let Latency = 2;
149 let NumMicroOps = 2; }
150 def M5WriteAC : SchedWriteRes<[M5UnitAX,
152 M5UnitC]> { let Latency = 3;
153 let NumMicroOps = 3; }
154 def M5WriteAD : SchedWriteRes<[M5UnitAW,
155 M5UnitC]> { let Latency = 2;
156 let NumMicroOps = 2; }
157 def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
158 let NumMicroOps = 2; }
159 def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
160 let NumMicroOps = 2; }
161 def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>,
162 SchedVar<ExynosArithPred, [M5WriteA1W]>,
163 SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
164 SchedVar<NoSchedPred, [M5WriteAAW]>]>;
165 def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M5WriteZ0]>,
166 SchedVar<ExynosArithPred, [M5WriteA1X]>,
167 SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
168 SchedVar<NoSchedPred, [M5WriteAAX]>]>;
169 def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>,
170 SchedVar<ExynosArithPred, [M5WriteA1W]>,
171 SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
172 SchedVar<NoSchedPred, [M5WriteAAW]>]>;
173 def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred, [M5WriteZ0]>,
174 SchedVar<ExynosArithPred, [M5WriteA1X]>,
175 SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
176 SchedVar<NoSchedPred, [M5WriteAAX]>]>;
177 def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1W]>,
178 SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
179 SchedVar<NoSchedPred, [M5WriteAAW]>]>;
180 def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M5WriteA1X]>,
181 SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
182 SchedVar<NoSchedPred, [M5WriteAAX]>]>;
183 def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>,
184 SchedVar<NoSchedPred, [M5WriteAFW]>]>;
185 def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>,
186 SchedVar<NoSchedPred, [M5WriteAFX]>]>;
188 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
189 def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
190 SchedVar<NoSchedPred, [M5WriteAB]>]>;
192 def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
193 def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
194 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
195 let ResourceCycles = [2]; }
197 def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
198 let ResourceCycles = [10]; }
199 def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
200 let ResourceCycles = [16]; }
202 def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
204 def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
205 def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
206 def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
207 def M5WriteLA : SchedWriteRes<[M5UnitL,
208 M5UnitL]> { let Latency = 6;
209 let NumMicroOps = 1; }
210 def M5WriteLB : SchedWriteRes<[M5UnitAX,
211 M5UnitL]> { let Latency = 6;
212 let NumMicroOps = 2; }
213 def M5WriteLC : SchedWriteRes<[M5UnitAX,
215 M5UnitL]> { let Latency = 6;
216 let NumMicroOps = 2; }
217 def M5WriteLD : SchedWriteRes<[M5UnitAX,
218 M5UnitL]> { let Latency = 4;
219 let NumMicroOps = 2; }
220 def M5WriteLE : SchedWriteRes<[M5UnitAX,
221 M5UnitL]> { let Latency = 7;
222 let NumMicroOps = 2; }
223 def M5WriteLFW : SchedWriteRes<[M5UnitAW,
227 M5UnitL]> { let Latency = 15;
229 let ResourceCycles = [1, 1, 1, 1, 15]; }
230 def M5WriteLFX : SchedWriteRes<[M5UnitAX,
234 M5UnitL]> { let Latency = 15;
236 let ResourceCycles = [1, 1, 1, 1, 15]; }
237 def M5WriteLGW : SchedWriteRes<[M5UnitAW,
238 M5UnitL]> { let Latency = 13;
240 let ResourceCycles = [1, 13]; }
241 def M5WriteLGX : SchedWriteRes<[M5UnitAX,
242 M5UnitL]> { let Latency = 13;
244 let ResourceCycles = [1, 13]; }
245 def M5WriteLH : SchedWriteRes<[]> { let Latency = 6;
246 let NumMicroOps = 0; }
247 def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
248 SchedVar<NoSchedPred, [M5WriteL4]>]>;
249 def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>,
250 SchedVar<NoSchedPred, [M5WriteL6]>]>;
252 def M5WriteS1 : SchedWriteRes<[M5UnitS]> { let Latency = 1; }
253 def M5WriteSA : SchedWriteRes<[M5UnitS0]> { let Latency = 4; }
254 def M5WriteSB : SchedWriteRes<[M5UnitAX,
255 M5UnitS]> { let Latency = 2;
256 let NumMicroOps = 1; }
257 def M5WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>,
258 SchedVar<NoSchedPred, [M5WriteS1]>]>;
260 def M5ReadAdrBase : SchedReadVariant<[SchedVar<
264 ExynosScaledIdxFn]>>, [ReadDefault]>,
265 SchedVar<NoSchedPred, [ReadDefault]>]>;
267 def M5WriteNEONB : SchedWriteRes<[M5UnitNALU,
268 M5UnitS0]> { let Latency = 5;
269 let NumMicroOps = 2; }
270 def M5WriteNEONH : SchedWriteRes<[M5UnitNALU,
271 M5UnitS0]> { let Latency = 2;
272 let NumMicroOps = 2; }
273 def M5WriteNEONI : SchedWriteRes<[M5UnitS0,
274 M5UnitNSHF]> { let Latency = 6;
275 let NumMicroOps = 2; }
276 def M5WriteNEONK : SchedWriteRes<[M5UnitNSHF,
278 M5UnitS0]> { let Latency = 5;
279 let NumMicroOps = 2; }
280 def M5WriteNEONN : SchedWriteRes<[M5UnitNMSC,
281 M5UnitNMSC]> { let Latency = 5;
283 let ResourceCycles = [7, 7]; }
284 def M5WriteNEONO : SchedWriteRes<[M5UnitNMSC,
286 M5UnitNMSC]> { let Latency = 8;
288 let ResourceCycles = [10, 10, 10]; }
289 def M5WriteNEONP : SchedWriteRes<[M5UnitNSHF,
291 M5UnitFCVT]> { let Latency = 7;
292 let NumMicroOps = 2; }
293 def M5WriteNEONQ : SchedWriteRes<[M5UnitNMSC,
294 M5UnitC]> { let Latency = 3;
295 let NumMicroOps = 1; }
296 def M5WriteNEONU : SchedWriteRes<[M5UnitFSQR,
297 M5UnitFSQR]> { let Latency = 7;
298 let ResourceCycles = [4, 4]; }
299 def M5WriteNEONV : SchedWriteRes<[M5UnitFDIV,
300 M5UnitFDIV]> { let Latency = 7;
301 let ResourceCycles = [6, 6]; }
302 def M5WriteNEONW : SchedWriteRes<[M5UnitFDIV,
303 M5UnitFDIV]> { let Latency = 12;
304 let ResourceCycles = [9, 9]; }
305 def M5WriteNEONX : SchedWriteRes<[M5UnitFSQR,
306 M5UnitFSQR]> { let Latency = 8;
307 let ResourceCycles = [5, 5]; }
308 def M5WriteNEONY : SchedWriteRes<[M5UnitFSQR,
309 M5UnitFSQR]> { let Latency = 12;
310 let ResourceCycles = [9, 9]; }
311 def M5WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
312 SchedVar<NoSchedPred, [M5WriteNEONN]>]>;
314 def M5WriteFADD2 : SchedWriteRes<[M5UnitFADD]> { let Latency = 2; }
316 def M5WriteFCVT2 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 2; }
317 def M5WriteFCVT2A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
318 def M5WriteFCVT3 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 3; }
319 def M5WriteFCVT3A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
320 def M5WriteFCVTA : SchedWriteRes<[M5UnitFCVT0,
321 M5UnitS0]> { let Latency = 3;
322 let NumMicroOps = 1; }
323 def M5WriteFCVTB : SchedWriteRes<[M5UnitFCVT,
324 M5UnitS0]> { let Latency = 4;
325 let NumMicroOps = 1; }
326 def M5WriteFCVTC : SchedWriteRes<[M5UnitFCVT,
327 M5UnitS0]> { let Latency = 6;
328 let NumMicroOps = 1; }
330 def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5;
331 let ResourceCycles = [2]; }
332 def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7;
333 let ResourceCycles = [4]; }
334 def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12;
335 let ResourceCycles = [9]; }
337 def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; }
338 def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; }
339 def M5WriteFMAC5 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 5; }
341 def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5;
342 let ResourceCycles = [2]; }
343 def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7;
344 let ResourceCycles = [4]; }
345 def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8;
346 let ResourceCycles = [5]; }
347 def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12;
348 let ResourceCycles = [9]; }
350 def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; }
351 def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; }
353 def M5WriteNDOT2 : SchedWriteRes<[M5UnitNDOT]> { let Latency = 2; }
355 def M5WriteNCRY2 : SchedWriteRes<[M5UnitNCRY]> { let Latency = 2; }
356 def M5WriteNCRY1A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }
357 def M5WriteNCRY2A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; }
358 def M5WriteNCRY3A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; }
359 def M5WriteNCRY5A : SchedWriteRes<[M5UnitNCRY]> { let Latency = 5; }
361 def M5WriteNHAD1 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 1; }
362 def M5WriteNHAD3 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 3; }
364 def M5WriteNMSC1 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 1; }
365 def M5WriteNMSC2 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 2; }
367 def M5WriteNMUL3 : SchedWriteRes<[M5UnitNMUL]> { let Latency = 3; }
369 def M5WriteNSHF1 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 1; }
370 def M5WriteNSHF2 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; }
371 def M5WriteNSHFA : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; }
372 def M5WriteNSHFB : SchedWriteRes<[M5UnitNSHF]> { let Latency = 4;
373 let NumMicroOps = 2; }
374 def M5WriteNSHFC : SchedWriteRes<[M5UnitNSHF]> { let Latency = 6;
375 let NumMicroOps = 3; }
376 def M5WriteNSHFD : SchedWriteRes<[M5UnitNSHF]> { let Latency = 8;
377 let NumMicroOps = 4; }
379 def M5WriteNSHT2 : SchedWriteRes<[M5UnitNSHT]> { let Latency = 2; }
380 def M5WriteNSHT4A : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; }
382 def M5WriteVLDA : SchedWriteRes<[M5UnitL,
383 M5UnitL]> { let Latency = 6;
384 let NumMicroOps = 2; }
385 def M5WriteVLDB : SchedWriteRes<[M5UnitL,
387 M5UnitL]> { let Latency = 7;
388 let NumMicroOps = 3; }
389 def M5WriteVLDC : SchedWriteRes<[M5UnitL,
392 M5UnitL]> { let Latency = 7;
393 let NumMicroOps = 4; }
394 def M5WriteVLDD : SchedWriteRes<[M5UnitL,
395 M5UnitNSHF]> { let Latency = 7;
397 let ResourceCycles = [2, 1]; }
398 def M5WriteVLDF : SchedWriteRes<[M5UnitL,
399 M5UnitL]> { let Latency = 11;
401 let ResourceCycles = [6, 5]; }
402 def M5WriteVLDG : SchedWriteRes<[M5UnitL,
404 M5UnitNSHF]> { let Latency = 7;
406 let ResourceCycles = [2, 1, 1]; }
407 def M5WriteVLDI : SchedWriteRes<[M5UnitL,
409 M5UnitL]> { let Latency = 13;
410 let NumMicroOps = 3; }
411 def M5WriteVLDJ : SchedWriteRes<[M5UnitL,
414 M5UnitNSHF]> { let Latency = 8;
415 let NumMicroOps = 4; }
416 def M5WriteVLDK : SchedWriteRes<[M5UnitL,
420 M5UnitNSHF]> { let Latency = 8;
421 let NumMicroOps = 5; }
422 def M5WriteVLDL : SchedWriteRes<[M5UnitL,
426 M5UnitNSHF]> { let Latency = 8;
427 let NumMicroOps = 5; }
428 def M5WriteVLDM : SchedWriteRes<[M5UnitL,
433 M5UnitNSHF]> { let Latency = 8;
434 let NumMicroOps = 6; }
435 def M5WriteVLDN : SchedWriteRes<[M5UnitL,
438 M5UnitL]> { let Latency = 15;
440 let ResourceCycles = [2, 2, 2, 2]; }
442 def M5WriteVST1 : SchedWriteRes<[M5UnitS,
443 M5UnitFST]> { let Latency = 1;
444 let NumMicroOps = 1; }
445 def M5WriteVSTA : SchedWriteRes<[M5UnitS,
448 M5UnitFST]> { let Latency = 2;
449 let NumMicroOps = 2; }
450 def M5WriteVSTB : SchedWriteRes<[M5UnitS,
455 M5UnitFST]> { let Latency = 3;
456 let NumMicroOps = 3; }
457 def M5WriteVSTC : SchedWriteRes<[M5UnitS,
464 M5UnitFST]> { let Latency = 4;
465 let NumMicroOps = 4; }
466 def M5WriteVSTD : SchedWriteRes<[M5UnitS,
467 M5UnitFST]> { let Latency = 2; }
468 def M5WriteVSTE : SchedWriteRes<[M5UnitS,
471 M5UnitFST]> { let Latency = 2;
472 let NumMicroOps = 1; }
473 def M5WriteVSTF : SchedWriteRes<[M5UnitNSHF,
476 M5UnitFST]> { let Latency = 4;
477 let NumMicroOps = 3; }
478 def M5WriteVSTG : SchedWriteRes<[M5UnitNSHF,
484 M5UnitFST]> { let Latency = 4;
485 let NumMicroOps = 5; }
486 def M5WriteVSTH : SchedWriteRes<[M5UnitS0,
487 M5UnitFST]> { let Latency = 1;
488 let NumMicroOps = 1; }
489 def M5WriteVSTI : SchedWriteRes<[M5UnitNSHF,
500 M5UnitFST]> { let Latency = 8;
502 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
503 def M5WriteVSTJ : SchedWriteRes<[M5UnitA,
505 M5UnitFST]> { let Latency = 1;
506 let NumMicroOps = 1; }
507 def M5WriteVSTK : SchedWriteRes<[M5UnitAX,
509 M5UnitFST]> { let Latency = 3;
510 let NumMicroOps = 2; }
511 def M5WriteVSTL : SchedWriteRes<[M5UnitNSHF,
516 M5UnitFST]> { let Latency = 4;
518 let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
519 def M5WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
520 SchedVar<NoSchedPred, [WriteVST]>]>;
523 def M5WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>,
524 SchedVar<NoSchedPred, [M5WriteZ0]>]>;
525 def M5WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>,
526 SchedVar<NoSchedPred, [M5WriteNALU1]>]>;
529 def M5ReadFM1 : SchedReadAdvance<+1, [M5WriteF2]>;
530 def M5ReadAESM2 : SchedReadAdvance<+2, [M5WriteNCRY2]>;
531 def M5ReadFMACM1 : SchedReadAdvance<+1, [M5WriteFMAC4,
533 def M5ReadNMULM1 : SchedReadAdvance<+1, [M5WriteNMUL3]>;
535 //===----------------------------------------------------------------------===//
536 // Coarse scheduling model.
538 // Branch instructions.
539 def : SchedAlias<WriteBr, M5WriteZ0>;
540 def : SchedAlias<WriteBrReg, M5WriteC1>;
542 // Arithmetic and logical integer instructions.
543 def : SchedAlias<WriteI, M5WriteA1W>;
544 def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
545 def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
546 def : SchedAlias<WriteIS, M5WriteA1W>;
548 // Move instructions.
549 def : SchedAlias<WriteImm, M5WriteA1W>;
551 // Divide and multiply instructions.
552 def : SchedAlias<WriteID32, M5WriteD10>;
553 def : SchedAlias<WriteID64, M5WriteD16>;
554 def : SchedAlias<WriteIM32, M5WriteC2>;
555 def : SchedAlias<WriteIM64, M5WriteCA>;
557 // Miscellaneous instructions.
558 def : SchedAlias<WriteExtr, M5WriteAYW>;
561 def : SchedAlias<WriteAdr, M5WriteZ1>;
562 def : SchedAlias<ReadAdrBase, M5ReadAdrBase>;
564 // Load instructions.
565 def : SchedAlias<WriteLD, M5WriteL4>;
566 def : SchedAlias<WriteLDHi, M5WriteZ4>;
567 def : SchedAlias<WriteLDIdx, M5WriteLX>;
569 // Store instructions.
570 def : SchedAlias<WriteST, M5WriteS1>;
571 def : SchedAlias<WriteSTP, M5WriteS1>;
572 def : SchedAlias<WriteSTX, M5WriteS1>;
573 def : SchedAlias<WriteSTIdx, M5WriteSX>;
575 // Atomic load and store instructions.
576 def : SchedAlias<WriteAtomic, M5WriteLGW>;
578 // FP data instructions.
579 def : SchedAlias<WriteF, M5WriteFADD2>;
580 def : SchedAlias<WriteFCmp, M5WriteNMSC2>;
581 def : SchedAlias<WriteFDiv, M5WriteFDIV12>;
582 def : SchedAlias<WriteFMul, M5WriteFMAC3>;
584 // FP miscellaneous instructions.
585 def : SchedAlias<WriteFCvt, M5WriteFCVT2>;
586 def : SchedAlias<WriteFImm, M5WriteNALU1>;
587 def : SchedAlias<WriteFCopy, M5WriteNALU2>;
589 // FP load instructions.
590 def : SchedAlias<WriteVLD, M5WriteL6>;
592 // FP store instructions.
593 def : SchedAlias<WriteVST, M5WriteVST1>;
595 // ASIMD FP instructions.
596 def : SchedAlias<WriteV, M5WriteNALU1>;
598 // Other miscellaneous instructions.
599 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
600 def : WriteRes<WriteHint, []> { let Latency = 1; }
601 def : WriteRes<WriteSys, []> { let Latency = 1; }
603 //===----------------------------------------------------------------------===//
604 // Generic fast forwarding.
606 // TODO: Add FP register forwarding rules.
608 def : ReadAdvance<ReadI, 0>;
609 def : ReadAdvance<ReadISReg, 0>;
610 def : ReadAdvance<ReadIEReg, 0>;
611 def : ReadAdvance<ReadIM, 0>;
612 // TODO: The forwarding for 32 bits actually saves 2 cycles.
613 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
614 def : ReadAdvance<ReadID, 0>;
615 def : ReadAdvance<ReadExtrHi, 0>;
616 def : ReadAdvance<ReadAdrBase, 0>;
617 def : ReadAdvance<ReadVLD, 0>;
619 //===----------------------------------------------------------------------===//
620 // Finer scheduling model.
622 // Branch instructions
623 def : InstRW<[M5WriteB1], (instrs Bcc)>;
624 def : InstRW<[M5WriteAFX], (instrs BL)>;
625 def : InstRW<[M5WriteBX], (instrs BLR)>;
626 def : InstRW<[M5WriteC1], (instregex "^CBN?Z[WX]")>;
627 def : InstRW<[M5WriteAD], (instregex "^TBN?ZW")>;
628 def : InstRW<[M5WriteAB], (instregex "^TBN?ZX")>;
630 // Arithmetic and logical integer instructions.
631 def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>;
632 def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>;
633 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
634 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
635 def : InstRW<[M5WriteAUW], (instrs ORRWrs)>;
636 def : InstRW<[M5WriteAUX], (instrs ORRXrs)>;
637 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
638 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
639 def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>;
640 def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>;
641 def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>;
642 def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>;
643 def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>;
644 def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>;
645 def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>;
646 def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>;
648 // Move instructions.
649 def : InstRW<[M5WriteCOPY], (instrs COPY)>;
650 def : InstRW<[M5WriteZ0], (instrs ADR, ADRP)>;
651 def : InstRW<[M5WriteZ0], (instregex "^MOV[NZ][WX]i$")>;
653 // Shift instructions.
654 def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>;
655 def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>;
657 // Miscellaneous instructions.
658 def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>;
659 def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>;
660 def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>;
661 def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>;
662 def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>;
663 def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>;
664 def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>;
665 def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>;
667 // Load instructions.
668 def : InstRW<[M5WriteLD,
670 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
671 def : InstRW<[M5WriteL5,
672 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
673 def : InstRW<[WriteLDIdx,
674 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
675 def : InstRW<[M5WriteL5,
676 ReadAdrBase], (instrs PRFMroW)>;
677 def : InstRW<[WriteLDIdx,
678 ReadAdrBase], (instrs PRFMroX)>;
680 // Store instructions.
681 def : InstRW<[M5WriteSB,
682 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
683 def : InstRW<[WriteST,
684 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
686 // Atomic load and store instructions.
687 def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>;
688 def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>;
689 def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>;
690 def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>;
691 def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
692 def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
693 def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>;
694 def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>;
696 // FP data instructions.
697 def : InstRW<[M5WriteNSHF1], (instrs FABSHr, FABSSr,FABSDr)>;
698 def : InstRW<[M5WriteFADD2], (instregex "^F(ADD|SUB)[HSD]rr")>;
699 def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.i(16|32|64)")>;
700 def : InstRW<[M5WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>;
701 def : InstRW<[M5WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>;
702 def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
703 def : InstRW<[M5WriteFDIV5], (instrs FDIVHrr)>;
704 def : InstRW<[M5WriteFDIV7], (instrs FDIVSrr)>;
705 def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>;
706 def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
707 def : InstRW<[M5WriteFMAC3], (instregex "^FN?MUL[HSD]rr")>;
708 def : InstRW<[M5WriteFMAC3], (instrs FMULX16, FMULX32, FMULX64)>;
709 def : InstRW<[M5WriteFMAC4,
710 M5ReadFMACM1], (instregex "^FN?M(ADD|SUB)[HSD]rrr")>;
711 def : InstRW<[M5WriteNALU2], (instrs FNEGHr, FNEGSr, FNEGDr)>;
712 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
713 def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
714 def : InstRW<[M5WriteFSQR5], (instrs FSQRTHr)>;
715 def : InstRW<[M5WriteFSQR8], (instrs FSQRTSr)>;
716 def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>;
718 // FP miscellaneous instructions.
719 def : InstRW<[M5WriteFCVT2], (instregex "^FCVT[HSD][HSD]r")>;
720 def : InstRW<[M5WriteFCVTC], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
721 def : InstRW<[M5WriteFCVTB], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
722 def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>;
723 def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>;
724 def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>;
725 def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>;
726 def : InstRW<[M5WriteNEONI], (instregex "^FMOVXDHighr")>;
727 def : InstRW<[M5WriteNEONK], (instregex "^FMOVDXHighr")>;
728 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
729 def : InstRW<[M5WriteNMSC1], (instregex "^FRECPXv1")>;
730 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
732 // FP load instructions.
733 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
734 def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>;
735 def : InstRW<[WriteVLD,
736 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
737 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
738 def : InstRW<[M5WriteLE,
739 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
740 def : InstRW<[WriteVLD,
741 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
742 def : InstRW<[M5WriteLY,
743 ReadAdrBase], (instrs LDRQroX)>;
744 def : InstRW<[WriteVLD,
745 M5WriteLH], (instregex "^LDN?P[SD]i")>;
746 def : InstRW<[M5WriteLA,
747 M5WriteLH], (instregex "^LDN?PQi")>;
748 def : InstRW<[M5WriteLB,
750 WriteAdr], (instregex "^LDP[SD](post|pre)")>;
751 def : InstRW<[M5WriteLC,
753 WriteAdr], (instregex "^LDPQ(post|pre)")>;
755 // FP store instructions.
756 def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>;
757 def : InstRW<[WriteVST,
758 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>;
759 def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>;
760 def : InstRW<[WriteVST,
761 ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>;
762 def : InstRW<[M5WriteVSTK,
763 ReadAdrBase], (instregex "^STRQroW")>;
764 def : InstRW<[M5WriteVSTY,
765 ReadAdrBase], (instregex "^STRQroX")>;
766 def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>;
767 def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>;
768 def : InstRW<[WriteVST,
769 WriteAdr], (instregex "^STP[SD](post|pre)")>;
770 def : InstRW<[M5WriteVSTJ,
771 WriteAdr], (instregex "^STPQ(post|pre)")>;
773 // ASIMD instructions.
774 def : InstRW<[M5WriteNHAD1], (instregex "^[SU]ABDL?v")>;
775 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ABAL?v")>;
776 def : InstRW<[M5WriteNMSC1], (instregex "^ABSv")>;
777 def : InstRW<[M5WriteNALU2], (instregex "^(ADD|NEG|SUB)v")>;
778 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>;
779 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>;
780 def : InstRW<[M5WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>;
781 def : InstRW<[M5WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>;
782 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>;
783 def : InstRW<[M5WriteNHAD3], (instregex "^(SU|US)QADDv")>;
784 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]RHADDv")>;
785 def : InstRW<[M5WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>;
786 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
787 def : InstRW<[M5WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
788 def : InstRW<[M5WriteNALU2], (instregex "^CMTSTv")>;
789 def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
790 def : InstRW<[M5WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
791 def : InstRW<[M5WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
792 def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
793 def : InstRW<[M5WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>;
794 def : InstRW<[M5WriteNMUL3,
795 M5ReadNMULM1], (instregex "^ML[AS]v")>;
796 def : InstRW<[M5WriteNMUL3,
797 M5ReadNMULM1], (instregex "^SQRDML[AS]H")>;
798 def : InstRW<[M5WriteNMUL3], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
799 def : InstRW<[M5WriteNMUL3,
800 M5ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
801 def : InstRW<[M5WriteNMUL3,
802 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
803 def : InstRW<[M5WriteNMUL3,
804 M5ReadNMULM1], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
805 def : InstRW<[M5WriteNDOT2], (instregex "^[SU]DOT(lane)?v")>;
806 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]ADALPv")>;
807 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
808 def : InstRW<[M5WriteNSHT2], (instregex "^SHL[dv]")>;
809 def : InstRW<[M5WriteNSHT2], (instregex "^S[LR]I[dv]")>;
810 def : InstRW<[M5WriteNSHT2], (instregex "^[SU]SH[LR][dv]")>;
811 def : InstRW<[M5WriteNSHT2], (instregex "^[SU]?SHLLv")>;
812 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
813 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
814 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
816 // ASIMD FP instructions.
817 def : InstRW<[M5WriteNSHF2], (instregex "^FABSv.f(16|32|64)")>;
818 def : InstRW<[M5WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>;
819 def : InstRW<[M5WriteFADD2], (instregex "^FADDPv.f(16|32|64)")>;
820 def : InstRW<[M5WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
821 def : InstRW<[M5WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>;
822 def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
823 def : InstRW<[M5WriteFCVT2], (instregex "^[SU]CVTFv.[fi](16|32|64)")>;
824 def : InstRW<[M5WriteFDIV7], (instrs FDIVv4f16)>;
825 def : InstRW<[M5WriteNEONV], (instrs FDIVv8f16)>;
826 def : InstRW<[M5WriteFDIV7], (instrs FDIVv2f32)>;
827 def : InstRW<[M5WriteNEONV], (instrs FDIVv4f32)>;
828 def : InstRW<[M5WriteNEONW], (instrs FDIVv2f64)>;
829 def : InstRW<[M5WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>;
830 def : InstRW<[M5WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
831 def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
832 def : InstRW<[M5WriteFMAC3], (instregex "^FMULX?v.[fi](16|32|64)")>;
833 def : InstRW<[M5WriteFMAC4,
834 M5ReadFMACM1], (instregex "^FML[AS]v.[fi](16|32|64)")>;
835 def : InstRW<[M5WriteNALU2], (instregex "^FNEGv.f(16|32|64)")>;
836 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
837 def : InstRW<[M5WriteFSQR7], (instrs FSQRTv4f16)>;
838 def : InstRW<[M5WriteNEONU], (instrs FSQRTv8f16)>;
839 def : InstRW<[M5WriteFSQR8], (instrs FSQRTv2f32)>;
840 def : InstRW<[M5WriteNEONX], (instrs FSQRTv4f32)>;
841 def : InstRW<[M5WriteNEONY], (instrs FSQRTv2f64)>;
843 // ASIMD miscellaneous instructions.
844 def : InstRW<[M5WriteNALU2], (instregex "^RBITv")>;
845 def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL)v")>;
846 def : InstRW<[M5WriteNALU2], (instregex "^CL[STZ]v")>;
847 def : InstRW<[M5WriteNEONB], (instregex "^DUPv.+gpr")>;
848 def : InstRW<[M5WriteNSHF2], (instregex "^CPY")>;
849 def : InstRW<[M5WriteNSHF2], (instregex "^DUPv.+lane")>;
850 def : InstRW<[M5WriteNSHF2], (instregex "^EXTv")>;
851 def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>;
852 def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
853 def : InstRW<[M5WriteNEONB], (instregex "^INSv.+gpr")>;
854 def : InstRW<[M5WriteNSHF2], (instregex "^INSv.+lane")>;
855 def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>;
856 def : InstRW<[M5WriteNALU1], (instregex "^FMOVv.f(16|32|64)")>;
857 def : InstRW<[M5WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
858 def : InstRW<[M5WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
859 def : InstRW<[M5WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
860 def : InstRW<[M5WriteNSHF2], (instregex "^REV(16|32|64)v")>;
861 def : InstRW<[M5WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>;
862 def : InstRW<[M5WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>;
863 def : InstRW<[M5WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>;
864 def : InstRW<[M5WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>;
865 def : InstRW<[M5WriteNEONP], (instregex "^[SU]MOVv")>;
866 def : InstRW<[M5WriteNSHF2], (instregex "^(TRN|UZP|ZIP)[12]v")>;
868 // ASIMD load instructions.
869 def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
870 def : InstRW<[WriteVLD,
872 WriteAdr], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
873 def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
874 def : InstRW<[M5WriteVLDA,
876 WriteAdr], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
877 def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
878 def : InstRW<[M5WriteVLDB,
880 WriteAdr], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
881 def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
882 def : InstRW<[M5WriteVLDC,
884 WriteAdr], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
885 def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
886 def : InstRW<[M5WriteVLDD,
888 WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
889 def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
890 def : InstRW<[WriteVLD,
892 WriteAdr], (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
893 def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>;
894 def : InstRW<[M5WriteVLDF,
896 WriteAdr], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
897 def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
898 def : InstRW<[M5WriteVLDG,
900 WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
901 def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
902 def : InstRW<[M5WriteVLDA,
904 WriteAdr], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
905 def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;
906 def : InstRW<[M5WriteVLDI,
908 WriteAdr], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
909 def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
910 def : InstRW<[M5WriteVLDJ,
912 WriteAdr], (instregex "LD3i(8|16|32)_POST$")>;
913 def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>;
914 def : InstRW<[M5WriteVLDL,
916 WriteAdr], (instregex "LD3i64_POST$")>;
917 def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
918 def : InstRW<[M5WriteVLDB,
919 M5WriteA1X], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
920 def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>;
921 def : InstRW<[M5WriteVLDN,
923 WriteAdr], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
924 def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>;
925 def : InstRW<[M5WriteVLDK,
927 WriteAdr], (instregex "LD4i(8|16|32)_POST$")>;
928 def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>;
929 def : InstRW<[M5WriteVLDM,
931 WriteAdr], (instregex "LD4i64_POST$")>;
932 def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
933 def : InstRW<[M5WriteVLDC,
935 WriteAdr], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
937 // ASIMD store instructions.
938 def : InstRW<[WriteVST], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
939 def : InstRW<[WriteVST,
941 WriteAdr], (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
942 def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
943 def : InstRW<[M5WriteVSTA,
945 WriteAdr], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
947 def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
948 def : InstRW<[M5WriteVSTB,
950 WriteAdr], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
951 def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
952 def : InstRW<[M5WriteVSTC,
954 WriteAdr], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
955 def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>;
956 def : InstRW<[WriteVST,
958 WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
959 def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
960 def : InstRW<[M5WriteVSTD,
962 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
963 def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
964 def : InstRW<[M5WriteVSTE,
966 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
967 def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
968 def : InstRW<[M5WriteVSTD,
970 WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
971 def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
972 def : InstRW<[M5WriteVSTF,
974 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
975 def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
976 def : InstRW<[M5WriteVSTG,
978 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
979 def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>;
980 def : InstRW<[M5WriteVSTA,
982 WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
983 def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
984 def : InstRW<[M5WriteVSTL,
986 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
987 def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
988 def : InstRW<[M5WriteVSTI,
990 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
991 def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>;
992 def : InstRW<[M5WriteVSTA,
994 WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
996 // Cryptography instructions.
997 def : InstRW<[M5WriteNCRY2], (instregex "^AES[DE]")>;
998 def : InstRW<[M5WriteNCRY2,
999 M5ReadAESM2], (instregex "^AESI?MC")>;
1000 def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>;
1001 def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1002 def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1003 def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>;
1004 def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>;
1005 def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>;
1006 def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>;
1007 def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>;
1009 // CRC instructions.
1010 def : InstRW<[M5WriteF2,
1011 M5ReadFM1], (instregex "^CRC32C?[BHWX]")>;
1013 } // SchedModel = ExynosM5Model