contrib/llvm-project/llvm/lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is the top level entry point for the PowerPC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // Get the target-independent interfaces which we are implementing.
  14 //
  15 include "llvm/Target/Target.td"
  16
  17 //===----------------------------------------------------------------------===//
  18 // PowerPC Subtarget features.
  19 //
  20
  21 //===----------------------------------------------------------------------===//
  22 // CPU Directives                                                             //
  23 //===----------------------------------------------------------------------===//
  24
  25 def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
  26 def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
  27 def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
  28 def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  29 def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  30 def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
  31 def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
  32 def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
  33 def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
  34 def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
  35 def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
  36 def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
  37 def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
  38                                        "PPC::DIR_E500", "">;
  39 def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
  40                                        "PPC::DIR_E500mc", "">;
  41 def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
  42                                        "PPC::DIR_E5500", "">;
  43 def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
  44 def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
  45 def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
  46 def DirectivePwr5x
  47     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
  48 def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
  49 def DirectivePwr6x
  50     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
  51 def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
  52 def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
  53 def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
  54 def DirectivePwrFuture
  55     : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
  56
  57 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  58                                         "Enable 64-bit instructions">;
  59 def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
  60                               "Enable floating-point instructions">;
  61 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  62                               "Enable 64-bit registers usage for ppc32 [beta]">;
  63 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  64                               "Use condition-register bits individually">;
  65 def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
  66                                         "Enable classic FPU instructions",
  67                                         [FeatureHardFloat]>;
  68 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  69                                         "Enable Altivec instructions",
  70                                         [FeatureFPU]>;
  71 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
  72                                         "Enable SPE instructions",
  73                                         [FeatureHardFloat]>;
  74 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  75                                         "Enable the MFOCRF instruction">;
  76 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  77                                         "Enable the fsqrt instruction",
  78                                         [FeatureFPU]>;
  79 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  80                                         "Enable the fcpsgn instruction",
  81                                         [FeatureFPU]>;
  82 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  83                                         "Enable the fre instruction",
  84                                         [FeatureFPU]>;
  85 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  86                                         "Enable the fres instruction",
  87                                         [FeatureFPU]>;
  88 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  89                                         "Enable the frsqrte instruction",
  90                                         [FeatureFPU]>;
  91 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  92                                         "Enable the frsqrtes instruction",
  93                                         [FeatureFPU]>;
  94 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  95                               "Assume higher precision reciprocal estimates">;
  96 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  97                                         "Enable the stfiwx instruction",
  98                                         [FeatureFPU]>;
  99 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
 100                                         "Enable the lfiwax instruction",
 101                                         [FeatureFPU]>;
 102 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
 103                                         "Enable the fri[mnpz] instructions",
 104                                         [FeatureFPU]>;
 105 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
 106   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
 107                                         [FeatureFPU]>;
 108 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
 109                                         "Enable the isel instruction">;
 110 def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
 111                                         "Enable the bpermd instruction">;
 112 def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
 113                                         "Enable extended divide instructions">;
 114 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
 115                                         "Enable the ldbrx instruction">;
 116 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
 117                                         "Enable the cmpb instruction">;
 118 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
 119                                         "Enable icbt instruction">;
 120 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
 121                                         "Enable Book E instructions",
 122                                         [FeatureICBT]>;
 123 def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
 124                               "Has only the msync instruction instead of sync",
 125                               [FeatureBookE]>;
 126 def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
 127                                         "Enable E500/E500mc instructions">;
 128 def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
 129                                         "Enable secure plt mode">;
 130 def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
 131                                         "Enable PPC 4xx instructions">;
 132 def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
 133                                         "Enable PPC 6xx instructions">;
 134 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
 135                                         "Enable QPX instructions",
 136                                         [FeatureFPU]>;
 137 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
 138                                         "Enable VSX instructions",
 139                                         [FeatureAltivec]>;
 140 def FeatureTwoConstNR :
 141   SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
 142                    "Requires two constant Newton-Raphson computation">;
 143 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
 144                                         "Enable POWER8 Altivec instructions",
 145                                         [FeatureAltivec]>;
 146 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
 147                                        "Enable POWER8 Crypto instructions",
 148                                        [FeatureP8Altivec]>;
 149 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
 150                                         "Enable POWER8 vector instructions",
 151                                         [FeatureVSX, FeatureP8Altivec]>;
 152 def FeatureDirectMove :
 153   SubtargetFeature<"direct-move", "HasDirectMove", "true",
 154                    "Enable Power8 direct move instructions",
 155                    [FeatureVSX]>;
 156 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
 157                                              "HasPartwordAtomics", "true",
 158                                              "Enable l[bh]arx and st[bh]cx.">;
 159 def FeatureInvariantFunctionDescriptors :
 160   SubtargetFeature<"invariant-function-descriptors",
 161                    "HasInvariantFunctionDescriptors", "true",
 162                    "Assume function descriptors are invariant">;
 163 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
 164                                        "Always use indirect calls">;
 165 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
 166                                   "Enable Hardware Transactional Memory instructions">;
 167 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
 168                                         "Implement mftb using the mfspr instruction">;
 169 def FeatureUnalignedFloats :
 170   SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
 171                    "true", "CPU does not trap on unaligned FP access">;
 172 def FeaturePPCPreRASched:
 173   SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
 174                    "Use PowerPC pre-RA scheduling strategy">;
 175 def FeaturePPCPostRASched:
 176   SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
 177                    "Use PowerPC post-RA scheduling strategy">;
 178 def FeatureFloat128 :
 179   SubtargetFeature<"float128", "HasFloat128", "true",
 180                    "Enable the __float128 data type for IEEE-754R Binary128.",
 181                    [FeatureVSX]>;
 182 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
 183                                         "POPCNTD_Fast",
 184                                         "Enable the popcnt[dw] instructions">;
 185 // Note that for the a2/a2q processor models we should not use popcnt[dw] by
 186 // default. These processors do support the instructions, but they're
 187 // microcoded, and the software emulation is about twice as fast.
 188 def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
 189                                           "POPCNTD_Slow",
 190                                           "Has slow popcnt[dw] instructions">;
 191
 192 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 193   "Treat vector data stream cache control instructions as deprecated">;
 194
 195 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
 196                                      "true",
 197                                      "Enable instructions added in ISA 3.0.">;
 198 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
 199                                         "Enable POWER9 Altivec instructions",
 200                                         [FeatureISA3_0, FeatureP8Altivec]>;
 201 def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
 202                                         "Enable POWER9 vector instructions",
 203                                         [FeatureISA3_0, FeatureP8Vector,
 204                                          FeatureP9Altivec]>;
 205 // A separate feature for this even though it is equivalent to P9Vector
 206 // because this is a feature of the implementation rather than the architecture
 207 // and may go away with future CPU's.
 208 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
 209                                                  "VectorsUseTwoUnits",
 210                                                  "true",
 211                                                  "Vectors use two units">;
 212
 213 // Since new processors generally contain a superset of features of those that
 214 // came before them, the idea is to make implementations of new processors
 215 // less error prone and easier to read.
 216 // Namely:
 217 //     list<SubtargetFeature> P8InheritableFeatures = ...
 218 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 219 //         [ features that Power8 does not support but inheritable ]
 220 //     list<SubtargetFeature> FutureProcessorSpecificFeatures =
 221 //         [ features that Power8 does not support and not inheritable ]
 222 //     list<SubtargetFeature> FutureProcessorInheritableFeatures =
 223 //         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
 224 //     list<SubtargetFeature> FutureProcessorFeatures =
 225 //         !listconcat(FutureProcessorInheritableFeatures,
 226 //                     FutureProcessorSpecificFeatures)
 227
 228 // Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
 229 // well as providing a single point of definition if the feature set will be
 230 // used elsewhere.
 231 def ProcessorFeatures {
 232   // Power7
 233   list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
 234                                                   FeatureAltivec,
 235                                                   FeatureVSX,
 236                                                   FeatureMFOCRF,
 237                                                   FeatureFCPSGN,
 238                                                   FeatureFSqrt,
 239                                                   FeatureFRE,
 240                                                   FeatureFRES,
 241                                                   FeatureFRSQRTE,
 242                                                   FeatureFRSQRTES,
 243                                                   FeatureRecipPrec,
 244                                                   FeatureSTFIWX,
 245                                                   FeatureLFIWAX,
 246                                                   FeatureFPRND,
 247                                                   FeatureFPCVT,
 248                                                   FeatureISEL,
 249                                                   FeaturePOPCNTD,
 250                                                   FeatureCMPB,
 251                                                   FeatureLDBRX,
 252                                                   Feature64Bit,
 253                                                   /* Feature64BitRegs, */
 254                                                   FeatureBPERMD,
 255                                                   FeatureExtDiv,
 256                                                   FeatureMFTB,
 257                                                   DeprecatedDST,
 258                                                   FeatureTwoConstNR,
 259                                                   FeatureUnalignedFloats];
 260   list<SubtargetFeature> P7SpecificFeatures = [];
 261   list<SubtargetFeature> P7Features =
 262     !listconcat(P7InheritableFeatures, P7SpecificFeatures);
 263
 264   // Power8
 265   list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8,
 266                                                  FeatureP8Altivec,
 267                                                  FeatureP8Vector,
 268                                                  FeatureP8Crypto,
 269                                                  FeatureHTM,
 270                                                  FeatureDirectMove,
 271                                                  FeatureICBT,
 272                                                  FeaturePartwordAtomic];
 273   list<SubtargetFeature> P8SpecificFeatures = [];
 274   list<SubtargetFeature> P8InheritableFeatures =
 275     !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
 276   list<SubtargetFeature> P8Features =
 277     !listconcat(P8InheritableFeatures, P8SpecificFeatures);
 278
 279   // Power9
 280   list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9,
 281                                                  FeatureP9Altivec,
 282                                                  FeatureP9Vector,
 283                                                  FeatureISA3_0];
 284   // Some features are unique to Power9 and there is no reason to assume
 285   // they will be part of any future CPUs. One example is the narrower
 286   // dispatch for vector operations than scalar ones. For the time being,
 287   // this list also includes scheduling-related features since we do not have
 288   // enough info to create custom scheduling strategies for future CPUs.
 289   list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
 290                                                FeaturePPCPreRASched,
 291                                                FeaturePPCPostRASched];
 292   list<SubtargetFeature> P9InheritableFeatures =
 293     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
 294   list<SubtargetFeature> P9Features =
 295     !listconcat(P9InheritableFeatures, P9SpecificFeatures);
 296
 297   // Future
 298   // For future CPU we assume that all of the existing features from Power 9
 299   // still exist with the exception of those we know are Power 9 specific.
 300   list<SubtargetFeature> FutureAdditionalFeatures = [];
 301   list<SubtargetFeature> FutureSpecificFeatures = [];
 302   list<SubtargetFeature> FutureInheritableFeatures =
 303     !listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
 304   list<SubtargetFeature> FutureFeatures =
 305     !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
 306 }
 307
 308 // Note: Future features to add when support is extended to more
 309 // recent ISA levels:
 310 //
 311 // DFP          p6, p6x, p7        decimal floating-point instructions
 312 // POPCNTB      p5 through p7      popcntb and related instructions
 313
 314 //===----------------------------------------------------------------------===//
 315 // Classes used for relation maps.
 316 //===----------------------------------------------------------------------===//
 317 // RecFormRel - Filter class used to relate non-record-form instructions with
 318 // their record-form variants.
 319 class RecFormRel;
 320
 321 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 322 // FMA instruction forms with their corresponding factor-killing forms.
 323 class AltVSXFMARel {
 324   bit IsVSXFMAAlt = 0;
 325 }
 326
 327 //===----------------------------------------------------------------------===//
 328 // Relation Map Definitions.
 329 //===----------------------------------------------------------------------===//
 330
 331 def getRecordFormOpcode : InstrMapping {
 332   let FilterClass = "RecFormRel";
 333   // Instructions with the same BaseName and Interpretation64Bit values
 334   // form a row.
 335   let RowFields = ["BaseName", "Interpretation64Bit"];
 336   // Instructions with the same RC value form a column.
 337   let ColFields = ["RC"];
 338   // The key column are the non-record-form instructions.
 339   let KeyCol = ["0"];
 340   // Value columns RC=1
 341   let ValueCols = [["1"]];
 342 }
 343
 344 def getNonRecordFormOpcode : InstrMapping {
 345   let FilterClass = "RecFormRel";
 346   // Instructions with the same BaseName and Interpretation64Bit values
 347   // form a row.
 348   let RowFields = ["BaseName", "Interpretation64Bit"];
 349   // Instructions with the same RC value form a column.
 350   let ColFields = ["RC"];
 351   // The key column are the record-form instructions.
 352   let KeyCol = ["1"];
 353   // Value columns are RC=0
 354   let ValueCols = [["0"]];
 355 }
 356
 357 def getAltVSXFMAOpcode : InstrMapping {
 358   let FilterClass = "AltVSXFMARel";
 359   // Instructions with the same BaseName value form a row.
 360   let RowFields = ["BaseName"];
 361   // Instructions with the same IsVSXFMAAlt value form a column.
 362   let ColFields = ["IsVSXFMAAlt"];
 363   // The key column are the (default) addend-killing instructions.
 364   let KeyCol = ["0"];
 365   // Value columns IsVSXFMAAlt=1
 366   let ValueCols = [["1"]];
 367 }
 368
 369 //===----------------------------------------------------------------------===//
 370 // Register File Description
 371 //===----------------------------------------------------------------------===//
 372
 373 include "PPCRegisterInfo.td"
 374 include "PPCSchedule.td"
 375
 376 //===----------------------------------------------------------------------===//
 377 // PowerPC processors supported.
 378 //
 379
 380 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
 381                                            FeatureMFTB]>;
 382 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 383                                           FeatureFRES, FeatureFRSQRTE,
 384                                           FeatureICBT, FeatureBookE,
 385                                           FeatureMSYNC, FeatureMFTB]>;
 386 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 387                                           FeatureFRES, FeatureFRSQRTE,
 388                                           FeatureICBT, FeatureBookE,
 389                                           FeatureMSYNC, FeatureMFTB]>;
 390 def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
 391 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
 392                                        FeatureMFTB]>;
 393 def : Processor<"603", G3Itineraries, [Directive603,
 394                                        FeatureFRES, FeatureFRSQRTE,
 395                                        FeatureMFTB]>;
 396 def : Processor<"603e", G3Itineraries, [Directive603,
 397                                         FeatureFRES, FeatureFRSQRTE,
 398                                         FeatureMFTB]>;
 399 def : Processor<"603ev", G3Itineraries, [Directive603,
 400                                          FeatureFRES, FeatureFRSQRTE,
 401                                          FeatureMFTB]>;
 402 def : Processor<"604", G3Itineraries, [Directive604,
 403                                        FeatureFRES, FeatureFRSQRTE,
 404                                        FeatureMFTB]>;
 405 def : Processor<"604e", G3Itineraries, [Directive604,
 406                                         FeatureFRES, FeatureFRSQRTE,
 407                                         FeatureMFTB]>;
 408 def : Processor<"620", G3Itineraries, [Directive620,
 409                                        FeatureFRES, FeatureFRSQRTE,
 410                                        FeatureMFTB]>;
 411 def : Processor<"750", G4Itineraries, [Directive750,
 412                                        FeatureFRES, FeatureFRSQRTE,
 413                                        FeatureMFTB]>;
 414 def : Processor<"g3", G3Itineraries, [Directive750,
 415                                       FeatureFRES, FeatureFRSQRTE,
 416                                       FeatureMFTB]>;
 417 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 418                                         FeatureFRES, FeatureFRSQRTE,
 419                                         FeatureMFTB]>;
 420 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 421                                       FeatureFRES, FeatureFRSQRTE,
 422                                       FeatureMFTB]>;
 423 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 424                                             FeatureFRES, FeatureFRSQRTE,
 425                                             FeatureMFTB]>;
 426 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 427                                            FeatureFRES, FeatureFRSQRTE,
 428                                            FeatureMFTB]>;
 429
 430 def : ProcessorModel<"970", G5Model,
 431                   [Directive970, FeatureAltivec,
 432                    FeatureMFOCRF, FeatureFSqrt,
 433                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 434                    Feature64Bit /*, Feature64BitRegs */,
 435                    FeatureMFTB]>;
 436 def : ProcessorModel<"g5", G5Model,
 437                   [Directive970, FeatureAltivec,
 438                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 439                    FeatureFRES, FeatureFRSQRTE,
 440                    Feature64Bit /*, Feature64BitRegs */,
 441                    FeatureMFTB, DeprecatedDST]>;
 442 def : ProcessorModel<"e500", PPCE500Model,
 443                   [DirectiveE500,
 444                    FeatureICBT, FeatureBookE,
 445                    FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
 446 def : ProcessorModel<"e500mc", PPCE500mcModel,
 447                   [DirectiveE500mc,
 448                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 449                    FeatureISEL, FeatureMFTB]>;
 450 def : ProcessorModel<"e5500", PPCE5500Model,
 451                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 452                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
 453                    FeatureISEL, FeatureMFTB]>;
 454 def : ProcessorModel<"a2", PPCA2Model,
 455                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 456                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 457                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 458                    FeatureSTFIWX, FeatureLFIWAX,
 459                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 460                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 461                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
 462 def : ProcessorModel<"a2q", PPCA2Model,
 463                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
 464                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 465                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 466                    FeatureSTFIWX, FeatureLFIWAX,
 467                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 468                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
 469                    Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
 470                    FeatureMFTB]>;
 471 def : ProcessorModel<"pwr3", G5Model,
 472                   [DirectivePwr3, FeatureAltivec,
 473                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 474                    FeatureSTFIWX, Feature64Bit]>;
 475 def : ProcessorModel<"pwr4", G5Model,
 476                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 477                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 478                    FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 479 def : ProcessorModel<"pwr5", G5Model,
 480                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 481                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 482                    FeatureFRSQRTE, FeatureFRSQRTES,
 483                    FeatureSTFIWX, Feature64Bit,
 484                    FeatureMFTB, DeprecatedDST]>;
 485 def : ProcessorModel<"pwr5x", G5Model,
 486                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 487                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 488                    FeatureFRSQRTE, FeatureFRSQRTES,
 489                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 490                    FeatureMFTB, DeprecatedDST]>;
 491 def : ProcessorModel<"pwr6", G5Model,
 492                   [DirectivePwr6, FeatureAltivec,
 493                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 494                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 495                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 496                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 497                    FeatureMFTB, DeprecatedDST]>;
 498 def : ProcessorModel<"pwr6x", G5Model,
 499                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 500                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 501                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 502                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
 503                    FeatureFPRND, Feature64Bit,
 504                    FeatureMFTB, DeprecatedDST]>;
 505 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
 506 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
 507 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
 508 // No scheduler model for future CPU.
 509 def : ProcessorModel<"future", NoSchedModel,
 510                   ProcessorFeatures.FutureFeatures>;
 511 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
 512                                        FeatureMFTB]>;
 513 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
 514                                          FeatureMFTB]>;
 515 def : ProcessorModel<"ppc64", G5Model,
 516                   [Directive64, FeatureAltivec,
 517                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 518                    FeatureFRSQRTE, FeatureSTFIWX,
 519                    Feature64Bit /*, Feature64BitRegs */,
 520                    FeatureMFTB]>;
 521 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
 522
 523 //===----------------------------------------------------------------------===//
 524 // Calling Conventions
 525 //===----------------------------------------------------------------------===//
 526
 527 include "PPCCallingConv.td"
 528
 529 def PPCInstrInfo : InstrInfo {
 530   let isLittleEndianEncoding = 1;
 531
 532   // FIXME: Unset this when no longer needed!
 533   let decodePositionallyEncodedOperands = 1;
 534
 535   let noNamedPositionallyEncodedOperands = 1;
 536 }
 537
 538 def PPCAsmParser : AsmParser {
 539   let ShouldEmitMatchRegisterName = 0;
 540 }
 541
 542 def PPCAsmParserVariant : AsmParserVariant {
 543   int Variant = 0;
 544
 545   // We do not use hard coded registers in asm strings.  However, some
 546   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 547   // so that those are not misinterpreted as registers.
 548   string RegisterPrefix = "%";
 549   string BreakCharacters = ".";
 550 }
 551
 552 def PPC : Target {
 553   // Information about the instructions.
 554   let InstructionSet = PPCInstrInfo;
 555
 556   let AssemblyParsers = [PPCAsmParser];
 557   let AssemblyParserVariants = [PPCAsmParserVariant];
 558   let AllowRegisterRenaming = 1;
 559 }
 560
 561 //===----------------------------------------------------------------------===//
 562 // Pfm Counters
 563 //===----------------------------------------------------------------------===//
 564
 565 include "PPCPfmCounters.td"