1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the Altivec extension to the PowerPC instruction set.
11 //===----------------------------------------------------------------------===//
13 // *********************************** NOTE ***********************************
14 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
16 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
17 // ** whether lanes are numbered from left to right. An instruction like **
18 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
19 // ** relies only on the corresponding lane of the source vectors. However, **
20 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
21 // ** "odd" lanes are different for big-endian and little-endian numbering. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
24 // ** are lane-sensitive. If so, they must be added to a switch statement **
25 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
26 // ****************************************************************************
29 //===----------------------------------------------------------------------===//
30 // Altivec transformation functions and pattern fragments.
33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
35 def vnot_ppc : PatFrag<(ops node:$in),
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
38 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
42 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
43 (vector_shuffle node:$lhs, node:$rhs), [{
44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
46 def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
47 (vector_shuffle node:$lhs, node:$rhs), [{
48 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
50 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
51 (vector_shuffle node:$lhs, node:$rhs), [{
52 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
54 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
55 (vector_shuffle node:$lhs, node:$rhs), [{
56 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
58 def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
59 (vector_shuffle node:$lhs, node:$rhs), [{
60 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
63 // These fragments are provided for little-endian, where the inputs must be
64 // swapped for correct semantics.
65 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
66 (vector_shuffle node:$lhs, node:$rhs), [{
67 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
69 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
70 (vector_shuffle node:$lhs, node:$rhs), [{
71 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
73 def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
74 (vector_shuffle node:$lhs, node:$rhs), [{
75 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
78 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
80 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
82 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
86 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
88 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
90 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
92 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
94 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
96 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
98 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
100 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
104 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
106 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
108 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
109 (vector_shuffle node:$lhs, node:$rhs), [{
110 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
112 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
113 (vector_shuffle node:$lhs, node:$rhs), [{
114 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
116 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
117 (vector_shuffle node:$lhs, node:$rhs), [{
118 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
120 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
121 (vector_shuffle node:$lhs, node:$rhs), [{
122 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
124 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
125 (vector_shuffle node:$lhs, node:$rhs), [{
126 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
130 // These fragments are provided for little-endian, where the inputs must be
131 // swapped for correct semantics.
132 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
134 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
136 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
137 (vector_shuffle node:$lhs, node:$rhs), [{
138 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
140 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
141 (vector_shuffle node:$lhs, node:$rhs), [{
142 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
144 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
145 (vector_shuffle node:$lhs, node:$rhs), [{
146 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
148 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
149 (vector_shuffle node:$lhs, node:$rhs), [{
150 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
152 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
153 (vector_shuffle node:$lhs, node:$rhs), [{
154 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
158 def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
159 (vector_shuffle node:$lhs, node:$rhs), [{
160 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG);
162 def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
163 (vector_shuffle node:$lhs, node:$rhs), [{
164 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG);
166 def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
167 (vector_shuffle node:$lhs, node:$rhs), [{
168 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG);
170 def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
171 (vector_shuffle node:$lhs, node:$rhs), [{
172 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG);
174 def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
175 (vector_shuffle node:$lhs, node:$rhs), [{
176 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG);
178 def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
179 (vector_shuffle node:$lhs, node:$rhs), [{
180 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG);
185 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
186 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));
188 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
189 (vector_shuffle node:$lhs, node:$rhs), [{
190 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
194 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
195 /// vector_shuffle(X,undef,mask) by the dag combiner.
196 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
197 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N));
199 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
200 (vector_shuffle node:$lhs, node:$rhs), [{
201 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
202 }], VSLDOI_unary_get_imm>;
205 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
206 /// the inputs must be swapped for correct semantics.
207 def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
208 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N));
210 def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
211 (vector_shuffle node:$lhs, node:$rhs), [{
212 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
216 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
217 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
218 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 1, *CurDAG), SDLoc(N));
220 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
221 (vector_shuffle node:$lhs, node:$rhs), [{
222 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
224 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
225 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 2, *CurDAG), SDLoc(N));
227 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
228 (vector_shuffle node:$lhs, node:$rhs), [{
229 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
231 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
232 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 4, *CurDAG), SDLoc(N));
234 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
235 (vector_shuffle node:$lhs, node:$rhs), [{
236 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
240 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
241 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
242 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
244 def vecspltisb : PatLeaf<(build_vector), [{
245 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr;
246 }], VSPLTISB_get_imm>;
248 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
249 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
250 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
252 def vecspltish : PatLeaf<(build_vector), [{
253 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr;
254 }], VSPLTISH_get_imm>;
256 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
257 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
258 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
260 def vecspltisw : PatLeaf<(build_vector), [{
261 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;
262 }], VSPLTISW_get_imm>;
264 def immEQOneV : PatLeaf<(build_vector), [{
265 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())
269 //===----------------------------------------------------------------------===//
270 // Helpers for defining instructions that directly correspond to intrinsics.
272 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
273 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
274 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
275 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
276 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
278 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
279 // inputs doesn't match the type of the output.
280 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
282 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
283 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
284 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
286 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
287 // input types and an output type.
288 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
289 ValueType In1Ty, ValueType In2Ty>
290 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
291 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
293 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
295 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
296 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
297 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
298 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
299 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
301 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
302 // inputs doesn't match the type of the output.
303 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
305 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
306 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
307 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
309 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
310 // input types and an output type.
311 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
312 ValueType In1Ty, ValueType In2Ty>
313 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
314 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
315 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
317 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
318 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
319 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
320 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
321 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
323 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
324 // inputs doesn't match the type of the output.
325 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
327 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
328 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
329 [(set OutTy:$vD, (IntID InTy:$vB))]>;
331 class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
332 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
333 !strconcat(opc, " $vD, $vA"), IIC_VecFP,
334 [(set Ty:$vD, (IntID Ty:$vA))]>;
336 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
337 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
338 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
339 [(set Ty:$vD, (IntID Ty:$vA, timm:$ST, timm:$SIX))]>;
341 //===----------------------------------------------------------------------===//
342 // Instruction Definitions.
344 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
345 let Predicates = [HasAltivec] in {
347 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
348 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
349 Deprecated<DeprecatedDST> {
354 def DSSALL : DSS_Form<1, 822, (outs), (ins),
355 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
356 Deprecated<DeprecatedDST> {
362 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
363 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
364 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
365 Deprecated<DeprecatedDST>;
367 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
368 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
369 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
370 Deprecated<DeprecatedDST>;
372 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
373 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
374 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
375 Deprecated<DeprecatedDST>;
377 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
378 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
379 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
380 Deprecated<DeprecatedDST>;
382 let isCodeGenOnly = 1 in {
383 // The very same instructions as above, but formally matching 64bit registers.
384 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
385 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
386 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
387 Deprecated<DeprecatedDST>;
389 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
390 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
391 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
392 Deprecated<DeprecatedDST>;
394 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
395 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
396 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
398 Deprecated<DeprecatedDST>;
400 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
401 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
402 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
404 Deprecated<DeprecatedDST>;
407 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
408 "mfvscr $vD", IIC_LdStStore,
409 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
410 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
411 "mtvscr $vB", IIC_LdStLoad,
412 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
414 let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads.
415 def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src),
416 "lvebx $vD, $src", IIC_LdStLoad,
417 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
418 def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src),
419 "lvehx $vD, $src", IIC_LdStLoad,
420 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
421 def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src),
422 "lvewx $vD, $src", IIC_LdStLoad,
423 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
424 def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src),
425 "lvx $vD, $src", IIC_LdStLoad,
426 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
427 def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src),
428 "lvxl $vD, $src", IIC_LdStLoad,
429 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
432 def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src),
433 "lvsl $vD, $src", IIC_LdStLoad,
434 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
436 def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src),
437 "lvsr $vD, $src", IIC_LdStLoad,
438 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
441 let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores.
442 def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
443 "stvebx $rS, $dst", IIC_LdStStore,
444 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
445 def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
446 "stvehx $rS, $dst", IIC_LdStStore,
447 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
448 def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
449 "stvewx $rS, $dst", IIC_LdStStore,
450 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
451 def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
452 "stvx $rS, $dst", IIC_LdStStore,
453 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
454 def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
455 "stvxl $rS, $dst", IIC_LdStStore,
456 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
459 let PPC970_Unit = 5 in { // VALU Operations.
460 // VA-Form instructions. 3-input AltiVec ops.
461 let isCommutable = 1 in {
462 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
463 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
465 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
467 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
468 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
469 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
470 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
471 (fneg v4f32:$vB))))]>;
473 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
474 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
476 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
479 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
480 v4i32, v4i32, v16i8>;
481 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
484 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH),
485 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
487 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>;
489 // VX-Form instructions. AltiVec arithmetic ops.
490 let isCommutable = 1 in {
491 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
492 "vaddfp $vD, $vA, $vB", IIC_VecFP,
493 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
495 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
496 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
497 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
498 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
499 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
500 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
501 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
502 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
503 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
505 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
506 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
507 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
508 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
509 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
510 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
511 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
514 let isCommutable = 1 in
515 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
516 "vand $vD, $vA, $vB", IIC_VecFP,
517 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
518 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
519 "vandc $vD, $vA, $vB", IIC_VecFP,
520 [(set v4i32:$vD, (and v4i32:$vA,
521 (vnot_ppc v4i32:$vB)))]>;
523 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
524 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
526 (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>;
527 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
528 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
530 (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>;
531 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
532 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
534 (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>;
535 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
536 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
538 (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>;
540 // Defines with the UIM field set to 0 for floating-point
541 // to integer (fp_to_sint/fp_to_uint) conversions and integer
542 // to floating-point (sint_to_fp/uint_to_fp) conversions.
543 let isCodeGenOnly = 1, VA = 0 in {
544 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
545 "vcfsx $vD, $vB, 0", IIC_VecFP,
547 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
548 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
549 "vctuxs $vD, $vB, 0", IIC_VecFP,
551 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
552 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
553 "vcfux $vD, $vB, 0", IIC_VecFP,
555 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
556 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
557 "vctsxs $vD, $vB, 0", IIC_VecFP,
559 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
561 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
562 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
564 let isCommutable = 1 in {
565 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
566 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
567 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
568 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
569 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
570 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
572 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
573 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
574 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
575 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
576 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
577 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
578 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
579 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
580 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
581 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
582 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
583 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
584 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
585 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
588 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
589 "vmrghb $vD, $vA, $vB", IIC_VecFP,
590 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
591 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
592 "vmrghh $vD, $vA, $vB", IIC_VecFP,
593 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
594 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
595 "vmrghw $vD, $vA, $vB", IIC_VecFP,
596 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
597 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
598 "vmrglb $vD, $vA, $vB", IIC_VecFP,
599 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
600 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
601 "vmrglh $vD, $vA, $vB", IIC_VecFP,
602 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
603 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
604 "vmrglw $vD, $vA, $vB", IIC_VecFP,
605 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
607 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
608 v4i32, v16i8, v4i32>;
609 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
610 v4i32, v8i16, v4i32>;
611 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
612 v4i32, v8i16, v4i32>;
613 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
614 v4i32, v16i8, v4i32>;
615 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
616 v4i32, v8i16, v4i32>;
617 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
618 v4i32, v8i16, v4i32>;
620 let isCommutable = 1 in {
621 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
623 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
625 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
627 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
629 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
631 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
633 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
635 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
639 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
640 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
641 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
642 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
643 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
644 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
646 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
648 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
649 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
650 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
651 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
652 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
653 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
654 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
655 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
656 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
657 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
658 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
659 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
661 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
662 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
663 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
664 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
665 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
666 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
668 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
669 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
671 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
672 v4i32, v16i8, v4i32>;
673 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
674 v4i32, v8i16, v4i32>;
675 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
676 v4i32, v16i8, v4i32>;
678 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
679 "vnor $vD, $vA, $vB", IIC_VecFP,
680 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
682 let isCommutable = 1 in {
683 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
684 "vor $vD, $vA, $vB", IIC_VecFP,
685 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
686 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
687 "vxor $vD, $vA, $vB", IIC_VecFP,
688 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
691 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
692 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
693 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
695 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
696 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
698 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
699 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
700 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
702 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
703 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
705 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
706 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
707 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
709 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
710 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
711 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
713 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
714 let isCodeGenOnly = 1, hasSideEffects = 0 in {
715 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
716 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>;
717 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB),
718 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>;
721 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
722 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
724 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
725 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
726 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
727 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
728 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
729 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
732 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
733 "vspltisb $vD, $SIMM", IIC_VecPerm,
734 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
735 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
736 "vspltish $vD, $SIMM", IIC_VecPerm,
737 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
738 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
739 "vspltisw $vD, $SIMM", IIC_VecPerm,
740 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
743 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
745 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
747 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
749 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
751 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
753 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
754 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
756 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
757 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
759 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
760 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
762 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
763 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
767 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
769 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
771 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
773 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
775 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
777 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
781 // Altivec Comparisons.
783 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
784 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
786 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
787 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
788 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
790 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
795 // f32 element comparisons.0
796 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
797 def VCMPBFP_rec : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
798 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
799 def VCMPEQFP_rec : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
800 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
801 def VCMPGEFP_rec : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
802 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
803 def VCMPGTFP_rec : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
805 // i8 element comparisons.
806 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
807 def VCMPEQUB_rec : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
808 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
809 def VCMPGTSB_rec : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
810 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
811 def VCMPGTUB_rec : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
813 // i16 element comparisons.
814 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
815 def VCMPEQUH_rec : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
816 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
817 def VCMPGTSH_rec : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
818 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
819 def VCMPGTUH_rec : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
821 // i32 element comparisons.
822 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
823 def VCMPEQUW_rec : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
824 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
825 def VCMPGTSW_rec : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
826 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
827 def VCMPGTUW_rec : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
829 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
830 isReMaterializable = 1 in {
832 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
833 "vxor $vD, $vD, $vD", IIC_VecFP,
834 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
835 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
836 "vxor $vD, $vD, $vD", IIC_VecFP,
837 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
838 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
839 "vxor $vD, $vD, $vD", IIC_VecFP,
840 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
843 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
844 "vspltisw $vD, -1", IIC_VecFP,
845 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
846 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
847 "vspltisw $vD, -1", IIC_VecFP,
848 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
849 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
850 "vspltisw $vD, -1", IIC_VecFP,
851 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
854 } // VALU Operations.
856 //===----------------------------------------------------------------------===//
857 // Additional Altivec Patterns
860 // Extended mnemonics
861 def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
862 def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>;
865 def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)),
866 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>;
867 def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)),
868 (v8i16 (VRLH v8i16:$vA, v8i16:$vB))>;
869 def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)),
870 (v4i32 (VRLW v4i32:$vA, v4i32:$vB))>;
873 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
876 def : Pat<(store v4i32:$rS, xoaddr:$dst),
877 (STVX $rS, xoaddr:$dst)>;
880 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
881 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
882 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
883 def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
884 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
886 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
887 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
888 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
889 def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
890 def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
892 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
893 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
894 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
895 def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
896 def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
898 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
899 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
900 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
901 def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
902 def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
904 def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
905 def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
906 def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
907 def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
908 def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
910 def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
911 def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
912 def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
913 def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
914 def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
917 def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)),
918 (v16i8 (VMAXUB $src1, $src2))>;
919 def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)),
920 (v16i8 (VMAXSB $src1, $src2))>;
921 def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)),
922 (v8i16 (VMAXUH $src1, $src2))>;
923 def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)),
924 (v8i16 (VMAXSH $src1, $src2))>;
925 def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)),
926 (v4i32 (VMAXUW $src1, $src2))>;
927 def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)),
928 (v4i32 (VMAXSW $src1, $src2))>;
929 def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)),
930 (v16i8 (VMINUB $src1, $src2))>;
931 def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)),
932 (v16i8 (VMINSB $src1, $src2))>;
933 def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)),
934 (v8i16 (VMINUH $src1, $src2))>;
935 def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)),
936 (v8i16 (VMINSH $src1, $src2))>;
937 def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)),
938 (v4i32 (VMINUW $src1, $src2))>;
939 def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)),
940 (v4i32 (VMINSW $src1, $src2))>;
944 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
945 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
946 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
947 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
949 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
951 def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB),
952 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>;
955 // Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
956 // These fragments are matched for little-endian, where the inputs must
957 // be swapped for correct semantics.
958 def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
959 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
960 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
962 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
966 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
968 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
970 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
972 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
974 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
976 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
979 // Match vmrg*(y,x), i.e., swapped operands. These fragments
980 // are matched for little-endian, where the inputs must be
981 // swapped for correct semantics.
982 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
984 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
986 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
988 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
990 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
992 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
995 // Logical Operations
996 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
998 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
1000 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
1003 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
1005 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>;
1007 // Fused multiply add and multiply sub for packed float. These are represented
1008 // separately from the real instructions above, for operations that must have
1009 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1010 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
1011 (VMADDFP $A, $B, $C)>;
1012 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
1013 (VNMSUBFP $A, $B, $C)>;
1015 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
1016 (VMADDFP $A, $B, $C)>;
1017 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
1018 (VNMSUBFP $A, $B, $C)>;
1020 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
1021 (VPERM $vA, $vB, $vC)>;
1023 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
1024 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
1027 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
1028 (v16i8 (VSLB $vA, $vB))>;
1029 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
1030 (v8i16 (VSLH $vA, $vB))>;
1031 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
1032 (v4i32 (VSLW $vA, $vB))>;
1033 def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)),
1034 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;
1035 def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)),
1036 (v16i8 (VSLB $vA, $vB))>;
1037 def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)),
1038 (v8i16 (VSLH $vA, $vB))>;
1039 def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)),
1040 (v4i32 (VSLW $vA, $vB))>;
1041 def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)),
1042 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;
1044 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
1045 (v16i8 (VSRB $vA, $vB))>;
1046 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
1047 (v8i16 (VSRH $vA, $vB))>;
1048 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
1049 (v4i32 (VSRW $vA, $vB))>;
1050 def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)),
1051 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;
1052 def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)),
1053 (v16i8 (VSRB $vA, $vB))>;
1054 def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)),
1055 (v8i16 (VSRH $vA, $vB))>;
1056 def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)),
1057 (v4i32 (VSRW $vA, $vB))>;
1058 def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)),
1059 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>;
1061 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
1062 (v16i8 (VSRAB $vA, $vB))>;
1063 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
1064 (v8i16 (VSRAH $vA, $vB))>;
1065 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
1066 (v4i32 (VSRAW $vA, $vB))>;
1067 def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)),
1068 (v16i8 (VSRAB $vA, $vB))>;
1069 def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)),
1070 (v8i16 (VSRAH $vA, $vB))>;
1071 def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)),
1072 (v4i32 (VSRAW $vA, $vB))>;
1074 // Float to integer and integer to float conversions
1075 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
1077 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
1079 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
1081 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
1084 // Floating-point rounding
1085 def : Pat<(v4f32 (ffloor v4f32:$vA)),
1087 def : Pat<(v4f32 (fceil v4f32:$vA)),
1089 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
1091 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
1095 def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
1096 (VSEL $vC, $vB, $vA)>;
1097 def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
1098 (VSEL $vC, $vB, $vA)>;
1099 def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
1100 (VSEL $vC, $vB, $vA)>;
1101 def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),
1102 (VSEL $vC, $vB, $vA)>;
1103 def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),
1104 (VSEL $vC, $vB, $vA)>;
1105 def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
1106 (VSEL $vC, $vB, $vA)>;
1108 // Vector Integer Average Instructions
1109 def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
1110 (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>;
1111 def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
1112 (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>;
1113 def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
1114 (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>;
1115 def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
1116 (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>;
1117 def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
1118 (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>;
1119 def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
1120 (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
1124 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
1125 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
1126 let Predicates = [HasP8Altivec] in {
1128 let isCommutable = 1 in {
1129 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
1131 def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
1133 def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
1135 def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
1137 def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1138 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral,
1139 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>;
1140 def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
1141 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
1142 def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
1143 def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
1147 def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1148 "vmrgew $vD, $vA, $vB", IIC_VecFP,
1150 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>;
1151 def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1152 "vmrgow $vD, $vA, $vB", IIC_VecFP,
1154 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>;
1156 // Match vmrgew(x,x) and vmrgow(x,x)
1157 def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef),
1159 def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef),
1162 // Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments
1163 // are matched for little-endian, where the inputs must be swapped for correct
1165 def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB),
1167 def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB),
1171 def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
1173 def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)),
1174 (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>;
1177 def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1178 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>;
1179 def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1180 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>;
1181 def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1182 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>;
1184 def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)),
1185 (v2i64 (VSLD $vA, $vB))>;
1186 def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)),
1187 (v2i64 (VSLD $vA, $vB))>;
1188 def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)),
1189 (v2i64 (VSRD $vA, $vB))>;
1190 def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)),
1191 (v2i64 (VSRD $vA, $vB))>;
1192 def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)),
1193 (v2i64 (VSRAD $vA, $vB))>;
1194 def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)),
1195 (v2i64 (VSRAD $vA, $vB))>;
1197 // Vector Integer Arithmetic Instructions
1198 let isCommutable = 1 in {
1199 def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1200 "vaddudm $vD, $vA, $vB", IIC_VecGeneral,
1201 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>;
1202 def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1203 "vadduqm $vD, $vA, $vB", IIC_VecGeneral,
1204 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>;
1207 // Vector Quadword Add
1208 def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>;
1209 def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>;
1210 def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>;
1212 // Vector Doubleword Subtract
1213 def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1214 "vsubudm $vD, $vA, $vB", IIC_VecGeneral,
1215 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>;
1217 // Vector Quadword Subtract
1218 def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1219 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral,
1220 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>;
1221 def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>;
1222 def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>;
1223 def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>;
1225 // Count Leading Zeros
1226 def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB),
1227 "vclzb $vD, $vB", IIC_VecGeneral,
1228 [(set v16i8:$vD, (ctlz v16i8:$vB))]>;
1229 def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB),
1230 "vclzh $vD, $vB", IIC_VecGeneral,
1231 [(set v8i16:$vD, (ctlz v8i16:$vB))]>;
1232 def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB),
1233 "vclzw $vD, $vB", IIC_VecGeneral,
1234 [(set v4i32:$vD, (ctlz v4i32:$vB))]>;
1235 def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB),
1236 "vclzd $vD, $vB", IIC_VecGeneral,
1237 [(set v2i64:$vD, (ctlz v2i64:$vB))]>;
1240 def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
1241 "vpopcntb $vD, $vB", IIC_VecGeneral,
1242 [(set v16i8:$vD, (ctpop v16i8:$vB))]>;
1243 def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
1244 "vpopcnth $vD, $vB", IIC_VecGeneral,
1245 [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
1246 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
1247 "vpopcntw $vD, $vB", IIC_VecGeneral,
1248 [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
1249 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
1250 "vpopcntd $vD, $vB", IIC_VecGeneral,
1251 [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
1253 let isCommutable = 1 in {
1254 // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
1255 // VSX equivalents. We need to fix this up at some point. Two possible
1256 // solutions for this problem:
1257 // 1. Disable Altivec patterns that compete with VSX patterns using the
1258 // !HasVSX predicate. This essentially favours VSX over Altivec, in
1259 // hopes of reducing register pressure (larger register set using VSX
1260 // instructions than VMX instructions)
1261 // 2. Employ a more disciplined use of AddedComplexity, which would provide
1262 // more fine-grained control than option 1. This would be beneficial
1263 // if we find situations where Altivec is really preferred over VSX.
1264 def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1265 "veqv $vD, $vA, $vB", IIC_VecGeneral,
1266 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
1267 def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1268 "vnand $vD, $vA, $vB", IIC_VecGeneral,
1269 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
1272 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1273 "vorc $vD, $vA, $vB", IIC_VecGeneral,
1274 [(set v4i32:$vD, (or v4i32:$vA,
1275 (vnot_ppc v4i32:$vB)))]>;
1277 // i64 element comparisons.
1278 def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
1279 def VCMPEQUD_rec : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
1280 def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
1281 def VCMPGTSD_rec : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
1282 def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
1283 def VCMPGTUD_rec : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
1285 // The cryptography instructions that do not require Category:Vector.Crypto
1286 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
1287 int_ppc_altivec_crypto_vpmsumb, v16i8>;
1288 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
1289 int_ppc_altivec_crypto_vpmsumh, v8i16>;
1290 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
1291 int_ppc_altivec_crypto_vpmsumw, v4i32>;
1292 def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
1293 int_ppc_altivec_crypto_vpmsumd, v2i64>;
1294 def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
1295 int_ppc_altivec_crypto_vpermxor, v16i8>;
1297 // Vector doubleword integer pack and unpack.
1298 def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
1300 def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
1302 def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1303 "vpkudum $vD, $vA, $vB", IIC_VecFP,
1305 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>;
1306 def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,
1308 def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw,
1310 def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
1313 // Shuffle patterns for unary and swapped (LE) vector pack modulo.
1314 def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef),
1315 (VPKUDUM $vA, $vA)>;
1316 def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB),
1317 (VPKUDUM $vB, $vA)>;
1319 def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>;
1320 def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq,
1322 } // end HasP8Altivec
1324 // Crypto instructions (from builtins)
1325 let Predicates = [HasP8Crypto] in {
1326 def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
1327 int_ppc_altivec_crypto_vshasigmaw, v4i32>;
1328 def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
1329 int_ppc_altivec_crypto_vshasigmad, v2i64>;
1330 def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
1332 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
1333 int_ppc_altivec_crypto_vcipherlast, v2i64>;
1334 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
1335 int_ppc_altivec_crypto_vncipher, v2i64>;
1336 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
1337 int_ppc_altivec_crypto_vncipherlast, v2i64>;
1338 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
1341 // The following altivec instructions were introduced in Power ISA 3.0
1342 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
1343 let Predicates = [HasP9Altivec] in {
1345 // Vector Multiply-Sum
1346 def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
1347 v1i128, v2i64, v1i128>;
1349 // i8 element comparisons.
1350 def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>;
1351 def VCMPNEB_rec : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
1352 def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
1353 def VCMPNEZB_rec : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
1355 // i16 element comparisons.
1356 def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>;
1357 def VCMPNEH_rec : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
1358 def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
1359 def VCMPNEZH_rec : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
1361 // i32 element comparisons.
1362 def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>;
1363 def VCMPNEW_rec : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
1364 def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
1365 def VCMPNEZW_rec : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
1367 // VX-Form: [PO VRT / UIM VRB XO].
1368 // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
1369 // "/ UIM" (1 + 4 bit)
1370 class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
1371 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
1372 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
1374 class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1375 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
1376 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>;
1378 // Vector Extract Unsigned
1379 def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
1380 def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
1381 def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
1382 def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
1384 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
1385 let hasSideEffects = 0 in {
1386 def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
1387 def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
1388 def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
1389 def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
1390 def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
1391 def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
1394 // Vector Insert Element Instructions
1395 def VINSERTB : VXForm_1<781, (outs vrrc:$vD),
1396 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB),
1397 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral,
1398 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB,
1399 imm32SExt16:$UIM))]>,
1400 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1401 def VINSERTH : VXForm_1<845, (outs vrrc:$vD),
1402 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB),
1403 "vinserth $vD, $vB, $UIM", IIC_VecGeneral,
1404 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB,
1405 imm32SExt16:$UIM))]>,
1406 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1407 def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
1408 def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
1410 class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
1411 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
1412 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
1413 class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
1414 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB),
1415 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
1417 // Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
1418 def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB),
1419 "vclzlsbb $rD, $vB", IIC_VecGeneral,
1420 [(set i32:$rD, (int_ppc_altivec_vclzlsbb
1422 def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB),
1423 "vctzlsbb $rD, $vB", IIC_VecGeneral,
1424 [(set i32:$rD, (int_ppc_altivec_vctzlsbb
1426 // Vector Count Trailing Zeros
1427 def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
1428 [(set v16i8:$vD, (cttz v16i8:$vB))]>;
1429 def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
1430 [(set v8i16:$vD, (cttz v8i16:$vB))]>;
1431 def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
1432 [(set v4i32:$vD, (cttz v4i32:$vB))]>;
1433 def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
1434 [(set v2i64:$vD, (cttz v2i64:$vB))]>;
1436 // Vector Extend Sign
1437 def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
1438 def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
1439 def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
1440 def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
1441 def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
1442 let isCodeGenOnly = 1 in {
1443 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
1444 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;
1445 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>;
1446 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>;
1447 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
1450 def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>;
1451 def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>;
1452 def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>;
1453 def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>;
1454 def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>;
1456 // Vector Integer Negate
1457 def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw",
1459 (sub (v4i32 immAllZerosV), v4i32:$vB))]>;
1461 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
1463 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))),
1466 // Vector Parity Byte
1467 def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,
1468 (int_ppc_altivec_vprtybw v4i32:$vB))]>;
1469 def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD,
1470 (int_ppc_altivec_vprtybd v2i64:$vB))]>;
1471 def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD,
1472 (int_ppc_altivec_vprtybq v1i128:$vB))]>;
1474 // Vector (Bit) Permute (Right-indexed)
1475 def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1476 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
1477 def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
1478 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
1480 class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
1481 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1482 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
1484 // Vector Rotate Left Mask/Mask-Insert
1485 def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm",
1487 (int_ppc_altivec_vrlwnm v4i32:$vA,
1489 def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
1490 "vrlwmi $vD, $vA, $vB", IIC_VecFP,
1492 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB,
1494 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1495 def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm",
1497 (int_ppc_altivec_vrldnm v2i64:$vA,
1499 def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
1500 "vrldmi $vD, $vA, $vB", IIC_VecFP,
1502 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB,
1504 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1506 // Vector Shift Left/Right
1507 def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
1508 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
1509 def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
1510 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
1512 // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
1513 def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
1514 "vmul10uq $vD, $vA", IIC_VecFP, []>;
1515 def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA),
1516 "vmul10cuq $vD, $vA", IIC_VecFP, []>;
1518 // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
1519 def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
1520 def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
1522 // Decimal Integer Format Conversion Instructions
1524 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
1525 class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
1527 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
1528 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
1532 // [PO VRT EO VRB 1 / XO]
1533 class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
1535 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
1536 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
1541 // Decimal Convert From/to National/Zoned/Signed-QWord
1542 def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
1543 def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
1544 def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>;
1545 def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
1546 def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
1547 def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
1549 // Decimal Copy-Sign/Set-Sign
1551 def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
1553 def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
1555 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
1556 class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1557 : VX_RD5_RSp5_PS1_XO9<xo,
1558 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
1559 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
1563 // [PO VRT VRA VRB 1 / XO]
1564 class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
1565 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1566 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
1571 // Decimal Shift/Unsigned-Shift/Shift-and-Round
1572 def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
1573 def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>;
1574 def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
1576 // Decimal (Unsigned) Truncate
1577 def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
1578 def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;
1580 // Absolute Difference
1581 def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1582 "vabsdub $vD, $vA, $vB", IIC_VecGeneral,
1583 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>;
1584 def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1585 "vabsduh $vD, $vA, $vB", IIC_VecGeneral,
1586 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>;
1587 def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1588 "vabsduw $vD, $vA, $vB", IIC_VecGeneral,
1589 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>;
1591 } // end HasP9Altivec