sys/amd64/amd64/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/power.h>
  54
  55 #include <machine/asmacros.h>
  56 #include <machine/clock.h>
  57 #include <machine/cputypes.h>
  58 #include <machine/frame.h>
  59 #include <machine/intr_machdep.h>
  60 #include <machine/segments.h>
  61 #include <machine/specialreg.h>
  62 #include <machine/md_var.h>
  63
  64 #include <amd64/vmm/intel/vmx_controls.h>
  65 #include <x86/isa/icu.h>
  66
  67 /* XXX - should be in header file: */
  68 void printcpuinfo(void);
  69 void identify_cpu(void);
  70 void earlysetcpuclass(void);
  71 void panicifcpuunsupported(void);
  72
  73 static u_int find_cpu_vendor_id(void);
  74 static void print_AMD_info(void);
  75 static void print_AMD_assoc(int i);
  76 static void print_via_padlock_info(void);
  77 static void print_vmx_info(void);
  78
  79 int     cpu_class;
  80 char machine[] = "amd64";
  81
  82 #ifdef SCTL_MASK32
  83 extern int adaptive_machine_arch;
  84 #endif
  85
  86 static int
  87 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  88 {
  89 #ifdef SCTL_MASK32
  90         static const char machine32[] = "i386";
  91 #endif
  92         int error;
  93
  94 #ifdef SCTL_MASK32
  95         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
  96                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
  97         else
  98 #endif
  99                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 100         return (error);
 101
 102 }
 103 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 104     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 105
 106 static char cpu_model[128];
 107 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 108     cpu_model, 0, "Machine model");
 109
 110 static int hw_clockrate;
 111 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 112     &hw_clockrate, 0, "CPU instruction clock rate");
 113
 114 static eventhandler_tag tsc_post_tag;
 115
 116 static char cpu_brand[48];
 117
 118 static struct {
 119         char    *cpu_name;
 120         int     cpu_class;
 121 } amd64_cpus[] = {
 122         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 123         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 124 };
 125
 126 static struct {
 127         char    *vendor;
 128         u_int   vendor_id;
 129 } cpu_vendors[] = {
 130         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 131         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 132         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 133 };
 134
 135
 136 void
 137 printcpuinfo(void)
 138 {
 139         u_int regs[4], i;
 140         char *brand;
 141
 142         cpu_class = amd64_cpus[cpu].cpu_class;
 143         printf("CPU: ");
 144         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
 145
 146         /* Check for extended CPUID information and a processor name. */
 147         if (cpu_exthigh >= 0x80000004) {
 148                 brand = cpu_brand;
 149                 for (i = 0x80000002; i < 0x80000005; i++) {
 150                         do_cpuid(i, regs);
 151                         memcpy(brand, regs, sizeof(regs));
 152                         brand += sizeof(regs);
 153                 }
 154         }
 155
 156         switch (cpu_vendor_id) {
 157         case CPU_VENDOR_INTEL:
 158                 /* Please make up your mind folks! */
 159                 strcat(cpu_model, "EM64T");
 160                 break;
 161         case CPU_VENDOR_AMD:
 162                 /*
 163                  * Values taken from AMD Processor Recognition
 164                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 165                  * (also describes ``Features'' encodings.
 166                  */
 167                 strcpy(cpu_model, "AMD ");
 168                 if ((cpu_id & 0xf00) == 0xf00)
 169                         strcat(cpu_model, "AMD64 Processor");
 170                 else
 171                         strcat(cpu_model, "Unknown");
 172                 break;
 173         case CPU_VENDOR_CENTAUR:
 174                 strcpy(cpu_model, "VIA ");
 175                 if ((cpu_id & 0xff0) == 0x6f0)
 176                         strcat(cpu_model, "Nano Processor");
 177                 else
 178                         strcat(cpu_model, "Unknown");
 179                 break;
 180         default:
 181                 strcat(cpu_model, "Unknown");
 182                 break;
 183         }
 184
 185         /*
 186          * Replace cpu_model with cpu_brand minus leading spaces if
 187          * we have one.
 188          */
 189         brand = cpu_brand;
 190         while (*brand == ' ')
 191                 ++brand;
 192         if (*brand != '\0')
 193                 strcpy(cpu_model, brand);
 194
 195         printf("%s (", cpu_model);
 196         switch(cpu_class) {
 197         case CPUCLASS_K8:
 198                 if (tsc_freq != 0) {
 199                         hw_clockrate = (tsc_freq + 5000) / 1000000;
 200                         printf("%jd.%02d-MHz ",
 201                                (intmax_t)(tsc_freq + 4999) / 1000000,
 202                                (u_int)((tsc_freq + 4999) / 10000) % 100);
 203                 }
 204                 printf("K8");
 205                 break;
 206         default:
 207                 printf("Unknown");      /* will panic below... */
 208         }
 209         printf("-class CPU)\n");
 210         if (*cpu_vendor)
 211                 printf("  Origin = \"%s\"", cpu_vendor);
 212         if (cpu_id)
 213                 printf("  Id = 0x%x", cpu_id);
 214
 215         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 216             cpu_vendor_id == CPU_VENDOR_AMD ||
 217             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 218                 printf("  Family = 0x%x", CPUID_TO_FAMILY(cpu_id));
 219                 printf("  Model = 0x%x", CPUID_TO_MODEL(cpu_id));
 220                 printf("  Stepping = %u", cpu_id & CPUID_STEPPING);
 221
 222                 /*
 223                  * AMD CPUID Specification
 224                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 225                  *
 226                  * Intel Processor Identification and CPUID Instruction
 227                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 228                  */
 229                 if (cpu_high > 0) {
 230
 231                         /*
 232                          * Here we should probably set up flags indicating
 233                          * whether or not various features are available.
 234                          * The interesting ones are probably VME, PSE, PAE,
 235                          * and PGE.  The code already assumes without bothering
 236                          * to check that all CPUs >= Pentium have a TSC and
 237                          * MSRs.
 238                          */
 239                         printf("\n  Features=0x%b", cpu_feature,
 240                         "\020"
 241                         "\001FPU"       /* Integral FPU */
 242                         "\002VME"       /* Extended VM86 mode support */
 243                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 244                         "\004PSE"       /* 4MByte page tables */
 245                         "\005TSC"       /* Timestamp counter */
 246                         "\006MSR"       /* Machine specific registers */
 247                         "\007PAE"       /* Physical address extension */
 248                         "\010MCE"       /* Machine Check support */
 249                         "\011CX8"       /* CMPEXCH8 instruction */
 250                         "\012APIC"      /* SMP local APIC */
 251                         "\013oldMTRR"   /* Previous implementation of MTRR */
 252                         "\014SEP"       /* Fast System Call */
 253                         "\015MTRR"      /* Memory Type Range Registers */
 254                         "\016PGE"       /* PG_G (global bit) support */
 255                         "\017MCA"       /* Machine Check Architecture */
 256                         "\020CMOV"      /* CMOV instruction */
 257                         "\021PAT"       /* Page attributes table */
 258                         "\022PSE36"     /* 36 bit address space support */
 259                         "\023PN"        /* Processor Serial number */
 260                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 261                         "\025<b20>"
 262                         "\026DTS"       /* Debug Trace Store */
 263                         "\027ACPI"      /* ACPI support */
 264                         "\030MMX"       /* MMX instructions */
 265                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 266                         "\032SSE"       /* Streaming SIMD Extensions */
 267                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 268                         "\034SS"        /* Self snoop */
 269                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 270                         "\036TM"        /* Thermal Monitor clock slowdown */
 271                         "\037IA64"      /* CPU can execute IA64 instructions */
 272                         "\040PBE"       /* Pending Break Enable */
 273                         );
 274
 275                         if (cpu_feature2 != 0) {
 276                                 printf("\n  Features2=0x%b", cpu_feature2,
 277                                 "\020"
 278                                 "\001SSE3"      /* SSE3 */
 279                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 280                                 "\003DTES64"    /* 64-bit Debug Trace */
 281                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 282                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 283                                 "\006VMX"       /* Virtual Machine Extensions */
 284                                 "\007SMX"       /* Safer Mode Extensions */
 285                                 "\010EST"       /* Enhanced SpeedStep */
 286                                 "\011TM2"       /* Thermal Monitor 2 */
 287                                 "\012SSSE3"     /* SSSE3 */
 288                                 "\013CNXT-ID"   /* L1 context ID available */
 289                                 "\014<b11>"
 290                                 "\015FMA"       /* Fused Multiply Add */
 291                                 "\016CX16"      /* CMPXCHG16B Instruction */
 292                                 "\017xTPR"      /* Send Task Priority Messages*/
 293                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 294                                 "\021<b16>"
 295                                 "\022PCID"      /* Process-context Identifiers*/
 296                                 "\023DCA"       /* Direct Cache Access */
 297                                 "\024SSE4.1"    /* SSE 4.1 */
 298                                 "\025SSE4.2"    /* SSE 4.2 */
 299                                 "\026x2APIC"    /* xAPIC Extensions */
 300                                 "\027MOVBE"     /* MOVBE Instruction */
 301                                 "\030POPCNT"    /* POPCNT Instruction */
 302                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 303                                 "\032AESNI"     /* AES Crypto */
 304                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 305                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 306                                 "\035AVX"       /* Advanced Vector Extensions */
 307                                 "\036F16C"      /* Half-precision conversions */
 308                                 "\037RDRAND"    /* RDRAND Instruction */
 309                                 "\040HV"        /* Hypervisor */
 310                                 );
 311                         }
 312
 313                         if (amd_feature != 0) {
 314                                 printf("\n  AMD Features=0x%b", amd_feature,
 315                                 "\020"          /* in hex */
 316                                 "\001<s0>"      /* Same */
 317                                 "\002<s1>"      /* Same */
 318                                 "\003<s2>"      /* Same */
 319                                 "\004<s3>"      /* Same */
 320                                 "\005<s4>"      /* Same */
 321                                 "\006<s5>"      /* Same */
 322                                 "\007<s6>"      /* Same */
 323                                 "\010<s7>"      /* Same */
 324                                 "\011<s8>"      /* Same */
 325                                 "\012<s9>"      /* Same */
 326                                 "\013<b10>"     /* Undefined */
 327                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 328                                 "\015<s12>"     /* Same */
 329                                 "\016<s13>"     /* Same */
 330                                 "\017<s14>"     /* Same */
 331                                 "\020<s15>"     /* Same */
 332                                 "\021<s16>"     /* Same */
 333                                 "\022<s17>"     /* Same */
 334                                 "\023<b18>"     /* Reserved, unknown */
 335                                 "\024MP"        /* Multiprocessor Capable */
 336                                 "\025NX"        /* Has EFER.NXE, NX */
 337                                 "\026<b21>"     /* Undefined */
 338                                 "\027MMX+"      /* AMD MMX Extensions */
 339                                 "\030<s23>"     /* Same */
 340                                 "\031<s24>"     /* Same */
 341                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 342                                 "\033Page1GB"   /* 1-GB large page support */
 343                                 "\034RDTSCP"    /* RDTSCP */
 344                                 "\035<b28>"     /* Undefined */
 345                                 "\036LM"        /* 64 bit long mode */
 346                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 347                                 "\0403DNow!"    /* AMD 3DNow! */
 348                                 );
 349                         }
 350
 351                         if (amd_feature2 != 0) {
 352                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 353                                 "\020"
 354                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 355                                 "\002CMP"       /* CMP legacy */
 356                                 "\003SVM"       /* Secure Virtual Mode */
 357                                 "\004ExtAPIC"   /* Extended APIC register */
 358                                 "\005CR8"       /* CR8 in legacy mode */
 359                                 "\006ABM"       /* LZCNT instruction */
 360                                 "\007SSE4A"     /* SSE4A */
 361                                 "\010MAS"       /* Misaligned SSE mode */
 362                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 363                                 "\012OSVW"      /* OS visible workaround */
 364                                 "\013IBS"       /* Instruction based sampling */
 365                                 "\014XOP"       /* XOP extended instructions */
 366                                 "\015SKINIT"    /* SKINIT/STGI */
 367                                 "\016WDT"       /* Watchdog timer */
 368                                 "\017<b14>"
 369                                 "\020LWP"       /* Lightweight Profiling */
 370                                 "\021FMA4"      /* 4-operand FMA instructions */
 371                                 "\022TCE"       /* Translation Cache Extension */
 372                                 "\023<b18>"
 373                                 "\024NodeId"    /* NodeId MSR support */
 374                                 "\025<b20>"
 375                                 "\026TBM"       /* Trailing Bit Manipulation */
 376                                 "\027Topology"  /* Topology Extensions */
 377                                 "\030PCXC"      /* Core perf count */
 378                                 "\031PNXC"      /* NB perf count */
 379                                 "\032<b25>"
 380                                 "\033DBE"       /* Data Breakpoint extension */
 381                                 "\034PTSC"      /* Performance TSC */
 382                                 "\035PL2I"      /* L2I perf count */
 383                                 "\036<b29>"
 384                                 "\037<b30>"
 385                                 "\040<b31>"
 386                                 );
 387                         }
 388
 389                         if (cpu_stdext_feature != 0) {
 390                                 printf("\n  Structured Extended Features=0x%b",
 391                                     cpu_stdext_feature,
 392                                        "\020"
 393                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 394                                        "\001FSGSBASE"
 395                                        "\002TSCADJ"
 396                                        /* Bit Manipulation Instructions */
 397                                        "\004BMI1"
 398                                        /* Hardware Lock Elision */
 399                                        "\005HLE"
 400                                        /* Advanced Vector Instructions 2 */
 401                                        "\006AVX2"
 402                                        /* Supervisor Mode Execution Prot. */
 403                                        "\010SMEP"
 404                                        /* Bit Manipulation Instructions */
 405                                        "\011BMI2"
 406                                        "\012ERMS"
 407                                        /* Invalidate Processor Context ID */
 408                                        "\013INVPCID"
 409                                        /* Restricted Transactional Memory */
 410                                        "\014RTM"
 411                                        /* Intel Memory Protection Extensions */
 412                                        "\017MPX"
 413                                        /* AVX512 Foundation */
 414                                        "\021AVX512F"
 415                                        /* Enhanced NRBG */
 416                                        "\023RDSEED"
 417                                        /* ADCX + ADOX */
 418                                        "\024ADX"
 419                                        /* Supervisor Mode Access Prevention */
 420                                        "\025SMAP"
 421                                        "\030CLFLUSHOPT"
 422                                        "\032PROCTRACE"
 423                                        "\033AVX512PF"
 424                                        "\034AVX512ER"
 425                                        "\035AVX512CD"
 426                                        "\036SHA"
 427                                        );
 428                         }
 429
 430                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 431                                 print_via_padlock_info();
 432
 433                         if (cpu_feature2 & CPUID2_VMX)
 434                                 print_vmx_info();
 435
 436                         if ((cpu_feature & CPUID_HTT) &&
 437                             cpu_vendor_id == CPU_VENDOR_AMD)
 438                                 cpu_feature &= ~CPUID_HTT;
 439
 440                         /*
 441                          * If this CPU supports P-state invariant TSC then
 442                          * mention the capability.
 443                          */
 444                         if (tsc_is_invariant) {
 445                                 printf("\n  TSC: P-state invariant");
 446                                 if (tsc_perf_stat)
 447                                         printf(", performance statistics");
 448                         }
 449
 450                 }
 451         }
 452         /* Avoid ugly blank lines: only print newline when we have to. */
 453         if (*cpu_vendor || cpu_id)
 454                 printf("\n");
 455
 456         if (!bootverbose)
 457                 return;
 458
 459         if (cpu_vendor_id == CPU_VENDOR_AMD)
 460                 print_AMD_info();
 461 }
 462
 463 void
 464 panicifcpuunsupported(void)
 465 {
 466
 467 #ifndef HAMMER
 468 #error "You need to specify a cpu type"
 469 #endif
 470         /*
 471          * Now that we have told the user what they have,
 472          * let them know if that machine type isn't configured.
 473          */
 474         switch (cpu_class) {
 475         case CPUCLASS_X86:
 476 #ifndef HAMMER
 477         case CPUCLASS_K8:
 478 #endif
 479                 panic("CPU class not configured");
 480         default:
 481                 break;
 482         }
 483 }
 484
 485
 486 /* Update TSC freq with the value indicated by the caller. */
 487 static void
 488 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
 489 {
 490
 491         /* If there was an error during the transition, don't do anything. */
 492         if (status != 0)
 493                 return;
 494
 495         /* Total setting for this level gives the new frequency in MHz. */
 496         hw_clockrate = level->total_set.freq;
 497 }
 498
 499 static void
 500 hook_tsc_freq(void *arg __unused)
 501 {
 502
 503         if (tsc_is_invariant)
 504                 return;
 505
 506         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
 507             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
 508 }
 509
 510 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
 511
 512 /*
 513  * Final stage of CPU identification.
 514  */
 515 void
 516 identify_cpu(void)
 517 {
 518         u_int regs[4], cpu_stdext_disable;
 519
 520         do_cpuid(0, regs);
 521         cpu_high = regs[0];
 522         ((u_int *)&cpu_vendor)[0] = regs[1];
 523         ((u_int *)&cpu_vendor)[1] = regs[3];
 524         ((u_int *)&cpu_vendor)[2] = regs[2];
 525         cpu_vendor[12] = '\0';
 526         cpu_vendor_id = find_cpu_vendor_id();
 527
 528         do_cpuid(1, regs);
 529         cpu_id = regs[0];
 530         cpu_procinfo = regs[1];
 531         cpu_feature = regs[3];
 532         cpu_feature2 = regs[2];
 533
 534         /*
 535          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
 536          * function number again if it is set from BIOS.  It is necessary
 537          * for probing correct CPU topology later.
 538          * XXX This is only done on the BSP package.
 539          */
 540         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) {
 541                 uint64_t msr;
 542                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
 543                 if ((msr & 0x400000ULL) != 0) {
 544                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
 545                         do_cpuid(0, regs);
 546                         cpu_high = regs[0];
 547                 }
 548         }
 549
 550         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
 551                 do_cpuid(5, regs);
 552                 cpu_mon_mwait_flags = regs[2];
 553                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
 554                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
 555         }
 556
 557         if (cpu_high >= 7) {
 558                 cpuid_count(7, 0, regs);
 559                 cpu_stdext_feature = regs[1];
 560
 561                 /*
 562                  * Some hypervisors fail to filter out unsupported
 563                  * extended features.  For now, disable the
 564                  * extensions, activation of which requires setting a
 565                  * bit in CR4, and which VM monitors do not support.
 566                  */
 567                 if (cpu_feature2 & CPUID2_HV) {
 568                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
 569                             CPUID_STDEXT_SMEP;
 570                 } else
 571                         cpu_stdext_disable = 0;
 572                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
 573                 cpu_stdext_feature &= ~cpu_stdext_disable;
 574         }
 575
 576         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 577             cpu_vendor_id == CPU_VENDOR_AMD ||
 578             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 579                 do_cpuid(0x80000000, regs);
 580                 cpu_exthigh = regs[0];
 581         }
 582         if (cpu_exthigh >= 0x80000001) {
 583                 do_cpuid(0x80000001, regs);
 584                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 585                 amd_feature2 = regs[2];
 586         }
 587         if (cpu_exthigh >= 0x80000007) {
 588                 do_cpuid(0x80000007, regs);
 589                 amd_pminfo = regs[3];
 590         }
 591         if (cpu_exthigh >= 0x80000008) {
 592                 do_cpuid(0x80000008, regs);
 593                 cpu_procinfo2 = regs[2];
 594         }
 595
 596         /* XXX */
 597         cpu = CPU_CLAWHAMMER;
 598 }
 599
 600 static u_int
 601 find_cpu_vendor_id(void)
 602 {
 603         int     i;
 604
 605         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
 606                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
 607                         return (cpu_vendors[i].vendor_id);
 608         return (0);
 609 }
 610
 611 static void
 612 print_AMD_assoc(int i)
 613 {
 614         if (i == 255)
 615                 printf(", fully associative\n");
 616         else
 617                 printf(", %d-way associative\n", i);
 618 }
 619
 620 static void
 621 print_AMD_l2_assoc(int i)
 622 {
 623         switch (i & 0x0f) {
 624         case 0: printf(", disabled/not present\n"); break;
 625         case 1: printf(", direct mapped\n"); break;
 626         case 2: printf(", 2-way associative\n"); break;
 627         case 4: printf(", 4-way associative\n"); break;
 628         case 6: printf(", 8-way associative\n"); break;
 629         case 8: printf(", 16-way associative\n"); break;
 630         case 15: printf(", fully associative\n"); break;
 631         default: printf(", reserved configuration\n"); break;
 632         }
 633 }
 634
 635 static void
 636 print_AMD_info(void)
 637 {
 638         u_int regs[4];
 639
 640         if (cpu_exthigh < 0x80000005)
 641                 return;
 642
 643         do_cpuid(0x80000005, regs);
 644         printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
 645         print_AMD_assoc(regs[0] >> 24);
 646
 647         printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
 648         print_AMD_assoc((regs[0] >> 8) & 0xff);
 649
 650         printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
 651         print_AMD_assoc(regs[1] >> 24);
 652
 653         printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
 654         print_AMD_assoc((regs[1] >> 8) & 0xff);
 655
 656         printf("L1 data cache: %d kbytes", regs[2] >> 24);
 657         printf(", %d bytes/line", regs[2] & 0xff);
 658         printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 659         print_AMD_assoc((regs[2] >> 16) & 0xff);
 660
 661         printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 662         printf(", %d bytes/line", regs[3] & 0xff);
 663         printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 664         print_AMD_assoc((regs[3] >> 16) & 0xff);
 665
 666         if (cpu_exthigh >= 0x80000006) {
 667                 do_cpuid(0x80000006, regs);
 668                 if ((regs[0] >> 16) != 0) {
 669                         printf("L2 2MB data TLB: %d entries",
 670                             (regs[0] >> 16) & 0xfff);
 671                         print_AMD_l2_assoc(regs[0] >> 28);
 672                         printf("L2 2MB instruction TLB: %d entries",
 673                             regs[0] & 0xfff);
 674                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 675                 } else {
 676                         printf("L2 2MB unified TLB: %d entries",
 677                             regs[0] & 0xfff);
 678                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 679                 }
 680                 if ((regs[1] >> 16) != 0) {
 681                         printf("L2 4KB data TLB: %d entries",
 682                             (regs[1] >> 16) & 0xfff);
 683                         print_AMD_l2_assoc(regs[1] >> 28);
 684
 685                         printf("L2 4KB instruction TLB: %d entries",
 686                             (regs[1] >> 16) & 0xfff);
 687                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 688                 } else {
 689                         printf("L2 4KB unified TLB: %d entries",
 690                             (regs[1] >> 16) & 0xfff);
 691                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 692                 }
 693                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
 694                 printf(", %d bytes/line", regs[2] & 0xff);
 695                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 696                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
 697         }
 698
 699         /*
 700          * Opteron Rev E shows a bug as in very rare occasions a read memory
 701          * barrier is not performed as expected if it is followed by a
 702          * non-atomic read-modify-write instruction.
 703          * As long as that bug pops up very rarely (intensive machine usage
 704          * on other operating systems generally generates one unexplainable
 705          * crash any 2 months) and as long as a model specific fix would be
 706          * impratical at this stage, print out a warning string if the broken
 707          * model and family are identified.
 708          */
 709         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
 710             CPUID_TO_MODEL(cpu_id) <= 0x3f)
 711                 printf("WARNING: This architecture revision has known SMP "
 712                     "hardware bugs which may cause random instability\n");
 713 }
 714
 715 static void
 716 print_via_padlock_info(void)
 717 {
 718         u_int regs[4];
 719
 720         do_cpuid(0xc0000001, regs);
 721         printf("\n  VIA Padlock Features=0x%b", regs[3],
 722         "\020"
 723         "\003RNG"               /* RNG */
 724         "\007AES"               /* ACE */
 725         "\011AES-CTR"           /* ACE2 */
 726         "\013SHA1,SHA256"       /* PHE */
 727         "\015RSA"               /* PMM */
 728         );
 729 }
 730
 731 static uint32_t
 732 vmx_settable(uint64_t basic, int msr, int true_msr)
 733 {
 734         uint64_t val;
 735
 736         if (basic & (1UL << 55))
 737                 val = rdmsr(true_msr);
 738         else
 739                 val = rdmsr(msr);
 740
 741         /* Just report the controls that can be set to 1. */
 742         return (val >> 32);
 743 }
 744
 745 static void
 746 print_vmx_info(void)
 747 {
 748         uint64_t basic, msr;
 749         uint32_t entry, exit, mask, pin, proc, proc2;
 750         int comma;
 751
 752         printf("\n  VT-x: ");
 753         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
 754         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
 755                 printf("(disabled in BIOS) ");
 756         basic = rdmsr(MSR_VMX_BASIC);
 757         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
 758             MSR_VMX_TRUE_PINBASED_CTLS);
 759         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
 760             MSR_VMX_TRUE_PROCBASED_CTLS);
 761         if (proc & PROCBASED_SECONDARY_CONTROLS)
 762                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
 763                     MSR_VMX_PROCBASED_CTLS2);
 764         else
 765                 proc2 = 0;
 766         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
 767         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
 768
 769         if (!bootverbose) {
 770                 comma = 0;
 771                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
 772                     entry & VM_ENTRY_LOAD_PAT) {
 773                         printf("%sPAT", comma ? "," : "");
 774                         comma = 1;
 775                 }
 776                 if (proc & PROCBASED_HLT_EXITING) {
 777                         printf("%sHLT", comma ? "," : "");
 778                         comma = 1;
 779                 }
 780                 if (proc & PROCBASED_MTF) {
 781                         printf("%sMTF", comma ? "," : "");
 782                         comma = 1;
 783                 }
 784                 if (proc & PROCBASED_PAUSE_EXITING) {
 785                         printf("%sPAUSE", comma ? "," : "");
 786                         comma = 1;
 787                 }
 788                 if (proc2 & PROCBASED2_ENABLE_EPT) {
 789                         printf("%sEPT", comma ? "," : "");
 790                         comma = 1;
 791                 }
 792                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
 793                         printf("%sUG", comma ? "," : "");
 794                         comma = 1;
 795                 }
 796                 if (proc2 & PROCBASED2_ENABLE_VPID) {
 797                         printf("%sVPID", comma ? "," : "");
 798                         comma = 1;
 799                 }
 800                 if (proc & PROCBASED_USE_TPR_SHADOW &&
 801                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
 802                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
 803                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
 804                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
 805                         printf("%sVID", comma ? "," : "");
 806                         comma = 1;
 807                         if (pin & PINBASED_POSTED_INTERRUPT)
 808                                 printf(",PostIntr");
 809                 }
 810                 return;
 811         }
 812
 813         mask = basic >> 32;
 814         printf("Basic Features=0x%b", mask,
 815         "\020"
 816         "\02132PA"              /* 32-bit physical addresses */
 817         "\022SMM"               /* SMM dual-monitor */
 818         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
 819         "\030TRUE"              /* TRUE_CTLS MSRs */
 820         );
 821         printf("\n        Pin-Based Controls=0x%b", pin,
 822         "\020"
 823         "\001ExtINT"            /* External-interrupt exiting */
 824         "\004NMI"               /* NMI exiting */
 825         "\006VNMI"              /* Virtual NMIs */
 826         "\007PreTmr"            /* Activate VMX-preemption timer */
 827         "\010PostIntr"          /* Process posted interrupts */
 828         );
 829         printf("\n        Primary Processor Controls=0x%b", proc,
 830         "\020"
 831         "\003INTWIN"            /* Interrupt-window exiting */
 832         "\004TSCOff"            /* Use TSC offsetting */
 833         "\010HLT"               /* HLT exiting */
 834         "\012INVLPG"            /* INVLPG exiting */
 835         "\013MWAIT"             /* MWAIT exiting */
 836         "\014RDPMC"             /* RDPMC exiting */
 837         "\015RDTSC"             /* RDTSC exiting */
 838         "\020CR3-LD"            /* CR3-load exiting */
 839         "\021CR3-ST"            /* CR3-store exiting */
 840         "\024CR8-LD"            /* CR8-load exiting */
 841         "\025CR8-ST"            /* CR8-store exiting */
 842         "\026TPR"               /* Use TPR shadow */
 843         "\027NMIWIN"            /* NMI-window exiting */
 844         "\030MOV-DR"            /* MOV-DR exiting */
 845         "\031IO"                /* Unconditional I/O exiting */
 846         "\032IOmap"             /* Use I/O bitmaps */
 847         "\034MTF"               /* Monitor trap flag */
 848         "\035MSRmap"            /* Use MSR bitmaps */
 849         "\036MONITOR"           /* MONITOR exiting */
 850         "\037PAUSE"             /* PAUSE exiting */
 851         );
 852         if (proc & PROCBASED_SECONDARY_CONTROLS)
 853                 printf("\n        Secondary Processor Controls=0x%b", proc2,
 854                 "\020"
 855                 "\001APIC"              /* Virtualize APIC accesses */
 856                 "\002EPT"               /* Enable EPT */
 857                 "\003DT"                /* Descriptor-table exiting */
 858                 "\004RDTSCP"            /* Enable RDTSCP */
 859                 "\005x2APIC"            /* Virtualize x2APIC mode */
 860                 "\006VPID"              /* Enable VPID */
 861                 "\007WBINVD"            /* WBINVD exiting */
 862                 "\010UG"                /* Unrestricted guest */
 863                 "\011APIC-reg"          /* APIC-register virtualization */
 864                 "\012VID"               /* Virtual-interrupt delivery */
 865                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
 866                 "\014RDRAND"            /* RDRAND exiting */
 867                 "\015INVPCID"           /* Enable INVPCID */
 868                 "\016VMFUNC"            /* Enable VM functions */
 869                 "\017VMCS"              /* VMCS shadowing */
 870                 "\020EPT#VE"            /* EPT-violation #VE */
 871                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
 872                 );
 873         printf("\n        Exit Controls=0x%b", mask,
 874         "\020"
 875         "\003DR"                /* Save debug controls */
 876                                 /* Ignore Host address-space size */
 877         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
 878         "\020AckInt"            /* Acknowledge interrupt on exit */
 879         "\023PAT-SV"            /* Save MSR_PAT */
 880         "\024PAT-LD"            /* Load MSR_PAT */
 881         "\025EFER-SV"           /* Save MSR_EFER */
 882         "\026EFER-LD"           /* Load MSR_EFER */
 883         "\027PTMR-SV"           /* Save VMX-preemption timer value */
 884         );
 885         printf("\n        Entry Controls=0x%b", mask,
 886         "\020"
 887         "\003DR"                /* Save debug controls */
 888                                 /* Ignore IA-32e mode guest */
 889                                 /* Ignore Entry to SMM */
 890                                 /* Ignore Deactivate dual-monitor treatment */
 891         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
 892         "\017PAT"               /* Load MSR_PAT */
 893         "\020EFER"              /* Load MSR_EFER */
 894         );
 895         if (proc & PROCBASED_SECONDARY_CONTROLS &&
 896             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
 897                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
 898                 mask = msr;
 899                 printf("\n        EPT Features=0x%b", mask,
 900                 "\020"
 901                 "\001XO"                /* Execute-only translations */
 902                 "\007PW4"               /* Page-walk length of 4 */
 903                 "\011UC"                /* EPT paging-structure mem can be UC */
 904                 "\017WB"                /* EPT paging-structure mem can be WB */
 905                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
 906                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
 907                 "\025INVEPT"            /* INVEPT is supported */
 908                 "\026AD"                /* Accessed and dirty flags for EPT */
 909                 "\032single"            /* INVEPT single-context type */
 910                 "\033all"               /* INVEPT all-context type */
 911                 );
 912                 mask = msr >> 32;
 913                 printf("\n        VPID Features=0x%b", mask,
 914                 "\020"
 915                 "\001INVVPID"           /* INVVPID is supported */
 916                 "\011individual"        /* INVVPID individual-address type */
 917                 "\012single"            /* INVVPID single-context type */
 918                 "\013all"               /* INVVPID all-context type */
 919                  /* INVVPID single-context-retaining-globals type */
 920                 "\014single-globals"
 921                 );
 922         }
 923 }