2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 void vmmdev_init(void);
34 int vmmdev_cleanup(void);
37 struct vm_memory_segment {
38 vm_paddr_t gpa; /* in */
45 int regnum; /* enum vm_reg_name */
49 struct vm_seg_desc { /* data or code segment */
51 int regnum; /* enum vm_reg_name */
57 uint64_t rip; /* start running here */
58 struct vm_exit vm_exit;
78 struct vm_ioapic_irq {
87 struct vm_isa_irq_trigger {
89 enum vm_intr_trigger trigger;
92 struct vm_capability {
94 enum vm_cap_type captype;
105 struct vm_pptdev_mmio {
114 struct vm_pptdev_msi {
119 int numvec; /* 0 means disabled */
124 struct vm_pptdev_msix {
131 uint32_t vector_control;
139 #define MAX_VM_STATS 64
142 int num_entries; /* out */
144 uint64_t statbuf[MAX_VM_STATS];
147 struct vm_stat_desc {
149 char desc[128]; /* out */
154 enum x2apic_state state;
158 uint64_t gpa; /* in */
159 uint64_t pte[4]; /* out */
164 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
168 enum vm_suspend_how how;
172 int vcpuid; /* inputs */
173 int prot; /* PROT_READ or PROT_WRITE */
175 struct vm_guest_paging paging;
176 int fault; /* outputs */
180 struct vm_activate_cpu {
189 #define VM_ACTIVE_CPUS 0
190 #define VM_SUSPENDED_CPUS 1
199 /* general routines */
202 IOCNUM_SET_CAPABILITY = 2,
203 IOCNUM_GET_CAPABILITY = 3,
208 IOCNUM_MAP_MEMORY = 10,
209 IOCNUM_GET_MEMORY_SEG = 11,
210 IOCNUM_GET_GPA_PMAP = 12,
213 /* register/state accessors */
214 IOCNUM_SET_REGISTER = 20,
215 IOCNUM_GET_REGISTER = 21,
216 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
217 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
219 /* interrupt injection */
220 IOCNUM_GET_INTINFO = 28,
221 IOCNUM_SET_INTINFO = 29,
222 IOCNUM_INJECT_EXCEPTION = 30,
223 IOCNUM_LAPIC_IRQ = 31,
224 IOCNUM_INJECT_NMI = 32,
225 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
226 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
227 IOCNUM_IOAPIC_PULSE_IRQ = 35,
228 IOCNUM_LAPIC_MSI = 36,
229 IOCNUM_LAPIC_LOCAL_IRQ = 37,
230 IOCNUM_IOAPIC_PINCOUNT = 38,
233 IOCNUM_BIND_PPTDEV = 40,
234 IOCNUM_UNBIND_PPTDEV = 41,
235 IOCNUM_MAP_PPTDEV_MMIO = 42,
236 IOCNUM_PPTDEV_MSI = 43,
237 IOCNUM_PPTDEV_MSIX = 44,
240 IOCNUM_VM_STATS = 50,
241 IOCNUM_VM_STAT_DESC = 51,
243 /* kernel device state */
244 IOCNUM_SET_X2APIC_STATE = 60,
245 IOCNUM_GET_X2APIC_STATE = 61,
246 IOCNUM_GET_HPET_CAPABILITIES = 62,
248 /* legacy interrupt injection */
249 IOCNUM_ISA_ASSERT_IRQ = 80,
250 IOCNUM_ISA_DEASSERT_IRQ = 81,
251 IOCNUM_ISA_PULSE_IRQ = 82,
252 IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
255 IOCNUM_ACTIVATE_CPU = 90,
256 IOCNUM_GET_CPUSET = 91,
260 _IOWR('v', IOCNUM_RUN, struct vm_run)
262 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
264 _IO('v', IOCNUM_REINIT)
265 #define VM_MAP_MEMORY \
266 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
267 #define VM_GET_MEMORY_SEG \
268 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
269 #define VM_SET_REGISTER \
270 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
271 #define VM_GET_REGISTER \
272 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
273 #define VM_SET_SEGMENT_DESCRIPTOR \
274 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
275 #define VM_GET_SEGMENT_DESCRIPTOR \
276 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
277 #define VM_INJECT_EXCEPTION \
278 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
279 #define VM_LAPIC_IRQ \
280 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
281 #define VM_LAPIC_LOCAL_IRQ \
282 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
283 #define VM_LAPIC_MSI \
284 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
285 #define VM_IOAPIC_ASSERT_IRQ \
286 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
287 #define VM_IOAPIC_DEASSERT_IRQ \
288 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
289 #define VM_IOAPIC_PULSE_IRQ \
290 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
291 #define VM_IOAPIC_PINCOUNT \
292 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
293 #define VM_ISA_ASSERT_IRQ \
294 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
295 #define VM_ISA_DEASSERT_IRQ \
296 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
297 #define VM_ISA_PULSE_IRQ \
298 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
299 #define VM_ISA_SET_IRQ_TRIGGER \
300 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
301 #define VM_SET_CAPABILITY \
302 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
303 #define VM_GET_CAPABILITY \
304 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
305 #define VM_BIND_PPTDEV \
306 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
307 #define VM_UNBIND_PPTDEV \
308 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
309 #define VM_MAP_PPTDEV_MMIO \
310 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
311 #define VM_PPTDEV_MSI \
312 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
313 #define VM_PPTDEV_MSIX \
314 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
315 #define VM_INJECT_NMI \
316 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
318 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
319 #define VM_STAT_DESC \
320 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
321 #define VM_SET_X2APIC_STATE \
322 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
323 #define VM_GET_X2APIC_STATE \
324 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
325 #define VM_GET_HPET_CAPABILITIES \
326 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
327 #define VM_GET_GPA_PMAP \
328 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
330 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
331 #define VM_ACTIVATE_CPU \
332 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
333 #define VM_GET_CPUS \
334 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
335 #define VM_SET_INTINFO \
336 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
337 #define VM_GET_INTINFO \
338 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)