2 * Copyright (c) 2001 Tsubai Masanari.
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
42 #include <sys/sysctl.h>
44 #include <dev/iicbus/iicbus.h>
45 #include <dev/iicbus/iiconf.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <arm/broadcom/bcm2835/bcm2835_gpio.h>
50 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
51 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
53 #include "iicbus_if.h"
55 static struct ofw_compat_data compat_data[] = {
56 {"broadcom,bcm2835-bsc", 1},
57 {"brcm,bcm2708-i2c", 1},
58 {"brcm,bcm2835-i2c", 1},
62 static void bcm_bsc_intr(void *);
63 static int bcm_bsc_detach(device_t);
66 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
71 mtx_assert(&sc->sc_mtx, MA_OWNED);
72 reg = BCM_BSC_READ(sc, off);
75 BCM_BSC_WRITE(sc, off, reg);
79 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
81 struct bcm_bsc_softc *sc;
84 sc = (struct bcm_bsc_softc *)arg1;
86 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
91 clk = BCM_BSC_CORE_CLK / clk;
93 return (sysctl_handle_int(oidp, &clk, 0, req));
97 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
99 struct bcm_bsc_softc *sc;
103 sc = (struct bcm_bsc_softc *)arg1;
106 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
109 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
110 if (error != 0 || req->newptr == NULL)
114 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
121 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
123 struct bcm_bsc_softc *sc;
127 sc = (struct bcm_bsc_softc *)arg1;
130 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
133 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
134 if (error != 0 || req->newptr == NULL)
138 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
139 clk = BCM_BSC_CORE_CLK / clk;
142 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
149 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
151 struct bcm_bsc_softc *sc;
155 sc = (struct bcm_bsc_softc *)arg1;
158 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
161 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
162 if (error != 0 || req->newptr == NULL)
166 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
167 clk = BCM_BSC_CORE_CLK / clk;
170 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
177 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
179 struct sysctl_ctx_list *ctx;
180 struct sysctl_oid *tree_node;
181 struct sysctl_oid_list *tree;
184 * Add system sysctl tree/handlers.
186 ctx = device_get_sysctl_ctx(sc->sc_dev);
187 tree_node = device_get_sysctl_tree(sc->sc_dev);
188 tree = SYSCTL_CHILDREN(tree_node);
189 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
190 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
191 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
192 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
193 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
194 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
195 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
196 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
197 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
198 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
199 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
200 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
204 bcm_bsc_reset(struct bcm_bsc_softc *sc)
207 /* Enable the BSC Controller, disable interrupts. */
208 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
209 /* Clear pending interrupts. */
210 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
211 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
212 /* Clear the FIFO. */
213 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
214 BCM_BSC_CTRL_CLEAR0);
218 bcm_bsc_probe(device_t dev)
221 if (!ofw_bus_status_okay(dev))
224 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
227 device_set_desc(dev, "BCM2708/2835 BSC controller");
229 return (BUS_PROBE_DEFAULT);
233 bcm_bsc_attach(device_t dev)
235 struct bcm_bsc_softc *sc;
240 sc = device_get_softc(dev);
244 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
246 if (!sc->sc_mem_res) {
247 device_printf(dev, "cannot allocate memory window\n");
251 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
252 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
254 /* Check the unit we are attaching by its base address. */
255 start = rman_get_start(sc->sc_mem_res);
256 for (i = 0; i < nitems(bcm_bsc_pins); i++) {
257 if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK))
260 if (i == nitems(bcm_bsc_pins)) {
261 device_printf(dev, "only bsc0 and bsc1 are supported\n");
262 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
267 * Configure the GPIO pins to ALT0 function to enable BSC control
270 gpio = devclass_get_device(devclass_find("gpio"), 0);
272 device_printf(dev, "cannot find gpio0\n");
273 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
276 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0);
277 bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0);
280 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
281 RF_ACTIVE | RF_SHAREABLE);
282 if (!sc->sc_irq_res) {
283 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
284 device_printf(dev, "cannot allocate interrupt\n");
288 /* Hook up our interrupt handler. */
289 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
290 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
292 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
293 device_printf(dev, "cannot setup the interrupt handler\n");
297 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
299 bcm_bsc_sysctl_init(sc);
301 /* Enable the BSC controller. Flush the FIFO. */
306 sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
307 if (sc->sc_iicbus == NULL) {
312 return (bus_generic_attach(dev));
316 bcm_bsc_detach(device_t dev)
318 struct bcm_bsc_softc *sc;
320 bus_generic_detach(dev);
322 sc = device_get_softc(dev);
323 mtx_destroy(&sc->sc_mtx);
325 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
329 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
335 bcm_bsc_intr(void *arg)
337 struct bcm_bsc_softc *sc;
340 sc = (struct bcm_bsc_softc *)arg;
344 /* The I2C interrupt is shared among all the BSC controllers. */
345 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
350 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
352 /* Check for errors. */
353 if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) {
354 /* Disable interrupts. */
356 sc->sc_flags |= BCM_I2C_ERROR;
362 if (sc->sc_flags & BCM_I2C_READ) {
363 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) {
364 *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA);
366 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
369 while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) {
370 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++);
372 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
376 if (status & BCM_BSC_STATUS_DONE) {
377 /* Disable interrupts. */
386 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
388 struct bcm_bsc_softc *sc;
389 uint32_t intr, read, status;
392 sc = device_get_softc(dev);
395 /* If the controller is busy wait until it is available. */
396 while (sc->sc_flags & BCM_I2C_BUSY)
397 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
399 /* Now we have control over the BSC controller. */
400 sc->sc_flags = BCM_I2C_BUSY;
402 /* Clear the FIFO and the pending interrupts. */
406 for (i = 0; i < nmsgs; i++) {
408 /* Write the slave address. */
409 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1);
411 /* Write the data length. */
412 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len);
414 sc->sc_data = msgs[i].buf;
415 sc->sc_resid = msgs[i].len;
416 if ((msgs[i].flags & IIC_M_RD) == 0) {
417 /* Fill up the TX FIFO. */
418 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
419 while (sc->sc_resid > 0 &&
420 (status & BCM_BSC_STATUS_TXD)) {
421 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
424 status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
427 intr = BCM_BSC_CTRL_INTT;
428 sc->sc_flags &= ~BCM_I2C_READ;
430 sc->sc_flags |= BCM_I2C_READ;
431 read = BCM_BSC_CTRL_READ;
432 intr = BCM_BSC_CTRL_INTR;
434 intr |= BCM_BSC_CTRL_INTD;
436 /* Start the transfer. */
437 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
438 BCM_BSC_CTRL_ST | read | intr);
440 /* Wait for the transaction to complete. */
441 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz);
443 /* Check for errors. */
444 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
450 /* Clean the controller flags. */
453 /* Wake up the threads waiting for bus. */
462 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
464 struct bcm_bsc_softc *sc;
467 sc = device_get_softc(dev);
470 if (sc->sc_iicbus == NULL)
473 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
474 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
477 return (IIC_ENOADDR);
481 bcm_bsc_get_node(device_t bus, device_t dev)
484 /* We only have one child, the I2C bus, which needs our own node. */
485 return (ofw_bus_get_node(bus));
488 static device_method_t bcm_bsc_methods[] = {
489 /* Device interface */
490 DEVMETHOD(device_probe, bcm_bsc_probe),
491 DEVMETHOD(device_attach, bcm_bsc_attach),
492 DEVMETHOD(device_detach, bcm_bsc_detach),
494 /* iicbus interface */
495 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset),
496 DEVMETHOD(iicbus_callback, iicbus_null_callback),
497 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer),
499 /* ofw_bus interface */
500 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node),
505 static devclass_t bcm_bsc_devclass;
507 static driver_t bcm_bsc_driver = {
510 sizeof(struct bcm_bsc_softc),
513 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0);
514 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);