2 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp>
3 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/queue.h>
40 #include <sys/resource.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
50 #include <machine/bus.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/pmap.h>
55 #include "bcm2835_dma.h"
56 #include "bcm2835_vcbus.h"
61 #define BCM_DMA_CH_USED 0x00000001
62 #define BCM_DMA_CH_FREE 0x40000000
63 #define BCM_DMA_CH_UNMAP 0x80000000
65 /* Register Map (4.2.1.2) */
66 #define BCM_DMA_CS(n) (0x100*(n) + 0x00)
67 #define CS_ACTIVE (1 << 0)
68 #define CS_END (1 << 1)
69 #define CS_INT (1 << 2)
70 #define CS_DREQ (1 << 3)
71 #define CS_ISPAUSED (1 << 4)
72 #define CS_ISHELD (1 << 5)
73 #define CS_ISWAIT (1 << 6)
74 #define CS_ERR (1 << 8)
75 #define CS_WAITWRT (1 << 28)
76 #define CS_DISDBG (1 << 29)
77 #define CS_ABORT (1 << 30)
78 #define CS_RESET (1 << 31)
79 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
80 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
81 #define INFO_INT_EN (1 << 0)
82 #define INFO_TDMODE (1 << 1)
83 #define INFO_WAIT_RESP (1 << 3)
84 #define INFO_D_INC (1 << 4)
85 #define INFO_D_WIDTH (1 << 5)
86 #define INFO_D_DREQ (1 << 6)
87 #define INFO_S_INC (1 << 8)
88 #define INFO_S_WIDTH (1 << 9)
89 #define INFO_S_DREQ (1 << 10)
90 #define INFO_WAITS_SHIFT (21)
91 #define INFO_PERMAP_SHIFT (16)
92 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT)
94 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C)
95 #define BCM_DMA_DST(n) (0x100*(n) + 0x10)
96 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14)
97 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18)
98 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C)
99 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20)
100 #define DEBUG_ERROR_MASK (7)
102 #define BCM_DMA_INT_STATUS 0xfe0
103 #define BCM_DMA_ENABLE 0xff0
105 /* relative offset from BCM_VC_DMA0_BASE (p.39) */
106 #define BCM_DMA_CH(n) (0x100*(n))
108 /* DMA Control Block - 256bit aligned (p.40) */
110 uint32_t info; /* Transfer Information */
111 uint32_t src; /* Source Address */
112 uint32_t dst; /* Destination Address */
113 uint32_t len; /* Transfer Length */
114 uint32_t stride; /* 2D Mode Stride */
115 uint32_t next; /* Next Control Block Address */
116 uint32_t rsvd1; /* Reserved */
117 uint32_t rsvd2; /* Reserved */
121 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb);
122 static void bcm_dma_reg_dump(int ch);
125 /* DMA channel private info */
129 struct bcm_dma_cb * cb;
131 bus_dmamap_t dma_map;
132 void (*intr_func)(int, void *);
136 struct bcm_dma_softc {
139 struct resource * sc_mem;
140 struct resource * sc_irq[BCM_DMA_CH_MAX];
141 void * sc_intrhand[BCM_DMA_CH_MAX];
142 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX];
143 bus_dma_tag_t sc_dma_tag;
146 static struct bcm_dma_softc *bcm_dma_sc = NULL;
149 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
157 addr = (bus_addr_t*)arg;
158 *addr = PHYS_TO_VCBUS(segs[0].ds_addr);
162 bcm_dma_reset(device_t dev, int ch)
164 struct bcm_dma_softc *sc = device_get_softc(dev);
165 struct bcm_dma_cb *cb;
169 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
172 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
174 if (cs & CS_ACTIVE) {
175 /* pause current task */
176 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);
180 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
181 } while (!(cs & CS_ISPAUSED) && (count-- > 0));
183 if (!(cs & CS_ISPAUSED)) {
185 "Can't abort DMA transfer at channel %d\n", ch);
188 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
190 /* Complete everything, clear interrupt */
191 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),
192 CS_ABORT | CS_INT | CS_END| CS_ACTIVE);
195 /* clear control blocks */
196 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);
197 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
199 /* Reset control block */
200 cb = sc->sc_dma_ch[ch].cb;
201 bzero(cb, sizeof(*cb));
202 cb->info = INFO_WAIT_RESP;
206 bcm_dma_init(device_t dev)
208 struct bcm_dma_softc *sc = device_get_softc(dev);
210 struct bcm_dma_ch *ch;
216 /* disable and clear interrupt status */
217 bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, 0);
218 bus_write_4(sc->sc_mem, BCM_DMA_INT_STATUS, 0);
220 /* Allocate DMA chunks control blocks */
221 /* p.40 of spec - control block should be 32-bit aligned */
222 err = bus_dma_tag_create(bus_get_dma_tag(dev),
223 1, 0, BUS_SPACE_MAXADDR_32BIT,
224 BUS_SPACE_MAXADDR, NULL, NULL,
225 sizeof(struct bcm_dma_cb), 1,
226 sizeof(struct bcm_dma_cb),
227 BUS_DMA_ALLOCNOW, NULL, NULL,
231 device_printf(dev, "failed allocate DMA tag");
235 /* setup initial settings */
236 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
237 ch = &sc->sc_dma_ch[i];
239 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt,
240 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
243 device_printf(dev, "cannot allocate DMA memory\n");
248 * Least alignment for busdma-allocated stuff is cache
249 * line size, so just make sure nothing stupid happend
250 * and we got properly aligned address
252 if ((uintptr_t)cb_virt & 0x1f) {
254 "DMA address is not 32-bytes aligned: %p\n",
259 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt,
260 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys,
263 device_printf(dev, "cannot load DMA memory\n");
267 bzero(ch, sizeof(struct bcm_dma_ch));
271 ch->intr_func = NULL;
273 ch->flags = BCM_DMA_CH_UNMAP;
275 ch->cb->info = INFO_WAIT_RESP;
277 /* reset DMA engine */
278 bcm_dma_reset(dev, i);
281 /* now use DMA2/DMA3 only */
282 sc->sc_dma_ch[2].flags = BCM_DMA_CH_FREE;
283 sc->sc_dma_ch[3].flags = BCM_DMA_CH_FREE;
288 for (i = 0; i < BCM_DMA_CH_MAX; i++)
289 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE)
292 bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, mask);
298 * Allocate DMA channel for further use, returns channel # or
302 bcm_dma_allocate(int req_ch)
304 struct bcm_dma_softc *sc = bcm_dma_sc;
305 int ch = BCM_DMA_CH_INVALID;
308 if (req_ch >= BCM_DMA_CH_MAX)
309 return (BCM_DMA_CH_INVALID);
311 /* Auto(req_ch < 0) or CH specified */
312 mtx_lock(&sc->sc_mtx);
315 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
316 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) {
318 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
319 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
325 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) {
327 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
328 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
332 mtx_unlock(&sc->sc_mtx);
337 * Frees allocated channel. Returns 0 on success, -1 otherwise
342 struct bcm_dma_softc *sc = bcm_dma_sc;
344 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
347 mtx_lock(&sc->sc_mtx);
348 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) {
349 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE;
350 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED;
351 sc->sc_dma_ch[ch].intr_func = NULL;
352 sc->sc_dma_ch[ch].intr_arg = NULL;
354 /* reset DMA engine */
355 bcm_dma_reset(sc->sc_dev, ch);
358 mtx_unlock(&sc->sc_mtx);
363 * Assign handler function for channel interrupt
364 * Returns 0 on success, -1 otherwise
367 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg)
369 struct bcm_dma_softc *sc = bcm_dma_sc;
370 struct bcm_dma_cb *cb;
372 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
375 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
378 sc->sc_dma_ch[ch].intr_func = func;
379 sc->sc_dma_ch[ch].intr_arg = arg;
380 cb = sc->sc_dma_ch[ch].cb;
381 cb->info |= INFO_INT_EN;
387 * Setup DMA source parameters
388 * ch - channel number
389 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
390 * source is physical memory
391 * inc_addr - BCM_DMA_INC_ADDR if source address
392 * should be increased after each access or
393 * BCM_DMA_SAME_ADDR if address should remain
395 * width - size of read operation, BCM_DMA_32BIT
396 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
398 * Returns 0 on success, -1 otherwise
401 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width)
403 struct bcm_dma_softc *sc = bcm_dma_sc;
406 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
409 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
412 info = sc->sc_dma_ch[ch].cb->info;
413 info &= ~INFO_PERMAP_MASK;
414 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
419 info &= ~INFO_S_DREQ;
421 if (width == BCM_DMA_128BIT)
422 info |= INFO_S_WIDTH;
424 info &= ~INFO_S_WIDTH;
426 if (inc_addr == BCM_DMA_INC_ADDR)
431 sc->sc_dma_ch[ch].cb->info = info;
437 * Setup DMA destination parameters
438 * ch - channel number
439 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
440 * destination is physical memory
441 * inc_addr - BCM_DMA_INC_ADDR if source address
442 * should be increased after each access or
443 * BCM_DMA_SAME_ADDR if address should remain
445 * width - size of write operation, BCM_DMA_32BIT
446 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
448 * Returns 0 on success, -1 otherwise
451 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width)
453 struct bcm_dma_softc *sc = bcm_dma_sc;
456 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
459 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
462 info = sc->sc_dma_ch[ch].cb->info;
463 info &= ~INFO_PERMAP_MASK;
464 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
469 info &= ~INFO_D_DREQ;
471 if (width == BCM_DMA_128BIT)
472 info |= INFO_D_WIDTH;
474 info &= ~INFO_D_WIDTH;
476 if (inc_addr == BCM_DMA_INC_ADDR)
481 sc->sc_dma_ch[ch].cb->info = info;
488 bcm_dma_cb_dump(struct bcm_dma_cb *cb)
492 printf("INFO: %8.8x ", cb->info);
493 printf("SRC: %8.8x ", cb->src);
494 printf("DST: %8.8x ", cb->dst);
495 printf("LEN: %8.8x ", cb->len);
497 printf("STRIDE: %8.8x ", cb->stride);
498 printf("NEXT: %8.8x ", cb->next);
499 printf("RSVD1: %8.8x ", cb->rsvd1);
500 printf("RSVD2: %8.8x ", cb->rsvd2);
505 bcm_dma_reg_dump(int ch)
507 struct bcm_dma_softc *sc = bcm_dma_sc;
511 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
514 printf("DMA%d: ", ch);
515 for (i = 0; i < MAX_REG; i++) {
516 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);
517 printf("%8.8x ", reg);
524 * Start DMA transaction
525 * ch - channel number
526 * src, dst - source and destination address in
527 * ARM physical memory address space.
528 * len - amount of bytes to be transfered
530 * Returns 0 on success, -1 otherwise
533 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len)
535 struct bcm_dma_softc *sc = bcm_dma_sc;
536 struct bcm_dma_cb *cb;
538 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
541 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
544 cb = sc->sc_dma_ch[ch].cb;
545 if (BCM2835_ARM_IS_IO(src))
546 cb->src = IO_TO_VCBUS(src);
548 cb->src = PHYS_TO_VCBUS(src);
549 if (BCM2835_ARM_IS_IO(dst))
550 cb->dst = IO_TO_VCBUS(dst);
552 cb->dst = PHYS_TO_VCBUS(dst);
555 bus_dmamap_sync(sc->sc_dma_tag,
556 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE);
558 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),
559 sc->sc_dma_ch[ch].vc_cb);
560 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);
563 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb);
564 bcm_dma_reg_dump(ch);
571 * Get length requested for DMA transaction
572 * ch - channel number
574 * Returns size of transaction, 0 if channel is invalid
577 bcm_dma_length(int ch)
579 struct bcm_dma_softc *sc = bcm_dma_sc;
580 struct bcm_dma_cb *cb;
582 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
585 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
588 cb = sc->sc_dma_ch[ch].cb;
594 bcm_dma_intr(void *arg)
596 struct bcm_dma_softc *sc = bcm_dma_sc;
597 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
601 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));
603 if (!(cs & (CS_INT | CS_ERR)))
607 if (!(ch->flags & BCM_DMA_CH_USED)) {
608 device_printf(sc->sc_dev,
609 "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs);
614 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
615 device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
616 debug & DEBUG_ERROR_MASK, ch->ch);
617 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),
618 debug & DEBUG_ERROR_MASK);
619 bcm_dma_reset(sc->sc_dev, ch->ch);
623 /* acknowledge interrupt */
624 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),
627 /* Prepare for possible access to len field */
628 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
629 BUS_DMASYNC_POSTWRITE);
631 /* save callback function and argument */
633 ch->intr_func(ch->ch, ch->intr_arg);
638 bcm_dma_probe(device_t dev)
641 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-dma"))
644 device_set_desc(dev, "BCM2835 DMA Controller");
645 return (BUS_PROBE_DEFAULT);
649 bcm_dma_attach(device_t dev)
651 struct bcm_dma_softc *sc = device_get_softc(dev);
660 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
661 sc->sc_irq[i] = NULL;
662 sc->sc_intrhand[i] = NULL;
667 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
668 if (sc->sc_mem == NULL) {
669 device_printf(dev, "could not allocate memory resource\n");
673 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */
674 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) {
675 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
677 if (sc->sc_irq[rid] == NULL) {
678 device_printf(dev, "cannot allocate interrupt\n");
682 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE,
683 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid],
684 &sc->sc_intrhand[rid])) {
685 device_printf(dev, "cannot setup interrupt handler\n");
691 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF);
694 err = bcm_dma_init(dev);
702 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem);
704 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
705 if (sc->sc_intrhand[i])
706 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]);
708 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]);
714 static device_method_t bcm_dma_methods[] = {
715 DEVMETHOD(device_probe, bcm_dma_probe),
716 DEVMETHOD(device_attach, bcm_dma_attach),
720 static driver_t bcm_dma_driver = {
723 sizeof(struct bcm_dma_softc),
726 static devclass_t bcm_dma_devclass;
728 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0);
729 MODULE_VERSION(bcm_dma, 1);