2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended to Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/module.h>
41 #include <machine/bus.h>
42 #include <machine/intr.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <arm/mv/mvreg.h>
48 #include <arm/mv/mvvar.h>
51 struct resource * ic_res[1];
52 bus_space_tag_t ic_bst;
53 bus_space_handle_t ic_bsh;
58 static struct resource_spec mv_ic_spec[] = {
59 { SYS_RES_MEMORY, 0, RF_ACTIVE },
63 static struct mv_ic_softc *mv_ic_sc = NULL;
65 static int mv_ic_probe(device_t);
66 static int mv_ic_attach(device_t);
68 uint32_t mv_ic_get_cause(void);
69 uint32_t mv_ic_get_mask(void);
70 void mv_ic_set_mask(uint32_t);
71 uint32_t mv_ic_get_cause_hi(void);
72 uint32_t mv_ic_get_mask_hi(void);
73 void mv_ic_set_mask_hi(uint32_t);
74 uint32_t mv_ic_get_cause_error(void);
75 uint32_t mv_ic_get_mask_error(void);
76 void mv_ic_set_mask_error(uint32_t);
77 static void arm_mask_irq_all(void);
80 mv_ic_probe(device_t dev)
83 if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
86 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
91 mv_ic_attach(device_t dev)
93 struct mv_ic_softc *sc;
94 uint32_t dev_id, rev_id;
97 sc = (struct mv_ic_softc *)device_get_softc(dev);
103 soc_id(&dev_id, &rev_id);
105 sc->ic_high_regs = 0;
106 sc->ic_error_regs = 0;
108 if (dev_id == MV_DEV_88F6281 || dev_id == MV_DEV_MV78100 ||
109 dev_id == MV_DEV_MV78100_Z0)
110 sc->ic_high_regs = 1;
112 if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
113 sc->ic_error_regs = 1;
115 error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
117 device_printf(dev, "could not allocate resources\n");
121 sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
122 sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
124 /* Mask all interrupts */
130 static device_method_t mv_ic_methods[] = {
131 DEVMETHOD(device_probe, mv_ic_probe),
132 DEVMETHOD(device_attach, mv_ic_attach),
136 static driver_t mv_ic_driver = {
139 sizeof(struct mv_ic_softc),
142 static devclass_t mv_ic_devclass;
144 DRIVER_MODULE(ic, simplebus, mv_ic_driver, mv_ic_devclass, 0, 0);
147 arm_get_next_irq(int last)
152 filt = ~((last >= 0) ? (2 << last) - 1 : 0);
153 irq = mv_ic_get_cause() & mv_ic_get_mask();
155 next = ffs(irq & filt) - 1;
158 if (mv_ic_sc->ic_high_regs) {
159 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
160 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
162 next = ffs(irq & filt) + 31;
166 if (mv_ic_sc->ic_error_regs) {
167 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
168 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
170 next = ffs(irq & filt) + 63;
177 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
182 arm_mask_irq_all(void)
187 if (mv_ic_sc->ic_high_regs)
188 mv_ic_set_mask_hi(0);
190 if (mv_ic_sc->ic_error_regs)
191 mv_ic_set_mask_error(0);
195 arm_mask_irq(uintptr_t nb)
200 mr = mv_ic_get_mask();
204 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
205 mr = mv_ic_get_mask_hi();
206 mr &= ~(1 << (nb - 32));
207 mv_ic_set_mask_hi(mr);
209 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
210 mr = mv_ic_get_mask_error();
211 mr &= ~(1 << (nb - 64));
212 mv_ic_set_mask_error(mr);
217 arm_unmask_irq(uintptr_t nb)
222 mr = mv_ic_get_mask();
226 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
227 mr = mv_ic_get_mask_hi();
228 mr |= (1 << (nb - 32));
229 mv_ic_set_mask_hi(mr);
231 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
232 mr = mv_ic_get_mask_error();
233 mr |= (1 << (nb - 64));
234 mv_ic_set_mask_error(mr);
239 mv_ic_set_mask(uint32_t val)
242 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
250 return (bus_space_read_4(mv_ic_sc->ic_bst,
251 mv_ic_sc->ic_bsh, IRQ_MASK));
255 mv_ic_get_cause(void)
258 return (bus_space_read_4(mv_ic_sc->ic_bst,
259 mv_ic_sc->ic_bsh, IRQ_CAUSE));
263 mv_ic_set_mask_hi(uint32_t val)
266 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
271 mv_ic_get_mask_hi(void)
274 return (bus_space_read_4(mv_ic_sc->ic_bst,
275 mv_ic_sc->ic_bsh, IRQ_MASK_HI));
279 mv_ic_get_cause_hi(void)
282 return (bus_space_read_4(mv_ic_sc->ic_bst,
283 mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
287 mv_ic_set_mask_error(uint32_t val)
290 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
291 IRQ_MASK_ERROR, val);
295 mv_ic_get_mask_error(void)
298 return (bus_space_read_4(mv_ic_sc->ic_bst,
299 mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
303 mv_ic_get_cause_error(void)
306 return (bus_space_read_4(mv_ic_sc->ic_bst,
307 mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));