2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * This software is derived from software provide by Kwikbyte who specifically
25 * disclaimed copyright on the code.
30 //*---------------------------------------------------------------------------
31 //* ATMEL Microcontroller Software Support - ROUSSET -
32 //*---------------------------------------------------------------------------
33 //* The software is delivered "AS IS" without warranty or condition of any
34 //* kind, either express, implied or statutory. This includes without
35 //* limitation any warranty or condition with respect to merchantability or
36 //* fitness for any particular purpose, or against the infringements of
37 //* intellectual property rights of others.
38 //*---------------------------------------------------------------------------
39 //* File Name : AT91C_MCI_Device.h
40 //* Object : Data Flash Atmel Description File
43 //* 1.0 26/11/02 FB : Creation
44 //*---------------------------------------------------------------------------
46 #ifndef __MCI_Device_h
47 #define __MCI_Device_h
49 #include <sys/types.h>
51 typedef unsigned int AT91S_MCIDeviceStatus;
53 ///////////////////////////////////////////////////////////////////////////////
55 #define AT91C_CARD_REMOVED 0
56 #define AT91C_MMC_CARD_INSERTED 1
57 #define AT91C_SD_CARD_INSERTED 2
59 #define AT91C_NO_ARGUMENT 0x0
61 #define AT91C_FIRST_RCA 0xCAFE
62 #define AT91C_MAX_MCI_CARDS 10
64 #define AT91C_BUS_WIDTH_1BIT 0x00
65 #define AT91C_BUS_WIDTH_4BITS 0x02
68 #define AT91C_MCI_IDLE 0x0
69 #define AT91C_MCI_TIMEOUT_ERROR 0x1
70 #define AT91C_MCI_RX_SINGLE_BLOCK 0x2
71 #define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3
72 #define AT91C_MCI_RX_STREAM 0x4
73 #define AT91C_MCI_TX_SINGLE_BLOCK 0x5
74 #define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6
75 #define AT91C_MCI_TX_STREAM 0x7
78 #define AT91C_TIMEOUT_CMDRDY 30
82 ///////////////////////////////////////////////////////////////////////////////
83 // MMC & SDCard Structures
84 ///////////////////////////////////////////////////////////////////////////////
86 /*---------------------------------------------*/
87 /* MCI Device Structure Definition */
88 /*---------------------------------------------*/
89 typedef struct _AT91S_MciDevice
91 volatile unsigned char state;
92 unsigned char SDCard_bus_width;
93 unsigned int RCA; // RCA
94 unsigned int READ_BL_LEN;
96 unsigned int Memory_Capacity;
100 #include <dev/mmc/mmcreg.h>
102 ///////////////////////////////////////////////////////////////////////////////
103 // Functions returnals
104 ///////////////////////////////////////////////////////////////////////////////
105 #define AT91C_CMD_SEND_OK 0 // Command ok
106 #define AT91C_CMD_SEND_ERROR -1 // Command failed
107 #define AT91C_INIT_OK 2 // Init Successfull
108 #define AT91C_INIT_ERROR 3 // Init Failed
109 #define AT91C_READ_OK 4 // Read Successfull
110 #define AT91C_READ_ERROR 5 // Read Failed
111 #define AT91C_WRITE_OK 6 // Write Successfull
112 #define AT91C_WRITE_ERROR 7 // Write Failed
113 #define AT91C_ERASE_OK 8 // Erase Successfull
114 #define AT91C_ERASE_ERROR 9 // Erase Failed
115 #define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull
116 #define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed
118 #define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \
119 AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \
120 AT91C_MCI_RDIRE | AT91C_MCI_RINDE)
122 #define MMC_CMDNB (0x1Fu << 0) // Command Number
123 #define MMC_RSPTYP (0x3u << 6) // Response Type
124 #define MMC_RSPTYP_NO (0x0u << 6) // No response
125 #define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response
126 #define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response
127 #define MMC_SPCMD (0x7u << 8) // Special CMD
128 #define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD
129 #define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD
130 #define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD
131 #define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command
132 #define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response
133 #define MMC_OPDCMD (0x1u << 11) // Open Drain Command
134 #define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond
135 #define MMC_TRCMD (0x3u << 16) // Transfer CMD
136 #define MMC_TRCMD_NO (0x0u << 16) // No transfer
137 #define MMC_TRCMD_START (0x1u << 16) // Start transfer
138 #define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer
139 #define MMC_TRDIR (0x1u << 18) // Transfer Direction
140 #define MMC_TRTYP (0x3u << 19) // Transfer Type
141 #define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type
142 #define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type
143 #define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type
145 ///////////////////////////////////////////////////////////////////////////////
146 // MCI_CMD Register Value
147 ///////////////////////////////////////////////////////////////////////////////
148 #define POWER_ON_INIT \
149 (0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD)
151 /////////////////////////////////////////////////////////////////
152 // Class 0 & 1 commands: Basic commands and Read Stream commands
153 /////////////////////////////////////////////////////////////////
155 #define GO_IDLE_STATE_CMD \
156 (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE )
157 #define MMC_GO_IDLE_STATE_CMD \
158 (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD)
159 #define MMC_SEND_OP_COND_CMD \
160 (1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
163 #define ALL_SEND_CID_CMD \
164 (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136)
165 #define MMC_ALL_SEND_CID_CMD \
166 (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
169 #define SET_RELATIVE_ADDR_CMD \
170 (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
172 #define MMC_SET_RELATIVE_ADDR_CMD \
173 (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
174 MMC_MAXLAT | MMC_OPDCMD)
176 #define SET_DSR_CMD \
177 (4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \
178 MMC_MAXLAT) // no tested
180 #define SEL_DESEL_CARD_CMD \
181 (7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
183 #define SEND_CSD_CMD \
184 (9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
186 #define SEND_CID_CMD \
187 (10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
189 #define MMC_READ_DAT_UNTIL_STOP_CMD \
190 (11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \
191 MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \
194 #define STOP_TRANSMISSION_CMD \
195 (12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
197 #define STOP_TRANSMISSION_SYNC_CMD \
198 (12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \
200 #define SEND_STATUS_CMD \
201 (13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
203 #define GO_INACTIVE_STATE_CMD \
206 //*------------------------------------------------
207 //* Class 2 commands: Block oriented Read commands
208 //*------------------------------------------------
210 #define SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT )
211 #define READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT)
212 #define READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT)
214 //*--------------------------------------------
215 //* Class 3 commands: Sequential write commands
216 //*--------------------------------------------
218 #define MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC
220 //*------------------------------------------------
221 //* Class 4 commands: Block oriented write commands
222 //*------------------------------------------------
224 #define WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT)
225 #define WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT)
226 #define PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 )
229 //*----------------------------------------
230 //* Class 6 commands: Group Write protect
231 //*----------------------------------------
233 #define SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 )
234 #define CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 )
235 #define SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 )
238 //*----------------------------------------
239 //* Class 5 commands: Erase commands
240 //*----------------------------------------
242 #define TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
243 #define TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
244 #define MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 )
245 #define MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 )
246 #define MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 )
247 #define MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 )
248 #define ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT )
250 //*----------------------------------------
251 //* Class 7 commands: Lock commands
252 //*----------------------------------------
254 #define LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
256 //*-----------------------------------------------
257 // Class 8 commands: Application specific commands
258 //*-----------------------------------------------
260 #define APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
261 #define GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
263 #define SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
264 #define SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
265 #define SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
266 #define SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
267 #define SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO )
268 #define SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
269 #define SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
271 #define SDCARD_APP_ALL_CMD (SDCARD_SET_BUS_WIDTH_CMD +\
273 SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
274 SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
275 SDCARD_APP_OP_COND_CMD +\
276 SDCARD_SET_CLR_CARD_DETECT_CMD +\
279 //*----------------------------------------
280 //* Class 9 commands: IO Mode commands
281 //*----------------------------------------
283 #define MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT)
284 #define MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
286 ///////////////////////////////////////////////////////////////////////////////
288 ///////////////////////////////////////////////////////////////////////////////
289 #define AT91C_VDD_16_17 (1 << 4)
290 #define AT91C_VDD_17_18 (1 << 5)
291 #define AT91C_VDD_18_19 (1 << 6)
292 #define AT91C_VDD_19_20 (1 << 7)
293 #define AT91C_VDD_20_21 (1 << 8)
294 #define AT91C_VDD_21_22 (1 << 9)
295 #define AT91C_VDD_22_23 (1 << 10)
296 #define AT91C_VDD_23_24 (1 << 11)
297 #define AT91C_VDD_24_25 (1 << 12)
298 #define AT91C_VDD_25_26 (1 << 13)
299 #define AT91C_VDD_26_27 (1 << 14)
300 #define AT91C_VDD_27_28 (1 << 15)
301 #define AT91C_VDD_28_29 (1 << 16)
302 #define AT91C_VDD_29_30 (1 << 17)
303 #define AT91C_VDD_30_31 (1 << 18)
304 #define AT91C_VDD_31_32 (1 << 19)
305 #define AT91C_VDD_32_33 (1 << 20)
306 #define AT91C_VDD_33_34 (1 << 21)
307 #define AT91C_VDD_34_35 (1 << 22)
308 #define AT91C_VDD_35_36 (1 << 23)
309 #define AT91C_CARD_POWER_UP_BUSY (1 << 31)
311 #define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \
312 AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33)
314 ///////////////////////////////////////////////////////////////////////////////
315 // CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
316 ///////////////////////////////////////////////////////////////////////////////
317 #define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus
318 #define AT91C_SR_IDLE (0 << 9)
319 #define AT91C_SR_READY (1 << 9)
320 #define AT91C_SR_IDENT (2 << 9)
321 #define AT91C_SR_STBY (3 << 9)
322 #define AT91C_SR_TRAN (4 << 9)
323 #define AT91C_SR_DATA (5 << 9)
324 #define AT91C_SR_RCV (6 << 9)
325 #define AT91C_SR_PRG (7 << 9)
326 #define AT91C_SR_DIS (8 << 9)
328 #define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
330 #define MMC_FIRST_RCA 0xCAFE
332 ///////////////////////////////////////////////////////////////////////////////
333 // MMC CSD register header File
334 // CSD_x_xxx_S for shift value for word x
335 // CSD_x_xxx_M for mask value for word x
336 ///////////////////////////////////////////////////////////////////////////////
338 // First Response INT <=> CSD[3] : bits 0 to 31
339 #define CSD_3_BIT0_S 0 // [0:0]
340 #define CSD_3_BIT0_M 0x01
341 #define CSD_3_CRC_S 1 // [7:1]
342 #define CSD_3_CRC_M 0x7F
343 #define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility
344 #define CSD_3_MMC_ECC_M 0x03
345 #define CSD_3_FILE_FMT_S 10 // [11:10]
346 #define CSD_3_FILE_FMT_M 0x03
347 #define CSD_3_TMP_WP_S 12 // [12:12]
348 #define CSD_3_TMP_WP_M 0x01
349 #define CSD_3_PERM_WP_S 13 // [13:13]
350 #define CSD_3_PERM_WP_M 0x01
351 #define CSD_3_COPY_S 14 // [14:14]
352 #define CSD_3_COPY_M 0x01
353 #define CSD_3_FILE_FMT_GRP_S 15 // [15:15]
354 #define CSD_3_FILE_FMT_GRP_M 0x01
355 // reserved 16 // [20:16]
357 #define CSD_3_WBLOCK_P_S 21 // [21:21]
358 #define CSD_3_WBLOCK_P_M 0x01
359 #define CSD_3_WBLEN_S 22 // [25:22]
360 #define CSD_3_WBLEN_M 0x0F
361 #define CSD_3_R2W_F_S 26 // [28:26]
362 #define CSD_3_R2W_F_M 0x07
363 #define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility
364 #define CSD_3_MMC_DEF_ECC_M 0x03
365 #define CSD_3_WP_GRP_EN_S 31 // [31:31]
366 #define CSD_3_WP_GRP_EN_M 0x01
368 // Seconde Response INT <=> CSD[2] : bits 32 to 63
369 #define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32]
370 #define CSD_2_v21_WP_GRP_SIZE_M 0x7F
371 #define CSD_2_v21_SECT_SIZE_S 7 // [45:39]
372 #define CSD_2_v21_SECT_SIZE_M 0x7F
373 #define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46]
374 #define CSD_2_v21_ER_BLEN_EN_M 0x01
376 #define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32]
377 #define CSD_2_v22_WP_GRP_SIZE_M 0x1F
378 #define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37]
379 #define CSD_2_v22_ER_GRP_SIZE_M 0x1F
380 #define CSD_2_v22_SECT_SIZE_S 10 // [46:42]
381 #define CSD_2_v22_SECT_SIZE_M 0x1F
383 #define CSD_2_C_SIZE_M_S 15 // [49:47]
384 #define CSD_2_C_SIZE_M_M 0x07
385 #define CSD_2_VDD_WMAX_S 18 // [52:50]
386 #define CSD_2_VDD_WMAX_M 0x07
387 #define CSD_2_VDD_WMIN_S 21 // [55:53]
388 #define CSD_2_VDD_WMIN_M 0x07
389 #define CSD_2_RCUR_MAX_S 24 // [58:56]
390 #define CSD_2_RCUR_MAX_M 0x07
391 #define CSD_2_RCUR_MIN_S 27 // [61:59]
392 #define CSD_2_RCUR_MIN_M 0x07
393 #define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE
394 #define CSD_2_CSIZE_L_M 0x03
396 // Third Response INT <=> CSD[1] : bits 64 to 95
397 #define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE
398 #define CSD_1_CSIZE_H_M 0x03FF
399 // reserved 10 // [75:74]
401 #define CSD_1_DSR_I_S 12 // [76:76]
402 #define CSD_1_DSR_I_M 0x01
403 #define CSD_1_RD_B_MIS_S 13 // [77:77]
404 #define CSD_1_RD_B_MIS_M 0x01
405 #define CSD_1_WR_B_MIS_S 14 // [78:78]
406 #define CSD_1_WR_B_MIS_M 0x01
407 #define CSD_1_RD_B_PAR_S 15 // [79:79]
408 #define CSD_1_RD_B_PAR_M 0x01
409 #define CSD_1_RD_B_LEN_S 16 // [83:80]
410 #define CSD_1_RD_B_LEN_M 0x0F
411 #define CSD_1_CCC_S 20 // [95:84]
412 #define CSD_1_CCC_M 0x0FFF
414 // Fourth Response INT <=> CSD[0] : bits 96 to 127
415 #define CSD_0_TRANS_SPEED_S 0 // [103:96]
416 #define CSD_0_TRANS_SPEED_M 0xFF
417 #define CSD_0_NSAC_S 8 // [111:104]
418 #define CSD_0_NSAC_M 0xFF
419 #define CSD_0_TAAC_S 16 // [119:112]
420 #define CSD_0_TAAC_M 0xFF
421 // reserved 24 // [121:120]
423 #define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility
424 #define CSD_0_MMC_SPEC_VERS_M 0x0F
425 #define CSD_0_STRUCT_S 30 // [127:126]
426 #define CSD_0_STRUCT_M 0x03
428 ///////////////////////////////////////////////////////////////////////////////