2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 interrupt-parent = <&AINTC>;
38 compatible = "simple-bus";
42 AINTC: interrupt-controller@48200000 {
43 compatible = "ti,aintc";
46 #interrupt-cells = <1>;
47 reg = < 0x48200000 0x1000 >;
51 compatible = "ti,scm";
52 reg = < 0x44e10000 0x2000 >;
56 compatible = "am335x,prcm";
59 reg = < 0x44E00000 0x1300 >;
63 compatible = "ti,am335x-dmtimer";
66 reg = < 0x44E05000 0x1000
74 interrupts = < 66 67 68 69 92 93 94 95 >;
75 interrupt-parent = <&AINTC>;
79 compatible = "ti,adc";
80 reg = <0x44E0D000 0x2000>;
82 interrupt-parent = <&AINTC>;
87 compatible = "ti,gpio";
89 reg =< 0x44E07000 0x1000
93 interrupts = < 96 97 98 99 32 33 62 63 >;
94 interrupt-parent = <&AINTC>;
97 uart0: serial@44E09000 {
98 compatible = "ti,ns16550";
99 reg = <0x44E09000 0x1000>;
102 interrupt-parent = <&AINTC>;
103 clock-frequency = < 48000000 >;
104 uart-device-id = < 0 >;
107 uart1: serial@48022000 {
108 compatible = "ti,ns16550";
109 reg = <0x48022000 0x1000>;
112 interrupt-parent = <&AINTC>;
113 clock-frequency = < 48000000 >;
114 uart-device-id = < 1 >;
118 uart2: serial@48024000 {
119 compatible = "ti,ns16550";
120 reg = <0x48024000 0x1000>;
123 interrupt-parent = <&AINTC>;
124 clock-frequency = < 48000000 >;
125 uart-device-id = < 2 >;
129 uart3: serial@481a6000 {
130 compatible = "ti,ns16550";
131 reg = <0x481A6000 0x1000>;
134 interrupt-parent = <&AINTC>;
135 clock-frequency = < 48000000 >;
136 uart-device-id = < 3 >;
140 uart4: serial@481a8000 {
141 compatible = "ti,ns16550";
142 reg = <0x481A8000 0x1000>;
145 interrupt-parent = <&AINTC>;
146 clock-frequency = < 48000000 >;
147 uart-device-id = < 4 >;
151 uart5: serial@481aa000 {
152 compatible = "ti,ns16550";
153 reg = <0x481AA000 0x1000>;
156 interrupt-parent = <&AINTC>;
157 clock-frequency = < 48000000 >;
158 uart-device-id = < 5 >;
163 compatible = "ti,edma3";
164 reg =< 0x49000000 0x100000 /* Channel Controller Regs */
165 0x49800000 0x100000 /* Transfer Controller 0 Regs */
166 0x49900000 0x100000 /* Transfer Controller 1 Regs */
167 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */
168 interrupts = <12 13 14>;
169 interrupt-parent = <&AINTC>;
173 compatible = "ti,omap3-hsmmc", "ti,mmchs";
174 reg =<0x48060000 0x1000 >;
176 interrupt-parent = <&AINTC>;
177 mmchs-device-id = <0>;
178 mmchs-wp-gpio-pin = <0xffffffff>;
183 compatible = "ti,omap3-hsmmc", "ti,mmchs";
184 reg =<0x481D8000 0x1000 >;
186 interrupt-parent = <&AINTC>;
187 mmchs-device-id = <1>;
188 mmchs-wp-gpio-pin = <0xffffffff>;
192 enet0: ethernet@4A100000 {
193 #address-cells = <1>;
195 compatible = "ti,cpsw";
196 reg = <0x4A100000 0x4000>;
197 interrupts = <40 41 42 43>;
198 interrupt-parent = <&AINTC>;
199 phy-handle = <&phy0>;
201 #address-cells = <1>;
203 compatible = "ti,cpsw-mdio";
204 phy0: ethernet-phy@0 {
211 #address-cells = <1>;
213 compatible = "ti,i2c";
214 reg =< 0x44e0b000 0x1000 >;
216 interrupt-parent = <&AINTC>;
221 #address-cells = <1>;
223 compatible = "ti,i2c";
224 reg =< 0x4802a000 0x1000 >;
226 interrupt-parent = <&AINTC>;
231 #address-cells = <1>;
233 compatible = "ti,i2c";
234 reg =< 0x4819c000 0x1000 >;
236 interrupt-parent = <&AINTC>;
241 compatible = "ti,am335x-pwm";
242 #address-cells = <1>;
244 reg = < 0x48300000 0x100 /* PWMSS0 */
245 0x48300100 0x80 /* eCAP0 */
246 0x48300180 0x80 /* eQEP0 */
247 0x48300200 0x60 /* ePWM0 */
249 interrupts = <86 58>; /* ePWM0INT, ePWM0_TZINT */
250 interrupt-parent = <&AINTC>;
255 compatible = "ti,am335x-pwm";
256 #address-cells = <1>;
258 reg = < 0x48302000 0x100 /* PWMSS1 */
259 0x48302100 0x80 /* eCAP1 */
260 0x48302180 0x80 /* eQEP1 */
261 0x48302200 0x60 /* ePWM1 */
263 interrupts = <87 59>; /* ePWM1INT, ePWM1_TZINT */
264 interrupt-parent = <&AINTC>;
269 compatible = "ti,am335x-pwm";
270 #address-cells = <1>;
272 reg = < 0x48304000 0x100 /* PWMSS2 */
273 0x48304100 0x80 /* eCAP2 */
274 0x48304180 0x80 /* eQEP2 */
275 0x48304200 0x60 /* ePWM2 */
277 interrupts = <88 60>; /* ePWM2INT, ePWM2_TZINT */
278 interrupt-parent = <&AINTC>;
283 #address-cells = <1>;
285 compatible = "ti,am335x-lcd";
286 reg =< 0x4830e000 0x1000 >;
288 interrupt-parent = <&AINTC>;
292 #address-cells = <1>;
294 compatible = "ti,musb-am33xx";
295 reg =< 0x47400000 0x1000 /* USBSS */
296 0x47401000 0x300 /* USB0 */
297 0x47401300 0x100 /* USB0_PHY */
298 0x47401400 0x400 /* USB0_CORE */
299 0x47401800 0x300 /* USB1 */
300 0x47401B00 0x100 /* USB1_PHY */
301 0x47401C00 0x400 /* USB1_CORE */
303 interrupts = <17 18 19>;
304 interrupt-parent = <&AINTC>;
305 /* 1 - Host Mode, 0 - Device Mode */
310 compatible = "am335x,system-mbox";
311 reg = < 0x480C8000 0x1000 >;
313 interrupt-parent = <&AINTC>;
317 compatible = "am335x,spinlock";
318 reg = < 0x480CA000 0x1000 >;
322 compatible = "ti,pruss-v2";
323 reg = <0x4A300000 0x80000>;
324 interrupt-parent = <&AINTC>;
325 interrupts = <20 21 22 23 24 25 26 27>;