sys/contrib/ena-com/ena_plat.h

   1 /*-
   2  * BSD LICENSE
   3  *
   4  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * * Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  * * Redistributions in binary form must reproduce the above copyright
  14  * notice, this list of conditions and the following disclaimer in
  15  * the documentation and/or other materials provided with the
  16  * distribution.
  17  * * Neither the name of copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived
  19  * from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef ENA_PLAT_H_
  35 #define ENA_PLAT_H_
  36
  37 #include <sys/cdefs.h>
  38 __FBSDID("$FreeBSD$");
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42
  43 #include <sys/bus.h>
  44 #include <sys/condvar.h>
  45 #include <sys/endian.h>
  46 #include <sys/kernel.h>
  47 #include <sys/kthread.h>
  48 #include <sys/malloc.h>
  49 #include <sys/mbuf.h>
  50 #include <sys/module.h>
  51 #include <sys/rman.h>
  52 #include <sys/proc.h>
  53 #include <sys/smp.h>
  54 #include <sys/socket.h>
  55 #include <sys/sockio.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/taskqueue.h>
  58 #include <sys/eventhandler.h>
  59 #include <sys/types.h>
  60 #include <sys/timetc.h>
  61 #include <sys/cdefs.h>
  62
  63 #include <machine/atomic.h>
  64 #include <machine/bus.h>
  65 #include <machine/in_cksum.h>
  66 #include <machine/pcpu.h>
  67 #include <machine/resource.h>
  68 #include <machine/_inttypes.h>
  69
  70 #include <net/bpf.h>
  71 #include <net/ethernet.h>
  72 #include <net/if.h>
  73 #include <net/if_var.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77
  78 #include <net/if_types.h>
  79 #include <net/if_vlan_var.h>
  80
  81 #include <netinet/in_systm.h>
  82 #include <netinet/in.h>
  83 #include <netinet/if_ether.h>
  84 #include <netinet/ip.h>
  85 #include <netinet/ip6.h>
  86 #include <netinet/tcp.h>
  87 #include <netinet/tcp_lro.h>
  88 #include <netinet/udp.h>
  89
  90 #include <dev/led/led.h>
  91 #include <dev/pci/pcivar.h>
  92 #include <dev/pci/pcireg.h>
  93
  94 extern struct ena_bus_space ebs;
  95
  96 /* Levels */
  97 #define ENA_ALERT       (1 << 0) /* Alerts are providing more error info.     */
  98 #define ENA_WARNING     (1 << 1) /* Driver output is more error sensitive.    */
  99 #define ENA_INFO        (1 << 2) /* Provides additional driver info.          */
 100 #define ENA_DBG         (1 << 3) /* Driver output for debugging.              */
 101 /* Detailed info that will be printed with ENA_INFO or ENA_DEBUG flag.        */
 102 #define ENA_TXPTH       (1 << 4) /* Allows TX path tracing.                   */
 103 #define ENA_RXPTH       (1 << 5) /* Allows RX path tracing.                   */
 104 #define ENA_RSC         (1 << 6) /* Goes with TXPTH or RXPTH, free/alloc res. */
 105 #define ENA_IOQ         (1 << 7) /* Detailed info about IO queues.            */
 106 #define ENA_ADMQ        (1 << 8) /* Detailed info about admin queue.          */
 107 #define ENA_NETMAP      (1 << 9) /* Detailed info about netmap.               */
 108
 109 #define DEFAULT_ALLOC_ALIGNMENT 8
 110
 111 extern int ena_log_level;
 112
 113 #define ena_trace_raw(level, fmt, args...)                      \
 114         do {                                                    \
 115                 if (((level) & ena_log_level) != (level))       \
 116                         break;                                  \
 117                 printf(fmt, ##args);                            \
 118         } while (0)
 119
 120 #define ena_trace(level, fmt, args...)                          \
 121         ena_trace_raw(level, "%s() [TID:%d]: "                  \
 122             fmt, __func__, curthread->td_tid, ##args)
 123
 124
 125 #define ena_trc_dbg(format, arg...)     ena_trace(ENA_DBG, format, ##arg)
 126 #define ena_trc_info(format, arg...)    ena_trace(ENA_INFO, format, ##arg)
 127 #define ena_trc_warn(format, arg...)    ena_trace(ENA_WARNING, format, ##arg)
 128 #define ena_trc_err(format, arg...)     ena_trace(ENA_ALERT, format, ##arg)
 129
 130 #define unlikely(x)     __predict_false(!!(x))
 131 #define likely(x)       __predict_true(!!(x))
 132
 133 #define __iomem
 134 #define ____cacheline_aligned __aligned(CACHE_LINE_SIZE)
 135
 136 #define MAX_ERRNO 4095
 137 #define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO)
 138
 139 #define ENA_ASSERT(cond, format, arg...)                                \
 140         do {                                                            \
 141                 if (unlikely(!(cond))) {                                \
 142                         ena_trc_err(                                    \
 143                                 "Assert failed on %s:%s:%d:" format,    \
 144                                 __FILE__, __func__, __LINE__, ##arg);   \
 145                 }                                                       \
 146         } while (0)
 147
 148 #define ENA_WARN(cond, format, arg...)                                  \
 149         do {                                                            \
 150                 if (unlikely((cond))) {                                 \
 151                         ena_trc_warn(format, ##arg);                    \
 152                 }                                                       \
 153         } while (0)
 154
 155 static inline long IS_ERR(const void *ptr)
 156 {
 157         return IS_ERR_VALUE((unsigned long)ptr);
 158 }
 159
 160 static inline void *ERR_PTR(long error)
 161 {
 162         return (void *)error;
 163 }
 164
 165 static inline long PTR_ERR(const void *ptr)
 166 {
 167         return (long) ptr;
 168 }
 169
 170 #define GENMASK(h, l)   (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
 171 #define GENMASK_ULL(h, l)       (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
 172 #define BIT(x)                  (1UL << (x))
 173
 174 #define ENA_ABORT()             BUG()
 175 #define BUG()                   panic("ENA BUG")
 176
 177 #define SZ_256                  (256)
 178 #define SZ_4K                   (4096)
 179
 180 #define ENA_COM_OK              0
 181 #define ENA_COM_FAULT           EFAULT
 182 #define ENA_COM_INVAL           EINVAL
 183 #define ENA_COM_NO_MEM          ENOMEM
 184 #define ENA_COM_NO_SPACE        ENOSPC
 185 #define ENA_COM_TRY_AGAIN       -1
 186 #define ENA_COM_UNSUPPORTED     EOPNOTSUPP
 187 #define ENA_COM_NO_DEVICE       ENODEV
 188 #define ENA_COM_PERMISSION      EPERM
 189 #define ENA_COM_TIMER_EXPIRED   ETIMEDOUT
 190
 191 #define ENA_MSLEEP(x)           pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0)
 192 #define ENA_USLEEP(x)           pause_sbt("ena", SBT_1US * (x), SBT_1US, 0)
 193 #define ENA_UDELAY(x)           DELAY(x)
 194 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
 195     ((long)cputick2usec(cpu_ticks()) + (timeout_us))
 196 #define ENA_TIME_EXPIRE(timeout)  ((timeout) < cputick2usec(cpu_ticks()))
 197 #define ENA_MIGHT_SLEEP()
 198
 199 #define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y))
 200 #define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y))
 201
 202 #define ENA_MIN32(x,y)  MIN(x, y)
 203 #define ENA_MIN16(x,y)  MIN(x, y)
 204 #define ENA_MIN8(x,y)   MIN(x, y)
 205
 206 #define ENA_MAX32(x,y)  MAX(x, y)
 207 #define ENA_MAX16(x,y)  MAX(x, y)
 208 #define ENA_MAX8(x,y)   MAX(x, y)
 209
 210 /* Spinlock related methods */
 211 #define ena_spinlock_t  struct mtx
 212 #define ENA_SPINLOCK_INIT(spinlock)                             \
 213         mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN)
 214 #define ENA_SPINLOCK_DESTROY(spinlock)                          \
 215         do {                                                    \
 216                 if (mtx_initialized(&(spinlock)))               \
 217                     mtx_destroy(&(spinlock));                   \
 218         } while (0)
 219 #define ENA_SPINLOCK_LOCK(spinlock, flags)                      \
 220         do {                                                    \
 221                 (void)(flags);                                  \
 222                 mtx_lock_spin(&(spinlock));                     \
 223         } while (0)
 224 #define ENA_SPINLOCK_UNLOCK(spinlock, flags)                    \
 225         do {                                                    \
 226                 (void)(flags);                                  \
 227                 mtx_unlock_spin(&(spinlock));                   \
 228         } while (0)
 229
 230
 231 /* Wait queue related methods */
 232 #define ena_wait_event_t struct { struct cv wq; struct mtx mtx; }
 233 #define ENA_WAIT_EVENT_INIT(waitqueue)                                  \
 234         do {                                                            \
 235                 cv_init(&((waitqueue).wq), "cv");                       \
 236                 mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF);      \
 237         } while (0)
 238 #define ENA_WAIT_EVENT_DESTROY(waitqueue)                               \
 239         do {                                                            \
 240                 cv_destroy(&((waitqueue).wq));                          \
 241                 mtx_destroy(&((waitqueue).mtx));                        \
 242         } while (0)
 243 #define ENA_WAIT_EVENT_CLEAR(waitqueue)                                 \
 244         cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description)
 245 #define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us)                      \
 246         do {                                                            \
 247                 mtx_lock(&((waitqueue).mtx));                           \
 248                 cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx),     \
 249                     timeout_us * hz / 1000 / 1000 );                    \
 250                 mtx_unlock(&((waitqueue).mtx));                         \
 251         } while (0)
 252 #define ENA_WAIT_EVENT_SIGNAL(waitqueue)                \
 253         do {                                            \
 254                 mtx_lock(&((waitqueue).mtx));           \
 255                 cv_broadcast(&((waitqueue).wq));        \
 256                 mtx_unlock(&((waitqueue).mtx));         \
 257         } while (0)
 258
 259 #define dma_addr_t      bus_addr_t
 260 #define u8              uint8_t
 261 #define u16             uint16_t
 262 #define u32             uint32_t
 263 #define u64             uint64_t
 264
 265 typedef struct {
 266         bus_addr_t              paddr;
 267         caddr_t                 vaddr;
 268         bus_dma_tag_t           tag;
 269         bus_dmamap_t            map;
 270         bus_dma_segment_t       seg;
 271         int                     nseg;
 272 } ena_mem_handle_t;
 273
 274 struct ena_bus {
 275         bus_space_handle_t      reg_bar_h;
 276         bus_space_tag_t         reg_bar_t;
 277         bus_space_handle_t      mem_bar_h;
 278         bus_space_tag_t         mem_bar_t;
 279 };
 280
 281 typedef uint32_t ena_atomic32_t;
 282
 283 #define ENA_PRIu64 PRIu64
 284
 285 typedef uint64_t ena_time_t;
 286
 287 void    ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg,
 288     int error);
 289 int     ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma,
 290     int mapflags, bus_size_t alignment);
 291
 292 static inline uint32_t
 293 ena_reg_read32(struct ena_bus *bus, bus_size_t offset)
 294 {
 295         uint32_t v = bus_space_read_4(bus->reg_bar_t, bus->reg_bar_h, offset);
 296         rmb();
 297         return v;
 298 }
 299
 300 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)                         \
 301         do {                                                            \
 302                 int count, i;                                           \
 303                 volatile uint64_t *to = (volatile uint64_t *)(dst);     \
 304                 const uint64_t *from = (const uint64_t *)(src);         \
 305                 count = (size) / 8;                                     \
 306                                                                         \
 307                 for (i = 0; i < count; i++, from++, to++)               \
 308                         *to = *from;                                    \
 309         } while (0)
 310
 311 #define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO)
 312 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL)
 313 #define ENA_MEM_FREE(dmadev, ptr, size)                                 \
 314         do {                                                            \
 315                 (void)(size);                                           \
 316                 free(ptr, M_DEVBUF);                                    \
 317         } while (0)
 318 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys,   \
 319     handle, node, dev_node, alignment)                                  \
 320         do {                                                            \
 321                 ((virt) = NULL);                                        \
 322                 (void)(dev_node);                                       \
 323         } while (0)
 324
 325 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle,   \
 326     node, dev_node)                                                     \
 327         ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt,         \
 328             phys, handle, node, dev_node, DEFAULT_ALLOC_ALIGNMENT)
 329
 330 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, dma,   \
 331     alignment)                                                          \
 332         do {                                                            \
 333                 ena_dma_alloc((dmadev), (size), &(dma), 0, alignment);  \
 334                 (virt) = (void *)(dma).vaddr;                           \
 335                 (phys) = (dma).paddr;                                   \
 336         } while (0)
 337
 338 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma)           \
 339         ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt,              \
 340             phys, dma, DEFAULT_ALLOC_ALIGNMENT)
 341
 342 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma)            \
 343         do {                                                            \
 344                 (void)size;                                             \
 345                 bus_dmamap_unload((dma).tag, (dma).map);                \
 346                 bus_dmamem_free((dma).tag, (virt), (dma).map);          \
 347                 bus_dma_tag_destroy((dma).tag);                         \
 348                 (dma).tag = NULL;                                       \
 349                 (virt) = NULL;                                          \
 350         } while (0)
 351
 352 /* Register R/W methods */
 353 #define ENA_REG_WRITE32(bus, value, offset)                             \
 354         do {                                                            \
 355                 wmb();                                                  \
 356                 ENA_REG_WRITE32_RELAXED(bus, value, offset);            \
 357         } while (0)
 358
 359 #define ENA_REG_WRITE32_RELAXED(bus, value, offset)                     \
 360         bus_space_write_4(                                              \
 361                           ((struct ena_bus*)bus)->reg_bar_t,            \
 362                           ((struct ena_bus*)bus)->reg_bar_h,            \
 363                           (bus_size_t)(offset), (value))
 364
 365 #define ENA_REG_READ32(bus, offset)                                     \
 366         ena_reg_read32((struct ena_bus*)(bus), (bus_size_t)(offset))
 367
 368 #define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync(                  \
 369         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE)
 370 #define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync(                \
 371         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD)
 372 #define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync(               \
 373         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD)
 374 #define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle)
 375
 376 #define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0)
 377
 378 #define VLAN_HLEN       sizeof(struct ether_vlan_header)
 379 #define CSUM_OFFLOAD    (CSUM_IP|CSUM_TCP|CSUM_UDP)
 380
 381 #define prefetch(x)     (void)(x)
 382 #define prefetchw(x)    (void)(x)
 383
 384 /* DMA buffers access */
 385 #define dma_unmap_addr(p, name)                 ((p)->dma->name)
 386 #define dma_unmap_addr_set(p, name, v)          (((p)->dma->name) = (v))
 387 #define dma_unmap_len(p, name)                  ((p)->name)
 388 #define dma_unmap_len_set(p, name, v)           (((p)->name) = (v))
 389
 390 #define memcpy_toio memcpy
 391
 392 #define ATOMIC32_INC(I32_PTR)           atomic_add_int(I32_PTR, 1)
 393 #define ATOMIC32_DEC(I32_PTR)           atomic_add_int(I32_PTR, -1)
 394 #define ATOMIC32_READ(I32_PTR)          atomic_load_acq_int(I32_PTR)
 395 #define ATOMIC32_SET(I32_PTR, VAL)      atomic_store_rel_int(I32_PTR, VAL)
 396
 397 #define barrier() __asm__ __volatile__("": : :"memory")
 398 #define dma_rmb() barrier()
 399 #define mmiowb() barrier()
 400
 401 #define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x))
 402 #define READ_ONCE(x)  ({                        \
 403                         __typeof(x) __var;      \
 404                         barrier();              \
 405                         __var = ACCESS_ONCE(x); \
 406                         barrier();              \
 407                         __var;                  \
 408                 })
 409 #define READ_ONCE8(x) READ_ONCE(x)
 410 #define READ_ONCE16(x) READ_ONCE(x)
 411 #define READ_ONCE32(x) READ_ONCE(x)
 412
 413 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
 414 #define lower_32_bits(n) ((uint32_t)(n))
 415
 416 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 417
 418 #define ENA_FFS(x) ffs(x)
 419
 420 void    ena_rss_key_fill(void *key, size_t size);
 421
 422 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)
 423
 424 #include "ena_defs/ena_includes.h"
 425
 426 #endif /* ENA_PLAT_H_ */