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46 * Definitions for enumerations used with Octeon CSRs.
48 * <hr>$Revision: 41586 $<hr>
51 #ifndef __CVMX_CSR_ENUMS_H__
52 #define __CVMX_CSR_ENUMS_H__
55 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
56 CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */
57 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
58 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
63 * Enumeration representing the amount of packet processing
64 * and validation performed by the input hardware.
68 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any
69 processing of the input packet. */
70 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed
71 with pointer starting at the L2
72 (ethernet MAC) header. */
73 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP.
74 Results from non IP packets is
75 undefined. Pointers reference the
76 beginning of the IP header. */
77 } cvmx_pip_port_parse_mode_t;
81 * This enumeration controls how a QoS watcher matches a packet.
83 * @deprecated This enumeration was used with cvmx_pip_config_watcher which has
88 CVMX_PIP_QOS_WATCH_DISABLE = 0ull, /**< QoS watcher is diabled */
89 CVMX_PIP_QOS_WATCH_PROTNH = 1ull, /**< QoS watcher will match based on the IP protocol */
90 CVMX_PIP_QOS_WATCH_TCP = 2ull, /**< QoS watcher will match TCP packets to a specific destination port */
91 CVMX_PIP_QOS_WATCH_UDP = 3ull /**< QoS watcher will match UDP packets to a specific destination port */
92 } cvmx_pip_qos_watch_types;
95 * This enumeration is used in PIP tag config to control how
96 * POW tags are generated by the hardware.
100 CVMX_PIP_TAG_MODE_TUPLE = 0ull, /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */
101 CVMX_PIP_TAG_MODE_MASK = 1ull, /**< Always use mask tag algorithm */
102 CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, /**< If packet is IP, use tuple else use mask */
103 CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull /**< tuple XOR mask */
104 } cvmx_pip_tag_mode_t;
107 * Tag type definitions
111 CVMX_POW_TAG_TYPE_ORDERED = 0L, /**< Tag ordering is maintained */
112 CVMX_POW_TAG_TYPE_ATOMIC = 1L, /**< Tag ordering is maintained, and at most one PP has the tag */
113 CVMX_POW_TAG_TYPE_NULL = 2L, /**< The work queue entry from the order
114 - NEVER tag switch from NULL to NULL */
115 CVMX_POW_TAG_TYPE_NULL_NULL = 3L /**< A tag switch to NULL, and there is no space reserved in POW
116 - NEVER tag switch to NULL_NULL
117 - NEVER tag switch from NULL_NULL
118 - NULL_NULL is entered at the beginning of time and on a deschedule.
119 - NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */
120 } cvmx_pow_tag_type_t;
124 * LCR bits 0 and 1 control the number of bits per character. See the following table for encodings:
126 * - 00 = 5 bits (bits 0-4 sent)
127 * - 01 = 6 bits (bits 0-5 sent)
128 * - 10 = 7 bits (bits 0-6 sent)
129 * - 11 = 8 bits (all bits sent)
141 * Interrupt Priority Interrupt Interrupt Interrupt
142 * ID Level Type Source Reset By
143 * ---------------------------------------------------------------------------------------------------------------------------------
146 * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register
149 * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register
150 * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below
151 * enabled) the trigger level (FIFOs enabled)
153 * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register
154 * Timeout during the last 4 character times and there
155 * Indication is at least 1 character in it during this
158 * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register
159 * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into
160 * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX
161 * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE
164 * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register
165 * Changed or Ring Indicator (RI) or Data Center
166 * Detect (DCD) changed
168 * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register
169 * Indication Control Register while the BUSY bit of the
170 * UART Status Register was set
174 CVMX_UART_IID_NONE = 1,
175 CVMX_UART_IID_RX_ERROR = 6,
176 CVMX_UART_IID_RX_DATA = 4,
177 CVMX_UART_IID_RX_TIMEOUT = 12,
178 CVMX_UART_IID_TX_EMPTY = 2,
179 CVMX_UART_IID_MODEM = 0,
180 CVMX_UART_IID_BUSY = 7
183 #endif /* __CVMX_CSR_ENUMS_H__ */