1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn50xx.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN50XX</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
59 * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
60 * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
61 * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
62 * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
63 * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
64 * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
65 * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
66 * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
67 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
68 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
69 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
70 * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
71 * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
72 * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
73 * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
74 * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
75 * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
76 * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
77 * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
78 * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
79 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
80 * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
81 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
82 * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
83 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
84 * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
85 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
86 * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
87 * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
88 * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
89 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
90 * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
91 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
92 * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
93 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
94 * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
95 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
96 * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
97 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
98 * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
99 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
100 * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
101 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
102 * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
103 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
104 * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
105 * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
106 * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
107 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
108 * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
109 * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
110 * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
111 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
112 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
113 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
114 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
115 * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
119 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
120 #include <asm/octeon/cvmx.h>
121 #include <asm/octeon/cvmx-error.h>
122 #include <asm/octeon/cvmx-error-custom.h>
123 #include <asm/octeon/cvmx-csr-typedefs.h>
126 #include "cvmx-error.h"
127 #include "cvmx-error-custom.h"
130 int cvmx_error_initialize_cn50xx(void);
132 int cvmx_error_initialize_cn50xx(void)
134 cvmx_error_info_t info;
137 /* CVMX_CIU_INTX_SUM0(0) */
138 info.reg_type = CVMX_ERROR_REGISTER_IO64;
139 info.status_addr = CVMX_CIU_INTX_SUM0(0);
140 info.status_mask = 0;
141 info.enable_addr = 0;
142 info.enable_mask = 0;
144 info.group = CVMX_ERROR_GROUP_INTERNAL;
145 info.group_index = 0;
146 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
147 info.parent.status_addr = 0;
148 info.parent.status_mask = 0;
149 info.func = __cvmx_error_decode;
151 fail |= cvmx_error_add(&info);
153 /* CVMX_PCMX_INT_SUM(0) */
154 info.reg_type = CVMX_ERROR_REGISTER_IO64;
155 info.status_addr = CVMX_PCMX_INT_SUM(0);
156 info.status_mask = 1ull<<0 /* fsyncmissed */;
157 info.enable_addr = CVMX_PCMX_INT_ENA(0);
158 info.enable_mask = 1ull<<0 /* fsyncmissed */;
160 info.group = CVMX_ERROR_GROUP_INTERNAL;
161 info.group_index = 0;
162 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
163 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
164 info.parent.status_mask = 1ull<<57 /* pcm */;
165 info.func = __cvmx_error_display;
166 info.user_info = (long)
167 "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
168 fail |= cvmx_error_add(&info);
170 info.reg_type = CVMX_ERROR_REGISTER_IO64;
171 info.status_addr = CVMX_PCMX_INT_SUM(0);
172 info.status_mask = 1ull<<1 /* fsyncextra */;
173 info.enable_addr = CVMX_PCMX_INT_ENA(0);
174 info.enable_mask = 1ull<<1 /* fsyncextra */;
176 info.group = CVMX_ERROR_GROUP_INTERNAL;
177 info.group_index = 0;
178 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
179 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
180 info.parent.status_mask = 1ull<<57 /* pcm */;
181 info.func = __cvmx_error_display;
182 info.user_info = (long)
183 "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
184 fail |= cvmx_error_add(&info);
186 info.reg_type = CVMX_ERROR_REGISTER_IO64;
187 info.status_addr = CVMX_PCMX_INT_SUM(0);
188 info.status_mask = 1ull<<6 /* txempty */;
189 info.enable_addr = CVMX_PCMX_INT_ENA(0);
190 info.enable_mask = 1ull<<6 /* txempty */;
192 info.group = CVMX_ERROR_GROUP_INTERNAL;
193 info.group_index = 0;
194 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
195 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
196 info.parent.status_mask = 1ull<<57 /* pcm */;
197 info.func = __cvmx_error_display;
198 info.user_info = (long)
199 "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
200 fail |= cvmx_error_add(&info);
202 info.reg_type = CVMX_ERROR_REGISTER_IO64;
203 info.status_addr = CVMX_PCMX_INT_SUM(0);
204 info.status_mask = 1ull<<7 /* rxovf */;
205 info.enable_addr = CVMX_PCMX_INT_ENA(0);
206 info.enable_mask = 1ull<<7 /* rxovf */;
208 info.group = CVMX_ERROR_GROUP_INTERNAL;
209 info.group_index = 0;
210 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
211 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
212 info.parent.status_mask = 1ull<<57 /* pcm */;
213 info.func = __cvmx_error_display;
214 info.user_info = (long)
215 "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
216 fail |= cvmx_error_add(&info);
218 /* CVMX_PCMX_INT_SUM(1) */
219 info.reg_type = CVMX_ERROR_REGISTER_IO64;
220 info.status_addr = CVMX_PCMX_INT_SUM(1);
221 info.status_mask = 1ull<<0 /* fsyncmissed */;
222 info.enable_addr = CVMX_PCMX_INT_ENA(1);
223 info.enable_mask = 1ull<<0 /* fsyncmissed */;
225 info.group = CVMX_ERROR_GROUP_INTERNAL;
226 info.group_index = 0;
227 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
228 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
229 info.parent.status_mask = 1ull<<57 /* pcm */;
230 info.func = __cvmx_error_display;
231 info.user_info = (long)
232 "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
233 fail |= cvmx_error_add(&info);
235 info.reg_type = CVMX_ERROR_REGISTER_IO64;
236 info.status_addr = CVMX_PCMX_INT_SUM(1);
237 info.status_mask = 1ull<<1 /* fsyncextra */;
238 info.enable_addr = CVMX_PCMX_INT_ENA(1);
239 info.enable_mask = 1ull<<1 /* fsyncextra */;
241 info.group = CVMX_ERROR_GROUP_INTERNAL;
242 info.group_index = 0;
243 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
244 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
245 info.parent.status_mask = 1ull<<57 /* pcm */;
246 info.func = __cvmx_error_display;
247 info.user_info = (long)
248 "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
249 fail |= cvmx_error_add(&info);
251 info.reg_type = CVMX_ERROR_REGISTER_IO64;
252 info.status_addr = CVMX_PCMX_INT_SUM(1);
253 info.status_mask = 1ull<<6 /* txempty */;
254 info.enable_addr = CVMX_PCMX_INT_ENA(1);
255 info.enable_mask = 1ull<<6 /* txempty */;
257 info.group = CVMX_ERROR_GROUP_INTERNAL;
258 info.group_index = 0;
259 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
260 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
261 info.parent.status_mask = 1ull<<57 /* pcm */;
262 info.func = __cvmx_error_display;
263 info.user_info = (long)
264 "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
265 fail |= cvmx_error_add(&info);
267 info.reg_type = CVMX_ERROR_REGISTER_IO64;
268 info.status_addr = CVMX_PCMX_INT_SUM(1);
269 info.status_mask = 1ull<<7 /* rxovf */;
270 info.enable_addr = CVMX_PCMX_INT_ENA(1);
271 info.enable_mask = 1ull<<7 /* rxovf */;
273 info.group = CVMX_ERROR_GROUP_INTERNAL;
274 info.group_index = 0;
275 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
276 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
277 info.parent.status_mask = 1ull<<57 /* pcm */;
278 info.func = __cvmx_error_display;
279 info.user_info = (long)
280 "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
281 fail |= cvmx_error_add(&info);
283 /* CVMX_PCMX_INT_SUM(2) */
284 info.reg_type = CVMX_ERROR_REGISTER_IO64;
285 info.status_addr = CVMX_PCMX_INT_SUM(2);
286 info.status_mask = 1ull<<0 /* fsyncmissed */;
287 info.enable_addr = CVMX_PCMX_INT_ENA(2);
288 info.enable_mask = 1ull<<0 /* fsyncmissed */;
290 info.group = CVMX_ERROR_GROUP_INTERNAL;
291 info.group_index = 0;
292 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
293 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
294 info.parent.status_mask = 1ull<<57 /* pcm */;
295 info.func = __cvmx_error_display;
296 info.user_info = (long)
297 "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
298 fail |= cvmx_error_add(&info);
300 info.reg_type = CVMX_ERROR_REGISTER_IO64;
301 info.status_addr = CVMX_PCMX_INT_SUM(2);
302 info.status_mask = 1ull<<1 /* fsyncextra */;
303 info.enable_addr = CVMX_PCMX_INT_ENA(2);
304 info.enable_mask = 1ull<<1 /* fsyncextra */;
306 info.group = CVMX_ERROR_GROUP_INTERNAL;
307 info.group_index = 0;
308 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
309 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
310 info.parent.status_mask = 1ull<<57 /* pcm */;
311 info.func = __cvmx_error_display;
312 info.user_info = (long)
313 "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
314 fail |= cvmx_error_add(&info);
316 info.reg_type = CVMX_ERROR_REGISTER_IO64;
317 info.status_addr = CVMX_PCMX_INT_SUM(2);
318 info.status_mask = 1ull<<6 /* txempty */;
319 info.enable_addr = CVMX_PCMX_INT_ENA(2);
320 info.enable_mask = 1ull<<6 /* txempty */;
322 info.group = CVMX_ERROR_GROUP_INTERNAL;
323 info.group_index = 0;
324 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
325 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
326 info.parent.status_mask = 1ull<<57 /* pcm */;
327 info.func = __cvmx_error_display;
328 info.user_info = (long)
329 "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
330 fail |= cvmx_error_add(&info);
332 info.reg_type = CVMX_ERROR_REGISTER_IO64;
333 info.status_addr = CVMX_PCMX_INT_SUM(2);
334 info.status_mask = 1ull<<7 /* rxovf */;
335 info.enable_addr = CVMX_PCMX_INT_ENA(2);
336 info.enable_mask = 1ull<<7 /* rxovf */;
338 info.group = CVMX_ERROR_GROUP_INTERNAL;
339 info.group_index = 0;
340 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
341 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
342 info.parent.status_mask = 1ull<<57 /* pcm */;
343 info.func = __cvmx_error_display;
344 info.user_info = (long)
345 "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
346 fail |= cvmx_error_add(&info);
348 /* CVMX_PCMX_INT_SUM(3) */
349 info.reg_type = CVMX_ERROR_REGISTER_IO64;
350 info.status_addr = CVMX_PCMX_INT_SUM(3);
351 info.status_mask = 1ull<<0 /* fsyncmissed */;
352 info.enable_addr = CVMX_PCMX_INT_ENA(3);
353 info.enable_mask = 1ull<<0 /* fsyncmissed */;
355 info.group = CVMX_ERROR_GROUP_INTERNAL;
356 info.group_index = 0;
357 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
358 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
359 info.parent.status_mask = 1ull<<57 /* pcm */;
360 info.func = __cvmx_error_display;
361 info.user_info = (long)
362 "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
363 fail |= cvmx_error_add(&info);
365 info.reg_type = CVMX_ERROR_REGISTER_IO64;
366 info.status_addr = CVMX_PCMX_INT_SUM(3);
367 info.status_mask = 1ull<<1 /* fsyncextra */;
368 info.enable_addr = CVMX_PCMX_INT_ENA(3);
369 info.enable_mask = 1ull<<1 /* fsyncextra */;
371 info.group = CVMX_ERROR_GROUP_INTERNAL;
372 info.group_index = 0;
373 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
374 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
375 info.parent.status_mask = 1ull<<57 /* pcm */;
376 info.func = __cvmx_error_display;
377 info.user_info = (long)
378 "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
379 fail |= cvmx_error_add(&info);
381 info.reg_type = CVMX_ERROR_REGISTER_IO64;
382 info.status_addr = CVMX_PCMX_INT_SUM(3);
383 info.status_mask = 1ull<<6 /* txempty */;
384 info.enable_addr = CVMX_PCMX_INT_ENA(3);
385 info.enable_mask = 1ull<<6 /* txempty */;
387 info.group = CVMX_ERROR_GROUP_INTERNAL;
388 info.group_index = 0;
389 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
390 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
391 info.parent.status_mask = 1ull<<57 /* pcm */;
392 info.func = __cvmx_error_display;
393 info.user_info = (long)
394 "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
395 fail |= cvmx_error_add(&info);
397 info.reg_type = CVMX_ERROR_REGISTER_IO64;
398 info.status_addr = CVMX_PCMX_INT_SUM(3);
399 info.status_mask = 1ull<<7 /* rxovf */;
400 info.enable_addr = CVMX_PCMX_INT_ENA(3);
401 info.enable_mask = 1ull<<7 /* rxovf */;
403 info.group = CVMX_ERROR_GROUP_INTERNAL;
404 info.group_index = 0;
405 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
406 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
407 info.parent.status_mask = 1ull<<57 /* pcm */;
408 info.func = __cvmx_error_display;
409 info.user_info = (long)
410 "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
411 fail |= cvmx_error_add(&info);
413 /* CVMX_CIU_INT_SUM1 */
414 /* CVMX_NPI_RSL_INT_BLOCKS */
415 info.reg_type = CVMX_ERROR_REGISTER_IO64;
416 info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
417 info.status_mask = 0;
418 info.enable_addr = 0;
419 info.enable_mask = 0;
421 info.group = CVMX_ERROR_GROUP_INTERNAL;
422 info.group_index = 0;
423 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
424 info.parent.status_addr = 0;
425 info.parent.status_mask = 0;
426 info.func = __cvmx_error_decode;
428 fail |= cvmx_error_add(&info);
431 info.reg_type = CVMX_ERROR_REGISTER_IO64;
432 info.status_addr = CVMX_L2D_ERR;
433 info.status_mask = 1ull<<3 /* sec_err */;
434 info.enable_addr = CVMX_L2D_ERR;
435 info.enable_mask = 1ull<<1 /* sec_intena */;
436 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
437 info.group = CVMX_ERROR_GROUP_INTERNAL;
438 info.group_index = 0;
439 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
440 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
441 info.parent.status_mask = 1ull<<16 /* l2c */;
442 info.func = __cvmx_error_handle_l2d_err_sec_err;
443 info.user_info = (long)
444 "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
445 fail |= cvmx_error_add(&info);
447 info.reg_type = CVMX_ERROR_REGISTER_IO64;
448 info.status_addr = CVMX_L2D_ERR;
449 info.status_mask = 1ull<<4 /* ded_err */;
450 info.enable_addr = CVMX_L2D_ERR;
451 info.enable_mask = 1ull<<2 /* ded_intena */;
453 info.group = CVMX_ERROR_GROUP_INTERNAL;
454 info.group_index = 0;
455 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
456 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
457 info.parent.status_mask = 1ull<<16 /* l2c */;
458 info.func = __cvmx_error_handle_l2d_err_ded_err;
459 info.user_info = (long)
460 "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
461 fail |= cvmx_error_add(&info);
464 info.reg_type = CVMX_ERROR_REGISTER_IO64;
465 info.status_addr = CVMX_L2T_ERR;
466 info.status_mask = 1ull<<3 /* sec_err */;
467 info.enable_addr = CVMX_L2T_ERR;
468 info.enable_mask = 1ull<<1 /* sec_intena */;
469 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
470 info.group = CVMX_ERROR_GROUP_INTERNAL;
471 info.group_index = 0;
472 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
473 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
474 info.parent.status_mask = 1ull<<16 /* l2c */;
475 info.func = __cvmx_error_handle_l2t_err_sec_err;
476 info.user_info = (long)
477 "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
478 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
479 " given index) are checked for single bit errors(SBEs).\n"
480 " This bit is set if ANY of the 8 sets contains an SBE.\n"
481 " SBEs are auto corrected in HW and generate an\n"
482 " interrupt(if enabled).\n";
483 fail |= cvmx_error_add(&info);
485 info.reg_type = CVMX_ERROR_REGISTER_IO64;
486 info.status_addr = CVMX_L2T_ERR;
487 info.status_mask = 1ull<<4 /* ded_err */;
488 info.enable_addr = CVMX_L2T_ERR;
489 info.enable_mask = 1ull<<2 /* ded_intena */;
491 info.group = CVMX_ERROR_GROUP_INTERNAL;
492 info.group_index = 0;
493 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
494 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
495 info.parent.status_mask = 1ull<<16 /* l2c */;
496 info.func = __cvmx_error_handle_l2t_err_ded_err;
497 info.user_info = (long)
498 "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
499 " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
500 " given index) are checked for double bit errors(DBEs).\n"
501 " This bit is set if ANY of the 8 sets contains a DBE.\n"
502 " DBEs also generated an interrupt(if enabled).\n";
503 fail |= cvmx_error_add(&info);
505 info.reg_type = CVMX_ERROR_REGISTER_IO64;
506 info.status_addr = CVMX_L2T_ERR;
507 info.status_mask = 1ull<<24 /* lckerr */;
508 info.enable_addr = CVMX_L2T_ERR;
509 info.enable_mask = 1ull<<25 /* lck_intena */;
511 info.group = CVMX_ERROR_GROUP_INTERNAL;
512 info.group_index = 0;
513 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
514 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
515 info.parent.status_mask = 1ull<<16 /* l2c */;
516 info.func = __cvmx_error_handle_l2t_err_lckerr;
517 info.user_info = (long)
518 "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
519 " the INDEX (which is ignored by HW - but reported to SW).\n"
520 " The LDD(L1 load-miss) for the LOCK operation is completed\n"
521 " successfully, however the address is NOT locked.\n"
522 " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
523 " into account. For example, if diagnostic PPx has\n"
524 " UMSKx defined to only use SETs [1:0], and SET1 had\n"
525 " been previously LOCKED, then an attempt to LOCK the\n"
526 " last available SET0 would result in a LCKERR. (This\n"
527 " is to ensure that at least 1 SET at each INDEX is\n"
528 " not LOCKED for general use by other PPs).\n";
529 fail |= cvmx_error_add(&info);
531 info.reg_type = CVMX_ERROR_REGISTER_IO64;
532 info.status_addr = CVMX_L2T_ERR;
533 info.status_mask = 1ull<<26 /* lckerr2 */;
534 info.enable_addr = CVMX_L2T_ERR;
535 info.enable_mask = 1ull<<27 /* lck_intena2 */;
537 info.group = CVMX_ERROR_GROUP_INTERNAL;
538 info.group_index = 0;
539 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
540 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
541 info.parent.status_mask = 1ull<<16 /* l2c */;
542 info.func = __cvmx_error_handle_l2t_err_lckerr2;
543 info.user_info = (long)
544 "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
545 " could not find an available/unlocked set (for\n"
547 " Most likely, this is a result of SW mixing SET\n"
548 " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
549 " another PP to LOCKDOWN all SETs available to PP#n,\n"
550 " then a Rd/Wr Miss from PP#n will be unable\n"
551 " to determine a 'valid' replacement set (since LOCKED\n"
552 " addresses should NEVER be replaced).\n"
553 " If such an event occurs, the HW will select the smallest\n"
554 " available SET(specified by UMSK'x)' as the replacement\n"
555 " set, and the address is unlocked.\n";
556 fail |= cvmx_error_add(&info);
558 /* CVMX_NPI_INT_SUM */
559 info.reg_type = CVMX_ERROR_REGISTER_IO64;
560 info.status_addr = CVMX_NPI_INT_SUM;
561 info.status_mask = 1ull<<0 /* rml_rto */;
562 info.enable_addr = CVMX_NPI_INT_ENB;
563 info.enable_mask = 1ull<<0 /* rml_rto */;
565 info.group = CVMX_ERROR_GROUP_PCI;
566 info.group_index = 0;
567 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
568 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
569 info.parent.status_mask = 1ull<<3 /* npi */;
570 info.func = __cvmx_error_display;
571 info.user_info = (long)
572 "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
573 " back from a RSL after sending a read command to\n"
575 fail |= cvmx_error_add(&info);
577 info.reg_type = CVMX_ERROR_REGISTER_IO64;
578 info.status_addr = CVMX_NPI_INT_SUM;
579 info.status_mask = 1ull<<1 /* rml_wto */;
580 info.enable_addr = CVMX_NPI_INT_ENB;
581 info.enable_mask = 1ull<<1 /* rml_wto */;
583 info.group = CVMX_ERROR_GROUP_PCI;
584 info.group_index = 0;
585 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
586 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
587 info.parent.status_mask = 1ull<<3 /* npi */;
588 info.func = __cvmx_error_display;
589 info.user_info = (long)
590 "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
591 " back from a RSL after sending a write command to\n"
593 fail |= cvmx_error_add(&info);
595 info.reg_type = CVMX_ERROR_REGISTER_IO64;
596 info.status_addr = CVMX_NPI_INT_SUM;
597 info.status_mask = 1ull<<3 /* po0_2sml */;
598 info.enable_addr = CVMX_NPI_INT_ENB;
599 info.enable_mask = 1ull<<3 /* po0_2sml */;
601 info.group = CVMX_ERROR_GROUP_PCI;
602 info.group_index = 0;
603 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
604 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
605 info.parent.status_mask = 1ull<<3 /* npi */;
606 info.func = __cvmx_error_display;
607 info.user_info = (long)
608 "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
609 " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
610 fail |= cvmx_error_add(&info);
612 info.reg_type = CVMX_ERROR_REGISTER_IO64;
613 info.status_addr = CVMX_NPI_INT_SUM;
614 info.status_mask = 1ull<<4 /* po1_2sml */;
615 info.enable_addr = CVMX_NPI_INT_ENB;
616 info.enable_mask = 1ull<<4 /* po1_2sml */;
618 info.group = CVMX_ERROR_GROUP_PCI;
619 info.group_index = 0;
620 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
621 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
622 info.parent.status_mask = 1ull<<3 /* npi */;
623 info.func = __cvmx_error_display;
624 info.user_info = (long)
625 "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
626 " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
627 fail |= cvmx_error_add(&info);
629 info.reg_type = CVMX_ERROR_REGISTER_IO64;
630 info.status_addr = CVMX_NPI_INT_SUM;
631 info.status_mask = 1ull<<7 /* i0_rtout */;
632 info.enable_addr = CVMX_NPI_INT_ENB;
633 info.enable_mask = 1ull<<7 /* i0_rtout */;
635 info.group = CVMX_ERROR_GROUP_PCI;
636 info.group_index = 0;
637 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
638 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
639 info.parent.status_mask = 1ull<<3 /* npi */;
640 info.func = __cvmx_error_display;
641 info.user_info = (long)
642 "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
643 " read instructions.\n";
644 fail |= cvmx_error_add(&info);
646 info.reg_type = CVMX_ERROR_REGISTER_IO64;
647 info.status_addr = CVMX_NPI_INT_SUM;
648 info.status_mask = 1ull<<8 /* i1_rtout */;
649 info.enable_addr = CVMX_NPI_INT_ENB;
650 info.enable_mask = 1ull<<8 /* i1_rtout */;
652 info.group = CVMX_ERROR_GROUP_PCI;
653 info.group_index = 0;
654 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
655 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
656 info.parent.status_mask = 1ull<<3 /* npi */;
657 info.func = __cvmx_error_display;
658 info.user_info = (long)
659 "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
660 " read instructions.\n";
661 fail |= cvmx_error_add(&info);
663 info.reg_type = CVMX_ERROR_REGISTER_IO64;
664 info.status_addr = CVMX_NPI_INT_SUM;
665 info.status_mask = 1ull<<11 /* i0_overf */;
666 info.enable_addr = CVMX_NPI_INT_ENB;
667 info.enable_mask = 1ull<<11 /* i0_overf */;
669 info.group = CVMX_ERROR_GROUP_PCI;
670 info.group_index = 0;
671 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
672 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
673 info.parent.status_mask = 1ull<<3 /* npi */;
674 info.func = __cvmx_error_display;
675 info.user_info = (long)
676 "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
677 " doorbell count was set.\n";
678 fail |= cvmx_error_add(&info);
680 info.reg_type = CVMX_ERROR_REGISTER_IO64;
681 info.status_addr = CVMX_NPI_INT_SUM;
682 info.status_mask = 1ull<<12 /* i1_overf */;
683 info.enable_addr = CVMX_NPI_INT_ENB;
684 info.enable_mask = 1ull<<12 /* i1_overf */;
686 info.group = CVMX_ERROR_GROUP_PCI;
687 info.group_index = 0;
688 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
689 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
690 info.parent.status_mask = 1ull<<3 /* npi */;
691 info.func = __cvmx_error_display;
692 info.user_info = (long)
693 "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
694 " doorbell count was set.\n";
695 fail |= cvmx_error_add(&info);
697 info.reg_type = CVMX_ERROR_REGISTER_IO64;
698 info.status_addr = CVMX_NPI_INT_SUM;
699 info.status_mask = 1ull<<15 /* p0_rtout */;
700 info.enable_addr = CVMX_NPI_INT_ENB;
701 info.enable_mask = 1ull<<15 /* p0_rtout */;
703 info.group = CVMX_ERROR_GROUP_PCI;
704 info.group_index = 0;
705 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
706 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
707 info.parent.status_mask = 1ull<<3 /* npi */;
708 info.func = __cvmx_error_display;
709 info.user_info = (long)
710 "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
711 " read packet data.\n";
712 fail |= cvmx_error_add(&info);
714 info.reg_type = CVMX_ERROR_REGISTER_IO64;
715 info.status_addr = CVMX_NPI_INT_SUM;
716 info.status_mask = 1ull<<16 /* p1_rtout */;
717 info.enable_addr = CVMX_NPI_INT_ENB;
718 info.enable_mask = 1ull<<16 /* p1_rtout */;
720 info.group = CVMX_ERROR_GROUP_PCI;
721 info.group_index = 0;
722 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
723 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
724 info.parent.status_mask = 1ull<<3 /* npi */;
725 info.func = __cvmx_error_display;
726 info.user_info = (long)
727 "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
728 " read packet data.\n";
729 fail |= cvmx_error_add(&info);
731 info.reg_type = CVMX_ERROR_REGISTER_IO64;
732 info.status_addr = CVMX_NPI_INT_SUM;
733 info.status_mask = 1ull<<19 /* p0_perr */;
734 info.enable_addr = CVMX_NPI_INT_ENB;
735 info.enable_mask = 1ull<<19 /* p0_perr */;
737 info.group = CVMX_ERROR_GROUP_PCI;
738 info.group_index = 0;
739 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
740 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
741 info.parent.status_mask = 1ull<<3 /* npi */;
742 info.func = __cvmx_error_display;
743 info.user_info = (long)
744 "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
745 " data this bit may be set.\n";
746 fail |= cvmx_error_add(&info);
748 info.reg_type = CVMX_ERROR_REGISTER_IO64;
749 info.status_addr = CVMX_NPI_INT_SUM;
750 info.status_mask = 1ull<<20 /* p1_perr */;
751 info.enable_addr = CVMX_NPI_INT_ENB;
752 info.enable_mask = 1ull<<20 /* p1_perr */;
754 info.group = CVMX_ERROR_GROUP_PCI;
755 info.group_index = 0;
756 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
757 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
758 info.parent.status_mask = 1ull<<3 /* npi */;
759 info.func = __cvmx_error_display;
760 info.user_info = (long)
761 "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
762 " data this bit may be set.\n";
763 fail |= cvmx_error_add(&info);
765 info.reg_type = CVMX_ERROR_REGISTER_IO64;
766 info.status_addr = CVMX_NPI_INT_SUM;
767 info.status_mask = 1ull<<23 /* g0_rtout */;
768 info.enable_addr = CVMX_NPI_INT_ENB;
769 info.enable_mask = 1ull<<23 /* g0_rtout */;
771 info.group = CVMX_ERROR_GROUP_PCI;
772 info.group_index = 0;
773 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
774 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
775 info.parent.status_mask = 1ull<<3 /* npi */;
776 info.func = __cvmx_error_display;
777 info.user_info = (long)
778 "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
779 " read a gather list.\n";
780 fail |= cvmx_error_add(&info);
782 info.reg_type = CVMX_ERROR_REGISTER_IO64;
783 info.status_addr = CVMX_NPI_INT_SUM;
784 info.status_mask = 1ull<<24 /* g1_rtout */;
785 info.enable_addr = CVMX_NPI_INT_ENB;
786 info.enable_mask = 1ull<<24 /* g1_rtout */;
788 info.group = CVMX_ERROR_GROUP_PCI;
789 info.group_index = 0;
790 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
791 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
792 info.parent.status_mask = 1ull<<3 /* npi */;
793 info.func = __cvmx_error_display;
794 info.user_info = (long)
795 "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
796 " read a gather list.\n";
797 fail |= cvmx_error_add(&info);
799 info.reg_type = CVMX_ERROR_REGISTER_IO64;
800 info.status_addr = CVMX_NPI_INT_SUM;
801 info.status_mask = 1ull<<27 /* p0_pperr */;
802 info.enable_addr = CVMX_NPI_INT_ENB;
803 info.enable_mask = 1ull<<27 /* p0_pperr */;
805 info.group = CVMX_ERROR_GROUP_PCI;
806 info.group_index = 0;
807 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
808 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
809 info.parent.status_mask = 1ull<<3 /* npi */;
810 info.func = __cvmx_error_display;
811 info.user_info = (long)
812 "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
813 " pointer-pair, this bit may be set.\n";
814 fail |= cvmx_error_add(&info);
816 info.reg_type = CVMX_ERROR_REGISTER_IO64;
817 info.status_addr = CVMX_NPI_INT_SUM;
818 info.status_mask = 1ull<<28 /* p1_pperr */;
819 info.enable_addr = CVMX_NPI_INT_ENB;
820 info.enable_mask = 1ull<<28 /* p1_pperr */;
822 info.group = CVMX_ERROR_GROUP_PCI;
823 info.group_index = 0;
824 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
825 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
826 info.parent.status_mask = 1ull<<3 /* npi */;
827 info.func = __cvmx_error_display;
828 info.user_info = (long)
829 "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
830 " pointer-pair, this bit may be set.\n";
831 fail |= cvmx_error_add(&info);
833 info.reg_type = CVMX_ERROR_REGISTER_IO64;
834 info.status_addr = CVMX_NPI_INT_SUM;
835 info.status_mask = 1ull<<31 /* p0_ptout */;
836 info.enable_addr = CVMX_NPI_INT_ENB;
837 info.enable_mask = 1ull<<31 /* p0_ptout */;
839 info.group = CVMX_ERROR_GROUP_PCI;
840 info.group_index = 0;
841 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
842 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
843 info.parent.status_mask = 1ull<<3 /* npi */;
844 info.func = __cvmx_error_display;
845 info.user_info = (long)
846 "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
848 fail |= cvmx_error_add(&info);
850 info.reg_type = CVMX_ERROR_REGISTER_IO64;
851 info.status_addr = CVMX_NPI_INT_SUM;
852 info.status_mask = 1ull<<32 /* p1_ptout */;
853 info.enable_addr = CVMX_NPI_INT_ENB;
854 info.enable_mask = 1ull<<32 /* p1_ptout */;
856 info.group = CVMX_ERROR_GROUP_PCI;
857 info.group_index = 0;
858 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
859 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
860 info.parent.status_mask = 1ull<<3 /* npi */;
861 info.func = __cvmx_error_display;
862 info.user_info = (long)
863 "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
865 fail |= cvmx_error_add(&info);
867 info.reg_type = CVMX_ERROR_REGISTER_IO64;
868 info.status_addr = CVMX_NPI_INT_SUM;
869 info.status_mask = 1ull<<35 /* i0_pperr */;
870 info.enable_addr = CVMX_NPI_INT_ENB;
871 info.enable_mask = 1ull<<35 /* i0_pperr */;
873 info.group = CVMX_ERROR_GROUP_PCI;
874 info.group_index = 0;
875 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
876 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
877 info.parent.status_mask = 1ull<<3 /* npi */;
878 info.func = __cvmx_error_display;
879 info.user_info = (long)
880 "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
881 " this bit may be set.\n";
882 fail |= cvmx_error_add(&info);
884 info.reg_type = CVMX_ERROR_REGISTER_IO64;
885 info.status_addr = CVMX_NPI_INT_SUM;
886 info.status_mask = 1ull<<36 /* i1_pperr */;
887 info.enable_addr = CVMX_NPI_INT_ENB;
888 info.enable_mask = 1ull<<36 /* i1_pperr */;
890 info.group = CVMX_ERROR_GROUP_PCI;
891 info.group_index = 0;
892 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
893 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
894 info.parent.status_mask = 1ull<<3 /* npi */;
895 info.func = __cvmx_error_display;
896 info.user_info = (long)
897 "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
898 " this bit may be set.\n";
899 fail |= cvmx_error_add(&info);
901 info.reg_type = CVMX_ERROR_REGISTER_IO64;
902 info.status_addr = CVMX_NPI_INT_SUM;
903 info.status_mask = 1ull<<39 /* win_rto */;
904 info.enable_addr = CVMX_NPI_INT_ENB;
905 info.enable_mask = 1ull<<39 /* win_rto */;
907 info.group = CVMX_ERROR_GROUP_PCI;
908 info.group_index = 0;
909 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
910 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
911 info.parent.status_mask = 1ull<<3 /* npi */;
912 info.func = __cvmx_error_display;
913 info.user_info = (long)
914 "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
915 fail |= cvmx_error_add(&info);
917 info.reg_type = CVMX_ERROR_REGISTER_IO64;
918 info.status_addr = CVMX_NPI_INT_SUM;
919 info.status_mask = 1ull<<40 /* p_dperr */;
920 info.enable_addr = CVMX_NPI_INT_ENB;
921 info.enable_mask = 1ull<<40 /* p_dperr */;
923 info.group = CVMX_ERROR_GROUP_PCI;
924 info.group_index = 0;
925 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
926 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
927 info.parent.status_mask = 1ull<<3 /* npi */;
928 info.func = __cvmx_error_display;
929 info.user_info = (long)
930 "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
931 " from the PCI this bit may be set.\n";
932 fail |= cvmx_error_add(&info);
934 info.reg_type = CVMX_ERROR_REGISTER_IO64;
935 info.status_addr = CVMX_NPI_INT_SUM;
936 info.status_mask = 1ull<<41 /* iobdma */;
937 info.enable_addr = CVMX_NPI_INT_ENB;
938 info.enable_mask = 1ull<<41 /* iobdma */;
940 info.group = CVMX_ERROR_GROUP_PCI;
941 info.group_index = 0;
942 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
943 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
944 info.parent.status_mask = 1ull<<3 /* npi */;
945 info.func = __cvmx_error_display;
946 info.user_info = (long)
947 "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
948 fail |= cvmx_error_add(&info);
950 info.reg_type = CVMX_ERROR_REGISTER_IO64;
951 info.status_addr = CVMX_NPI_INT_SUM;
952 info.status_mask = 1ull<<42 /* fcr_s_e */;
953 info.enable_addr = CVMX_NPI_INT_ENB;
954 info.enable_mask = 1ull<<42 /* fcr_s_e */;
956 info.group = CVMX_ERROR_GROUP_PCI;
957 info.group_index = 0;
958 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
959 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
960 info.parent.status_mask = 1ull<<3 /* npi */;
961 info.func = __cvmx_error_display;
962 info.user_info = (long)
963 "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
964 fail |= cvmx_error_add(&info);
966 info.reg_type = CVMX_ERROR_REGISTER_IO64;
967 info.status_addr = CVMX_NPI_INT_SUM;
968 info.status_mask = 1ull<<43 /* fcr_a_f */;
969 info.enable_addr = CVMX_NPI_INT_ENB;
970 info.enable_mask = 1ull<<43 /* fcr_a_f */;
972 info.group = CVMX_ERROR_GROUP_PCI;
973 info.group_index = 0;
974 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
975 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
976 info.parent.status_mask = 1ull<<3 /* npi */;
977 info.func = __cvmx_error_display;
978 info.user_info = (long)
979 "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
980 fail |= cvmx_error_add(&info);
982 info.reg_type = CVMX_ERROR_REGISTER_IO64;
983 info.status_addr = CVMX_NPI_INT_SUM;
984 info.status_mask = 1ull<<44 /* pcr_s_e */;
985 info.enable_addr = CVMX_NPI_INT_ENB;
986 info.enable_mask = 1ull<<44 /* pcr_s_e */;
988 info.group = CVMX_ERROR_GROUP_PCI;
989 info.group_index = 0;
990 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
991 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
992 info.parent.status_mask = 1ull<<3 /* npi */;
993 info.func = __cvmx_error_display;
994 info.user_info = (long)
995 "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
996 fail |= cvmx_error_add(&info);
998 info.reg_type = CVMX_ERROR_REGISTER_IO64;
999 info.status_addr = CVMX_NPI_INT_SUM;
1000 info.status_mask = 1ull<<45 /* pcr_a_f */;
1001 info.enable_addr = CVMX_NPI_INT_ENB;
1002 info.enable_mask = 1ull<<45 /* pcr_a_f */;
1004 info.group = CVMX_ERROR_GROUP_PCI;
1005 info.group_index = 0;
1006 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1007 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1008 info.parent.status_mask = 1ull<<3 /* npi */;
1009 info.func = __cvmx_error_display;
1010 info.user_info = (long)
1011 "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
1012 fail |= cvmx_error_add(&info);
1014 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1015 info.status_addr = CVMX_NPI_INT_SUM;
1016 info.status_mask = 1ull<<46 /* q2_s_e */;
1017 info.enable_addr = CVMX_NPI_INT_ENB;
1018 info.enable_mask = 1ull<<46 /* q2_s_e */;
1020 info.group = CVMX_ERROR_GROUP_PCI;
1021 info.group_index = 0;
1022 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1023 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1024 info.parent.status_mask = 1ull<<3 /* npi */;
1025 info.func = __cvmx_error_display;
1026 info.user_info = (long)
1027 "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
1028 fail |= cvmx_error_add(&info);
1030 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1031 info.status_addr = CVMX_NPI_INT_SUM;
1032 info.status_mask = 1ull<<47 /* q2_a_f */;
1033 info.enable_addr = CVMX_NPI_INT_ENB;
1034 info.enable_mask = 1ull<<47 /* q2_a_f */;
1036 info.group = CVMX_ERROR_GROUP_PCI;
1037 info.group_index = 0;
1038 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1039 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1040 info.parent.status_mask = 1ull<<3 /* npi */;
1041 info.func = __cvmx_error_display;
1042 info.user_info = (long)
1043 "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
1044 fail |= cvmx_error_add(&info);
1046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1047 info.status_addr = CVMX_NPI_INT_SUM;
1048 info.status_mask = 1ull<<48 /* q3_s_e */;
1049 info.enable_addr = CVMX_NPI_INT_ENB;
1050 info.enable_mask = 1ull<<48 /* q3_s_e */;
1052 info.group = CVMX_ERROR_GROUP_PCI;
1053 info.group_index = 0;
1054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1055 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1056 info.parent.status_mask = 1ull<<3 /* npi */;
1057 info.func = __cvmx_error_display;
1058 info.user_info = (long)
1059 "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
1060 fail |= cvmx_error_add(&info);
1062 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1063 info.status_addr = CVMX_NPI_INT_SUM;
1064 info.status_mask = 1ull<<49 /* q3_a_f */;
1065 info.enable_addr = CVMX_NPI_INT_ENB;
1066 info.enable_mask = 1ull<<49 /* q3_a_f */;
1068 info.group = CVMX_ERROR_GROUP_PCI;
1069 info.group_index = 0;
1070 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1071 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1072 info.parent.status_mask = 1ull<<3 /* npi */;
1073 info.func = __cvmx_error_display;
1074 info.user_info = (long)
1075 "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
1076 fail |= cvmx_error_add(&info);
1078 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1079 info.status_addr = CVMX_NPI_INT_SUM;
1080 info.status_mask = 1ull<<50 /* com_s_e */;
1081 info.enable_addr = CVMX_NPI_INT_ENB;
1082 info.enable_mask = 1ull<<50 /* com_s_e */;
1084 info.group = CVMX_ERROR_GROUP_PCI;
1085 info.group_index = 0;
1086 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1087 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1088 info.parent.status_mask = 1ull<<3 /* npi */;
1089 info.func = __cvmx_error_display;
1090 info.user_info = (long)
1091 "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
1092 fail |= cvmx_error_add(&info);
1094 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1095 info.status_addr = CVMX_NPI_INT_SUM;
1096 info.status_mask = 1ull<<51 /* com_a_f */;
1097 info.enable_addr = CVMX_NPI_INT_ENB;
1098 info.enable_mask = 1ull<<51 /* com_a_f */;
1100 info.group = CVMX_ERROR_GROUP_PCI;
1101 info.group_index = 0;
1102 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1103 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1104 info.parent.status_mask = 1ull<<3 /* npi */;
1105 info.func = __cvmx_error_display;
1106 info.user_info = (long)
1107 "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
1108 fail |= cvmx_error_add(&info);
1110 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1111 info.status_addr = CVMX_NPI_INT_SUM;
1112 info.status_mask = 1ull<<52 /* pnc_s_e */;
1113 info.enable_addr = CVMX_NPI_INT_ENB;
1114 info.enable_mask = 1ull<<52 /* pnc_s_e */;
1116 info.group = CVMX_ERROR_GROUP_PCI;
1117 info.group_index = 0;
1118 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1119 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1120 info.parent.status_mask = 1ull<<3 /* npi */;
1121 info.func = __cvmx_error_display;
1122 info.user_info = (long)
1123 "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
1124 fail |= cvmx_error_add(&info);
1126 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1127 info.status_addr = CVMX_NPI_INT_SUM;
1128 info.status_mask = 1ull<<53 /* pnc_a_f */;
1129 info.enable_addr = CVMX_NPI_INT_ENB;
1130 info.enable_mask = 1ull<<53 /* pnc_a_f */;
1132 info.group = CVMX_ERROR_GROUP_PCI;
1133 info.group_index = 0;
1134 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1135 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1136 info.parent.status_mask = 1ull<<3 /* npi */;
1137 info.func = __cvmx_error_display;
1138 info.user_info = (long)
1139 "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
1140 fail |= cvmx_error_add(&info);
1142 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1143 info.status_addr = CVMX_NPI_INT_SUM;
1144 info.status_mask = 1ull<<54 /* rwx_s_e */;
1145 info.enable_addr = CVMX_NPI_INT_ENB;
1146 info.enable_mask = 1ull<<54 /* rwx_s_e */;
1148 info.group = CVMX_ERROR_GROUP_PCI;
1149 info.group_index = 0;
1150 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1151 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1152 info.parent.status_mask = 1ull<<3 /* npi */;
1153 info.func = __cvmx_error_display;
1154 info.user_info = (long)
1155 "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
1156 fail |= cvmx_error_add(&info);
1158 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1159 info.status_addr = CVMX_NPI_INT_SUM;
1160 info.status_mask = 1ull<<55 /* rdx_s_e */;
1161 info.enable_addr = CVMX_NPI_INT_ENB;
1162 info.enable_mask = 1ull<<55 /* rdx_s_e */;
1164 info.group = CVMX_ERROR_GROUP_PCI;
1165 info.group_index = 0;
1166 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1167 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1168 info.parent.status_mask = 1ull<<3 /* npi */;
1169 info.func = __cvmx_error_display;
1170 info.user_info = (long)
1171 "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
1172 fail |= cvmx_error_add(&info);
1174 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1175 info.status_addr = CVMX_NPI_INT_SUM;
1176 info.status_mask = 1ull<<56 /* pcf_p_e */;
1177 info.enable_addr = CVMX_NPI_INT_ENB;
1178 info.enable_mask = 1ull<<56 /* pcf_p_e */;
1180 info.group = CVMX_ERROR_GROUP_PCI;
1181 info.group_index = 0;
1182 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1183 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1184 info.parent.status_mask = 1ull<<3 /* npi */;
1185 info.func = __cvmx_error_display;
1186 info.user_info = (long)
1187 "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
1188 fail |= cvmx_error_add(&info);
1190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1191 info.status_addr = CVMX_NPI_INT_SUM;
1192 info.status_mask = 1ull<<57 /* pcf_p_f */;
1193 info.enable_addr = CVMX_NPI_INT_ENB;
1194 info.enable_mask = 1ull<<57 /* pcf_p_f */;
1196 info.group = CVMX_ERROR_GROUP_PCI;
1197 info.group_index = 0;
1198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1199 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1200 info.parent.status_mask = 1ull<<3 /* npi */;
1201 info.func = __cvmx_error_display;
1202 info.user_info = (long)
1203 "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
1204 fail |= cvmx_error_add(&info);
1206 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1207 info.status_addr = CVMX_NPI_INT_SUM;
1208 info.status_mask = 1ull<<58 /* pdf_p_e */;
1209 info.enable_addr = CVMX_NPI_INT_ENB;
1210 info.enable_mask = 1ull<<58 /* pdf_p_e */;
1212 info.group = CVMX_ERROR_GROUP_PCI;
1213 info.group_index = 0;
1214 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1215 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1216 info.parent.status_mask = 1ull<<3 /* npi */;
1217 info.func = __cvmx_error_display;
1218 info.user_info = (long)
1219 "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
1220 fail |= cvmx_error_add(&info);
1222 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1223 info.status_addr = CVMX_NPI_INT_SUM;
1224 info.status_mask = 1ull<<59 /* pdf_p_f */;
1225 info.enable_addr = CVMX_NPI_INT_ENB;
1226 info.enable_mask = 1ull<<59 /* pdf_p_f */;
1228 info.group = CVMX_ERROR_GROUP_PCI;
1229 info.group_index = 0;
1230 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1231 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1232 info.parent.status_mask = 1ull<<3 /* npi */;
1233 info.func = __cvmx_error_display;
1234 info.user_info = (long)
1235 "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
1236 fail |= cvmx_error_add(&info);
1238 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1239 info.status_addr = CVMX_NPI_INT_SUM;
1240 info.status_mask = 1ull<<60 /* q1_s_e */;
1241 info.enable_addr = CVMX_NPI_INT_ENB;
1242 info.enable_mask = 1ull<<60 /* q1_s_e */;
1244 info.group = CVMX_ERROR_GROUP_PCI;
1245 info.group_index = 0;
1246 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1247 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1248 info.parent.status_mask = 1ull<<3 /* npi */;
1249 info.func = __cvmx_error_display;
1250 info.user_info = (long)
1251 "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
1252 fail |= cvmx_error_add(&info);
1254 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1255 info.status_addr = CVMX_NPI_INT_SUM;
1256 info.status_mask = 1ull<<61 /* q1_a_f */;
1257 info.enable_addr = CVMX_NPI_INT_ENB;
1258 info.enable_mask = 1ull<<61 /* q1_a_f */;
1260 info.group = CVMX_ERROR_GROUP_PCI;
1261 info.group_index = 0;
1262 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1263 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1264 info.parent.status_mask = 1ull<<3 /* npi */;
1265 info.func = __cvmx_error_display;
1266 info.user_info = (long)
1267 "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
1268 fail |= cvmx_error_add(&info);
1270 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1271 info.status_addr = CVMX_NPI_INT_SUM;
1272 info.status_mask = 0;
1273 info.enable_addr = 0;
1274 info.enable_mask = 0;
1276 info.group = CVMX_ERROR_GROUP_INTERNAL;
1277 info.group_index = 0;
1278 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1279 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1280 info.parent.status_mask = 1ull<<3 /* npi */;
1281 info.func = __cvmx_error_decode;
1283 fail |= cvmx_error_add(&info);
1285 /* CVMX_NPI_PCI_INT_SUM2 */
1286 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1287 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1288 info.status_mask = 1ull<<0 /* tr_wabt */;
1289 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1290 info.enable_mask = 1ull<<0 /* rtr_wabt */;
1292 info.group = CVMX_ERROR_GROUP_PCI;
1293 info.group_index = 0;
1294 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1295 info.parent.status_addr = CVMX_NPI_INT_SUM;
1296 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1297 info.func = __cvmx_error_display;
1298 info.user_info = (long)
1299 "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
1300 fail |= cvmx_error_add(&info);
1302 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1303 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1304 info.status_mask = 1ull<<1 /* mr_wabt */;
1305 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1306 info.enable_mask = 1ull<<1 /* rmr_wabt */;
1308 info.group = CVMX_ERROR_GROUP_PCI;
1309 info.group_index = 0;
1310 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1311 info.parent.status_addr = CVMX_NPI_INT_SUM;
1312 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1313 info.func = __cvmx_error_display;
1314 info.user_info = (long)
1315 "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
1316 fail |= cvmx_error_add(&info);
1318 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1319 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1320 info.status_mask = 1ull<<2 /* mr_wtto */;
1321 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1322 info.enable_mask = 1ull<<2 /* rmr_wtto */;
1324 info.group = CVMX_ERROR_GROUP_PCI;
1325 info.group_index = 0;
1326 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1327 info.parent.status_addr = CVMX_NPI_INT_SUM;
1328 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1329 info.func = __cvmx_error_display;
1330 info.user_info = (long)
1331 "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
1332 fail |= cvmx_error_add(&info);
1334 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1335 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1336 info.status_mask = 1ull<<3 /* tr_abt */;
1337 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1338 info.enable_mask = 1ull<<3 /* rtr_abt */;
1340 info.group = CVMX_ERROR_GROUP_PCI;
1341 info.group_index = 0;
1342 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1343 info.parent.status_addr = CVMX_NPI_INT_SUM;
1344 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1345 info.func = __cvmx_error_display;
1346 info.user_info = (long)
1347 "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
1348 fail |= cvmx_error_add(&info);
1350 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1351 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1352 info.status_mask = 1ull<<4 /* mr_abt */;
1353 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1354 info.enable_mask = 1ull<<4 /* rmr_abt */;
1356 info.group = CVMX_ERROR_GROUP_PCI;
1357 info.group_index = 0;
1358 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1359 info.parent.status_addr = CVMX_NPI_INT_SUM;
1360 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1361 info.func = __cvmx_error_display;
1362 info.user_info = (long)
1363 "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
1364 fail |= cvmx_error_add(&info);
1366 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1367 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1368 info.status_mask = 1ull<<5 /* mr_tto */;
1369 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1370 info.enable_mask = 1ull<<5 /* rmr_tto */;
1372 info.group = CVMX_ERROR_GROUP_PCI;
1373 info.group_index = 0;
1374 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1375 info.parent.status_addr = CVMX_NPI_INT_SUM;
1376 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1377 info.func = __cvmx_error_display;
1378 info.user_info = (long)
1379 "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
1380 fail |= cvmx_error_add(&info);
1382 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1383 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1384 info.status_mask = 1ull<<6 /* msi_per */;
1385 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1386 info.enable_mask = 1ull<<6 /* rmsi_per */;
1388 info.group = CVMX_ERROR_GROUP_PCI;
1389 info.group_index = 0;
1390 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1391 info.parent.status_addr = CVMX_NPI_INT_SUM;
1392 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1393 info.func = __cvmx_error_display;
1394 info.user_info = (long)
1395 "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
1396 fail |= cvmx_error_add(&info);
1398 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1399 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1400 info.status_mask = 1ull<<7 /* msi_tabt */;
1401 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1402 info.enable_mask = 1ull<<7 /* rmsi_tabt */;
1404 info.group = CVMX_ERROR_GROUP_PCI;
1405 info.group_index = 0;
1406 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1407 info.parent.status_addr = CVMX_NPI_INT_SUM;
1408 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1409 info.func = __cvmx_error_display;
1410 info.user_info = (long)
1411 "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
1412 fail |= cvmx_error_add(&info);
1414 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1415 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1416 info.status_mask = 1ull<<8 /* msi_mabt */;
1417 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1418 info.enable_mask = 1ull<<8 /* rmsi_mabt */;
1420 info.group = CVMX_ERROR_GROUP_PCI;
1421 info.group_index = 0;
1422 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1423 info.parent.status_addr = CVMX_NPI_INT_SUM;
1424 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1425 info.func = __cvmx_error_display;
1426 info.user_info = (long)
1427 "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
1428 fail |= cvmx_error_add(&info);
1430 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1431 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1432 info.status_mask = 1ull<<9 /* msc_msg */;
1433 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1434 info.enable_mask = 1ull<<9 /* rmsc_msg */;
1436 info.group = CVMX_ERROR_GROUP_PCI;
1437 info.group_index = 0;
1438 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1439 info.parent.status_addr = CVMX_NPI_INT_SUM;
1440 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1441 info.func = __cvmx_error_display;
1442 info.user_info = (long)
1443 "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
1444 fail |= cvmx_error_add(&info);
1446 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1447 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1448 info.status_mask = 1ull<<10 /* tsr_abt */;
1449 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1450 info.enable_mask = 1ull<<10 /* rtsr_abt */;
1452 info.group = CVMX_ERROR_GROUP_PCI;
1453 info.group_index = 0;
1454 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1455 info.parent.status_addr = CVMX_NPI_INT_SUM;
1456 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1457 info.func = __cvmx_error_display;
1458 info.user_info = (long)
1459 "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
1460 fail |= cvmx_error_add(&info);
1462 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1463 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1464 info.status_mask = 1ull<<11 /* serr */;
1465 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1466 info.enable_mask = 1ull<<11 /* rserr */;
1468 info.group = CVMX_ERROR_GROUP_PCI;
1469 info.group_index = 0;
1470 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1471 info.parent.status_addr = CVMX_NPI_INT_SUM;
1472 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1473 info.func = __cvmx_error_display;
1474 info.user_info = (long)
1475 "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
1476 fail |= cvmx_error_add(&info);
1478 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1479 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1480 info.status_mask = 1ull<<12 /* aperr */;
1481 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1482 info.enable_mask = 1ull<<12 /* raperr */;
1484 info.group = CVMX_ERROR_GROUP_PCI;
1485 info.group_index = 0;
1486 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1487 info.parent.status_addr = CVMX_NPI_INT_SUM;
1488 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1489 info.func = __cvmx_error_display;
1490 info.user_info = (long)
1491 "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
1492 fail |= cvmx_error_add(&info);
1494 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1495 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1496 info.status_mask = 1ull<<13 /* dperr */;
1497 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1498 info.enable_mask = 1ull<<13 /* rdperr */;
1500 info.group = CVMX_ERROR_GROUP_PCI;
1501 info.group_index = 0;
1502 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1503 info.parent.status_addr = CVMX_NPI_INT_SUM;
1504 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1505 info.func = __cvmx_error_display;
1506 info.user_info = (long)
1507 "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
1508 fail |= cvmx_error_add(&info);
1510 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1511 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1512 info.status_mask = 1ull<<14 /* ill_rwr */;
1513 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1514 info.enable_mask = 1ull<<14 /* ill_rwr */;
1516 info.group = CVMX_ERROR_GROUP_PCI;
1517 info.group_index = 0;
1518 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1519 info.parent.status_addr = CVMX_NPI_INT_SUM;
1520 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1521 info.func = __cvmx_error_display;
1522 info.user_info = (long)
1523 "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
1524 fail |= cvmx_error_add(&info);
1526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1527 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1528 info.status_mask = 1ull<<15 /* ill_rrd */;
1529 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1530 info.enable_mask = 1ull<<15 /* ill_rrd */;
1532 info.group = CVMX_ERROR_GROUP_PCI;
1533 info.group_index = 0;
1534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1535 info.parent.status_addr = CVMX_NPI_INT_SUM;
1536 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1537 info.func = __cvmx_error_display;
1538 info.user_info = (long)
1539 "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
1540 fail |= cvmx_error_add(&info);
1542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1543 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1544 info.status_mask = 1ull<<31 /* win_wr */;
1545 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1546 info.enable_mask = 1ull<<31 /* win_wr */;
1548 info.group = CVMX_ERROR_GROUP_PCI;
1549 info.group_index = 0;
1550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1551 info.parent.status_addr = CVMX_NPI_INT_SUM;
1552 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1553 info.func = __cvmx_error_display;
1554 info.user_info = (long)
1555 "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
1556 " Read-Address Register took place.\n";
1557 fail |= cvmx_error_add(&info);
1559 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1560 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1561 info.status_mask = 1ull<<32 /* ill_wr */;
1562 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1563 info.enable_mask = 1ull<<32 /* ill_wr */;
1565 info.group = CVMX_ERROR_GROUP_PCI;
1566 info.group_index = 0;
1567 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1568 info.parent.status_addr = CVMX_NPI_INT_SUM;
1569 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1570 info.func = __cvmx_error_display;
1571 info.user_info = (long)
1572 "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
1573 " when the mem area is disabled.\n";
1574 fail |= cvmx_error_add(&info);
1576 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1577 info.status_addr = CVMX_NPI_PCI_INT_SUM2;
1578 info.status_mask = 1ull<<33 /* ill_rd */;
1579 info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
1580 info.enable_mask = 1ull<<33 /* ill_rd */;
1582 info.group = CVMX_ERROR_GROUP_PCI;
1583 info.group_index = 0;
1584 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1585 info.parent.status_addr = CVMX_NPI_INT_SUM;
1586 info.parent.status_mask = 1ull<<2 /* pci_rsl */;
1587 info.func = __cvmx_error_display;
1588 info.user_info = (long)
1589 "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
1590 " when the mem area is disabled.\n";
1591 fail |= cvmx_error_add(&info);
1593 /* CVMX_FPA_INT_SUM */
1594 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1595 info.status_addr = CVMX_FPA_INT_SUM;
1596 info.status_mask = 1ull<<0 /* fed0_sbe */;
1597 info.enable_addr = CVMX_FPA_INT_ENB;
1598 info.enable_mask = 1ull<<0 /* fed0_sbe */;
1600 info.group = CVMX_ERROR_GROUP_INTERNAL;
1601 info.group_index = 0;
1602 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1603 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1604 info.parent.status_mask = 1ull<<5 /* fpa */;
1605 info.func = __cvmx_error_display;
1606 info.user_info = (long)
1607 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
1608 fail |= cvmx_error_add(&info);
1610 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1611 info.status_addr = CVMX_FPA_INT_SUM;
1612 info.status_mask = 1ull<<1 /* fed0_dbe */;
1613 info.enable_addr = CVMX_FPA_INT_ENB;
1614 info.enable_mask = 1ull<<1 /* fed0_dbe */;
1616 info.group = CVMX_ERROR_GROUP_INTERNAL;
1617 info.group_index = 0;
1618 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1619 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1620 info.parent.status_mask = 1ull<<5 /* fpa */;
1621 info.func = __cvmx_error_display;
1622 info.user_info = (long)
1623 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
1624 fail |= cvmx_error_add(&info);
1626 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1627 info.status_addr = CVMX_FPA_INT_SUM;
1628 info.status_mask = 1ull<<2 /* fed1_sbe */;
1629 info.enable_addr = CVMX_FPA_INT_ENB;
1630 info.enable_mask = 1ull<<2 /* fed1_sbe */;
1632 info.group = CVMX_ERROR_GROUP_INTERNAL;
1633 info.group_index = 0;
1634 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1635 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1636 info.parent.status_mask = 1ull<<5 /* fpa */;
1637 info.func = __cvmx_error_display;
1638 info.user_info = (long)
1639 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
1640 fail |= cvmx_error_add(&info);
1642 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1643 info.status_addr = CVMX_FPA_INT_SUM;
1644 info.status_mask = 1ull<<3 /* fed1_dbe */;
1645 info.enable_addr = CVMX_FPA_INT_ENB;
1646 info.enable_mask = 1ull<<3 /* fed1_dbe */;
1648 info.group = CVMX_ERROR_GROUP_INTERNAL;
1649 info.group_index = 0;
1650 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1651 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1652 info.parent.status_mask = 1ull<<5 /* fpa */;
1653 info.func = __cvmx_error_display;
1654 info.user_info = (long)
1655 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
1656 fail |= cvmx_error_add(&info);
1658 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1659 info.status_addr = CVMX_FPA_INT_SUM;
1660 info.status_mask = 1ull<<4 /* q0_und */;
1661 info.enable_addr = CVMX_FPA_INT_ENB;
1662 info.enable_mask = 1ull<<4 /* q0_und */;
1664 info.group = CVMX_ERROR_GROUP_INTERNAL;
1665 info.group_index = 0;
1666 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1667 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1668 info.parent.status_mask = 1ull<<5 /* fpa */;
1669 info.func = __cvmx_error_display;
1670 info.user_info = (long)
1671 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
1673 fail |= cvmx_error_add(&info);
1675 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1676 info.status_addr = CVMX_FPA_INT_SUM;
1677 info.status_mask = 1ull<<5 /* q0_coff */;
1678 info.enable_addr = CVMX_FPA_INT_ENB;
1679 info.enable_mask = 1ull<<5 /* q0_coff */;
1681 info.group = CVMX_ERROR_GROUP_INTERNAL;
1682 info.group_index = 0;
1683 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1684 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1685 info.parent.status_mask = 1ull<<5 /* fpa */;
1686 info.func = __cvmx_error_display;
1687 info.user_info = (long)
1688 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
1689 " the count available is greater than pointers\n"
1690 " present in the FPA.\n";
1691 fail |= cvmx_error_add(&info);
1693 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1694 info.status_addr = CVMX_FPA_INT_SUM;
1695 info.status_mask = 1ull<<6 /* q0_perr */;
1696 info.enable_addr = CVMX_FPA_INT_ENB;
1697 info.enable_mask = 1ull<<6 /* q0_perr */;
1699 info.group = CVMX_ERROR_GROUP_INTERNAL;
1700 info.group_index = 0;
1701 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1702 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1703 info.parent.status_mask = 1ull<<5 /* fpa */;
1704 info.func = __cvmx_error_display;
1705 info.user_info = (long)
1706 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
1707 " the L2C does not have the FPA owner ship bit set.\n";
1708 fail |= cvmx_error_add(&info);
1710 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1711 info.status_addr = CVMX_FPA_INT_SUM;
1712 info.status_mask = 1ull<<7 /* q1_und */;
1713 info.enable_addr = CVMX_FPA_INT_ENB;
1714 info.enable_mask = 1ull<<7 /* q1_und */;
1716 info.group = CVMX_ERROR_GROUP_INTERNAL;
1717 info.group_index = 0;
1718 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1719 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1720 info.parent.status_mask = 1ull<<5 /* fpa */;
1721 info.func = __cvmx_error_display;
1722 info.user_info = (long)
1723 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
1725 fail |= cvmx_error_add(&info);
1727 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1728 info.status_addr = CVMX_FPA_INT_SUM;
1729 info.status_mask = 1ull<<8 /* q1_coff */;
1730 info.enable_addr = CVMX_FPA_INT_ENB;
1731 info.enable_mask = 1ull<<8 /* q1_coff */;
1733 info.group = CVMX_ERROR_GROUP_INTERNAL;
1734 info.group_index = 0;
1735 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1736 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1737 info.parent.status_mask = 1ull<<5 /* fpa */;
1738 info.func = __cvmx_error_display;
1739 info.user_info = (long)
1740 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
1741 " the count available is greater than pointers\n"
1742 " present in the FPA.\n";
1743 fail |= cvmx_error_add(&info);
1745 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1746 info.status_addr = CVMX_FPA_INT_SUM;
1747 info.status_mask = 1ull<<9 /* q1_perr */;
1748 info.enable_addr = CVMX_FPA_INT_ENB;
1749 info.enable_mask = 1ull<<9 /* q1_perr */;
1751 info.group = CVMX_ERROR_GROUP_INTERNAL;
1752 info.group_index = 0;
1753 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1754 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1755 info.parent.status_mask = 1ull<<5 /* fpa */;
1756 info.func = __cvmx_error_display;
1757 info.user_info = (long)
1758 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
1759 " the L2C does not have the FPA owner ship bit set.\n";
1760 fail |= cvmx_error_add(&info);
1762 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1763 info.status_addr = CVMX_FPA_INT_SUM;
1764 info.status_mask = 1ull<<10 /* q2_und */;
1765 info.enable_addr = CVMX_FPA_INT_ENB;
1766 info.enable_mask = 1ull<<10 /* q2_und */;
1768 info.group = CVMX_ERROR_GROUP_INTERNAL;
1769 info.group_index = 0;
1770 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1771 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1772 info.parent.status_mask = 1ull<<5 /* fpa */;
1773 info.func = __cvmx_error_display;
1774 info.user_info = (long)
1775 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
1777 fail |= cvmx_error_add(&info);
1779 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1780 info.status_addr = CVMX_FPA_INT_SUM;
1781 info.status_mask = 1ull<<11 /* q2_coff */;
1782 info.enable_addr = CVMX_FPA_INT_ENB;
1783 info.enable_mask = 1ull<<11 /* q2_coff */;
1785 info.group = CVMX_ERROR_GROUP_INTERNAL;
1786 info.group_index = 0;
1787 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1788 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1789 info.parent.status_mask = 1ull<<5 /* fpa */;
1790 info.func = __cvmx_error_display;
1791 info.user_info = (long)
1792 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
1793 " the count available is greater than than pointers\n"
1794 " present in the FPA.\n";
1795 fail |= cvmx_error_add(&info);
1797 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1798 info.status_addr = CVMX_FPA_INT_SUM;
1799 info.status_mask = 1ull<<12 /* q2_perr */;
1800 info.enable_addr = CVMX_FPA_INT_ENB;
1801 info.enable_mask = 1ull<<12 /* q2_perr */;
1803 info.group = CVMX_ERROR_GROUP_INTERNAL;
1804 info.group_index = 0;
1805 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1806 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1807 info.parent.status_mask = 1ull<<5 /* fpa */;
1808 info.func = __cvmx_error_display;
1809 info.user_info = (long)
1810 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
1811 " the L2C does not have the FPA owner ship bit set.\n";
1812 fail |= cvmx_error_add(&info);
1814 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1815 info.status_addr = CVMX_FPA_INT_SUM;
1816 info.status_mask = 1ull<<13 /* q3_und */;
1817 info.enable_addr = CVMX_FPA_INT_ENB;
1818 info.enable_mask = 1ull<<13 /* q3_und */;
1820 info.group = CVMX_ERROR_GROUP_INTERNAL;
1821 info.group_index = 0;
1822 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1823 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1824 info.parent.status_mask = 1ull<<5 /* fpa */;
1825 info.func = __cvmx_error_display;
1826 info.user_info = (long)
1827 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
1829 fail |= cvmx_error_add(&info);
1831 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1832 info.status_addr = CVMX_FPA_INT_SUM;
1833 info.status_mask = 1ull<<14 /* q3_coff */;
1834 info.enable_addr = CVMX_FPA_INT_ENB;
1835 info.enable_mask = 1ull<<14 /* q3_coff */;
1837 info.group = CVMX_ERROR_GROUP_INTERNAL;
1838 info.group_index = 0;
1839 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1840 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1841 info.parent.status_mask = 1ull<<5 /* fpa */;
1842 info.func = __cvmx_error_display;
1843 info.user_info = (long)
1844 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
1845 " the count available is greater than than pointers\n"
1846 " present in the FPA.\n";
1847 fail |= cvmx_error_add(&info);
1849 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1850 info.status_addr = CVMX_FPA_INT_SUM;
1851 info.status_mask = 1ull<<15 /* q3_perr */;
1852 info.enable_addr = CVMX_FPA_INT_ENB;
1853 info.enable_mask = 1ull<<15 /* q3_perr */;
1855 info.group = CVMX_ERROR_GROUP_INTERNAL;
1856 info.group_index = 0;
1857 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1858 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1859 info.parent.status_mask = 1ull<<5 /* fpa */;
1860 info.func = __cvmx_error_display;
1861 info.user_info = (long)
1862 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
1863 " the L2C does not have the FPA owner ship bit set.\n";
1864 fail |= cvmx_error_add(&info);
1866 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1867 info.status_addr = CVMX_FPA_INT_SUM;
1868 info.status_mask = 1ull<<16 /* q4_und */;
1869 info.enable_addr = CVMX_FPA_INT_ENB;
1870 info.enable_mask = 1ull<<16 /* q4_und */;
1872 info.group = CVMX_ERROR_GROUP_INTERNAL;
1873 info.group_index = 0;
1874 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1875 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1876 info.parent.status_mask = 1ull<<5 /* fpa */;
1877 info.func = __cvmx_error_display;
1878 info.user_info = (long)
1879 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
1881 fail |= cvmx_error_add(&info);
1883 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1884 info.status_addr = CVMX_FPA_INT_SUM;
1885 info.status_mask = 1ull<<17 /* q4_coff */;
1886 info.enable_addr = CVMX_FPA_INT_ENB;
1887 info.enable_mask = 1ull<<17 /* q4_coff */;
1889 info.group = CVMX_ERROR_GROUP_INTERNAL;
1890 info.group_index = 0;
1891 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1892 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1893 info.parent.status_mask = 1ull<<5 /* fpa */;
1894 info.func = __cvmx_error_display;
1895 info.user_info = (long)
1896 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
1897 " the count available is greater than than pointers\n"
1898 " present in the FPA.\n";
1899 fail |= cvmx_error_add(&info);
1901 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1902 info.status_addr = CVMX_FPA_INT_SUM;
1903 info.status_mask = 1ull<<18 /* q4_perr */;
1904 info.enable_addr = CVMX_FPA_INT_ENB;
1905 info.enable_mask = 1ull<<18 /* q4_perr */;
1907 info.group = CVMX_ERROR_GROUP_INTERNAL;
1908 info.group_index = 0;
1909 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1910 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1911 info.parent.status_mask = 1ull<<5 /* fpa */;
1912 info.func = __cvmx_error_display;
1913 info.user_info = (long)
1914 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
1915 " the L2C does not have the FPA owner ship bit set.\n";
1916 fail |= cvmx_error_add(&info);
1918 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1919 info.status_addr = CVMX_FPA_INT_SUM;
1920 info.status_mask = 1ull<<19 /* q5_und */;
1921 info.enable_addr = CVMX_FPA_INT_ENB;
1922 info.enable_mask = 1ull<<19 /* q5_und */;
1924 info.group = CVMX_ERROR_GROUP_INTERNAL;
1925 info.group_index = 0;
1926 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1927 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1928 info.parent.status_mask = 1ull<<5 /* fpa */;
1929 info.func = __cvmx_error_display;
1930 info.user_info = (long)
1931 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
1933 fail |= cvmx_error_add(&info);
1935 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1936 info.status_addr = CVMX_FPA_INT_SUM;
1937 info.status_mask = 1ull<<20 /* q5_coff */;
1938 info.enable_addr = CVMX_FPA_INT_ENB;
1939 info.enable_mask = 1ull<<20 /* q5_coff */;
1941 info.group = CVMX_ERROR_GROUP_INTERNAL;
1942 info.group_index = 0;
1943 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1944 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1945 info.parent.status_mask = 1ull<<5 /* fpa */;
1946 info.func = __cvmx_error_display;
1947 info.user_info = (long)
1948 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
1949 " the count available is greater than than pointers\n"
1950 " present in the FPA.\n";
1951 fail |= cvmx_error_add(&info);
1953 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1954 info.status_addr = CVMX_FPA_INT_SUM;
1955 info.status_mask = 1ull<<21 /* q5_perr */;
1956 info.enable_addr = CVMX_FPA_INT_ENB;
1957 info.enable_mask = 1ull<<21 /* q5_perr */;
1959 info.group = CVMX_ERROR_GROUP_INTERNAL;
1960 info.group_index = 0;
1961 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1962 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1963 info.parent.status_mask = 1ull<<5 /* fpa */;
1964 info.func = __cvmx_error_display;
1965 info.user_info = (long)
1966 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
1967 " the L2C does not have the FPA owner ship bit set.\n";
1968 fail |= cvmx_error_add(&info);
1970 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1971 info.status_addr = CVMX_FPA_INT_SUM;
1972 info.status_mask = 1ull<<22 /* q6_und */;
1973 info.enable_addr = CVMX_FPA_INT_ENB;
1974 info.enable_mask = 1ull<<22 /* q6_und */;
1976 info.group = CVMX_ERROR_GROUP_INTERNAL;
1977 info.group_index = 0;
1978 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1979 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1980 info.parent.status_mask = 1ull<<5 /* fpa */;
1981 info.func = __cvmx_error_display;
1982 info.user_info = (long)
1983 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
1985 fail |= cvmx_error_add(&info);
1987 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1988 info.status_addr = CVMX_FPA_INT_SUM;
1989 info.status_mask = 1ull<<23 /* q6_coff */;
1990 info.enable_addr = CVMX_FPA_INT_ENB;
1991 info.enable_mask = 1ull<<23 /* q6_coff */;
1993 info.group = CVMX_ERROR_GROUP_INTERNAL;
1994 info.group_index = 0;
1995 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1996 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
1997 info.parent.status_mask = 1ull<<5 /* fpa */;
1998 info.func = __cvmx_error_display;
1999 info.user_info = (long)
2000 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
2001 " the count available is greater than than pointers\n"
2002 " present in the FPA.\n";
2003 fail |= cvmx_error_add(&info);
2005 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2006 info.status_addr = CVMX_FPA_INT_SUM;
2007 info.status_mask = 1ull<<24 /* q6_perr */;
2008 info.enable_addr = CVMX_FPA_INT_ENB;
2009 info.enable_mask = 1ull<<24 /* q6_perr */;
2011 info.group = CVMX_ERROR_GROUP_INTERNAL;
2012 info.group_index = 0;
2013 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2014 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2015 info.parent.status_mask = 1ull<<5 /* fpa */;
2016 info.func = __cvmx_error_display;
2017 info.user_info = (long)
2018 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
2019 " the L2C does not have the FPA owner ship bit set.\n";
2020 fail |= cvmx_error_add(&info);
2022 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2023 info.status_addr = CVMX_FPA_INT_SUM;
2024 info.status_mask = 1ull<<25 /* q7_und */;
2025 info.enable_addr = CVMX_FPA_INT_ENB;
2026 info.enable_mask = 1ull<<25 /* q7_und */;
2028 info.group = CVMX_ERROR_GROUP_INTERNAL;
2029 info.group_index = 0;
2030 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2031 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2032 info.parent.status_mask = 1ull<<5 /* fpa */;
2033 info.func = __cvmx_error_display;
2034 info.user_info = (long)
2035 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
2037 fail |= cvmx_error_add(&info);
2039 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2040 info.status_addr = CVMX_FPA_INT_SUM;
2041 info.status_mask = 1ull<<26 /* q7_coff */;
2042 info.enable_addr = CVMX_FPA_INT_ENB;
2043 info.enable_mask = 1ull<<26 /* q7_coff */;
2045 info.group = CVMX_ERROR_GROUP_INTERNAL;
2046 info.group_index = 0;
2047 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2048 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2049 info.parent.status_mask = 1ull<<5 /* fpa */;
2050 info.func = __cvmx_error_display;
2051 info.user_info = (long)
2052 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
2053 " the count available is greater than than pointers\n"
2054 " present in the FPA.\n";
2055 fail |= cvmx_error_add(&info);
2057 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2058 info.status_addr = CVMX_FPA_INT_SUM;
2059 info.status_mask = 1ull<<27 /* q7_perr */;
2060 info.enable_addr = CVMX_FPA_INT_ENB;
2061 info.enable_mask = 1ull<<27 /* q7_perr */;
2063 info.group = CVMX_ERROR_GROUP_INTERNAL;
2064 info.group_index = 0;
2065 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2066 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2067 info.parent.status_mask = 1ull<<5 /* fpa */;
2068 info.func = __cvmx_error_display;
2069 info.user_info = (long)
2070 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
2071 " the L2C does not have the FPA owner ship bit set.\n";
2072 fail |= cvmx_error_add(&info);
2074 /* CVMX_MIO_BOOT_ERR */
2075 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2076 info.status_addr = CVMX_MIO_BOOT_ERR;
2077 info.status_mask = 1ull<<0 /* adr_err */;
2078 info.enable_addr = CVMX_MIO_BOOT_INT;
2079 info.enable_mask = 1ull<<0 /* adr_int */;
2081 info.group = CVMX_ERROR_GROUP_INTERNAL;
2082 info.group_index = 0;
2083 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2084 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2085 info.parent.status_mask = 1ull<<0 /* mio */;
2086 info.func = __cvmx_error_display;
2087 info.user_info = (long)
2088 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
2089 fail |= cvmx_error_add(&info);
2091 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2092 info.status_addr = CVMX_MIO_BOOT_ERR;
2093 info.status_mask = 1ull<<1 /* wait_err */;
2094 info.enable_addr = CVMX_MIO_BOOT_INT;
2095 info.enable_mask = 1ull<<1 /* wait_int */;
2097 info.group = CVMX_ERROR_GROUP_INTERNAL;
2098 info.group_index = 0;
2099 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2100 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2101 info.parent.status_mask = 1ull<<0 /* mio */;
2102 info.func = __cvmx_error_display;
2103 info.user_info = (long)
2104 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
2105 fail |= cvmx_error_add(&info);
2107 /* CVMX_IPD_INT_SUM */
2108 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2109 info.status_addr = CVMX_IPD_INT_SUM;
2110 info.status_mask = 1ull<<0 /* prc_par0 */;
2111 info.enable_addr = CVMX_IPD_INT_ENB;
2112 info.enable_mask = 1ull<<0 /* prc_par0 */;
2114 info.group = CVMX_ERROR_GROUP_INTERNAL;
2115 info.group_index = 0;
2116 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2117 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2118 info.parent.status_mask = 1ull<<9 /* ipd */;
2119 info.func = __cvmx_error_display;
2120 info.user_info = (long)
2121 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
2122 " [31:0] of the PBM memory.\n";
2123 fail |= cvmx_error_add(&info);
2125 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2126 info.status_addr = CVMX_IPD_INT_SUM;
2127 info.status_mask = 1ull<<1 /* prc_par1 */;
2128 info.enable_addr = CVMX_IPD_INT_ENB;
2129 info.enable_mask = 1ull<<1 /* prc_par1 */;
2131 info.group = CVMX_ERROR_GROUP_INTERNAL;
2132 info.group_index = 0;
2133 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2134 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2135 info.parent.status_mask = 1ull<<9 /* ipd */;
2136 info.func = __cvmx_error_display;
2137 info.user_info = (long)
2138 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
2139 " [63:32] of the PBM memory.\n";
2140 fail |= cvmx_error_add(&info);
2142 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2143 info.status_addr = CVMX_IPD_INT_SUM;
2144 info.status_mask = 1ull<<2 /* prc_par2 */;
2145 info.enable_addr = CVMX_IPD_INT_ENB;
2146 info.enable_mask = 1ull<<2 /* prc_par2 */;
2148 info.group = CVMX_ERROR_GROUP_INTERNAL;
2149 info.group_index = 0;
2150 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2151 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2152 info.parent.status_mask = 1ull<<9 /* ipd */;
2153 info.func = __cvmx_error_display;
2154 info.user_info = (long)
2155 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
2156 " [95:64] of the PBM memory.\n";
2157 fail |= cvmx_error_add(&info);
2159 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2160 info.status_addr = CVMX_IPD_INT_SUM;
2161 info.status_mask = 1ull<<3 /* prc_par3 */;
2162 info.enable_addr = CVMX_IPD_INT_ENB;
2163 info.enable_mask = 1ull<<3 /* prc_par3 */;
2165 info.group = CVMX_ERROR_GROUP_INTERNAL;
2166 info.group_index = 0;
2167 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2168 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2169 info.parent.status_mask = 1ull<<9 /* ipd */;
2170 info.func = __cvmx_error_display;
2171 info.user_info = (long)
2172 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
2173 " [127:96] of the PBM memory.\n";
2174 fail |= cvmx_error_add(&info);
2176 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2177 info.status_addr = CVMX_IPD_INT_SUM;
2178 info.status_mask = 1ull<<4 /* bp_sub */;
2179 info.enable_addr = CVMX_IPD_INT_ENB;
2180 info.enable_mask = 1ull<<4 /* bp_sub */;
2182 info.group = CVMX_ERROR_GROUP_INTERNAL;
2183 info.group_index = 0;
2184 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2185 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2186 info.parent.status_mask = 1ull<<9 /* ipd */;
2187 info.func = __cvmx_error_display;
2188 info.user_info = (long)
2189 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
2190 " supplied illegal value.\n";
2191 fail |= cvmx_error_add(&info);
2193 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2194 info.status_addr = CVMX_IPD_INT_SUM;
2195 info.status_mask = 1ull<<5 /* dc_ovr */;
2196 info.enable_addr = CVMX_IPD_INT_ENB;
2197 info.enable_mask = 1ull<<5 /* dc_ovr */;
2199 info.group = CVMX_ERROR_GROUP_INTERNAL;
2200 info.group_index = 0;
2201 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2202 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2203 info.parent.status_mask = 1ull<<9 /* ipd */;
2204 info.func = __cvmx_error_display;
2205 info.user_info = (long)
2206 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
2207 " This is a PASS-3 Field.\n";
2208 fail |= cvmx_error_add(&info);
2210 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2211 info.status_addr = CVMX_IPD_INT_SUM;
2212 info.status_mask = 1ull<<6 /* cc_ovr */;
2213 info.enable_addr = CVMX_IPD_INT_ENB;
2214 info.enable_mask = 1ull<<6 /* cc_ovr */;
2216 info.group = CVMX_ERROR_GROUP_INTERNAL;
2217 info.group_index = 0;
2218 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2219 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2220 info.parent.status_mask = 1ull<<9 /* ipd */;
2221 info.func = __cvmx_error_display;
2222 info.user_info = (long)
2223 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
2224 " This is a PASS-3 Field.\n";
2225 fail |= cvmx_error_add(&info);
2227 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2228 info.status_addr = CVMX_IPD_INT_SUM;
2229 info.status_mask = 1ull<<7 /* c_coll */;
2230 info.enable_addr = CVMX_IPD_INT_ENB;
2231 info.enable_mask = 1ull<<7 /* c_coll */;
2233 info.group = CVMX_ERROR_GROUP_INTERNAL;
2234 info.group_index = 0;
2235 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2236 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2237 info.parent.status_mask = 1ull<<9 /* ipd */;
2238 info.func = __cvmx_error_display;
2239 info.user_info = (long)
2240 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
2242 " This is a PASS-3 Field.\n";
2243 fail |= cvmx_error_add(&info);
2245 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2246 info.status_addr = CVMX_IPD_INT_SUM;
2247 info.status_mask = 1ull<<8 /* d_coll */;
2248 info.enable_addr = CVMX_IPD_INT_ENB;
2249 info.enable_mask = 1ull<<8 /* d_coll */;
2251 info.group = CVMX_ERROR_GROUP_INTERNAL;
2252 info.group_index = 0;
2253 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2254 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2255 info.parent.status_mask = 1ull<<9 /* ipd */;
2256 info.func = __cvmx_error_display;
2257 info.user_info = (long)
2258 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
2260 " This is a PASS-3 Field.\n";
2261 fail |= cvmx_error_add(&info);
2263 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2264 info.status_addr = CVMX_IPD_INT_SUM;
2265 info.status_mask = 1ull<<9 /* bc_ovr */;
2266 info.enable_addr = CVMX_IPD_INT_ENB;
2267 info.enable_mask = 1ull<<9 /* bc_ovr */;
2269 info.group = CVMX_ERROR_GROUP_INTERNAL;
2270 info.group_index = 0;
2271 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2272 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2273 info.parent.status_mask = 1ull<<9 /* ipd */;
2274 info.func = __cvmx_error_display;
2275 info.user_info = (long)
2276 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
2277 " This is a PASS-3 Field.\n";
2278 fail |= cvmx_error_add(&info);
2280 /* CVMX_POW_ECC_ERR */
2281 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2282 info.status_addr = CVMX_POW_ECC_ERR;
2283 info.status_mask = 1ull<<0 /* sbe */;
2284 info.enable_addr = CVMX_POW_ECC_ERR;
2285 info.enable_mask = 1ull<<2 /* sbe_ie */;
2286 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2287 info.group = CVMX_ERROR_GROUP_INTERNAL;
2288 info.group_index = 0;
2289 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2290 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2291 info.parent.status_mask = 1ull<<12 /* pow */;
2292 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
2293 info.user_info = (long)
2294 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
2295 fail |= cvmx_error_add(&info);
2297 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2298 info.status_addr = CVMX_POW_ECC_ERR;
2299 info.status_mask = 1ull<<1 /* dbe */;
2300 info.enable_addr = CVMX_POW_ECC_ERR;
2301 info.enable_mask = 1ull<<3 /* dbe_ie */;
2303 info.group = CVMX_ERROR_GROUP_INTERNAL;
2304 info.group_index = 0;
2305 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2306 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2307 info.parent.status_mask = 1ull<<12 /* pow */;
2308 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
2309 info.user_info = (long)
2310 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
2311 fail |= cvmx_error_add(&info);
2313 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2314 info.status_addr = CVMX_POW_ECC_ERR;
2315 info.status_mask = 1ull<<12 /* rpe */;
2316 info.enable_addr = CVMX_POW_ECC_ERR;
2317 info.enable_mask = 1ull<<13 /* rpe_ie */;
2319 info.group = CVMX_ERROR_GROUP_INTERNAL;
2320 info.group_index = 0;
2321 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2322 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2323 info.parent.status_mask = 1ull<<12 /* pow */;
2324 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
2325 info.user_info = (long)
2326 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
2327 fail |= cvmx_error_add(&info);
2329 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2330 info.status_addr = CVMX_POW_ECC_ERR;
2331 info.status_mask = 0x1fffull<<16 /* iop */;
2332 info.enable_addr = CVMX_POW_ECC_ERR;
2333 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
2335 info.group = CVMX_ERROR_GROUP_INTERNAL;
2336 info.group_index = 0;
2337 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2338 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2339 info.parent.status_mask = 1ull<<12 /* pow */;
2340 info.func = __cvmx_error_handle_pow_ecc_err_iop;
2341 info.user_info = (long)
2342 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
2343 fail |= cvmx_error_add(&info);
2345 /* CVMX_ASXX_INT_REG(0) */
2346 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2347 info.status_addr = CVMX_ASXX_INT_REG(0);
2348 info.status_mask = 0x7ull<<0 /* ovrflw */;
2349 info.enable_addr = CVMX_ASXX_INT_EN(0);
2350 info.enable_mask = 0x7ull<<0 /* ovrflw */;
2352 info.group = CVMX_ERROR_GROUP_ETHERNET;
2353 info.group_index = 0;
2354 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2355 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2356 info.parent.status_mask = 1ull<<22 /* asx0 */;
2357 info.func = __cvmx_error_display;
2358 info.user_info = (long)
2359 "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
2360 fail |= cvmx_error_add(&info);
2362 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2363 info.status_addr = CVMX_ASXX_INT_REG(0);
2364 info.status_mask = 0x7ull<<4 /* txpop */;
2365 info.enable_addr = CVMX_ASXX_INT_EN(0);
2366 info.enable_mask = 0x7ull<<4 /* txpop */;
2368 info.group = CVMX_ERROR_GROUP_ETHERNET;
2369 info.group_index = 0;
2370 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2371 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2372 info.parent.status_mask = 1ull<<22 /* asx0 */;
2373 info.func = __cvmx_error_display;
2374 info.user_info = (long)
2375 "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
2376 fail |= cvmx_error_add(&info);
2378 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2379 info.status_addr = CVMX_ASXX_INT_REG(0);
2380 info.status_mask = 0x7ull<<8 /* txpsh */;
2381 info.enable_addr = CVMX_ASXX_INT_EN(0);
2382 info.enable_mask = 0x7ull<<8 /* txpsh */;
2384 info.group = CVMX_ERROR_GROUP_ETHERNET;
2385 info.group_index = 0;
2386 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2387 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2388 info.parent.status_mask = 1ull<<22 /* asx0 */;
2389 info.func = __cvmx_error_display;
2390 info.user_info = (long)
2391 "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
2392 fail |= cvmx_error_add(&info);
2394 /* CVMX_PKO_REG_ERROR */
2395 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2396 info.status_addr = CVMX_PKO_REG_ERROR;
2397 info.status_mask = 1ull<<0 /* parity */;
2398 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2399 info.enable_mask = 1ull<<0 /* parity */;
2401 info.group = CVMX_ERROR_GROUP_INTERNAL;
2402 info.group_index = 0;
2403 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2404 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2405 info.parent.status_mask = 1ull<<10 /* pko */;
2406 info.func = __cvmx_error_display;
2407 info.user_info = (long)
2408 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2409 fail |= cvmx_error_add(&info);
2411 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2412 info.status_addr = CVMX_PKO_REG_ERROR;
2413 info.status_mask = 1ull<<1 /* doorbell */;
2414 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2415 info.enable_mask = 1ull<<1 /* doorbell */;
2417 info.group = CVMX_ERROR_GROUP_INTERNAL;
2418 info.group_index = 0;
2419 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2420 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2421 info.parent.status_mask = 1ull<<10 /* pko */;
2422 info.func = __cvmx_error_display;
2423 info.user_info = (long)
2424 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2425 fail |= cvmx_error_add(&info);
2427 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2428 info.status_addr = CVMX_PKO_REG_ERROR;
2429 info.status_mask = 1ull<<2 /* currzero */;
2430 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2431 info.enable_mask = 1ull<<2 /* currzero */;
2433 info.group = CVMX_ERROR_GROUP_INTERNAL;
2434 info.group_index = 0;
2435 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2436 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2437 info.parent.status_mask = 1ull<<10 /* pko */;
2438 info.func = __cvmx_error_display;
2439 info.user_info = (long)
2440 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
2441 fail |= cvmx_error_add(&info);
2443 /* CVMX_TIM_REG_ERROR */
2444 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2445 info.status_addr = CVMX_TIM_REG_ERROR;
2446 info.status_mask = 0xffffull<<0 /* mask */;
2447 info.enable_addr = CVMX_TIM_REG_INT_MASK;
2448 info.enable_mask = 0xffffull<<0 /* mask */;
2450 info.group = CVMX_ERROR_GROUP_INTERNAL;
2451 info.group_index = 0;
2452 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2453 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2454 info.parent.status_mask = 1ull<<11 /* tim */;
2455 info.func = __cvmx_error_display;
2456 info.user_info = (long)
2457 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
2458 fail |= cvmx_error_add(&info);
2460 /* CVMX_PIP_INT_REG */
2461 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2462 info.status_addr = CVMX_PIP_INT_REG;
2463 info.status_mask = 1ull<<3 /* prtnxa */;
2464 info.enable_addr = CVMX_PIP_INT_EN;
2465 info.enable_mask = 1ull<<3 /* prtnxa */;
2467 info.group = CVMX_ERROR_GROUP_INTERNAL;
2468 info.group_index = 0;
2469 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2470 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2471 info.parent.status_mask = 1ull<<20 /* pip */;
2472 info.func = __cvmx_error_display;
2473 info.user_info = (long)
2474 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
2475 fail |= cvmx_error_add(&info);
2477 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2478 info.status_addr = CVMX_PIP_INT_REG;
2479 info.status_mask = 1ull<<4 /* badtag */;
2480 info.enable_addr = CVMX_PIP_INT_EN;
2481 info.enable_mask = 1ull<<4 /* badtag */;
2483 info.group = CVMX_ERROR_GROUP_INTERNAL;
2484 info.group_index = 0;
2485 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2486 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2487 info.parent.status_mask = 1ull<<20 /* pip */;
2488 info.func = __cvmx_error_display;
2489 info.user_info = (long)
2490 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
2491 fail |= cvmx_error_add(&info);
2493 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2494 info.status_addr = CVMX_PIP_INT_REG;
2495 info.status_mask = 1ull<<5 /* skprunt */;
2496 info.enable_addr = CVMX_PIP_INT_EN;
2497 info.enable_mask = 1ull<<5 /* skprunt */;
2499 info.group = CVMX_ERROR_GROUP_INTERNAL;
2500 info.group_index = 0;
2501 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2502 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2503 info.parent.status_mask = 1ull<<20 /* pip */;
2504 info.func = __cvmx_error_display;
2505 info.user_info = (long)
2506 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
2507 " This interrupt can occur with received PARTIAL\n"
2508 " packets that are truncated to SKIP bytes or\n"
2510 fail |= cvmx_error_add(&info);
2512 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2513 info.status_addr = CVMX_PIP_INT_REG;
2514 info.status_mask = 1ull<<6 /* todoovr */;
2515 info.enable_addr = CVMX_PIP_INT_EN;
2516 info.enable_mask = 1ull<<6 /* todoovr */;
2518 info.group = CVMX_ERROR_GROUP_INTERNAL;
2519 info.group_index = 0;
2520 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2521 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2522 info.parent.status_mask = 1ull<<20 /* pip */;
2523 info.func = __cvmx_error_display;
2524 info.user_info = (long)
2525 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
2526 fail |= cvmx_error_add(&info);
2528 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2529 info.status_addr = CVMX_PIP_INT_REG;
2530 info.status_mask = 1ull<<7 /* feperr */;
2531 info.enable_addr = CVMX_PIP_INT_EN;
2532 info.enable_mask = 1ull<<7 /* feperr */;
2534 info.group = CVMX_ERROR_GROUP_INTERNAL;
2535 info.group_index = 0;
2536 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2537 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2538 info.parent.status_mask = 1ull<<20 /* pip */;
2539 info.func = __cvmx_error_display;
2540 info.user_info = (long)
2541 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
2542 fail |= cvmx_error_add(&info);
2544 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2545 info.status_addr = CVMX_PIP_INT_REG;
2546 info.status_mask = 1ull<<8 /* beperr */;
2547 info.enable_addr = CVMX_PIP_INT_EN;
2548 info.enable_mask = 1ull<<8 /* beperr */;
2550 info.group = CVMX_ERROR_GROUP_INTERNAL;
2551 info.group_index = 0;
2552 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2553 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2554 info.parent.status_mask = 1ull<<20 /* pip */;
2555 info.func = __cvmx_error_display;
2556 info.user_info = (long)
2557 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
2558 fail |= cvmx_error_add(&info);
2560 /* CVMX_GMXX_BAD_REG(0) */
2561 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2562 info.status_addr = CVMX_GMXX_BAD_REG(0);
2563 info.status_mask = 0x7ull<<2 /* out_ovr */;
2564 info.enable_addr = 0;
2565 info.enable_mask = 0;
2567 info.group = CVMX_ERROR_GROUP_ETHERNET;
2568 info.group_index = 0;
2569 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2570 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2571 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2572 info.func = __cvmx_error_display;
2573 info.user_info = (long)
2574 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
2575 fail |= cvmx_error_add(&info);
2577 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2578 info.status_addr = CVMX_GMXX_BAD_REG(0);
2579 info.status_mask = 0x7ull<<22 /* loststat */;
2580 info.enable_addr = 0;
2581 info.enable_mask = 0;
2583 info.group = CVMX_ERROR_GROUP_ETHERNET;
2584 info.group_index = 0;
2585 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2586 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2587 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2588 info.func = __cvmx_error_display;
2589 info.user_info = (long)
2590 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
2591 " TX Stats are corrupted\n";
2592 fail |= cvmx_error_add(&info);
2594 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2595 info.status_addr = CVMX_GMXX_BAD_REG(0);
2596 info.status_mask = 1ull<<26 /* statovr */;
2597 info.enable_addr = 0;
2598 info.enable_mask = 0;
2600 info.group = CVMX_ERROR_GROUP_ETHERNET;
2601 info.group_index = 0;
2602 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2603 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2604 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2605 info.func = __cvmx_error_display;
2606 info.user_info = (long)
2607 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
2608 fail |= cvmx_error_add(&info);
2610 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2611 info.status_addr = CVMX_GMXX_BAD_REG(0);
2612 info.status_mask = 0xfull<<27 /* inb_nxa */;
2613 info.enable_addr = 0;
2614 info.enable_mask = 0;
2616 info.group = CVMX_ERROR_GROUP_ETHERNET;
2617 info.group_index = 0;
2618 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2619 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2620 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2621 info.func = __cvmx_error_display;
2622 info.user_info = (long)
2623 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
2624 fail |= cvmx_error_add(&info);
2626 /* CVMX_GMXX_RXX_INT_REG(0,0) */
2627 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2628 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
2629 info.status_mask = 1ull<<1 /* carext */;
2630 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
2631 info.enable_mask = 1ull<<1 /* carext */;
2633 info.group = CVMX_ERROR_GROUP_ETHERNET;
2634 info.group_index = 0;
2635 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2636 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2637 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2638 info.func = __cvmx_error_display;
2639 info.user_info = (long)
2640 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
2641 fail |= cvmx_error_add(&info);
2643 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2644 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
2645 info.status_mask = 1ull<<5 /* alnerr */;
2646 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
2647 info.enable_mask = 1ull<<5 /* alnerr */;
2649 info.group = CVMX_ERROR_GROUP_ETHERNET;
2650 info.group_index = 0;
2651 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2652 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2653 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2654 info.func = __cvmx_error_display;
2655 info.user_info = (long)
2656 "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
2657 fail |= cvmx_error_add(&info);
2659 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2660 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
2661 info.status_mask = 1ull<<8 /* skperr */;
2662 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
2663 info.enable_mask = 1ull<<8 /* skperr */;
2665 info.group = CVMX_ERROR_GROUP_ETHERNET;
2666 info.group_index = 0;
2667 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2668 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2669 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2670 info.func = __cvmx_error_display;
2671 info.user_info = (long)
2672 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
2673 fail |= cvmx_error_add(&info);
2675 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2676 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
2677 info.status_mask = 1ull<<9 /* niberr */;
2678 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
2679 info.enable_mask = 1ull<<9 /* niberr */;
2681 info.group = CVMX_ERROR_GROUP_ETHERNET;
2682 info.group_index = 0;
2683 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2684 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2685 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2686 info.func = __cvmx_error_display;
2687 info.user_info = (long)
2688 "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2689 fail |= cvmx_error_add(&info);
2691 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2692 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
2693 info.status_mask = 1ull<<10 /* ovrerr */;
2694 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
2695 info.enable_mask = 1ull<<10 /* ovrerr */;
2697 info.group = CVMX_ERROR_GROUP_ETHERNET;
2698 info.group_index = 0;
2699 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2700 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2701 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2702 info.func = __cvmx_error_display;
2703 info.user_info = (long)
2704 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2705 " This interrupt should never assert\n";
2706 fail |= cvmx_error_add(&info);
2708 /* CVMX_GMXX_RXX_INT_REG(1,0) */
2709 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2710 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
2711 info.status_mask = 1ull<<1 /* carext */;
2712 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
2713 info.enable_mask = 1ull<<1 /* carext */;
2715 info.group = CVMX_ERROR_GROUP_ETHERNET;
2716 info.group_index = 1;
2717 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2718 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2719 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2720 info.func = __cvmx_error_display;
2721 info.user_info = (long)
2722 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
2723 fail |= cvmx_error_add(&info);
2725 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2726 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
2727 info.status_mask = 1ull<<5 /* alnerr */;
2728 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
2729 info.enable_mask = 1ull<<5 /* alnerr */;
2731 info.group = CVMX_ERROR_GROUP_ETHERNET;
2732 info.group_index = 1;
2733 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2734 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2735 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2736 info.func = __cvmx_error_display;
2737 info.user_info = (long)
2738 "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
2739 fail |= cvmx_error_add(&info);
2741 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2742 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
2743 info.status_mask = 1ull<<8 /* skperr */;
2744 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
2745 info.enable_mask = 1ull<<8 /* skperr */;
2747 info.group = CVMX_ERROR_GROUP_ETHERNET;
2748 info.group_index = 1;
2749 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2750 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2751 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2752 info.func = __cvmx_error_display;
2753 info.user_info = (long)
2754 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
2755 fail |= cvmx_error_add(&info);
2757 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2758 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
2759 info.status_mask = 1ull<<9 /* niberr */;
2760 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
2761 info.enable_mask = 1ull<<9 /* niberr */;
2763 info.group = CVMX_ERROR_GROUP_ETHERNET;
2764 info.group_index = 1;
2765 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2766 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2767 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2768 info.func = __cvmx_error_display;
2769 info.user_info = (long)
2770 "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2771 fail |= cvmx_error_add(&info);
2773 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2774 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
2775 info.status_mask = 1ull<<10 /* ovrerr */;
2776 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
2777 info.enable_mask = 1ull<<10 /* ovrerr */;
2779 info.group = CVMX_ERROR_GROUP_ETHERNET;
2780 info.group_index = 1;
2781 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2782 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2783 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2784 info.func = __cvmx_error_display;
2785 info.user_info = (long)
2786 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2787 " This interrupt should never assert\n";
2788 fail |= cvmx_error_add(&info);
2790 /* CVMX_GMXX_RXX_INT_REG(2,0) */
2791 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2792 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
2793 info.status_mask = 1ull<<1 /* carext */;
2794 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
2795 info.enable_mask = 1ull<<1 /* carext */;
2797 info.group = CVMX_ERROR_GROUP_ETHERNET;
2798 info.group_index = 2;
2799 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2800 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2801 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2802 info.func = __cvmx_error_display;
2803 info.user_info = (long)
2804 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
2805 fail |= cvmx_error_add(&info);
2807 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2808 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
2809 info.status_mask = 1ull<<5 /* alnerr */;
2810 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
2811 info.enable_mask = 1ull<<5 /* alnerr */;
2813 info.group = CVMX_ERROR_GROUP_ETHERNET;
2814 info.group_index = 2;
2815 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2816 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2817 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2818 info.func = __cvmx_error_display;
2819 info.user_info = (long)
2820 "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
2821 fail |= cvmx_error_add(&info);
2823 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2824 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
2825 info.status_mask = 1ull<<8 /* skperr */;
2826 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
2827 info.enable_mask = 1ull<<8 /* skperr */;
2829 info.group = CVMX_ERROR_GROUP_ETHERNET;
2830 info.group_index = 2;
2831 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2832 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2833 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2834 info.func = __cvmx_error_display;
2835 info.user_info = (long)
2836 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
2837 fail |= cvmx_error_add(&info);
2839 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2840 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
2841 info.status_mask = 1ull<<9 /* niberr */;
2842 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
2843 info.enable_mask = 1ull<<9 /* niberr */;
2845 info.group = CVMX_ERROR_GROUP_ETHERNET;
2846 info.group_index = 2;
2847 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2848 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2849 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2850 info.func = __cvmx_error_display;
2851 info.user_info = (long)
2852 "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
2853 fail |= cvmx_error_add(&info);
2855 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2856 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
2857 info.status_mask = 1ull<<10 /* ovrerr */;
2858 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
2859 info.enable_mask = 1ull<<10 /* ovrerr */;
2861 info.group = CVMX_ERROR_GROUP_ETHERNET;
2862 info.group_index = 2;
2863 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2864 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2865 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2866 info.func = __cvmx_error_display;
2867 info.user_info = (long)
2868 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
2869 " This interrupt should never assert\n";
2870 fail |= cvmx_error_add(&info);
2872 /* CVMX_GMXX_TX_INT_REG(0) */
2873 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2874 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
2875 info.status_mask = 1ull<<0 /* pko_nxa */;
2876 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
2877 info.enable_mask = 1ull<<0 /* pko_nxa */;
2879 info.group = CVMX_ERROR_GROUP_ETHERNET;
2880 info.group_index = 0;
2881 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2882 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2883 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2884 info.func = __cvmx_error_display;
2885 info.user_info = (long)
2886 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
2887 fail |= cvmx_error_add(&info);
2889 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2890 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
2891 info.status_mask = 0x7ull<<2 /* undflw */;
2892 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
2893 info.enable_mask = 0x7ull<<2 /* undflw */;
2895 info.group = CVMX_ERROR_GROUP_ETHERNET;
2896 info.group_index = 0;
2897 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2898 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2899 info.parent.status_mask = 1ull<<1 /* gmx0 */;
2900 info.func = __cvmx_error_display;
2901 info.user_info = (long)
2902 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
2903 fail |= cvmx_error_add(&info);
2905 /* CVMX_LMCX_MEM_CFG0(0) */
2906 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2907 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
2908 info.status_mask = 0xfull<<21 /* sec_err */;
2909 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
2910 info.enable_mask = 1ull<<19 /* intr_sec_ena */;
2911 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
2912 info.group = CVMX_ERROR_GROUP_LMC;
2913 info.group_index = 0;
2914 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2915 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2916 info.parent.status_mask = 1ull<<17 /* lmc */;
2917 info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
2918 info.user_info = (long)
2919 "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
2920 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2921 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2922 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2923 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2924 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2925 " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
2926 " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
2927 " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
2928 " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
2929 " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
2930 " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
2931 " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
2932 " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
2933 " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
2934 " where _cC_pP denotes cycle C and phase P\n"
2935 " Write of 1 will clear the corresponding error bit\n";
2936 fail |= cvmx_error_add(&info);
2938 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2939 info.status_addr = CVMX_LMCX_MEM_CFG0(0);
2940 info.status_mask = 0xfull<<25 /* ded_err */;
2941 info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
2942 info.enable_mask = 1ull<<20 /* intr_ded_ena */;
2944 info.group = CVMX_ERROR_GROUP_LMC;
2945 info.group_index = 0;
2946 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2947 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2948 info.parent.status_mask = 1ull<<17 /* lmc */;
2949 info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
2950 info.user_info = (long)
2951 "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
2952 " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
2953 " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
2954 " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
2955 " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
2956 " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
2957 " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
2958 " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
2959 " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
2960 " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
2961 " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
2962 " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
2963 " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
2964 " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
2965 " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
2966 " where _cC_pP denotes cycle C and phase P\n"
2967 " Write of 1 will clear the corresponding error bit\n";
2968 fail |= cvmx_error_add(&info);
2970 /* CVMX_IOB_INT_SUM */
2971 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2972 info.status_addr = CVMX_IOB_INT_SUM;
2973 info.status_mask = 1ull<<0 /* np_sop */;
2974 info.enable_addr = CVMX_IOB_INT_ENB;
2975 info.enable_mask = 1ull<<0 /* np_sop */;
2977 info.group = CVMX_ERROR_GROUP_INTERNAL;
2978 info.group_index = 0;
2979 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2980 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
2981 info.parent.status_mask = 1ull<<30 /* iob */;
2982 info.func = __cvmx_error_display;
2983 info.user_info = (long)
2984 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
2985 " port for a non-passthrough packet.\n"
2986 " The first detected error associated with bits [3:0]\n"
2987 " of this register will only be set here. A new bit\n"
2988 " can be set when the previous reported bit is cleared.\n";
2989 fail |= cvmx_error_add(&info);
2991 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2992 info.status_addr = CVMX_IOB_INT_SUM;
2993 info.status_mask = 1ull<<1 /* np_eop */;
2994 info.enable_addr = CVMX_IOB_INT_ENB;
2995 info.enable_mask = 1ull<<1 /* np_eop */;
2997 info.group = CVMX_ERROR_GROUP_INTERNAL;
2998 info.group_index = 0;
2999 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3000 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3001 info.parent.status_mask = 1ull<<30 /* iob */;
3002 info.func = __cvmx_error_display;
3003 info.user_info = (long)
3004 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
3005 " port for a non-passthrough packet.\n"
3006 " The first detected error associated with bits [3:0]\n"
3007 " of this register will only be set here. A new bit\n"
3008 " can be set when the previous reported bit is cleared.\n";
3009 fail |= cvmx_error_add(&info);
3011 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3012 info.status_addr = CVMX_IOB_INT_SUM;
3013 info.status_mask = 1ull<<2 /* p_sop */;
3014 info.enable_addr = CVMX_IOB_INT_ENB;
3015 info.enable_mask = 1ull<<2 /* p_sop */;
3017 info.group = CVMX_ERROR_GROUP_INTERNAL;
3018 info.group_index = 0;
3019 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3020 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3021 info.parent.status_mask = 1ull<<30 /* iob */;
3022 info.func = __cvmx_error_display;
3023 info.user_info = (long)
3024 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
3025 " port for a passthrough packet.\n"
3026 " The first detected error associated with bits [3:0]\n"
3027 " of this register will only be set here. A new bit\n"
3028 " can be set when the previous reported bit is cleared.\n";
3029 fail |= cvmx_error_add(&info);
3031 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3032 info.status_addr = CVMX_IOB_INT_SUM;
3033 info.status_mask = 1ull<<3 /* p_eop */;
3034 info.enable_addr = CVMX_IOB_INT_ENB;
3035 info.enable_mask = 1ull<<3 /* p_eop */;
3037 info.group = CVMX_ERROR_GROUP_INTERNAL;
3038 info.group_index = 0;
3039 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3040 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3041 info.parent.status_mask = 1ull<<30 /* iob */;
3042 info.func = __cvmx_error_display;
3043 info.user_info = (long)
3044 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
3045 " port for a passthrough packet.\n"
3046 " The first detected error associated with bits [3:0]\n"
3047 " of this register will only be set here. A new bit\n"
3048 " can be set when the previous reported bit is cleared.\n";
3049 fail |= cvmx_error_add(&info);
3051 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3052 info.status_addr = CVMX_IOB_INT_SUM;
3053 info.status_mask = 1ull<<4 /* np_dat */;
3054 info.enable_addr = CVMX_IOB_INT_ENB;
3055 info.enable_mask = 1ull<<4 /* np_dat */;
3057 info.group = CVMX_ERROR_GROUP_INTERNAL;
3058 info.group_index = 0;
3059 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3060 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3061 info.parent.status_mask = 1ull<<30 /* iob */;
3062 info.func = __cvmx_error_display;
3063 info.user_info = (long)
3064 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
3065 " port for a non-passthrough packet.\n"
3066 " The first detected error associated with bits [5:0]\n"
3067 " of this register will only be set here. A new bit\n"
3068 " can be set when the previous reported bit is cleared.\n";
3069 fail |= cvmx_error_add(&info);
3071 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3072 info.status_addr = CVMX_IOB_INT_SUM;
3073 info.status_mask = 1ull<<5 /* p_dat */;
3074 info.enable_addr = CVMX_IOB_INT_ENB;
3075 info.enable_mask = 1ull<<5 /* p_dat */;
3077 info.group = CVMX_ERROR_GROUP_INTERNAL;
3078 info.group_index = 0;
3079 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3080 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3081 info.parent.status_mask = 1ull<<30 /* iob */;
3082 info.func = __cvmx_error_display;
3083 info.user_info = (long)
3084 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
3085 " port for a passthrough packet.\n"
3086 " The first detected error associated with bits [5:0]\n"
3087 " of this register will only be set here. A new bit\n"
3088 " can be set when the previous reported bit is cleared.\n";
3089 fail |= cvmx_error_add(&info);
3091 /* CVMX_USBNX_INT_SUM(0) */
3092 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3093 info.status_addr = CVMX_USBNX_INT_SUM(0);
3094 info.status_mask = 1ull<<0 /* pr_po_e */;
3095 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3096 info.enable_mask = 1ull<<0 /* pr_po_e */;
3098 info.group = CVMX_ERROR_GROUP_USB;
3099 info.group_index = 0;
3100 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3101 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3102 info.parent.status_mask = 1ull<<13 /* usb */;
3103 info.func = __cvmx_error_display;
3104 info.user_info = (long)
3105 "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
3106 fail |= cvmx_error_add(&info);
3108 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3109 info.status_addr = CVMX_USBNX_INT_SUM(0);
3110 info.status_mask = 1ull<<1 /* pr_pu_f */;
3111 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3112 info.enable_mask = 1ull<<1 /* pr_pu_f */;
3114 info.group = CVMX_ERROR_GROUP_USB;
3115 info.group_index = 0;
3116 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3117 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3118 info.parent.status_mask = 1ull<<13 /* usb */;
3119 info.func = __cvmx_error_display;
3120 info.user_info = (long)
3121 "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
3122 fail |= cvmx_error_add(&info);
3124 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3125 info.status_addr = CVMX_USBNX_INT_SUM(0);
3126 info.status_mask = 1ull<<2 /* nr_po_e */;
3127 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3128 info.enable_mask = 1ull<<2 /* nr_po_e */;
3130 info.group = CVMX_ERROR_GROUP_USB;
3131 info.group_index = 0;
3132 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3133 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3134 info.parent.status_mask = 1ull<<13 /* usb */;
3135 info.func = __cvmx_error_display;
3136 info.user_info = (long)
3137 "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
3138 fail |= cvmx_error_add(&info);
3140 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3141 info.status_addr = CVMX_USBNX_INT_SUM(0);
3142 info.status_mask = 1ull<<3 /* nr_pu_f */;
3143 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3144 info.enable_mask = 1ull<<3 /* nr_pu_f */;
3146 info.group = CVMX_ERROR_GROUP_USB;
3147 info.group_index = 0;
3148 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3149 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3150 info.parent.status_mask = 1ull<<13 /* usb */;
3151 info.func = __cvmx_error_display;
3152 info.user_info = (long)
3153 "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
3154 fail |= cvmx_error_add(&info);
3156 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3157 info.status_addr = CVMX_USBNX_INT_SUM(0);
3158 info.status_mask = 1ull<<4 /* lr_po_e */;
3159 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3160 info.enable_mask = 1ull<<4 /* lr_po_e */;
3162 info.group = CVMX_ERROR_GROUP_USB;
3163 info.group_index = 0;
3164 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3165 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3166 info.parent.status_mask = 1ull<<13 /* usb */;
3167 info.func = __cvmx_error_display;
3168 info.user_info = (long)
3169 "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
3170 fail |= cvmx_error_add(&info);
3172 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3173 info.status_addr = CVMX_USBNX_INT_SUM(0);
3174 info.status_mask = 1ull<<5 /* lr_pu_f */;
3175 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3176 info.enable_mask = 1ull<<5 /* lr_pu_f */;
3178 info.group = CVMX_ERROR_GROUP_USB;
3179 info.group_index = 0;
3180 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3181 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3182 info.parent.status_mask = 1ull<<13 /* usb */;
3183 info.func = __cvmx_error_display;
3184 info.user_info = (long)
3185 "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
3186 fail |= cvmx_error_add(&info);
3188 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3189 info.status_addr = CVMX_USBNX_INT_SUM(0);
3190 info.status_mask = 1ull<<6 /* pt_po_e */;
3191 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3192 info.enable_mask = 1ull<<6 /* pt_po_e */;
3194 info.group = CVMX_ERROR_GROUP_USB;
3195 info.group_index = 0;
3196 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3197 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3198 info.parent.status_mask = 1ull<<13 /* usb */;
3199 info.func = __cvmx_error_display;
3200 info.user_info = (long)
3201 "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
3202 fail |= cvmx_error_add(&info);
3204 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3205 info.status_addr = CVMX_USBNX_INT_SUM(0);
3206 info.status_mask = 1ull<<7 /* pt_pu_f */;
3207 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3208 info.enable_mask = 1ull<<7 /* pt_pu_f */;
3210 info.group = CVMX_ERROR_GROUP_USB;
3211 info.group_index = 0;
3212 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3213 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3214 info.parent.status_mask = 1ull<<13 /* usb */;
3215 info.func = __cvmx_error_display;
3216 info.user_info = (long)
3217 "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
3218 fail |= cvmx_error_add(&info);
3220 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3221 info.status_addr = CVMX_USBNX_INT_SUM(0);
3222 info.status_mask = 1ull<<8 /* nt_po_e */;
3223 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3224 info.enable_mask = 1ull<<8 /* nt_po_e */;
3226 info.group = CVMX_ERROR_GROUP_USB;
3227 info.group_index = 0;
3228 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3229 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3230 info.parent.status_mask = 1ull<<13 /* usb */;
3231 info.func = __cvmx_error_display;
3232 info.user_info = (long)
3233 "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
3234 fail |= cvmx_error_add(&info);
3236 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3237 info.status_addr = CVMX_USBNX_INT_SUM(0);
3238 info.status_mask = 1ull<<9 /* nt_pu_f */;
3239 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3240 info.enable_mask = 1ull<<9 /* nt_pu_f */;
3242 info.group = CVMX_ERROR_GROUP_USB;
3243 info.group_index = 0;
3244 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3245 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3246 info.parent.status_mask = 1ull<<13 /* usb */;
3247 info.func = __cvmx_error_display;
3248 info.user_info = (long)
3249 "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
3250 fail |= cvmx_error_add(&info);
3252 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3253 info.status_addr = CVMX_USBNX_INT_SUM(0);
3254 info.status_mask = 1ull<<10 /* lt_po_e */;
3255 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3256 info.enable_mask = 1ull<<10 /* lt_po_e */;
3258 info.group = CVMX_ERROR_GROUP_USB;
3259 info.group_index = 0;
3260 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3261 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3262 info.parent.status_mask = 1ull<<13 /* usb */;
3263 info.func = __cvmx_error_display;
3264 info.user_info = (long)
3265 "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
3266 fail |= cvmx_error_add(&info);
3268 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3269 info.status_addr = CVMX_USBNX_INT_SUM(0);
3270 info.status_mask = 1ull<<11 /* lt_pu_f */;
3271 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3272 info.enable_mask = 1ull<<11 /* lt_pu_f */;
3274 info.group = CVMX_ERROR_GROUP_USB;
3275 info.group_index = 0;
3276 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3277 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3278 info.parent.status_mask = 1ull<<13 /* usb */;
3279 info.func = __cvmx_error_display;
3280 info.user_info = (long)
3281 "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
3282 fail |= cvmx_error_add(&info);
3284 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3285 info.status_addr = CVMX_USBNX_INT_SUM(0);
3286 info.status_mask = 1ull<<12 /* dcred_e */;
3287 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3288 info.enable_mask = 1ull<<12 /* dcred_e */;
3290 info.group = CVMX_ERROR_GROUP_USB;
3291 info.group_index = 0;
3292 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3293 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3294 info.parent.status_mask = 1ull<<13 /* usb */;
3295 info.func = __cvmx_error_display;
3296 info.user_info = (long)
3297 "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
3298 fail |= cvmx_error_add(&info);
3300 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3301 info.status_addr = CVMX_USBNX_INT_SUM(0);
3302 info.status_mask = 1ull<<13 /* dcred_f */;
3303 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3304 info.enable_mask = 1ull<<13 /* dcred_f */;
3306 info.group = CVMX_ERROR_GROUP_USB;
3307 info.group_index = 0;
3308 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3309 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3310 info.parent.status_mask = 1ull<<13 /* usb */;
3311 info.func = __cvmx_error_display;
3312 info.user_info = (long)
3313 "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
3314 fail |= cvmx_error_add(&info);
3316 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3317 info.status_addr = CVMX_USBNX_INT_SUM(0);
3318 info.status_mask = 1ull<<14 /* l2c_s_e */;
3319 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3320 info.enable_mask = 1ull<<14 /* l2c_s_e */;
3322 info.group = CVMX_ERROR_GROUP_USB;
3323 info.group_index = 0;
3324 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3325 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3326 info.parent.status_mask = 1ull<<13 /* usb */;
3327 info.func = __cvmx_error_display;
3328 info.user_info = (long)
3329 "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
3330 fail |= cvmx_error_add(&info);
3332 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3333 info.status_addr = CVMX_USBNX_INT_SUM(0);
3334 info.status_mask = 1ull<<15 /* l2c_a_f */;
3335 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3336 info.enable_mask = 1ull<<15 /* l2c_a_f */;
3338 info.group = CVMX_ERROR_GROUP_USB;
3339 info.group_index = 0;
3340 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3341 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3342 info.parent.status_mask = 1ull<<13 /* usb */;
3343 info.func = __cvmx_error_display;
3344 info.user_info = (long)
3345 "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
3346 fail |= cvmx_error_add(&info);
3348 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3349 info.status_addr = CVMX_USBNX_INT_SUM(0);
3350 info.status_mask = 1ull<<16 /* lt_fi_e */;
3351 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3352 info.enable_mask = 1ull<<16 /* l2_fi_e */;
3354 info.group = CVMX_ERROR_GROUP_USB;
3355 info.group_index = 0;
3356 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3357 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3358 info.parent.status_mask = 1ull<<13 /* usb */;
3359 info.func = __cvmx_error_display;
3360 info.user_info = (long)
3361 "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
3362 fail |= cvmx_error_add(&info);
3364 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3365 info.status_addr = CVMX_USBNX_INT_SUM(0);
3366 info.status_mask = 1ull<<17 /* lt_fi_f */;
3367 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3368 info.enable_mask = 1ull<<17 /* l2_fi_f */;
3370 info.group = CVMX_ERROR_GROUP_USB;
3371 info.group_index = 0;
3372 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3373 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3374 info.parent.status_mask = 1ull<<13 /* usb */;
3375 info.func = __cvmx_error_display;
3376 info.user_info = (long)
3377 "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
3378 fail |= cvmx_error_add(&info);
3380 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3381 info.status_addr = CVMX_USBNX_INT_SUM(0);
3382 info.status_mask = 1ull<<18 /* rg_fi_e */;
3383 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3384 info.enable_mask = 1ull<<18 /* rg_fi_e */;
3386 info.group = CVMX_ERROR_GROUP_USB;
3387 info.group_index = 0;
3388 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3389 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3390 info.parent.status_mask = 1ull<<13 /* usb */;
3391 info.func = __cvmx_error_display;
3392 info.user_info = (long)
3393 "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
3394 fail |= cvmx_error_add(&info);
3396 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3397 info.status_addr = CVMX_USBNX_INT_SUM(0);
3398 info.status_mask = 1ull<<19 /* rg_fi_f */;
3399 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3400 info.enable_mask = 1ull<<19 /* rg_fi_f */;
3402 info.group = CVMX_ERROR_GROUP_USB;
3403 info.group_index = 0;
3404 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3405 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3406 info.parent.status_mask = 1ull<<13 /* usb */;
3407 info.func = __cvmx_error_display;
3408 info.user_info = (long)
3409 "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
3410 fail |= cvmx_error_add(&info);
3412 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3413 info.status_addr = CVMX_USBNX_INT_SUM(0);
3414 info.status_mask = 1ull<<20 /* rq_q2_f */;
3415 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3416 info.enable_mask = 1ull<<20 /* rq_q2_f */;
3418 info.group = CVMX_ERROR_GROUP_USB;
3419 info.group_index = 0;
3420 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3421 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3422 info.parent.status_mask = 1ull<<13 /* usb */;
3423 info.func = __cvmx_error_display;
3424 info.user_info = (long)
3425 "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
3426 fail |= cvmx_error_add(&info);
3428 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3429 info.status_addr = CVMX_USBNX_INT_SUM(0);
3430 info.status_mask = 1ull<<21 /* rq_q2_e */;
3431 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3432 info.enable_mask = 1ull<<21 /* rq_q2_e */;
3434 info.group = CVMX_ERROR_GROUP_USB;
3435 info.group_index = 0;
3436 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3437 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3438 info.parent.status_mask = 1ull<<13 /* usb */;
3439 info.func = __cvmx_error_display;
3440 info.user_info = (long)
3441 "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
3442 fail |= cvmx_error_add(&info);
3444 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3445 info.status_addr = CVMX_USBNX_INT_SUM(0);
3446 info.status_mask = 1ull<<22 /* rq_q3_f */;
3447 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3448 info.enable_mask = 1ull<<22 /* rq_q3_f */;
3450 info.group = CVMX_ERROR_GROUP_USB;
3451 info.group_index = 0;
3452 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3453 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3454 info.parent.status_mask = 1ull<<13 /* usb */;
3455 info.func = __cvmx_error_display;
3456 info.user_info = (long)
3457 "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
3458 fail |= cvmx_error_add(&info);
3460 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3461 info.status_addr = CVMX_USBNX_INT_SUM(0);
3462 info.status_mask = 1ull<<23 /* rq_q3_e */;
3463 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3464 info.enable_mask = 1ull<<23 /* rq_q3_e */;
3466 info.group = CVMX_ERROR_GROUP_USB;
3467 info.group_index = 0;
3468 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3469 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3470 info.parent.status_mask = 1ull<<13 /* usb */;
3471 info.func = __cvmx_error_display;
3472 info.user_info = (long)
3473 "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
3474 fail |= cvmx_error_add(&info);
3476 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3477 info.status_addr = CVMX_USBNX_INT_SUM(0);
3478 info.status_mask = 1ull<<24 /* uod_pe */;
3479 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3480 info.enable_mask = 1ull<<24 /* uod_pe */;
3482 info.group = CVMX_ERROR_GROUP_USB;
3483 info.group_index = 0;
3484 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3485 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3486 info.parent.status_mask = 1ull<<13 /* usb */;
3487 info.func = __cvmx_error_display;
3488 info.user_info = (long)
3489 "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
3490 fail |= cvmx_error_add(&info);
3492 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3493 info.status_addr = CVMX_USBNX_INT_SUM(0);
3494 info.status_mask = 1ull<<25 /* uod_pf */;
3495 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3496 info.enable_mask = 1ull<<25 /* uod_pf */;
3498 info.group = CVMX_ERROR_GROUP_USB;
3499 info.group_index = 0;
3500 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3501 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3502 info.parent.status_mask = 1ull<<13 /* usb */;
3503 info.func = __cvmx_error_display;
3504 info.user_info = (long)
3505 "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
3506 fail |= cvmx_error_add(&info);
3508 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3509 info.status_addr = CVMX_USBNX_INT_SUM(0);
3510 info.status_mask = 1ull<<32 /* ltl_f_pe */;
3511 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3512 info.enable_mask = 1ull<<32 /* ltl_f_pe */;
3514 info.group = CVMX_ERROR_GROUP_USB;
3515 info.group_index = 0;
3516 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3517 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3518 info.parent.status_mask = 1ull<<13 /* usb */;
3519 info.func = __cvmx_error_display;
3520 info.user_info = (long)
3521 "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
3522 fail |= cvmx_error_add(&info);
3524 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3525 info.status_addr = CVMX_USBNX_INT_SUM(0);
3526 info.status_mask = 1ull<<33 /* ltl_f_pf */;
3527 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3528 info.enable_mask = 1ull<<33 /* ltl_f_pf */;
3530 info.group = CVMX_ERROR_GROUP_USB;
3531 info.group_index = 0;
3532 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3533 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3534 info.parent.status_mask = 1ull<<13 /* usb */;
3535 info.func = __cvmx_error_display;
3536 info.user_info = (long)
3537 "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
3538 fail |= cvmx_error_add(&info);
3540 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3541 info.status_addr = CVMX_USBNX_INT_SUM(0);
3542 info.status_mask = 1ull<<34 /* nd4o_rpe */;
3543 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3544 info.enable_mask = 1ull<<34 /* nd4o_rpe */;
3546 info.group = CVMX_ERROR_GROUP_USB;
3547 info.group_index = 0;
3548 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3549 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3550 info.parent.status_mask = 1ull<<13 /* usb */;
3551 info.func = __cvmx_error_display;
3552 info.user_info = (long)
3553 "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
3554 fail |= cvmx_error_add(&info);
3556 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3557 info.status_addr = CVMX_USBNX_INT_SUM(0);
3558 info.status_mask = 1ull<<35 /* nd4o_rpf */;
3559 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3560 info.enable_mask = 1ull<<35 /* nd4o_rpf */;
3562 info.group = CVMX_ERROR_GROUP_USB;
3563 info.group_index = 0;
3564 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3565 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3566 info.parent.status_mask = 1ull<<13 /* usb */;
3567 info.func = __cvmx_error_display;
3568 info.user_info = (long)
3569 "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
3570 fail |= cvmx_error_add(&info);
3572 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3573 info.status_addr = CVMX_USBNX_INT_SUM(0);
3574 info.status_mask = 1ull<<36 /* nd4o_dpe */;
3575 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3576 info.enable_mask = 1ull<<36 /* nd4o_dpe */;
3578 info.group = CVMX_ERROR_GROUP_USB;
3579 info.group_index = 0;
3580 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3581 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3582 info.parent.status_mask = 1ull<<13 /* usb */;
3583 info.func = __cvmx_error_display;
3584 info.user_info = (long)
3585 "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
3586 fail |= cvmx_error_add(&info);
3588 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3589 info.status_addr = CVMX_USBNX_INT_SUM(0);
3590 info.status_mask = 1ull<<37 /* nd4o_dpf */;
3591 info.enable_addr = CVMX_USBNX_INT_ENB(0);
3592 info.enable_mask = 1ull<<37 /* nd4o_dpf */;
3594 info.group = CVMX_ERROR_GROUP_USB;
3595 info.group_index = 0;
3596 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3597 info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
3598 info.parent.status_mask = 1ull<<13 /* usb */;
3599 info.func = __cvmx_error_display;
3600 info.user_info = (long)
3601 "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
3602 fail |= cvmx_error_add(&info);