1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_KEY_TYPEDEFS_H__
53 #define __CVMX_KEY_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
57 static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
60 cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180020000018ull);
64 #define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
68 static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
71 cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180020000010ull);
75 #define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
79 static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
82 cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180020000008ull);
86 #define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
90 static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
93 cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180020000000ull);
97 #define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
103 * KEY_BIST_REG = KEY's BIST Status Register
105 * The KEY's BIST status for memories.
107 union cvmx_key_bist_reg
110 struct cvmx_key_bist_reg_s
112 #if __BYTE_ORDER == __BIG_ENDIAN
113 uint64_t reserved_3_63 : 61;
114 uint64_t rrc : 1; /**< RRC bist status. */
115 uint64_t mem1 : 1; /**< MEM - 1 bist status. */
116 uint64_t mem0 : 1; /**< MEM - 0 bist status. */
121 uint64_t reserved_3_63 : 61;
124 struct cvmx_key_bist_reg_s cn38xx;
125 struct cvmx_key_bist_reg_s cn38xxp2;
126 struct cvmx_key_bist_reg_s cn56xx;
127 struct cvmx_key_bist_reg_s cn56xxp1;
128 struct cvmx_key_bist_reg_s cn58xx;
129 struct cvmx_key_bist_reg_s cn58xxp1;
130 struct cvmx_key_bist_reg_s cn63xx;
131 struct cvmx_key_bist_reg_s cn63xxp1;
133 typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
136 * cvmx_key_ctl_status
138 * KEY_CTL_STATUS = KEY's Control/Status Register
140 * The KEY's interrupt enable register.
142 union cvmx_key_ctl_status
145 struct cvmx_key_ctl_status_s
147 #if __BYTE_ORDER == __BIG_ENDIAN
148 uint64_t reserved_14_63 : 50;
149 uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32
150 respective to bit 13:7 of this field, for FPF
152 uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32
153 respective to bit 6:0 of this field, for FPF
156 uint64_t mem0_err : 7;
157 uint64_t mem1_err : 7;
158 uint64_t reserved_14_63 : 50;
161 struct cvmx_key_ctl_status_s cn38xx;
162 struct cvmx_key_ctl_status_s cn38xxp2;
163 struct cvmx_key_ctl_status_s cn56xx;
164 struct cvmx_key_ctl_status_s cn56xxp1;
165 struct cvmx_key_ctl_status_s cn58xx;
166 struct cvmx_key_ctl_status_s cn58xxp1;
167 struct cvmx_key_ctl_status_s cn63xx;
168 struct cvmx_key_ctl_status_s cn63xxp1;
170 typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
175 * KEY_INT_ENB = KEY's Interrupt Enable
177 * The KEY's interrupt enable register.
179 union cvmx_key_int_enb
182 struct cvmx_key_int_enb_s
184 #if __BYTE_ORDER == __BIG_ENDIAN
185 uint64_t reserved_4_63 : 60;
186 uint64_t ked1_dbe : 1; /**< When set (1) and bit 3 of the KEY_INT_SUM
187 register is asserted the KEY will assert an
189 uint64_t ked1_sbe : 1; /**< When set (1) and bit 2 of the KEY_INT_SUM
190 register is asserted the KEY will assert an
192 uint64_t ked0_dbe : 1; /**< When set (1) and bit 1 of the KEY_INT_SUM
193 register is asserted the KEY will assert an
195 uint64_t ked0_sbe : 1; /**< When set (1) and bit 0 of the KEY_INT_SUM
196 register is asserted the KEY will assert an
199 uint64_t ked0_sbe : 1;
200 uint64_t ked0_dbe : 1;
201 uint64_t ked1_sbe : 1;
202 uint64_t ked1_dbe : 1;
203 uint64_t reserved_4_63 : 60;
206 struct cvmx_key_int_enb_s cn38xx;
207 struct cvmx_key_int_enb_s cn38xxp2;
208 struct cvmx_key_int_enb_s cn56xx;
209 struct cvmx_key_int_enb_s cn56xxp1;
210 struct cvmx_key_int_enb_s cn58xx;
211 struct cvmx_key_int_enb_s cn58xxp1;
212 struct cvmx_key_int_enb_s cn63xx;
213 struct cvmx_key_int_enb_s cn63xxp1;
215 typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
220 * KEY_INT_SUM = KEY's Interrupt Summary Register
222 * Contains the diffrent interrupt summary bits of the KEY.
224 union cvmx_key_int_sum
227 struct cvmx_key_int_sum_s
229 #if __BYTE_ORDER == __BIG_ENDIAN
230 uint64_t reserved_4_63 : 60;
231 uint64_t ked1_dbe : 1;
232 uint64_t ked1_sbe : 1;
233 uint64_t ked0_dbe : 1;
234 uint64_t ked0_sbe : 1;
236 uint64_t ked0_sbe : 1;
237 uint64_t ked0_dbe : 1;
238 uint64_t ked1_sbe : 1;
239 uint64_t ked1_dbe : 1;
240 uint64_t reserved_4_63 : 60;
243 struct cvmx_key_int_sum_s cn38xx;
244 struct cvmx_key_int_sum_s cn38xxp2;
245 struct cvmx_key_int_sum_s cn56xx;
246 struct cvmx_key_int_sum_s cn56xxp1;
247 struct cvmx_key_int_sum_s cn58xx;
248 struct cvmx_key_int_sum_s cn58xxp1;
249 struct cvmx_key_int_sum_s cn63xx;
250 struct cvmx_key_int_sum_s cn63xxp1;
252 typedef union cvmx_key_int_sum cvmx_key_int_sum_t;