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37 ***********************license end**************************************/
47 * PCI / PCIe packet engine related structures.
49 * <hr>$Revision: 41586 $<hr>
52 #ifndef __CVMX_NPI_H__
53 #define __CVMX_NPI_H__
60 * PCI / PCIe packet instruction header format
67 #if __BYTE_ORDER == __BIG_ENDIAN
68 uint64_t r : 1; /**< Packet is RAW */
69 uint64_t g : 1; /**< Gather list is used */
70 uint64_t dlengsz : 14; /**< Data length / Gather list size */
71 uint64_t fsz : 6; /**< Front data size */
72 uint64_t qos : 3; /**< POW QoS queue */
73 uint64_t grp : 4; /**< POW Group */
74 uint64_t rs : 1; /**< Real short */
75 cvmx_pow_tag_type_t tt : 2; /**< POW Tag type */
76 uint64_t tag : 32; /**< POW 32 bit tag */
79 cvmx_pow_tag_type_t tt : 2;
84 uint64_t dlengsz : 14;
89 } cvmx_npi_inst_hdr_t;
92 * PCI / PCIe packet data pointer formats 0-3
99 #if __BYTE_ORDER == __BIG_ENDIAN
100 uint64_t es : 2; /**< Endian swap mode */
101 uint64_t ns : 1; /**< No snoop */
102 uint64_t ro : 1; /**< Relaxed ordering */
103 uint64_t addr : 60; /**< PCI/PCIe address */
113 #if __BYTE_ORDER == __BIG_ENDIAN
114 uint64_t pm : 2; /**< Parse mode */
115 uint64_t sl : 7; /**< Skip length */
116 uint64_t addr : 55; /**< PCI/PCIe address */
125 #if __BYTE_ORDER == __BIG_ENDIAN
126 uint64_t es : 2; /**< Endian swap mode */
127 uint64_t ns : 1; /**< No snoop */
128 uint64_t ro : 1; /**< Relaxed ordering */
129 uint64_t pm : 2; /**< Parse mode */
130 uint64_t sl : 7; /**< Skip length */
131 uint64_t addr : 51; /**< PCI/PCIe address */
147 #endif /* __CVMX_NPI_H__ */