1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
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19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
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28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_RAD_TYPEDEFS_H__
53 #define __CVMX_RAD_TYPEDEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
57 static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
60 cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180070001000ull);
64 #define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
68 static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
71 cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180070001008ull);
75 #define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
79 static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
82 cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180070001010ull);
86 #define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
90 static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
93 cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180070000080ull);
97 #define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
101 static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
104 cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180070000008ull);
108 #define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
112 static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
115 cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180070000000ull);
119 #define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
123 static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
126 cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180070000100ull);
130 #define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
134 static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
137 cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180070000108ull);
141 #define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull))
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
145 static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
147 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
148 cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x0001180070000150ull);
152 #define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull))
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 #define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
156 static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
159 cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
160 return CVMX_ADD_IO_SEG(0x0001180070000158ull);
163 #define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull))
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 #define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
167 static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
169 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
170 cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
171 return CVMX_ADD_IO_SEG(0x0001180070000160ull);
174 #define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull))
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 #define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
178 static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
180 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
181 cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
182 return CVMX_ADD_IO_SEG(0x0001180070000110ull);
185 #define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull))
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 #define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
189 static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
191 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
192 cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
193 return CVMX_ADD_IO_SEG(0x0001180070000118ull);
196 #define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull))
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 #define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
200 static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
203 cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
204 return CVMX_ADD_IO_SEG(0x0001180070000120ull);
207 #define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull))
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 #define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
211 static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
213 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
214 cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
215 return CVMX_ADD_IO_SEG(0x0001180070000128ull);
218 #define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull))
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 #define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
222 static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
224 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
225 cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
226 return CVMX_ADD_IO_SEG(0x0001180070000130ull);
229 #define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull))
231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
232 #define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
233 static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
235 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
236 cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
237 return CVMX_ADD_IO_SEG(0x0001180070000138ull);
240 #define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull))
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
243 #define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
244 static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
246 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
247 cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
248 return CVMX_ADD_IO_SEG(0x0001180070000140ull);
251 #define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull))
253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
254 #define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
255 static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
257 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
258 cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
259 return CVMX_ADD_IO_SEG(0x0001180070000148ull);
262 #define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull))
264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
265 #define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
266 static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
268 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
269 cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
270 return CVMX_ADD_IO_SEG(0x0001180070000088ull);
273 #define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull))
275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
276 #define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
277 static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
279 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
280 cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
281 return CVMX_ADD_IO_SEG(0x0001180070000090ull);
284 #define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull))
286 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
287 #define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
288 static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
290 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
291 cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
292 return CVMX_ADD_IO_SEG(0x0001180070000010ull);
295 #define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull))
297 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
298 #define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
299 static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
301 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
302 cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
303 return CVMX_ADD_IO_SEG(0x0001180070000018ull);
306 #define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull))
310 * cvmx_rad_mem_debug0
313 * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
314 * CSR read operations to this address can be performed. A read of any entry that has not been
315 * previously written is illegal and will result in unpredictable CSR read data.
317 union cvmx_rad_mem_debug0
320 struct cvmx_rad_mem_debug0_s
322 #if __BYTE_ORDER == __BIG_ENDIAN
323 uint64_t iword : 64; /**< IWord */
328 struct cvmx_rad_mem_debug0_s cn52xx;
329 struct cvmx_rad_mem_debug0_s cn52xxp1;
330 struct cvmx_rad_mem_debug0_s cn56xx;
331 struct cvmx_rad_mem_debug0_s cn56xxp1;
332 struct cvmx_rad_mem_debug0_s cn63xx;
333 struct cvmx_rad_mem_debug0_s cn63xxp1;
335 typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
338 * cvmx_rad_mem_debug1
341 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
342 * CSR read operations to this address can be performed. A read of any entry that has not been
343 * previously written is illegal and will result in unpredictable CSR read data.
345 union cvmx_rad_mem_debug1
348 struct cvmx_rad_mem_debug1_s
350 #if __BYTE_ORDER == __BIG_ENDIAN
351 uint64_t p_dat : 64; /**< P data */
356 struct cvmx_rad_mem_debug1_s cn52xx;
357 struct cvmx_rad_mem_debug1_s cn52xxp1;
358 struct cvmx_rad_mem_debug1_s cn56xx;
359 struct cvmx_rad_mem_debug1_s cn56xxp1;
360 struct cvmx_rad_mem_debug1_s cn63xx;
361 struct cvmx_rad_mem_debug1_s cn63xxp1;
363 typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
366 * cvmx_rad_mem_debug2
369 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
370 * CSR read operations to this address can be performed. A read of any entry that has not been
371 * previously written is illegal and will result in unpredictable CSR read data.
373 union cvmx_rad_mem_debug2
376 struct cvmx_rad_mem_debug2_s
378 #if __BYTE_ORDER == __BIG_ENDIAN
379 uint64_t q_dat : 64; /**< Q data */
384 struct cvmx_rad_mem_debug2_s cn52xx;
385 struct cvmx_rad_mem_debug2_s cn52xxp1;
386 struct cvmx_rad_mem_debug2_s cn56xx;
387 struct cvmx_rad_mem_debug2_s cn56xxp1;
388 struct cvmx_rad_mem_debug2_s cn63xx;
389 struct cvmx_rad_mem_debug2_s cn63xxp1;
391 typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
394 * cvmx_rad_reg_bist_result
397 * Access to the internal BiST results
398 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
400 union cvmx_rad_reg_bist_result
403 struct cvmx_rad_reg_bist_result_s
405 #if __BYTE_ORDER == __BIG_ENDIAN
406 uint64_t reserved_6_63 : 58;
407 uint64_t sta : 1; /**< BiST result of the STA memories */
408 uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */
409 uint64_t ncb_inb : 2; /**< BiST result of the NCB_INB memories */
410 uint64_t dat : 2; /**< BiST result of the DAT memories */
413 uint64_t ncb_inb : 2;
414 uint64_t ncb_oub : 1;
416 uint64_t reserved_6_63 : 58;
419 struct cvmx_rad_reg_bist_result_s cn52xx;
420 struct cvmx_rad_reg_bist_result_s cn52xxp1;
421 struct cvmx_rad_reg_bist_result_s cn56xx;
422 struct cvmx_rad_reg_bist_result_s cn56xxp1;
423 struct cvmx_rad_reg_bist_result_s cn63xx;
424 struct cvmx_rad_reg_bist_result_s cn63xxp1;
426 typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
429 * cvmx_rad_reg_cmd_buf
432 * Sets the command buffer parameters
433 * The size of the command buffer segments is measured in uint64s. The pool specifies 1 of 8 free
434 * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next
435 * pointer each time that the command buffer segment is exhausted.
437 union cvmx_rad_reg_cmd_buf
440 struct cvmx_rad_reg_cmd_buf_s
442 #if __BYTE_ORDER == __BIG_ENDIAN
443 uint64_t reserved_58_63 : 6;
444 uint64_t dwb : 9; /**< Number of DontWriteBacks */
445 uint64_t pool : 3; /**< Free list used to free command buffer segments */
446 uint64_t size : 13; /**< Number of uint64s per command buffer segment */
447 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
453 uint64_t reserved_58_63 : 6;
456 struct cvmx_rad_reg_cmd_buf_s cn52xx;
457 struct cvmx_rad_reg_cmd_buf_s cn52xxp1;
458 struct cvmx_rad_reg_cmd_buf_s cn56xx;
459 struct cvmx_rad_reg_cmd_buf_s cn56xxp1;
460 struct cvmx_rad_reg_cmd_buf_s cn63xx;
461 struct cvmx_rad_reg_cmd_buf_s cn63xxp1;
463 typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
469 * MAX_READ is a throttle to control NCB usage. Values >8 are illegal.
472 union cvmx_rad_reg_ctl
475 struct cvmx_rad_reg_ctl_s
477 #if __BYTE_ORDER == __BIG_ENDIAN
478 uint64_t reserved_6_63 : 58;
479 uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */
480 uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */
481 uint64_t reset : 1; /**< Reset oneshot pulse (lasts for 4 cycles) */
484 uint64_t store_le : 1;
485 uint64_t max_read : 4;
486 uint64_t reserved_6_63 : 58;
489 struct cvmx_rad_reg_ctl_s cn52xx;
490 struct cvmx_rad_reg_ctl_s cn52xxp1;
491 struct cvmx_rad_reg_ctl_s cn56xx;
492 struct cvmx_rad_reg_ctl_s cn56xxp1;
493 struct cvmx_rad_reg_ctl_s cn63xx;
494 struct cvmx_rad_reg_ctl_s cn63xxp1;
496 typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t;
499 * cvmx_rad_reg_debug0
501 union cvmx_rad_reg_debug0
504 struct cvmx_rad_reg_debug0_s
506 #if __BYTE_ORDER == __BIG_ENDIAN
507 uint64_t reserved_57_63 : 7;
508 uint64_t loop : 25; /**< Loop offset */
509 uint64_t reserved_22_31 : 10;
510 uint64_t iridx : 6; /**< IWords read index */
511 uint64_t reserved_14_15 : 2;
512 uint64_t iwidx : 6; /**< IWords write index */
513 uint64_t owordqv : 1; /**< Valid for OWORDQ */
514 uint64_t owordpv : 1; /**< Valid for OWORDP */
515 uint64_t commit : 1; /**< Waiting for write commit */
516 uint64_t state : 5; /**< Main state */
520 uint64_t owordpv : 1;
521 uint64_t owordqv : 1;
523 uint64_t reserved_14_15 : 2;
525 uint64_t reserved_22_31 : 10;
527 uint64_t reserved_57_63 : 7;
530 struct cvmx_rad_reg_debug0_s cn52xx;
531 struct cvmx_rad_reg_debug0_s cn52xxp1;
532 struct cvmx_rad_reg_debug0_s cn56xx;
533 struct cvmx_rad_reg_debug0_s cn56xxp1;
534 struct cvmx_rad_reg_debug0_s cn63xx;
535 struct cvmx_rad_reg_debug0_s cn63xxp1;
537 typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t;
540 * cvmx_rad_reg_debug1
542 union cvmx_rad_reg_debug1
545 struct cvmx_rad_reg_debug1_s
547 #if __BYTE_ORDER == __BIG_ENDIAN
548 uint64_t cword : 64; /**< CWord */
553 struct cvmx_rad_reg_debug1_s cn52xx;
554 struct cvmx_rad_reg_debug1_s cn52xxp1;
555 struct cvmx_rad_reg_debug1_s cn56xx;
556 struct cvmx_rad_reg_debug1_s cn56xxp1;
557 struct cvmx_rad_reg_debug1_s cn63xx;
558 struct cvmx_rad_reg_debug1_s cn63xxp1;
560 typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t;
563 * cvmx_rad_reg_debug10
565 union cvmx_rad_reg_debug10
568 struct cvmx_rad_reg_debug10_s
570 #if __BYTE_ORDER == __BIG_ENDIAN
571 uint64_t flags : 8; /**< OCTL flags */
572 uint64_t size : 16; /**< OCTL size (bytes) */
573 uint64_t ptr : 40; /**< OCTL pointer */
580 struct cvmx_rad_reg_debug10_s cn52xx;
581 struct cvmx_rad_reg_debug10_s cn52xxp1;
582 struct cvmx_rad_reg_debug10_s cn56xx;
583 struct cvmx_rad_reg_debug10_s cn56xxp1;
584 struct cvmx_rad_reg_debug10_s cn63xx;
585 struct cvmx_rad_reg_debug10_s cn63xxp1;
587 typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t;
590 * cvmx_rad_reg_debug11
592 union cvmx_rad_reg_debug11
595 struct cvmx_rad_reg_debug11_s
597 #if __BYTE_ORDER == __BIG_ENDIAN
598 uint64_t reserved_13_63 : 51;
599 uint64_t q : 1; /**< OCTL q flag */
600 uint64_t p : 1; /**< OCTL p flag */
601 uint64_t wc : 1; /**< OCTL write commit flag */
602 uint64_t eod : 1; /**< OCTL eod flag */
603 uint64_t sod : 1; /**< OCTL sod flag */
604 uint64_t index : 8; /**< OCTL index */
612 uint64_t reserved_13_63 : 51;
615 struct cvmx_rad_reg_debug11_s cn52xx;
616 struct cvmx_rad_reg_debug11_s cn52xxp1;
617 struct cvmx_rad_reg_debug11_s cn56xx;
618 struct cvmx_rad_reg_debug11_s cn56xxp1;
619 struct cvmx_rad_reg_debug11_s cn63xx;
620 struct cvmx_rad_reg_debug11_s cn63xxp1;
622 typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t;
625 * cvmx_rad_reg_debug12
627 union cvmx_rad_reg_debug12
630 struct cvmx_rad_reg_debug12_s
632 #if __BYTE_ORDER == __BIG_ENDIAN
633 uint64_t reserved_15_63 : 49;
634 uint64_t asserts : 15; /**< Various assertion checks */
636 uint64_t asserts : 15;
637 uint64_t reserved_15_63 : 49;
640 struct cvmx_rad_reg_debug12_s cn52xx;
641 struct cvmx_rad_reg_debug12_s cn52xxp1;
642 struct cvmx_rad_reg_debug12_s cn56xx;
643 struct cvmx_rad_reg_debug12_s cn56xxp1;
644 struct cvmx_rad_reg_debug12_s cn63xx;
645 struct cvmx_rad_reg_debug12_s cn63xxp1;
647 typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t;
650 * cvmx_rad_reg_debug2
652 union cvmx_rad_reg_debug2
655 struct cvmx_rad_reg_debug2_s
657 #if __BYTE_ORDER == __BIG_ENDIAN
658 uint64_t owordp : 64; /**< OWordP */
660 uint64_t owordp : 64;
663 struct cvmx_rad_reg_debug2_s cn52xx;
664 struct cvmx_rad_reg_debug2_s cn52xxp1;
665 struct cvmx_rad_reg_debug2_s cn56xx;
666 struct cvmx_rad_reg_debug2_s cn56xxp1;
667 struct cvmx_rad_reg_debug2_s cn63xx;
668 struct cvmx_rad_reg_debug2_s cn63xxp1;
670 typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t;
673 * cvmx_rad_reg_debug3
675 union cvmx_rad_reg_debug3
678 struct cvmx_rad_reg_debug3_s
680 #if __BYTE_ORDER == __BIG_ENDIAN
681 uint64_t owordq : 64; /**< OWordQ */
683 uint64_t owordq : 64;
686 struct cvmx_rad_reg_debug3_s cn52xx;
687 struct cvmx_rad_reg_debug3_s cn52xxp1;
688 struct cvmx_rad_reg_debug3_s cn56xx;
689 struct cvmx_rad_reg_debug3_s cn56xxp1;
690 struct cvmx_rad_reg_debug3_s cn63xx;
691 struct cvmx_rad_reg_debug3_s cn63xxp1;
693 typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t;
696 * cvmx_rad_reg_debug4
698 union cvmx_rad_reg_debug4
701 struct cvmx_rad_reg_debug4_s
703 #if __BYTE_ORDER == __BIG_ENDIAN
704 uint64_t rword : 64; /**< RWord */
709 struct cvmx_rad_reg_debug4_s cn52xx;
710 struct cvmx_rad_reg_debug4_s cn52xxp1;
711 struct cvmx_rad_reg_debug4_s cn56xx;
712 struct cvmx_rad_reg_debug4_s cn56xxp1;
713 struct cvmx_rad_reg_debug4_s cn63xx;
714 struct cvmx_rad_reg_debug4_s cn63xxp1;
716 typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t;
719 * cvmx_rad_reg_debug5
721 union cvmx_rad_reg_debug5
724 struct cvmx_rad_reg_debug5_s
726 #if __BYTE_ORDER == __BIG_ENDIAN
727 uint64_t reserved_53_63 : 11;
728 uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */
729 uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */
730 uint64_t nirval7 : 5; /**< NCBI rval (stage7 grant) */
731 uint64_t niropc6 : 3; /**< NCBI ropc (stage6 arb) */
732 uint64_t nirque6 : 2; /**< NCBI rque (stage6 arb) */
733 uint64_t nirarb6 : 1; /**< NCBI rarb (stage6 arb) */
734 uint64_t nirval6 : 5; /**< NCBI rval (stage6 arb) */
735 uint64_t niridx1 : 4; /**< NCBI ridx1 */
736 uint64_t niwidx1 : 4; /**< NCBI widx1 */
737 uint64_t niridx0 : 4; /**< NCBI ridx0 */
738 uint64_t niwidx0 : 4; /**< NCBI widx0 */
739 uint64_t wccreds : 2; /**< WC credits */
740 uint64_t fpacreds : 2; /**< POW credits */
741 uint64_t reserved_10_11 : 2;
742 uint64_t powcreds : 2; /**< POW credits */
743 uint64_t n1creds : 4; /**< NCBI1 credits */
744 uint64_t n0creds : 4; /**< NCBI0 credits */
746 uint64_t n0creds : 4;
747 uint64_t n1creds : 4;
748 uint64_t powcreds : 2;
749 uint64_t reserved_10_11 : 2;
750 uint64_t fpacreds : 2;
751 uint64_t wccreds : 2;
752 uint64_t niwidx0 : 4;
753 uint64_t niridx0 : 4;
754 uint64_t niwidx1 : 4;
755 uint64_t niridx1 : 4;
756 uint64_t nirval6 : 5;
757 uint64_t nirarb6 : 1;
758 uint64_t nirque6 : 2;
759 uint64_t niropc6 : 3;
760 uint64_t nirval7 : 5;
761 uint64_t nirque7 : 2;
762 uint64_t niropc7 : 3;
763 uint64_t reserved_53_63 : 11;
766 struct cvmx_rad_reg_debug5_s cn52xx;
767 struct cvmx_rad_reg_debug5_s cn52xxp1;
768 struct cvmx_rad_reg_debug5_s cn56xx;
769 struct cvmx_rad_reg_debug5_s cn56xxp1;
770 struct cvmx_rad_reg_debug5_s cn63xx;
771 struct cvmx_rad_reg_debug5_s cn63xxp1;
773 typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t;
776 * cvmx_rad_reg_debug6
778 union cvmx_rad_reg_debug6
781 struct cvmx_rad_reg_debug6_s
783 #if __BYTE_ORDER == __BIG_ENDIAN
784 uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */
785 uint64_t size : 16; /**< CCTL size (bytes) */
786 uint64_t ptr : 40; /**< CCTL pointer */
793 struct cvmx_rad_reg_debug6_s cn52xx;
794 struct cvmx_rad_reg_debug6_s cn52xxp1;
795 struct cvmx_rad_reg_debug6_s cn56xx;
796 struct cvmx_rad_reg_debug6_s cn56xxp1;
797 struct cvmx_rad_reg_debug6_s cn63xx;
798 struct cvmx_rad_reg_debug6_s cn63xxp1;
800 typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t;
803 * cvmx_rad_reg_debug7
805 union cvmx_rad_reg_debug7
808 struct cvmx_rad_reg_debug7_s
810 #if __BYTE_ORDER == __BIG_ENDIAN
811 uint64_t reserved_15_63 : 49;
812 uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */
815 uint64_t reserved_15_63 : 49;
818 struct cvmx_rad_reg_debug7_s cn52xx;
819 struct cvmx_rad_reg_debug7_s cn52xxp1;
820 struct cvmx_rad_reg_debug7_s cn56xx;
821 struct cvmx_rad_reg_debug7_s cn56xxp1;
822 struct cvmx_rad_reg_debug7_s cn63xx;
823 struct cvmx_rad_reg_debug7_s cn63xxp1;
825 typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t;
828 * cvmx_rad_reg_debug8
830 union cvmx_rad_reg_debug8
833 struct cvmx_rad_reg_debug8_s
835 #if __BYTE_ORDER == __BIG_ENDIAN
836 uint64_t flags : 8; /**< ICTL flags */
837 uint64_t size : 16; /**< ICTL size (bytes) */
838 uint64_t ptr : 40; /**< ICTL pointer */
845 struct cvmx_rad_reg_debug8_s cn52xx;
846 struct cvmx_rad_reg_debug8_s cn52xxp1;
847 struct cvmx_rad_reg_debug8_s cn56xx;
848 struct cvmx_rad_reg_debug8_s cn56xxp1;
849 struct cvmx_rad_reg_debug8_s cn63xx;
850 struct cvmx_rad_reg_debug8_s cn63xxp1;
852 typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t;
855 * cvmx_rad_reg_debug9
857 union cvmx_rad_reg_debug9
860 struct cvmx_rad_reg_debug9_s
862 #if __BYTE_ORDER == __BIG_ENDIAN
863 uint64_t reserved_20_63 : 44;
864 uint64_t eod : 1; /**< ICTL eod flag */
865 uint64_t ini : 1; /**< ICTL init flag */
866 uint64_t q : 1; /**< ICTL q enable */
867 uint64_t p : 1; /**< ICTL p enable */
868 uint64_t mul : 8; /**< ICTL multiplier */
869 uint64_t index : 8; /**< ICTL index */
877 uint64_t reserved_20_63 : 44;
880 struct cvmx_rad_reg_debug9_s cn52xx;
881 struct cvmx_rad_reg_debug9_s cn52xxp1;
882 struct cvmx_rad_reg_debug9_s cn56xx;
883 struct cvmx_rad_reg_debug9_s cn56xxp1;
884 struct cvmx_rad_reg_debug9_s cn63xx;
885 struct cvmx_rad_reg_debug9_s cn63xxp1;
887 typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t;
892 union cvmx_rad_reg_error
895 struct cvmx_rad_reg_error_s
897 #if __BYTE_ORDER == __BIG_ENDIAN
898 uint64_t reserved_1_63 : 63;
899 uint64_t doorbell : 1; /**< A doorbell count has overflowed */
901 uint64_t doorbell : 1;
902 uint64_t reserved_1_63 : 63;
905 struct cvmx_rad_reg_error_s cn52xx;
906 struct cvmx_rad_reg_error_s cn52xxp1;
907 struct cvmx_rad_reg_error_s cn56xx;
908 struct cvmx_rad_reg_error_s cn56xxp1;
909 struct cvmx_rad_reg_error_s cn63xx;
910 struct cvmx_rad_reg_error_s cn63xxp1;
912 typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
915 * cvmx_rad_reg_int_mask
918 * When a mask bit is set, the corresponding interrupt is enabled.
921 union cvmx_rad_reg_int_mask
924 struct cvmx_rad_reg_int_mask_s
926 #if __BYTE_ORDER == __BIG_ENDIAN
927 uint64_t reserved_1_63 : 63;
928 uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
930 uint64_t doorbell : 1;
931 uint64_t reserved_1_63 : 63;
934 struct cvmx_rad_reg_int_mask_s cn52xx;
935 struct cvmx_rad_reg_int_mask_s cn52xxp1;
936 struct cvmx_rad_reg_int_mask_s cn56xx;
937 struct cvmx_rad_reg_int_mask_s cn56xxp1;
938 struct cvmx_rad_reg_int_mask_s cn63xx;
939 struct cvmx_rad_reg_int_mask_s cn63xxp1;
941 typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
944 * cvmx_rad_reg_polynomial
947 * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
950 union cvmx_rad_reg_polynomial
953 struct cvmx_rad_reg_polynomial_s
955 #if __BYTE_ORDER == __BIG_ENDIAN
956 uint64_t reserved_8_63 : 56;
957 uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */
960 uint64_t reserved_8_63 : 56;
963 struct cvmx_rad_reg_polynomial_s cn52xx;
964 struct cvmx_rad_reg_polynomial_s cn52xxp1;
965 struct cvmx_rad_reg_polynomial_s cn56xx;
966 struct cvmx_rad_reg_polynomial_s cn56xxp1;
967 struct cvmx_rad_reg_polynomial_s cn63xx;
968 struct cvmx_rad_reg_polynomial_s cn63xxp1;
970 typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
973 * cvmx_rad_reg_read_idx
976 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
977 * as memories. The names of these CSRs begin with the prefix "RAD_MEM_".
978 * IDX[15:0] is the read index. INC[15:0] is an increment that is added to IDX[15:0] after any CSR read.
979 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire
980 * contents of a CSR memory can be read with consecutive CSR read commands.
982 union cvmx_rad_reg_read_idx
985 struct cvmx_rad_reg_read_idx_s
987 #if __BYTE_ORDER == __BIG_ENDIAN
988 uint64_t reserved_32_63 : 32;
989 uint64_t inc : 16; /**< Increment to add to current index for next index */
990 uint64_t index : 16; /**< Index to use for next memory CSR read */
994 uint64_t reserved_32_63 : 32;
997 struct cvmx_rad_reg_read_idx_s cn52xx;
998 struct cvmx_rad_reg_read_idx_s cn52xxp1;
999 struct cvmx_rad_reg_read_idx_s cn56xx;
1000 struct cvmx_rad_reg_read_idx_s cn56xxp1;
1001 struct cvmx_rad_reg_read_idx_s cn63xx;
1002 struct cvmx_rad_reg_read_idx_s cn63xxp1;
1004 typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t;