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48 * Interface to the Trace buffer hardware.
50 * WRITING THE TRACE BUFFER
52 * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once
53 * (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled
54 * by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC
55 * commands that are traced is determined by the filter and the two triggers, each of which is comprised of
56 * masks for command, sid, did, and address). If triggers are disabled, then only those commands matching
57 * the filter are traced. If triggers are enabled, then only those commands matching the filter, the start
58 * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger.
60 * For a given command, its XMC data is written immediately to the buffer. If the command has XMD data,
61 * then that data comes in-order at some later time. The XMD data is accumulated across all valid
62 * XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer
63 * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC
64 * data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost.
67 * READING THE TRACE BUFFER
69 * Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order,
70 * as soon as it has access to the (single-ported) trace buffer.
73 * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
75 * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow
76 * conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write
77 * (traced event) increments the write pointer and each read increments the read pointer. During the overflow
78 * condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is
79 * resolved. The first entry that is written immediately following the overflow condition may be marked to
80 * indicate that a tracing discontinuity has occurred before this entry. During the underflow condition,
81 * reading does not increment the read pointer and the read data is marked to indicate that no read data is
84 * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4).
85 * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the
86 * absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs
87 * every time the desired level of "fullness" is achieved.
90 * Trace buffer entry format
93 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
94 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
95 * |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp|
96 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
97 * |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp|
98 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
99 * |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp|
100 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
101 * |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp|
102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
103 * |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp|
104 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
105 * |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp|
106 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
107 * |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp|
108 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
109 * |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp|
110 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
111 * |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp|
112 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
113 * |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp|
114 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
115 * |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp|
116 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
117 * |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp|
118 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
119 * |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp|
120 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
121 * |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp|
122 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
123 * |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp|
124 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
125 * |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp|
126 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
129 * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the
130 * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
131 * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
133 * 0x2=valid, no discontinuity
134 * 0x3=valid, discontinuity
135 * - commands are encoded as follows:
152 * - For non IOB* commands
153 * - source id is encoded as follows:
157 * 0x12=IOB(ReqLoad, ReqStore)
161 * - dest id is unused (can only be L2c)
162 * - For IOB* commands
163 * - source id is encoded as follows:
165 * - dest id is encoded as follows:
169 * 0x12=IOB(ReqLoad, ReqStore)
174 * Source of data for each command
175 * command source id dest id address length/mask
176 * -------+------------+------------+-----------------------+----------------------------------------------
177 * LDI xmc_sid[8:3] x xmc_adr[35:3] x
178 * LDT xmc_sid[8:3] x xmc_adr[35:3] x
179 * STF xmc_sid[8:3] x xmc_adr[35:3] 16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
180 * STC xmc_sid[8:3] x xmc_adr[35:3] 16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
181 * STP xmc_sid[8:3] x xmc_adr[35:3] 16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
182 * STT xmc_sid[8:3] x xmc_adr[35:3] 16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
183 * DWB xmc_sid[8:3] x xmc_adr[35:3] x
184 * PL2 xmc_sid[8:3] x xmc_adr[35:3] x
185 * PSL1 xmc_sid[8:3] x xmc_adr[35:3] x
186 * IOBLD8 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:0] x
187 * IOBLD16 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:1] x
188 * IOBLD32 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:2] x
189 * IOBLD64 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3] x
190 * IOBST xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3] 16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
191 * IOBDMA xmc_sid[8:3] xmc_did[8:3] (xmd_[wrval,eow,dat[]]) length(xmd_[wrval,eow,dat[]])
192 * IOBRSP not traced, but monitored to keep XMC and XMD data in sync.
195 * <hr>$Revision: 41586 $<hr>
198 #ifndef __CVMX_TRA_H__
199 #define __CVMX_TRA_H__
208 /* CSR typedefs have been moved to cvmx-csr-*.h */
211 * Enumeration of the data types stored in cvmx_tra_data_t
215 CVMX_TRA_DATA_DWB = 0x0,
216 CVMX_TRA_DATA_PL2 = 0x1,
217 CVMX_TRA_DATA_PSL1 = 0x2,
218 CVMX_TRA_DATA_LDD = 0x3,
219 CVMX_TRA_DATA_LDI = 0x4,
220 CVMX_TRA_DATA_LDT = 0x5,
221 CVMX_TRA_DATA_STC = 0x6,
222 CVMX_TRA_DATA_STF = 0x7,
223 CVMX_TRA_DATA_STP = 0x8,
224 CVMX_TRA_DATA_STT = 0x9,
225 CVMX_TRA_DATA_IOBLD8 = 0xa,
226 CVMX_TRA_DATA_IOBLD16 = 0xb,
227 CVMX_TRA_DATA_IOBLD32 = 0xc,
228 CVMX_TRA_DATA_IOBLD64 = 0xd,
229 CVMX_TRA_DATA_IOBST = 0xe,
230 CVMX_TRA_DATA_IOBDMA = 0xf,
231 CVMX_TRA_DATA_SAA = 0x10,
232 } cvmx_tra_data_type_t;
235 * TRA data format definition. Use the type field to
236 * determine which union element to use.
243 #if __BYTE_ORDER == __BIG_ENDIAN
245 uint64_t discontinuity:1;
246 uint64_t address : 36;
247 uint64_t reserved : 5;
249 uint64_t reserved2 : 3;
250 cvmx_tra_data_type_t type:5;
251 uint64_t timestamp : 8;
253 uint64_t timestamp : 8;
254 cvmx_tra_data_type_t type:5;
255 uint64_t reserved2 : 3;
257 uint64_t reserved : 5;
258 uint64_t address : 36;
259 uint64_t discontinuity:1;
262 } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
265 #if __BYTE_ORDER == __BIG_ENDIAN
267 uint64_t discontinuity:1;
268 uint64_t address : 33;
271 uint64_t reserved2 : 3;
272 cvmx_tra_data_type_t type:5;
273 uint64_t timestamp : 8;
275 uint64_t timestamp : 8;
276 cvmx_tra_data_type_t type:5;
277 uint64_t reserved2 : 3;
280 uint64_t address : 33;
281 uint64_t discontinuity:1;
284 } store; /**< STC, STF, STP, STT */
287 #if __BYTE_ORDER == __BIG_ENDIAN
289 uint64_t discontinuity:1;
290 uint64_t address : 36;
291 uint64_t reserved : 2;
296 uint64_t timestamp : 8;
298 uint64_t timestamp : 8;
303 uint64_t reserved : 2;
304 uint64_t address : 36;
305 uint64_t discontinuity:1;
308 } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
311 #if __BYTE_ORDER == __BIG_ENDIAN
313 uint64_t discontinuity:1;
314 uint64_t address : 33;
319 uint64_t timestamp : 8;
321 uint64_t timestamp : 8;
326 uint64_t address : 33;
327 uint64_t discontinuity:1;
330 } iob; /**< for IOBDMA */
335 * Setup the TRA buffer for use
337 * @param control TRA control setup
338 * @param filter Which events to log
339 * @param source_filter
343 * @param address Address compare
344 * @param address_mask
347 extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
348 cvmx_tra_filt_sid_t source_filter, cvmx_tra_filt_did_t dest_filter,
349 uint64_t address, uint64_t address_mask);
352 * Setup a TRA trigger. How the triggers are used should be
353 * setup using cvmx_tra_setup.
355 * @param trigger Trigger to setup (0 or 1)
356 * @param filter Which types of events to trigger on
357 * @param source_filter
358 * Source trigger match
360 * Destination trigger match
361 * @param address Trigger address compare
362 * @param address_mask
363 * Trigger address mask
365 extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
366 cvmx_tra_filt_sid_t source_filter, cvmx_tra_trig0_did_t dest_filter,
367 uint64_t address, uint64_t address_mask);
370 * Read an entry from the TRA buffer
372 * @return Value return. High bit will be zero if there wasn't any data
374 extern cvmx_tra_data_t cvmx_tra_read(void);
377 * Decode a TRA entry into human readable output
379 * @param tra_ctl Trace control setup
380 * @param data Data to decode
382 extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
385 * Display the entire trace buffer. It is advised that you
386 * disable the trace buffer before calling this routine
387 * otherwise it could infinitely loop displaying trace data
390 extern void cvmx_tra_display(void);
393 * Enable or disable the TRA hardware
395 * @param enable 1=enable, 0=disable
397 static inline void cvmx_tra_enable(int enable)
399 cvmx_tra_ctl_t control;
400 control.u64 = cvmx_read_csr(CVMX_TRA_CTL);
401 control.s.ena = enable;
402 cvmx_write_csr(CVMX_TRA_CTL, control.u64);
403 cvmx_read_csr(CVMX_TRA_CTL);