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47 * This header file defines the work queue entry (wqe) data structure.
48 * Since this is a commonly used structure that depends on structures
49 * from several hardware blocks, those definitions have been placed
50 * in this file to create a single point of definition of the wqe
52 * Data structures are still named according to the block that they
55 * This file must not depend on any other header files, except for cvmx.h!!!
58 * <hr>$Revision: 41586 $<hr>
64 #ifndef __CVMX_WQE_H__
65 #define __CVMX_WQE_H__
71 #define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
72 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
73 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
78 * HW decode / err_code in work queue entry
84 /** Use this struct if the hardware determines that the packet is IP */
87 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
88 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
89 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
90 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
91 uint64_t unassigned : 1;
92 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
93 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
94 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
95 uint64_t unassigned2 : 8;
96 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
97 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
98 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
99 uint64_t is_v6 : 1; /**< the packet is IPv6 */
101 // (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.)
103 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
104 // exceptional conditions below
105 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
106 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
107 failure indicated in err_code below, decode:
109 - 2 = L4 Checksum Error: the L4 checksum value is
110 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
111 remains in the IP packet (as defined by the IP header length field).
112 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
113 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
114 - 9 = TCP No Flags: the packet is TCP and no flags are set.
115 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
116 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
117 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
118 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
122 uint64_t is_frag : 1; /**< set if the packet is a fragment */
123 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
124 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
125 - 1 = Not IP: the IP version field is neither 4 nor 6.
126 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
127 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
128 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
129 header. Pad is allowed.
130 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
133 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
134 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
135 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
136 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
137 /* lower err_code = first-level descriptor of the work */
138 /* zero for packet submitted by hardware that isn't on the slow path */
140 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
143 /**< use this to get at the 16 vlan bits */
146 uint64_t unused1 :16;
148 uint64_t unused2 :32;
151 /**< use this struct if the hardware could not determine that the packet is ip */
154 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
156 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
157 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
158 uint64_t unassigned : 1;
159 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
160 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
161 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
162 uint64_t unassigned2 :12;
163 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
164 uint64_t unassigned3 : 1;
165 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
166 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
167 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
168 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
169 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
170 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
171 Failure indicated in err_code below, decode:
172 - 1 = partial error: a packet was partially received, but internal
173 buffering / bandwidth was not adequate to receive the entire packet.
174 - 2 = jabber error: the RGMII packet was too large and is truncated.
175 - 3 = overrun error: the RGMII packet is longer than allowed and had
177 - 4 = oversize error: the RGMII packet is longer than allowed.
178 - 5 = alignment error: the RGMII packet is not an integer number of bytes
179 and had an FCS error (100M and 10M only).
180 - 6 = fragment error: the RGMII packet is shorter than allowed and had an
182 - 7 = GMX FCS error: the RGMII packet had an FCS error.
183 - 8 = undersize error: the RGMII packet is shorter than allowed.
184 - 9 = extend error: the RGMII packet had an extend error.
185 - 10 = length mismatch error: the RGMII packet had a length that did not
186 match the length field in the L2 HDR.
187 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
188 data reception errors (RXERR) or the SPI4 packet had one or more DIP4
190 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
191 enough to cover the skipped bytes or the SPI4 packet was terminated
193 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
194 studder error (data not repeated - 10/100M only) or the SPI4 packet
196 - 16 = FCS error: a SPI4.2 packet had an FCS error.
197 - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
198 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
201 /* lower err_code = first-level descriptor of the work */
202 /* zero for packet submitted by hardware that isn't on the slow path */
203 uint64_t err_code : 8; // type is cvmx_pip_err_t (union, so can't use directly
206 } cvmx_pip_wqe_word2;
216 * Work queue entry format
218 * must be 8-byte aligned
223 /*****************************************************************
225 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
229 * raw chksum result generated by the HW
233 * Field unused by hardware - available for software
237 * Next pointer used by hardware for list maintenance.
238 * May be written/read by HW before the work queue
239 * entry is scheduled to a PP
240 * (Only 36 bits used in Octeon 1)
242 uint64_t next_ptr : 40;
245 /*****************************************************************
247 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
251 * HW sets to the total number of bytes in the packet
255 * HW sets this to input physical port
260 * HW sets this to what it thought the priority of the input packet was
265 * the group that the work queue entry will be scheduled to
269 * the type of the tag (ORDERED, ATOMIC, NULL)
271 cvmx_pow_tag_type_t tag_type : 3;
273 * the synchronization/ordering tag
279 * HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
280 * This indicates a variety of status and error conditions.
282 cvmx_pip_wqe_word2 word2;
285 * Pointer to the first segment of the packet.
287 cvmx_buf_ptr_t packet_ptr;
290 * HW WRITE: octeon will fill in a programmable amount from the
291 * packet, up to (at most, but perhaps less) the amount
292 * needed to fill the work queue entry to 128 bytes
293 * If the packet is recognized to be IP, the hardware starts (except that
294 * the IPv4 header is padded for appropriate alignment) writing here where
295 * the IP header starts.
296 * If the packet is not recognized to be IP, the hardware starts writing
297 * the beginning of the packet here.
299 uint8_t packet_data[96];
303 * If desired, SW can make the work Q entry any length. For the
304 * purposes of discussion here, Assume 128B always, as this is all that
305 * the hardware deals with.
309 } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
315 #endif /* __CVMX_WQE_H__ */