2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_ati_chipinit(device_t dev);
56 static int ata_ati_dumb_ch_attach(device_t dev);
57 static int ata_ati_ixp700_ch_attach(device_t dev);
58 static int ata_ati_setmode(device_t dev, int target, int mode);
61 #define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */
62 #define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */
64 #define ATI_SATA SII_MEMIO
68 static int force_ahci = 1;
69 TUNABLE_INT("hw.ahci.force", &force_ahci);
72 * ATI chipset support functions
75 ata_ati_probe(device_t dev)
77 struct ata_pci_controller *ctlr = device_get_softc(dev);
78 static const struct ata_chip_id ids[] =
79 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" },
80 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" },
81 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" },
82 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" },
83 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" },
84 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" },
85 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" },
86 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" },
87 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" },
88 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
89 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
90 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
91 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
92 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
93 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
94 { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" },
95 { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
96 { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
97 { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
98 { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
99 { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
100 { 0, 0, 0, 0, 0, 0}};
102 if (pci_get_vendor(dev) != ATA_ATI_ID)
105 if (!(ctlr->chip = ata_match_chip(dev, ids)))
110 switch (ctlr->chip->cfg1) {
112 ctlr->chipinit = ata_ati_chipinit;
116 * the ATI SATA controller is actually a SiI 3112 controller
118 ctlr->chipinit = ata_sii_chipinit;
121 if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE)
122 ctlr->chipinit = ata_ahci_chipinit;
124 ctlr->chipinit = ata_ati_chipinit;
127 return (BUS_PROBE_DEFAULT);
131 ata_ati_chipinit(device_t dev)
133 struct ata_pci_controller *ctlr = device_get_softc(dev);
137 if (ata_setup_interrupt(dev, ata_generic_intr))
140 if (ctlr->chip->cfg1 == ATI_AHCI) {
141 ctlr->ch_attach = ata_ati_dumb_ch_attach;
142 ctlr->setmode = ata_sata_setmode;
145 switch (ctlr->chip->chipid) {
147 /* IXP600 only has 1 PATA channel */
152 * When "combined mode" is enabled, an additional PATA channel is
153 * emulated with two SATA ports and appears on this device.
154 * This mode can only be detected via SMB controller.
156 smbdev = pci_find_device(ATA_ATI_ID, 0x4385);
157 if (smbdev != NULL) {
158 satacfg = pci_read_config(smbdev, 0xad, 1);
160 device_printf(dev, "SATA controller %s (%s%s channel)\n",
161 (satacfg & 0x01) == 0 ? "disabled" : "enabled",
162 (satacfg & 0x08) == 0 ? "" : "combined mode, ",
163 (satacfg & 0x10) == 0 ? "primary" : "secondary");
164 ctlr->chipset_data = (void *)(uintptr_t)satacfg;
166 * If SATA controller is enabled but combined mode is disabled,
167 * we have only one PATA channel. Ignore a non-existent channel.
169 if ((satacfg & 0x09) == 0x01)
170 ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4));
172 ctlr->ch_attach = ata_ati_ixp700_ch_attach;
178 ctlr->setmode = ata_ati_setmode;
183 ata_ati_dumb_ch_attach(device_t dev)
185 struct ata_channel *ch = device_get_softc(dev);
187 if (ata_pci_ch_attach(dev))
189 ch->flags |= ATA_SATA;
194 ata_ati_ixp700_ch_attach(device_t dev)
196 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
197 struct ata_channel *ch = device_get_softc(dev);
198 uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data;
200 /* Setup the usual register normal pci style. */
201 if (ata_pci_ch_attach(dev))
204 /* One of channels is PATA, another is SATA. */
205 if (ch->unit == ((satacfg & 0x10) >> 4))
206 ch->flags |= ATA_SATA;
211 ata_ati_setmode(device_t dev, int target, int mode)
213 device_t parent = device_get_parent(dev);
214 struct ata_pci_controller *ctlr = device_get_softc(parent);
215 struct ata_channel *ch = device_get_softc(dev);
216 int devno = (ch->unit << 1) + target;
217 int offset = (devno ^ 0x01) << 3;
219 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
220 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
222 mode = min(mode, ctlr->chip->max_dma);
223 if (mode >= ATA_UDMA0) {
224 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
225 pci_write_config(parent, 0x56,
226 (pci_read_config(parent, 0x56, 2) &
227 ~(0xf << (devno << 2))) |
228 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
229 pci_write_config(parent, 0x54,
230 pci_read_config(parent, 0x54, 1) |
232 pci_write_config(parent, 0x44,
233 (pci_read_config(parent, 0x44, 4) &
235 (dmatimings[2] << offset), 4);
237 } else if (mode >= ATA_WDMA0) {
238 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
239 pci_write_config(parent, 0x54,
240 pci_read_config(parent, 0x54, 1) &
241 ~(0x01 << devno), 1);
242 pci_write_config(parent, 0x44,
243 (pci_read_config(parent, 0x44, 4) &
245 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
246 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
247 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
249 /* Disable UDMA, set requested PIO. */
250 pci_write_config(parent, 0x54,
251 pci_read_config(parent, 0x54, 1) &
252 ~(0x01 << devno), 1);
255 /* Set PIO mode and timings, calculated above. */
256 pci_write_config(parent, 0x4a,
257 (pci_read_config(parent, 0x4a, 2) &
258 ~(0xf << (devno << 2))) |
259 ((piomode - ATA_PIO0) << (devno<<2)),2);
260 pci_write_config(parent, 0x40,
261 (pci_read_config(parent, 0x40, 4) &
263 (piotimings[ata_mode2idx(piomode)] << offset), 4);
267 ATA_DECLARE_DRIVER(ata_ati);
268 MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
269 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);