2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_intel_chipinit(device_t dev);
56 static int ata_intel_chipdeinit(device_t dev);
57 static int ata_intel_ch_attach(device_t dev);
58 static void ata_intel_reset(device_t dev);
59 static int ata_intel_old_setmode(device_t dev, int target, int mode);
60 static int ata_intel_new_setmode(device_t dev, int target, int mode);
61 static int ata_intel_sch_setmode(device_t dev, int target, int mode);
62 static int ata_intel_sata_getrev(device_t dev, int target);
63 static int ata_intel_sata_status(device_t dev);
64 static int ata_intel_sata_ahci_read(device_t dev, int port,
65 int reg, u_int32_t *result);
66 static int ata_intel_sata_cscr_read(device_t dev, int port,
67 int reg, u_int32_t *result);
68 static int ata_intel_sata_sidpr_read(device_t dev, int port,
69 int reg, u_int32_t *result);
70 static int ata_intel_sata_ahci_write(device_t dev, int port,
71 int reg, u_int32_t result);
72 static int ata_intel_sata_cscr_write(device_t dev, int port,
73 int reg, u_int32_t result);
74 static int ata_intel_sata_sidpr_write(device_t dev, int port,
75 int reg, u_int32_t result);
76 static int ata_intel_sata_sidpr_test(device_t dev);
77 static int ata_intel_31244_ch_attach(device_t dev);
78 static int ata_intel_31244_ch_detach(device_t dev);
79 static int ata_intel_31244_status(device_t dev);
80 static void ata_intel_31244_tf_write(struct ata_request *request);
81 static void ata_intel_31244_reset(device_t dev);
90 struct ata_intel_data {
95 #define ATA_INTEL_SMAP(ctlr, ch) \
96 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2]
97 #define ATA_INTEL_LOCK(ctlr) \
98 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock)
99 #define ATA_INTEL_UNLOCK(ctlr) \
100 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock)
103 * Intel chipset support functions
106 ata_intel_probe(device_t dev)
108 struct ata_pci_controller *ctlr = device_get_softc(dev);
109 static const struct ata_chip_id ids[] =
110 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" },
111 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" },
112 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" },
113 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
114 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
115 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" },
116 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" },
117 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" },
118 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" },
119 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" },
120 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" },
121 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" },
122 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" },
123 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" },
124 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" },
125 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" },
126 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" },
127 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" },
128 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
129 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
130 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
131 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
132 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
133 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
134 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
135 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
136 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
137 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
138 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
139 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
140 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
141 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
142 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" },
143 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
144 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
145 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
146 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" },
147 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
148 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
149 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
150 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
151 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
152 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" },
153 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
154 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
155 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" },
156 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
157 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
158 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
159 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
160 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
161 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
162 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
163 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
164 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
165 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
166 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
167 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
168 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
169 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
170 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
171 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
172 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
173 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
174 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
175 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
176 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
177 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
178 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
179 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
180 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
181 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
182 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
183 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
184 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
185 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
186 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
187 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
188 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
189 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
190 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
191 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
192 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
193 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
194 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
195 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
196 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
197 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" },
198 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
199 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
200 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
201 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
202 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
203 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
204 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
205 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
206 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
207 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
208 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
209 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
210 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
211 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
212 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
213 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
214 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
215 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
216 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
217 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
218 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
219 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
220 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
221 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
222 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
223 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
224 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
225 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
226 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
227 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
228 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },
229 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
230 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
231 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
232 { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" },
233 { 0, 0, 0, 0, 0, 0}};
235 if (pci_get_vendor(dev) != ATA_INTEL_ID)
238 if (!(ctlr->chip = ata_match_chip(dev, ids)))
242 ctlr->chipinit = ata_intel_chipinit;
243 ctlr->chipdeinit = ata_intel_chipdeinit;
244 return (BUS_PROBE_DEFAULT);
248 ata_intel_chipinit(device_t dev)
250 struct ata_pci_controller *ctlr = device_get_softc(dev);
251 struct ata_intel_data *data;
253 if (ata_setup_interrupt(dev, ata_generic_intr))
256 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO);
257 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF);
258 ctlr->chipset_data = (void *)data;
260 /* good old PIIX needs special treatment (not implemented) */
261 if (ctlr->chip->chipid == ATA_I82371FB) {
262 ctlr->setmode = ata_intel_old_setmode;
265 /* the intel 31244 needs special care if in DPA mode */
266 else if (ctlr->chip->chipid == ATA_I31244) {
267 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
268 ctlr->r_type2 = SYS_RES_MEMORY;
269 ctlr->r_rid2 = PCIR_BAR(0);
270 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
275 ctlr->ch_attach = ata_intel_31244_ch_attach;
276 ctlr->ch_detach = ata_intel_31244_ch_detach;
277 ctlr->reset = ata_intel_31244_reset;
279 ctlr->setmode = ata_sata_setmode;
280 ctlr->getrev = ata_sata_getrev;
283 else if (ctlr->chip->chipid == ATA_ISCH) {
285 ctlr->ch_attach = ata_intel_ch_attach;
286 ctlr->ch_detach = ata_pci_ch_detach;
287 ctlr->setmode = ata_intel_sch_setmode;
289 /* non SATA intel chips goes here */
290 else if (ctlr->chip->max_dma < ATA_SA150) {
291 ctlr->channels = ctlr->chip->cfg2;
292 ctlr->ch_attach = ata_intel_ch_attach;
293 ctlr->ch_detach = ata_pci_ch_detach;
294 ctlr->setmode = ata_intel_new_setmode;
297 /* SATA parts can be either compat or AHCI */
299 /* force all ports active "the legacy way" */
300 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
302 ctlr->ch_attach = ata_intel_ch_attach;
303 ctlr->ch_detach = ata_pci_ch_detach;
304 ctlr->reset = ata_intel_reset;
307 * if we have AHCI capability and AHCI or RAID mode enabled
308 * in BIOS we try for AHCI mode
310 if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
311 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
312 (ata_ahci_chipinit(dev) != ENXIO))
315 /* BAR(5) may point to SATA interface registers */
316 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
317 ctlr->r_type2 = SYS_RES_MEMORY;
318 ctlr->r_rid2 = PCIR_BAR(5);
319 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
320 &ctlr->r_rid2, RF_ACTIVE);
321 if (ctlr->r_res2 != NULL) {
322 /* Set SCRAE bit to enable registers access. */
323 pci_write_config(dev, 0x94,
324 pci_read_config(dev, 0x94, 4) | (1 << 9), 4);
325 /* Set Ports Implemented register bits. */
326 ATA_OUTL(ctlr->r_res2, 0x0C,
327 ATA_INL(ctlr->r_res2, 0x0C) | 0xf);
329 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */
330 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 ||
331 pci_get_subvendor(dev) != 0x106b) {
332 ctlr->r_type2 = SYS_RES_IOPORT;
333 ctlr->r_rid2 = PCIR_BAR(5);
334 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
335 &ctlr->r_rid2, RF_ACTIVE);
337 if (ctlr->r_res2 != NULL ||
338 (ctlr->chip->cfg1 & INTEL_ICH5))
339 ctlr->getrev = ata_intel_sata_getrev;
340 ctlr->setmode = ata_sata_setmode;
346 ata_intel_chipdeinit(device_t dev)
348 struct ata_pci_controller *ctlr = device_get_softc(dev);
349 struct ata_intel_data *data;
351 data = ctlr->chipset_data;
352 mtx_destroy(&data->lock);
353 free(data, M_ATAPCI);
354 ctlr->chipset_data = NULL;
359 ata_intel_ch_attach(device_t dev)
361 struct ata_pci_controller *ctlr;
362 struct ata_channel *ch;
366 /* setup the usual register normal pci style */
367 if (ata_pci_ch_attach(dev))
370 ctlr = device_get_softc(device_get_parent(dev));
371 ch = device_get_softc(dev);
373 /* if r_res2 is valid it points to SATA interface registers */
375 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
376 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
377 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
378 ch->r_io[ATA_IDX_DATA].offset = 0x04;
381 ch->flags |= ATA_ALWAYS_DMASTAT;
382 if (ctlr->chip->max_dma >= ATA_SA150) {
383 smap = ATA_INTEL_SMAP(ctlr, ch);
384 map = pci_read_config(device_get_parent(dev), 0x90, 1);
385 if (ctlr->chip->cfg1 & INTEL_ICH5) {
387 if ((map & 0x04) == 0) {
388 ch->flags |= ATA_SATA;
389 ch->flags |= ATA_NO_SLAVE;
390 smap[0] = (map & 0x01) ^ ch->unit;
392 } else if ((map & 0x02) == 0 && ch->unit == 0) {
393 ch->flags |= ATA_SATA;
394 smap[0] = (map & 0x01) ? 1 : 0;
395 smap[1] = (map & 0x01) ? 0 : 1;
396 } else if ((map & 0x02) != 0 && ch->unit == 1) {
397 ch->flags |= ATA_SATA;
398 smap[0] = (map & 0x01) ? 1 : 0;
399 smap[1] = (map & 0x01) ? 0 : 1;
401 } else if (ctlr->chip->cfg1 & INTEL_6CH2) {
402 ch->flags |= ATA_SATA;
403 ch->flags |= ATA_NO_SLAVE;
404 smap[0] = (ch->unit == 0) ? 0 : 1;
409 ch->flags |= ATA_SATA;
410 smap[0] = (ch->unit == 0) ? 0 : 1;
411 smap[1] = (ch->unit == 0) ? 2 : 3;
412 } else if (map == 0x02 && ch->unit == 0) {
413 ch->flags |= ATA_SATA;
416 } else if (map == 0x01 && ch->unit == 1) {
417 ch->flags |= ATA_SATA;
422 if (ch->flags & ATA_SATA) {
423 if ((ctlr->chip->cfg1 & INTEL_ICH5)) {
424 ch->hw.pm_read = ata_intel_sata_cscr_read;
425 ch->hw.pm_write = ata_intel_sata_cscr_write;
426 } else if (ctlr->r_res2) {
427 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
428 ch->hw.pm_read = ata_intel_sata_ahci_read;
429 ch->hw.pm_write = ata_intel_sata_ahci_write;
430 } else if (ata_intel_sata_sidpr_test(dev)) {
431 ch->hw.pm_read = ata_intel_sata_sidpr_read;
432 ch->hw.pm_write = ata_intel_sata_sidpr_write;
435 if (ch->hw.pm_write != NULL) {
436 ch->flags |= ATA_PERIODIC_POLL;
437 ch->hw.status = ata_intel_sata_status;
438 ata_sata_scr_write(ch, 0,
439 ATA_SERROR, 0xffffffff);
440 if ((ch->flags & ATA_NO_SLAVE) == 0) {
441 ata_sata_scr_write(ch, 1,
442 ATA_SERROR, 0xffffffff);
446 ctlr->setmode = ata_intel_new_setmode;
447 } else if (ctlr->chip->chipid != ATA_ISCH)
448 ch->flags |= ATA_CHECKS_CABLE;
453 ata_intel_reset(device_t dev)
455 device_t parent = device_get_parent(dev);
456 struct ata_pci_controller *ctlr = device_get_softc(parent);
457 struct ata_channel *ch = device_get_softc(dev);
458 int mask, pshift, timeout, devs;
462 /* In combined mode, skip SATA stuff for PATA channel. */
463 if ((ch->flags & ATA_SATA) == 0)
464 return (ata_generic_reset(dev));
466 /* Do hard-reset on respective SATA ports. */
467 smap = ATA_INTEL_SMAP(ctlr, ch);
469 if ((ch->flags & ATA_NO_SLAVE) == 0)
470 mask |= (1 << smap[1]);
471 pci_write_config(parent, 0x92,
472 pci_read_config(parent, 0x92, 2) & ~mask, 2);
474 pci_write_config(parent, 0x92,
475 pci_read_config(parent, 0x92, 2) | mask, 2);
477 /* Wait up to 1 sec for "connect well". */
478 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2))
482 for (timeout = 0; timeout < 100 ; timeout++) {
483 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask;
484 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
490 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs);
491 /* If any device found, do soft-reset. */
492 if (ch->hw.pm_read != NULL) {
493 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0;
494 if ((ch->flags & ATA_NO_SLAVE) == 0)
495 devs |= ata_sata_phy_reset(dev, 1, 2) ?
498 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0;
499 if ((ch->flags & ATA_NO_SLAVE) == 0)
500 devs |= (pcs & (1 << smap[1])) ?
504 ata_generic_reset(dev);
505 /* Reset may give fake slave when only ATAPI master present. */
506 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER));
512 ata_intel_old_setmode(device_t dev, int target, int mode)
514 device_t parent = device_get_parent(dev);
515 struct ata_pci_controller *ctlr = device_get_softc(parent);
517 mode = min(mode, ctlr->chip->max_dma);
522 ata_intel_new_setmode(device_t dev, int target, int mode)
524 device_t parent = device_get_parent(dev);
525 struct ata_pci_controller *ctlr = device_get_softc(parent);
526 struct ata_channel *ch = device_get_softc(dev);
527 int devno = (ch->unit << 1) + target;
529 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
530 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
531 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
532 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
533 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
534 u_int32_t mask40 = 0, new40 = 0;
535 u_int8_t mask44 = 0, new44 = 0;
536 static const uint8_t timings[] =
537 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
538 static const uint8_t utimings[] =
539 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
541 /* In combined mode, skip PATA stuff for SATA channel. */
542 if (ch->flags & ATA_SATA)
543 return (ata_sata_setmode(dev, target, mode));
545 mode = min(mode, ctlr->chip->max_dma);
546 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
547 !(reg54 & (0x10 << devno))) {
548 ata_print_cable(dev, "controller");
551 /* Enable/disable UDMA and set timings. */
552 if (mode >= ATA_UDMA0) {
553 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
554 pci_write_config(parent, 0x4a,
555 (reg4a & ~(0x3 << (devno << 2))) |
556 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
559 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
560 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
564 /* Set UDMA reference clock (33/66/133MHz). */
565 reg54 &= ~(0x1001 << devno);
566 if (mode >= ATA_UDMA5)
567 reg54 |= (0x1000 << devno);
568 else if (mode >= ATA_UDMA3)
569 reg54 |= (0x1 << devno);
570 pci_write_config(parent, 0x54, reg54, 2);
571 /* Allow PIO/WDMA timing controls. */
572 reg40 &= ~0x00ff00ff;
574 /* Set PIO/WDMA timings. */
577 new40 = timings[ata_mode2idx(piomode)] << 8;
580 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
581 (timings[ata_mode2idx(piomode)] & 0x03);
589 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
590 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
595 ata_intel_sch_setmode(device_t dev, int target, int mode)
597 device_t parent = device_get_parent(dev);
598 struct ata_pci_controller *ctlr = device_get_softc(parent);
599 u_int8_t dtim = 0x80 + (target << 2);
600 u_int32_t tim = pci_read_config(parent, dtim, 4);
603 mode = min(mode, ctlr->chip->max_dma);
604 if (mode >= ATA_UDMA0) {
607 tim |= ((mode & ATA_MODE_MASK) << 16);
609 } else if (mode >= ATA_WDMA0) {
612 tim |= ((mode & ATA_MODE_MASK) << 8);
613 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
614 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
618 tim |= (piomode & 0x7);
619 pci_write_config(parent, dtim, tim, 4);
624 ata_intel_sata_getrev(device_t dev, int target)
626 struct ata_channel *ch = device_get_softc(dev);
629 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0)
630 return ((status & 0x0f0) >> 4);
635 ata_intel_sata_status(device_t dev)
637 struct ata_channel *ch = device_get_softc(dev);
639 ata_sata_phy_check_events(dev, 0);
640 if ((ch->flags & ATA_NO_SLAVE) == 0)
641 ata_sata_phy_check_events(dev, 1);
643 return ata_pci_status(dev);
647 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result)
649 struct ata_pci_controller *ctlr;
650 struct ata_channel *ch;
655 parent = device_get_parent(dev);
656 ctlr = device_get_softc(parent);
657 ch = device_get_softc(dev);
658 port = (port == 1) ? 1 : 0;
659 smap = ATA_INTEL_SMAP(ctlr, ch);
660 offset = 0x100 + smap[port] * 0x80;
674 *result = ATA_INL(ctlr->r_res2, offset + reg);
679 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result)
681 struct ata_pci_controller *ctlr;
682 struct ata_channel *ch;
686 parent = device_get_parent(dev);
687 ctlr = device_get_softc(parent);
688 ch = device_get_softc(dev);
689 smap = ATA_INTEL_SMAP(ctlr, ch);
690 port = (port == 1) ? 1 : 0;
704 ATA_INTEL_LOCK(ctlr);
705 pci_write_config(parent, 0xa0,
706 0x50 + smap[port] * 0x10 + reg * 4, 4);
707 *result = pci_read_config(parent, 0xa4, 4);
708 ATA_INTEL_UNLOCK(ctlr);
713 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result)
715 struct ata_pci_controller *ctlr;
716 struct ata_channel *ch;
719 parent = device_get_parent(dev);
720 ctlr = device_get_softc(parent);
721 ch = device_get_softc(dev);
722 port = (port == 1) ? 1 : 0;
736 ATA_INTEL_LOCK(ctlr);
737 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
738 *result = ATA_IDX_INL(ch, ATA_IDX_DATA);
739 ATA_INTEL_UNLOCK(ctlr);
744 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value)
746 struct ata_pci_controller *ctlr;
747 struct ata_channel *ch;
752 parent = device_get_parent(dev);
753 ctlr = device_get_softc(parent);
754 ch = device_get_softc(dev);
755 port = (port == 1) ? 1 : 0;
756 smap = ATA_INTEL_SMAP(ctlr, ch);
757 offset = 0x100 + smap[port] * 0x80;
771 ATA_OUTL(ctlr->r_res2, offset + reg, value);
776 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value)
778 struct ata_pci_controller *ctlr;
779 struct ata_channel *ch;
783 parent = device_get_parent(dev);
784 ctlr = device_get_softc(parent);
785 ch = device_get_softc(dev);
786 smap = ATA_INTEL_SMAP(ctlr, ch);
787 port = (port == 1) ? 1 : 0;
801 ATA_INTEL_LOCK(ctlr);
802 pci_write_config(parent, 0xa0,
803 0x50 + smap[port] * 0x10 + reg * 4, 4);
804 pci_write_config(parent, 0xa4, value, 4);
805 ATA_INTEL_UNLOCK(ctlr);
810 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value)
812 struct ata_pci_controller *ctlr;
813 struct ata_channel *ch;
816 parent = device_get_parent(dev);
817 ctlr = device_get_softc(parent);
818 ch = device_get_softc(dev);
819 port = (port == 1) ? 1 : 0;
833 ATA_INTEL_LOCK(ctlr);
834 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
835 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value);
836 ATA_INTEL_UNLOCK(ctlr);
841 ata_intel_sata_sidpr_test(device_t dev)
843 struct ata_channel *ch = device_get_softc(dev);
847 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1;
848 for (; port >= 0; port--) {
849 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val);
850 if ((val & ATA_SC_IPM_MASK) ==
851 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
853 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER;
854 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val);
855 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val);
856 if ((val & ATA_SC_IPM_MASK) ==
857 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
862 "SControl registers are not functional: %08x\n", val);
867 ata_intel_31244_ch_attach(device_t dev)
869 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
870 struct ata_channel *ch = device_get_softc(dev);
874 ata_pci_dmainit(dev);
876 ch_offset = 0x200 + ch->unit * 0x200;
878 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
879 ch->r_io[i].res = ctlr->r_res2;
881 /* setup ATA registers */
882 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
883 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
884 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
885 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
886 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
887 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
888 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
889 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
890 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
891 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
892 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
893 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
895 /* setup DMA registers */
896 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
897 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
898 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
900 /* setup SATA registers */
901 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
902 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
903 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
905 ch->flags |= ATA_NO_SLAVE;
906 ch->flags |= ATA_SATA;
908 ch->hw.status = ata_intel_31244_status;
909 ch->hw.tf_write = ata_intel_31244_tf_write;
911 /* enable PHY state change interrupt */
912 ATA_OUTL(ctlr->r_res2, 0x4,
913 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
918 ata_intel_31244_ch_detach(device_t dev)
921 ata_pci_dmafini(dev);
926 ata_intel_31244_status(device_t dev)
928 /* do we have any PHY events ? */
929 ata_sata_phy_check_events(dev, -1);
931 /* any drive action to take care of ? */
932 return ata_pci_status(dev);
936 ata_intel_31244_tf_write(struct ata_request *request)
938 struct ata_channel *ch = device_get_softc(request->parent);
940 struct ata_device *atadev = device_get_softc(request->dev);
943 if (request->flags & ATA_R_48BIT) {
944 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
945 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
946 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
947 (request->u.ata.lba & 0x00ff));
948 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
949 ((request->u.ata.lba >> 8) & 0x00ff));
950 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
951 ((request->u.ata.lba >> 16) & 0x00ff));
952 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
955 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
956 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
958 if (atadev->flags & ATA_D_USE_CHS) {
961 if (atadev->param.atavalid & ATA_FLAG_54_58) {
962 heads = atadev->param.current_heads;
963 sectors = atadev->param.current_sectors;
966 heads = atadev->param.heads;
967 sectors = atadev->param.sectors;
969 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
970 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
971 (request->u.ata.lba / (sectors * heads)));
972 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
973 (request->u.ata.lba / (sectors * heads)) >> 8);
974 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
975 (((request->u.ata.lba% (sectors * heads)) /
980 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
981 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
982 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
983 ATA_IDX_OUTB(ch, ATA_DRIVE,
984 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
985 ((request->u.ata.lba >> 24) & 0x0f));
993 ata_intel_31244_reset(device_t dev)
995 struct ata_channel *ch = device_get_softc(dev);
997 if (ata_sata_phy_reset(dev, -1, 1))
998 ata_generic_reset(dev);
1003 ATA_DECLARE_DRIVER(ata_intel);
1004 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);