2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_via_chipinit(device_t dev);
56 static int ata_via_ch_attach(device_t dev);
57 static int ata_via_ch_detach(device_t dev);
58 static void ata_via_reset(device_t dev);
59 static int ata_via_status(device_t dev);
60 static int ata_via_old_setmode(device_t dev, int target, int mode);
61 static void ata_via_southbridge_fixup(device_t dev);
62 static int ata_via_new_setmode(device_t dev, int target, int mode);
63 static int ata_via_sata_ch_attach(device_t dev);
64 static int ata_via_sata_getrev(device_t dev, int target);
65 static int ata_via_sata_setmode(device_t dev, int target, int mode);
81 * VIA Technologies Inc. chipset support functions
84 ata_via_probe(device_t dev)
86 struct ata_pci_controller *ctlr = device_get_softc(dev);
87 static struct ata_chip_id ids[] =
88 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
89 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
90 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
91 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
92 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
93 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
94 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
95 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
96 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
97 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
98 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
99 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
100 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
101 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
102 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
103 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
104 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
105 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
106 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" },
107 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" },
108 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" },
109 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" },
110 { 0, 0, 0, 0, 0, 0 }};
111 static struct ata_chip_id new_ids[] =
112 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
113 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
114 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
115 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
116 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
117 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
118 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
119 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
120 { 0, 0, 0, 0, 0, 0 }};
122 if (pci_get_vendor(dev) != ATA_VIA_ID)
125 if (pci_get_devid(dev) == ATA_VIA82C571 ||
126 pci_get_devid(dev) == ATA_VIACX700IDE ||
127 pci_get_devid(dev) == ATA_VIASATAIDE ||
128 pci_get_devid(dev) == ATA_VIASATAIDE2 ||
129 pci_get_devid(dev) == ATA_VIASATAIDE3) {
130 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
134 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
139 ctlr->chipinit = ata_via_chipinit;
140 return (BUS_PROBE_DEFAULT);
144 ata_via_chipinit(device_t dev)
146 struct ata_pci_controller *ctlr = device_get_softc(dev);
148 if (ata_setup_interrupt(dev, ata_generic_intr))
152 if (ctlr->chip->cfg2 & VIAAHCI) {
153 if (ata_ahci_chipinit(dev) != ENXIO)
156 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
157 if (ctlr->chip->cfg2 & VIASATA) {
158 ctlr->ch_attach = ata_via_sata_ch_attach;
159 ctlr->setmode = ata_via_sata_setmode;
160 ctlr->getrev = ata_via_sata_getrev;
163 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
164 if (ctlr->chip->max_dma >= ATA_SA150) {
165 ctlr->r_type2 = SYS_RES_IOPORT;
166 ctlr->r_rid2 = PCIR_BAR(5);
167 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
168 &ctlr->r_rid2, RF_ACTIVE))) {
169 ctlr->ch_attach = ata_via_ch_attach;
170 ctlr->ch_detach = ata_via_ch_detach;
171 ctlr->reset = ata_via_reset;
173 if (ctlr->chip->cfg2 & VIABAR) {
175 ctlr->setmode = ata_via_new_setmode;
177 ctlr->setmode = ata_sata_setmode;
178 ctlr->getrev = ata_sata_getrev;
182 /* prepare for ATA-66 on the 82C686a and 82C596b */
183 if (ctlr->chip->cfg2 & VIACLK)
184 pci_write_config(dev, 0x50, 0x030b030b, 4);
186 /* the southbridge might need the data corruption fix */
187 if (ctlr->chip->cfg2 & VIABUG)
188 ata_via_southbridge_fixup(dev);
190 /* set fifo configuration half'n'half */
191 pci_write_config(dev, 0x43,
192 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
194 /* set status register read retry */
195 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
197 /* set DMA read & end-of-sector fifo flush */
198 pci_write_config(dev, 0x46,
199 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
201 /* set sector size */
202 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
203 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
205 ctlr->setmode = ata_via_old_setmode;
210 ata_via_ch_attach(device_t dev)
212 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
213 struct ata_channel *ch = device_get_softc(dev);
215 /* newer SATA chips has resources in one BAR for each channel */
216 if (ctlr->chip->cfg2 & VIABAR) {
217 struct resource *r_io;
220 ata_pci_dmainit(dev);
222 rid = PCIR_BAR(ch->unit);
223 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
228 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
229 ch->r_io[i].res = r_io;
230 ch->r_io[i].offset = i;
232 ch->r_io[ATA_CONTROL].res = r_io;
233 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
234 ch->r_io[ATA_IDX_ADDR].res = r_io;
235 ata_default_registers(dev);
236 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
237 ch->r_io[i].res = ctlr->r_res1;
238 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
245 /* setup the usual register normal pci style */
246 if (ata_pci_ch_attach(dev))
250 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
251 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
252 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
253 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
254 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
255 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
256 ch->hw.status = ata_via_status;
257 ch->flags |= ATA_NO_SLAVE;
258 ch->flags |= ATA_SATA;
259 ch->flags |= ATA_PERIODIC_POLL;
261 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff);
267 ata_via_ch_detach(device_t dev)
269 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
270 struct ata_channel *ch = device_get_softc(dev);
272 /* newer SATA chips has resources in one BAR for each channel */
273 if (ctlr->chip->cfg2 & VIABAR) {
276 rid = PCIR_BAR(ch->unit);
277 bus_release_resource(device_get_parent(dev),
278 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res);
280 ata_pci_dmafini(dev);
283 /* setup the usual register normal pci style */
284 if (ata_pci_ch_detach(dev))
292 ata_via_reset(device_t dev)
294 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
295 struct ata_channel *ch = device_get_softc(dev);
297 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
298 ata_generic_reset(dev);
300 if (ata_sata_phy_reset(dev, -1, 1))
301 ata_generic_reset(dev);
308 ata_via_status(device_t dev)
311 ata_sata_phy_check_events(dev, -1);
312 return (ata_pci_status(dev));
316 ata_via_new_setmode(device_t dev, int target, int mode)
318 device_t parent = device_get_parent(dev);
319 struct ata_pci_controller *ctlr = device_get_softc(parent);
320 struct ata_channel *ch = device_get_softc(dev);
322 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
324 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20 };
325 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
327 /* This chip can't do WDMA. */
328 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0)
330 if (mode >= ATA_UDMA0) {
331 pci_write_config(parent, 0xb3,
332 dma_timings[mode & ATA_MODE_MASK], 1);
336 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
338 mode = ata_sata_setmode(dev, target, mode);
343 ata_via_old_setmode(device_t dev, int target, int mode)
345 device_t parent = device_get_parent(dev);
346 struct ata_pci_controller *ctlr = device_get_softc(parent);
347 struct ata_channel *ch = device_get_softc(dev);
348 int devno = (ch->unit << 1) + target;
349 int reg = 0x53 - devno;
351 uint8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
352 uint8_t modes[][7] = {
353 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
354 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
355 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
356 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
358 mode = min(mode, ctlr->chip->max_dma);
359 /* Set UDMA timings */
360 if (mode >= ATA_UDMA0) {
361 pci_write_config(parent, reg,
362 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
365 pci_write_config(parent, reg, 0x8b, 1);
368 /* Set WDMA/PIO timings */
369 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);
374 ata_via_southbridge_fixup(device_t dev)
379 if (device_get_children(device_get_parent(dev), &children, &nchildren))
382 for (i = 0; i < nchildren; i++) {
383 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
384 pci_get_devid(children[i]) == ATA_VIA8371 ||
385 pci_get_devid(children[i]) == ATA_VIA8662 ||
386 pci_get_devid(children[i]) == ATA_VIA8361) {
387 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
389 if ((reg76 & 0xf0) != 0xd0) {
391 "Correcting VIA config for southbridge data corruption bug\n");
392 pci_write_config(children[i], 0x75, 0x80, 1);
393 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
398 free(children, M_TEMP);
402 ata_via_sata_ch_attach(device_t dev)
404 struct ata_channel *ch = device_get_softc(dev);
406 if (ata_pci_ch_attach(dev))
409 ch->flags |= ATA_SATA;
414 ata_via_sata_getrev(device_t dev, int target)
416 struct ata_channel *ch = device_get_softc(dev);
424 ata_via_sata_setmode(device_t dev, int target, int mode)
426 struct ata_channel *ch = device_get_softc(dev);
430 return (ata_via_old_setmode(dev, target, mode));
433 ATA_DECLARE_DRIVER(ata_via);
434 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);