2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
3 * Copyright (c) 2008 Sam Leffler, Errno Consulting
4 * Copyright (c) 2008 Atheros Communications, Inc.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifndef _AH_EEPROM_V4K_H_
21 #define _AH_EEPROM_V4K_H_
23 #include "ah_eeprom.h"
24 #include "ah_eeprom_v14.h"
26 #if _BYTE_ORDER == _BIG_ENDIAN
27 #define __BIG_ENDIAN_BITFIELD
30 #define AR9285_RDEXT_DEFAULT 0x1F
32 #define AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT 58
34 #undef owl_eep_start_loc
35 #ifdef __LINUX_ARM_ARCH__ /* AP71 */
36 #define owl_eep_start_loc 0
38 #define owl_eep_start_loc 64
41 // 16-bit offset location start of calibration struct
42 #define AR5416_4K_EEP_START_LOC 64
43 #define AR5416_4K_NUM_2G_CAL_PIERS 3
44 #define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
45 #define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
46 #define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
47 #define AR5416_4K_NUM_CTLS 12
48 #define AR5416_4K_NUM_BAND_EDGES 4
49 #define AR5416_4K_NUM_PD_GAINS 2
50 #define AR5416_4K_MAX_CHAINS 1
53 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
54 * and length are swapped). We reverse their position after reading
55 * the data into host memory so the version field is at the same
56 * offset as in previous EEPROM layouts. This makes utilities that
57 * inspect the EEPROM contents work without looking at the PCI device
58 * id which may or may not be reliable.
60 typedef struct BaseEepHeader4k {
61 uint16_t version; /* NB: length in EEPROM */
63 uint16_t length; /* NB: version in EEPROM */
71 uint16_t blueToothOptions;
73 uint32_t binBuildNumber;
75 uint8_t txGainType; /* high power tx gain table support */
76 } __packed BASE_EEP4K_HEADER; // 32 B
78 typedef struct ModalEepHeader4k {
79 uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 4
80 uint32_t antCtrlCommon; // 4
81 int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
82 uint8_t switchSettling; // 1
83 uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
84 uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
85 uint8_t adcDesiredSize; // 1
86 int8_t pgaDesiredSize; // 1
87 uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
88 uint8_t txEndToXpaOff; // 1
89 uint8_t txEndToRxOn; // 1
90 uint8_t txFrameToXpaOn; // 1
91 uint8_t thresh62; // 1
92 uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
95 int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
96 int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
98 uint8_t pdGainOverlap; // 1
100 #ifdef __BIG_ENDIAN_BITFIELD
101 uint8_t ob_1:4, ob_0:4; // 1
102 uint8_t db1_1:4, db1_0:4; // 1
104 uint8_t ob_0:4, ob_1:4;
105 uint8_t db1_0:4, db1_1:4;
108 uint8_t xpaBiasLvl; // 1
109 uint8_t txFrameToDataStart; // 1
110 uint8_t txFrameToPaOn; // 1
111 uint8_t ht40PowerIncForPdadc; // 1
112 uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
113 uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
114 uint8_t swSettleHt40; // 1
115 uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
116 uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
118 #ifdef __BIG_ENDIAN_BITFIELD
119 uint8_t db2_1:4, db2_0:4; // 1
121 uint8_t db2_0:4, db2_1:4; // 1
124 uint8_t version; // 1
126 #ifdef __BIG_ENDIAN_BITFIELD
127 uint8_t ob_3:4, ob_2:4; // 1
128 uint8_t antdiv_ctl1:4, ob_4:4; // 1
129 uint8_t db1_3:4, db1_2:4; // 1
130 uint8_t antdiv_ctl2:4, db1_4:4; // 1
131 uint8_t db2_2:4, db2_3:4; // 1
132 uint8_t reserved:4, db2_4:4; // 1
134 uint8_t ob_2:4, ob_3:4;
135 uint8_t ob_4:4, antdiv_ctl1:4;
136 uint8_t db1_2:4, db1_3:4;
137 uint8_t db1_4:4, antdiv_ctl2:4;
138 uint8_t db2_2:4, db2_3:4;
139 uint8_t db2_4:4, reserved:4;
141 uint8_t tx_diversity;
142 uint8_t flc_pwr_thresh;
143 uint8_t bb_scale_smrt_antenna;
144 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
145 uint8_t futureModal[1];
147 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
148 } __packed MODAL_EEP4K_HEADER; // == 68 B
150 typedef struct CalCtlData4k {
151 CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
152 } __packed CAL_CTL_DATA_4K;
154 typedef struct calDataPerFreq4k {
155 uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
156 uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
157 } __packed CAL_DATA_PER_FREQ_4K;
159 struct ar5416eeprom_4k {
160 BASE_EEP4K_HEADER baseEepHeader; // 32 B
161 uint8_t custData[20]; // 20 B
162 MODAL_EEP4K_HEADER modalHeader; // 68 B
163 uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
164 CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
165 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
166 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
167 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
168 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
169 uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
170 CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
175 struct ar5416eeprom_4k ee_base;
178 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
179 /* XXX these are dynamically calculated for use by shared code */
180 int8_t ee_antennaGainMax;
182 #endif /* _AH_EEPROM_V4K_H_ */