2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
32 ar5212GetRxDP(struct ath_hal *ath)
34 return OS_REG_READ(ath, AR_RXDP);
41 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
43 OS_REG_WRITE(ah, AR_RXDP, rxdp);
44 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
48 * Set Receive Enable bits.
51 ar5212EnableReceive(struct ath_hal *ah)
53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
57 * Stop Receive at the DMA engine
60 ar5212StopDmaReceive(struct ath_hal *ah)
62 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
63 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
64 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
65 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
67 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
68 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
70 OS_REG_READ(ah, AR_CR),
71 OS_REG_READ(ah, AR_DIAG_SW));
80 * Start Transmit at the PCU engine (unpause receive)
83 ar5212StartPcuReceive(struct ath_hal *ah)
85 struct ath_hal_private *ahp = AH_PRIVATE(ah);
87 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START);
88 OS_REG_WRITE(ah, AR_DIAG_SW,
89 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
90 ar5212EnableMibCounters(ah);
91 /* NB: restore current settings */
92 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
96 * Stop Transmit at the PCU engine (pause receive)
99 ar5212StopPcuReceive(struct ath_hal *ah)
101 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP);
102 OS_REG_WRITE(ah, AR_DIAG_SW,
103 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
104 ar5212DisableMibCounters(ah);
108 * Set multicast filter 0 (lower 32-bits)
109 * filter 1 (upper 32-bits)
112 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
114 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
115 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
119 * Clear multicast filter by index
122 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
129 val = OS_REG_READ(ah, AR_MCAST_FIL1);
130 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
132 val = OS_REG_READ(ah, AR_MCAST_FIL0);
133 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
139 * Set multicast filter by index
142 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
149 val = OS_REG_READ(ah, AR_MCAST_FIL1);
150 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
152 val = OS_REG_READ(ah, AR_MCAST_FIL0);
153 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
159 * Get the receive filter.
162 ar5212GetRxFilter(struct ath_hal *ah)
164 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
165 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
166 if (phybits & AR_PHY_ERR_RADAR)
167 bits |= HAL_RX_FILTER_PHYRADAR;
168 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
169 bits |= HAL_RX_FILTER_PHYERR;
170 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
171 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
172 bits |= HAL_RX_FILTER_BSSID;
177 * Set the receive filter.
180 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
182 struct ath_hal_5212 *ahp = AH5212(ah);
185 OS_REG_WRITE(ah, AR_RX_FILTER,
186 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
187 HAL_RX_FILTER_BSSID));
189 if (bits & HAL_RX_FILTER_PHYRADAR)
190 phybits |= AR_PHY_ERR_RADAR;
191 if (bits & HAL_RX_FILTER_PHYERR)
192 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
193 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
195 OS_REG_WRITE(ah, AR_RXCFG,
196 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
198 OS_REG_WRITE(ah, AR_RXCFG,
199 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
201 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
202 if (bits & HAL_RX_FILTER_BSSID)
203 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
205 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
206 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
211 * Initialize RX descriptor, by clearing the status and setting
212 * the size (and any other flags).
215 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
216 uint32_t size, u_int flags)
218 struct ar5212_desc *ads = AR5212DESC(ds);
220 HALASSERT((size &~ AR_BufLen) == 0);
223 ads->ds_ctl1 = size & AR_BufLen;
225 if (flags & HAL_RXDESC_INTREQ)
226 ads->ds_ctl1 |= AR_RxInterReq;
227 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
233 * Process an RX descriptor, and return the status to the caller.
234 * Copy some hardware specific items into the software portion
237 * NB: the caller is responsible for validating the memory contents
238 * of the descriptor (e.g. flushing any cached copy).
241 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
242 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
243 struct ath_rx_status *rs)
245 struct ar5212_desc *ads = AR5212DESC(ds);
246 struct ar5212_desc *ands = AR5212DESC(nds);
248 if ((ads->ds_rxstatus1 & AR_Done) == 0)
249 return HAL_EINPROGRESS;
251 * Given the use of a self-linked tail be very sure that the hw is
252 * done with this descriptor; the hw may have done this descriptor
253 * once and picked it up again...make sure the hw has moved on.
255 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
256 return HAL_EINPROGRESS;
258 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
259 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
261 /* XXX what about KeyCacheMiss? */
262 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
263 /* discard invalid h/w rssi data */
264 if (rs->rs_rssi == -128)
266 if (ads->ds_rxstatus1 & AR_KeyIdxValid)
267 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
269 rs->rs_keyix = HAL_RXKEYIX_INVALID;
270 /* NB: caller expected to do rate table mapping */
271 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
272 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
273 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
275 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
277 * These four bits should not be set together. The
278 * 5212 spec states a Michael error can only occur if
279 * DecryptCRCErr not set (and TKIP is used). Experience
280 * indicates however that you can also get Michael errors
281 * when a CRC error is detected, but these are specious.
282 * Consequently we filter them out here so we don't
283 * confuse and/or complicate drivers.
285 if (ads->ds_rxstatus1 & AR_CRCErr)
286 rs->rs_status |= HAL_RXERR_CRC;
287 else if (ads->ds_rxstatus1 & AR_PHYErr) {
290 rs->rs_status |= HAL_RXERR_PHY;
291 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
292 rs->rs_phyerr = phyerr;
293 if (!AH5212(ah)->ah_hasHwPhyCounters &&
294 phyerr != HAL_PHYERR_RADAR)
295 ar5212AniPhyErrReport(ah, rs);
296 } else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
297 rs->rs_status |= HAL_RXERR_DECRYPT;
298 else if (ads->ds_rxstatus1 & AR_MichaelErr)
299 rs->rs_status |= HAL_RXERR_MIC;