sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2010 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5706S A2, A3
  38  *   BCM5708C B1, B2
  39  *   BCM5708S B1, B2
  40  *   BCM5709C A1, C0
  41  *   BCM5709S A1, C0
  42  *   BCM5716C C0
  43  *   BCM5716S C0
  44  *
  45  * The following controllers are not supported by this driver:
  46  *   BCM5706C A0, A1 (pre-production)
  47  *   BCM5706S A0, A1 (pre-production)
  48  *   BCM5708C A0, B0 (pre-production)
  49  *   BCM5708S A0, B0 (pre-production)
  50  *   BCM5709C A0  B0, B1, B2 (pre-production)
  51  *   BCM5709S A0, B0, B1, B2 (pre-production)
  52  */
  53
  54 #include "opt_bce.h"
  55
  56 #include <dev/bce/if_bcereg.h>
  57 #include <dev/bce/if_bcefw.h>
  58
  59 /****************************************************************************/
  60 /* BCE Debug Options                                                        */
  61 /****************************************************************************/
  62 #ifdef BCE_DEBUG
  63         u32 bce_debug = BCE_WARN;
  64
  65         /*          0 = Never              */
  66         /*          1 = 1 in 2,147,483,648 */
  67         /*        256 = 1 in     8,388,608 */
  68         /*       2048 = 1 in     1,048,576 */
  69         /*      65536 = 1 in        32,768 */
  70         /*    1048576 = 1 in         2,048 */
  71         /*  268435456 = 1 in             8 */
  72         /*  536870912 = 1 in             4 */
  73         /* 1073741824 = 1 in             2 */
  74
  75         /* Controls how often the l2_fhdr frame error check will fail. */
  76         int l2fhdr_error_sim_control = 0;
  77
  78         /* Controls how often the unexpected attention check will fail. */
  79         int unexpected_attention_sim_control = 0;
  80
  81         /* Controls how often to simulate an mbuf allocation failure. */
  82         int mbuf_alloc_failed_sim_control = 0;
  83
  84         /* Controls how often to simulate a DMA mapping failure. */
  85         int dma_map_addr_failed_sim_control = 0;
  86
  87         /* Controls how often to simulate a bootcode failure. */
  88         int bootcode_running_failure_sim_control = 0;
  89 #endif
  90
  91 /****************************************************************************/
  92 /* PCI Device ID Table                                                      */
  93 /*                                                                          */
  94 /* Used by bce_probe() to identify the devices supported by this driver.    */
  95 /****************************************************************************/
  96 #define BCE_DEVDESC_MAX         64
  97
  98 static const struct bce_type bce_devs[] = {
  99         /* BCM5706C Controllers and OEM boards. */
 100         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 101                 "HP NC370T Multifunction Gigabit Server Adapter" },
 102         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 103                 "HP NC370i Multifunction Gigabit Server Adapter" },
 104         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 105                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 107                 "HP NC371i Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 109                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 110
 111         /* BCM5706S controllers and OEM boards. */
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 113                 "HP NC370F Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 116
 117         /* BCM5708C controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 119                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 121                 "HP NC373i Multifunction Gigabit Server Adapter" },
 122         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 123                 "HP NC374m PCIe Multifunction Adapter" },
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 125                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 126
 127         /* BCM5708S controllers and OEM boards. */
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 129                 "HP NC373m Multifunction Gigabit Server Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 131                 "HP NC373i Multifunction Gigabit Server Adapter" },
 132         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 133                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 135                 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 136
 137         /* BCM5709C controllers and OEM boards. */
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 139                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 141                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 143                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 144
 145         /* BCM5709S controllers and OEM boards. */
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 147                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 149                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 151                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 152
 153         /* BCM5716 controllers and OEM boards. */
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 155                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 156
 157         { 0, 0, 0, 0, NULL }
 158 };
 159
 160
 161 /****************************************************************************/
 162 /* Supported Flash NVRAM device data.                                       */
 163 /****************************************************************************/
 164 static const struct flash_spec flash_table[] =
 165 {
 166 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 167 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 168
 169         /* Slow EEPROM */
 170         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 171          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 172          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 173          "EEPROM - slow"},
 174         /* Expansion entry 0001 */
 175         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 177          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 178          "Entry 0001"},
 179         /* Saifun SA25F010 (non-buffered flash) */
 180         /* strap, cfg1, & write1 need updates */
 181         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 184          "Non-buffered flash (128kB)"},
 185         /* Saifun SA25F020 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 190          "Non-buffered flash (256kB)"},
 191         /* Expansion entry 0100 */
 192         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 0100"},
 196         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 197         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 199          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 200          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 201         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 202         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 204          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 205          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 206         /* Saifun SA25F005 (non-buffered flash) */
 207         /* strap, cfg1, & write1 need updates */
 208         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 210          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 211          "Non-buffered flash (64kB)"},
 212         /* Fast EEPROM */
 213         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 214          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 215          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 216          "EEPROM - fast"},
 217         /* Expansion entry 1001 */
 218         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 219          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 220          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 221          "Entry 1001"},
 222         /* Expansion entry 1010 */
 223         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 224          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 225          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 226          "Entry 1010"},
 227         /* ATMEL AT45DB011B (buffered flash) */
 228         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 229          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 230          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 231          "Buffered flash (128kB)"},
 232         /* Expansion entry 1100 */
 233         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 234          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 235          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 236          "Entry 1100"},
 237         /* Expansion entry 1101 */
 238         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 1101"},
 242         /* Ateml Expansion entry 1110 */
 243         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 244          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 245          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 246          "Entry 1110 (Atmel)"},
 247         /* ATMEL AT45DB021B (buffered flash) */
 248         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 249          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 250          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 251          "Buffered flash (256kB)"},
 252 };
 253
 254 /*
 255  * The BCM5709 controllers transparently handle the
 256  * differences between Atmel 264 byte pages and all
 257  * flash devices which use 256 byte pages, so no
 258  * logical-to-physical mapping is required in the
 259  * driver.
 260  */
 261 static const struct flash_spec flash_5709 = {
 262         .flags          = BCE_NV_BUFFERED,
 263         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 264         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 265         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 266         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 267         .name           = "5709/5716 buffered flash (256kB)",
 268 };
 269
 270
 271 /****************************************************************************/
 272 /* FreeBSD device entry points.                                             */
 273 /****************************************************************************/
 274 static int  bce_probe                   (device_t);
 275 static int  bce_attach                  (device_t);
 276 static int  bce_detach                  (device_t);
 277 static int  bce_shutdown                (device_t);
 278
 279
 280 /****************************************************************************/
 281 /* BCE Debug Data Structure Dump Routines                                   */
 282 /****************************************************************************/
 283 #ifdef BCE_DEBUG
 284 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 285 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 286 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 287 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 288 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 289 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 290 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 291 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 292 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 293 static void bce_dump_txbd                       (struct bce_softc *,
 294     int, struct tx_bd *);
 295 static void bce_dump_rxbd                       (struct bce_softc *,
 296     int, struct rx_bd *);
 297 static void bce_dump_pgbd                       (struct bce_softc *,
 298     int, struct rx_bd *);
 299 static void bce_dump_l2fhdr             (struct bce_softc *,
 300     int, struct l2_fhdr *);
 301 static void bce_dump_ctx                        (struct bce_softc *, u16);
 302 static void bce_dump_ftqs                       (struct bce_softc *);
 303 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 304 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 305 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 306 static void bce_dump_status_block       (struct bce_softc *);
 307 static void bce_dump_stats_block        (struct bce_softc *);
 308 static void bce_dump_driver_state       (struct bce_softc *);
 309 static void bce_dump_hw_state           (struct bce_softc *);
 310 static void bce_dump_shmem_state        (struct bce_softc *);
 311 static void bce_dump_mq_regs            (struct bce_softc *);
 312 static void bce_dump_bc_state           (struct bce_softc *);
 313 static void bce_dump_txp_state          (struct bce_softc *, int);
 314 static void bce_dump_rxp_state          (struct bce_softc *, int);
 315 static void bce_dump_tpat_state (struct bce_softc *, int);
 316 static void bce_dump_cp_state           (struct bce_softc *, int);
 317 static void bce_dump_com_state          (struct bce_softc *, int);
 318 static void bce_dump_rv2p_state (struct bce_softc *);
 319 static void bce_breakpoint                      (struct bce_softc *);
 320 #endif /*BCE_DEBUG */
 321
 322
 323 /****************************************************************************/
 324 /* BCE Register/Memory Access Routines                                      */
 325 /****************************************************************************/
 326 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 327 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 328 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 329 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 330 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 331 static int  bce_miibus_read_reg         (device_t, int, int);
 332 static int  bce_miibus_write_reg        (device_t, int, int, int);
 333 static void bce_miibus_statchg          (device_t);
 334
 335 #ifdef BCE_DEBUG
 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 337 #ifdef BCE_NVRAM_WRITE_SUPPORT
 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 339 #endif
 340 #endif
 341
 342 /****************************************************************************/
 343 /* BCE NVRAM Access Routines                                                */
 344 /****************************************************************************/
 345 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 346 static int  bce_release_nvram_lock      (struct bce_softc *);
 347 static void bce_enable_nvram_access(struct bce_softc *);
 348 static void bce_disable_nvram_access(struct bce_softc *);
 349 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 350 static int  bce_init_nvram                      (struct bce_softc *);
 351 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 352 static int  bce_nvram_test                      (struct bce_softc *);
 353 #ifdef BCE_NVRAM_WRITE_SUPPORT
 354 static int  bce_enable_nvram_write      (struct bce_softc *);
 355 static void bce_disable_nvram_write(struct bce_softc *);
 356 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 357 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 358 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 359 #endif
 360
 361 /****************************************************************************/
 362 /*                                                                          */
 363 /****************************************************************************/
 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 365 static void bce_get_media                       (struct bce_softc *);
 366 static void bce_init_media                      (struct bce_softc *);
 367 static u32 bce_get_rphy_link            (struct bce_softc *);
 368 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 369 static int  bce_dma_alloc                       (device_t);
 370 static void bce_dma_free                        (struct bce_softc *);
 371 static void bce_release_resources       (struct bce_softc *);
 372
 373 /****************************************************************************/
 374 /* BCE Firmware Synchronization and Load                                    */
 375 /****************************************************************************/
 376 static void bce_fw_cap_init                     (struct bce_softc *);
 377 static int  bce_fw_sync                 (struct bce_softc *, u32);
 378 static void bce_load_rv2p_fw            (struct bce_softc *, u32 *, u32, u32);
 379 static void bce_load_cpu_fw             (struct bce_softc *,
 380     struct cpu_reg *, struct fw_info *);
 381 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 382 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 383 static void bce_start_rxp_cpu           (struct bce_softc *);
 384 static void bce_init_rxp_cpu            (struct bce_softc *);
 385 static void bce_init_txp_cpu            (struct bce_softc *);
 386 static void bce_init_tpat_cpu           (struct bce_softc *);
 387 static void bce_init_cp_cpu             (struct bce_softc *);
 388 static void bce_init_com_cpu            (struct bce_softc *);
 389 static void bce_init_cpus                       (struct bce_softc *);
 390
 391 static void bce_print_adapter_info      (struct bce_softc *);
 392 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 393 static void bce_stop                            (struct bce_softc *);
 394 static int  bce_reset                           (struct bce_softc *, u32);
 395 static int  bce_chipinit                        (struct bce_softc *);
 396 static int  bce_blockinit                       (struct bce_softc *);
 397
 398 static int  bce_init_tx_chain           (struct bce_softc *);
 399 static void bce_free_tx_chain           (struct bce_softc *);
 400
 401 static int  bce_get_rx_buf                      (struct bce_softc *,
 402     struct mbuf *, u16 *, u16 *, u32 *);
 403 static int  bce_init_rx_chain           (struct bce_softc *);
 404 static void bce_fill_rx_chain           (struct bce_softc *);
 405 static void bce_free_rx_chain           (struct bce_softc *);
 406
 407 static int  bce_get_pg_buf                      (struct bce_softc *,
 408     struct mbuf *, u16 *, u16 *);
 409 static int  bce_init_pg_chain           (struct bce_softc *);
 410 static void bce_fill_pg_chain           (struct bce_softc *);
 411 static void bce_free_pg_chain           (struct bce_softc *);
 412
 413 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 414     struct mbuf **, u16 *);
 415 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 416 static void bce_start_locked            (struct ifnet *);
 417 static void bce_start                           (struct ifnet *);
 418 static int  bce_ioctl                           (struct ifnet *, u_long, caddr_t);
 419 static void bce_watchdog                        (struct bce_softc *);
 420 static int  bce_ifmedia_upd             (struct ifnet *);
 421 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 422 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 423 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 424 static void bce_init_locked             (struct bce_softc *);
 425 static void bce_init                            (void *);
 426 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 427
 428 static int  bce_init_ctx                        (struct bce_softc *);
 429 static void bce_get_mac_addr            (struct bce_softc *);
 430 static void bce_set_mac_addr            (struct bce_softc *);
 431 static void bce_phy_intr                        (struct bce_softc *);
 432 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 433 static void bce_rx_intr                 (struct bce_softc *);
 434 static void bce_tx_intr                 (struct bce_softc *);
 435 static void bce_disable_intr            (struct bce_softc *);
 436 static void bce_enable_intr             (struct bce_softc *, int);
 437
 438 static void bce_intr                            (void *);
 439 static void bce_set_rx_mode             (struct bce_softc *);
 440 static void bce_stats_update            (struct bce_softc *);
 441 static void bce_tick                            (void *);
 442 static void bce_pulse                           (void *);
 443 static void bce_add_sysctls             (struct bce_softc *);
 444
 445
 446 /****************************************************************************/
 447 /* FreeBSD device dispatch table.                                           */
 448 /****************************************************************************/
 449 static device_method_t bce_methods[] = {
 450         /* Device interface (device_if.h) */
 451         DEVMETHOD(device_probe,         bce_probe),
 452         DEVMETHOD(device_attach,        bce_attach),
 453         DEVMETHOD(device_detach,        bce_detach),
 454         DEVMETHOD(device_shutdown,      bce_shutdown),
 455 /* Supported by device interface but not used here. */
 456 /*      DEVMETHOD(device_identify,      bce_identify),      */
 457 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 458 /*      DEVMETHOD(device_resume,        bce_resume),        */
 459 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 460
 461         /* MII interface (miibus_if.h) */
 462         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 463         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 464         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 465 /* Supported by MII interface but not used here.       */
 466 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 467 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 468
 469         DEVMETHOD_END
 470 };
 471
 472 static driver_t bce_driver = {
 473         "bce",
 474         bce_methods,
 475         sizeof(struct bce_softc)
 476 };
 477
 478 static devclass_t bce_devclass;
 479
 480 MODULE_DEPEND(bce, pci, 1, 1, 1);
 481 MODULE_DEPEND(bce, ether, 1, 1, 1);
 482 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 483
 484 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 485 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 486
 487
 488 /****************************************************************************/
 489 /* Tunable device values                                                    */
 490 /****************************************************************************/
 491 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 492
 493 /* Allowable values are TRUE or FALSE */
 494 static int bce_verbose = TRUE;
 495 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
 496 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 497     "Verbose output enable/disable");
 498
 499 /* Allowable values are TRUE or FALSE */
 500 static int bce_tso_enable = TRUE;
 501 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 502 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 503     "TSO Enable/Disable");
 504
 505 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 506 /* ToDo: Add MSI-X support. */
 507 static int bce_msi_enable = 1;
 508 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 509 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 510     "MSI-X|MSI|INTx selector");
 511
 512 /* Allowable values are 1, 2, 4, 8. */
 513 static int bce_rx_pages = DEFAULT_RX_PAGES;
 514 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 515 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 516     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 517
 518 /* Allowable values are 1, 2, 4, 8. */
 519 static int bce_tx_pages = DEFAULT_TX_PAGES;
 520 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 521 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 522     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 523
 524 /* Allowable values are TRUE or FALSE. */
 525 static int bce_hdr_split = TRUE;
 526 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
 527 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 528     "Frame header/payload splitting Enable/Disable");
 529
 530 /* Allowable values are TRUE or FALSE. */
 531 static int bce_strict_rx_mtu = FALSE;
 532 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
 533 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN,
 534     &bce_strict_rx_mtu, 0,
 535     "Enable/Disable strict RX frame size checking");
 536
 537 /* Allowable values are 0 ... 100 */
 538 #ifdef BCE_DEBUG
 539 /* Generate 1 interrupt for every transmit completion. */
 540 static int bce_tx_quick_cons_trip_int = 1;
 541 #else
 542 /* Generate 1 interrupt for every 20 transmit completions. */
 543 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 544 #endif
 545 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
 546 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 547     &bce_tx_quick_cons_trip_int, 0,
 548     "Transmit BD trip point during interrupts");
 549
 550 /* Allowable values are 0 ... 100 */
 551 /* Generate 1 interrupt for every transmit completion. */
 552 #ifdef BCE_DEBUG
 553 static int bce_tx_quick_cons_trip = 1;
 554 #else
 555 /* Generate 1 interrupt for every 20 transmit completions. */
 556 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 557 #endif
 558 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
 559 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 560     &bce_tx_quick_cons_trip, 0,
 561     "Transmit BD trip point");
 562
 563 /* Allowable values are 0 ... 100 */
 564 #ifdef BCE_DEBUG
 565 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 566 static int bce_tx_ticks_int = 0;
 567 #else
 568 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 569 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 570 #endif
 571 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 572 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 573     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 574
 575 /* Allowable values are 0 ... 100 */
 576 #ifdef BCE_DEBUG
 577 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 578 static int bce_tx_ticks = 0;
 579 #else
 580 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 581 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 582 #endif
 583 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 584 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 585     &bce_tx_ticks, 0, "Transmit ticks count");
 586
 587 /* Allowable values are 1 ... 100 */
 588 #ifdef BCE_DEBUG
 589 /* Generate 1 interrupt for every received frame. */
 590 static int bce_rx_quick_cons_trip_int = 1;
 591 #else
 592 /* Generate 1 interrupt for every 6 received frames. */
 593 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 594 #endif
 595 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
 596 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 597     &bce_rx_quick_cons_trip_int, 0,
 598     "Receive BD trip point duirng interrupts");
 599
 600 /* Allowable values are 1 ... 100 */
 601 #ifdef BCE_DEBUG
 602 /* Generate 1 interrupt for every received frame. */
 603 static int bce_rx_quick_cons_trip = 1;
 604 #else
 605 /* Generate 1 interrupt for every 6 received frames. */
 606 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 607 #endif
 608 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
 609 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 610     &bce_rx_quick_cons_trip, 0,
 611     "Receive BD trip point");
 612
 613 /* Allowable values are 0 ... 100 */
 614 #ifdef BCE_DEBUG
 615 /* Generate an int. if 0us have elapsed since the last received frame. */
 616 static int bce_rx_ticks_int = 0;
 617 #else
 618 /* Generate an int. if 18us have elapsed since the last received frame. */
 619 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 620 #endif
 621 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 622 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 623     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 624
 625 /* Allowable values are 0 ... 100 */
 626 #ifdef BCE_DEBUG
 627 /* Generate an int. if 0us have elapsed since the last received frame. */
 628 static int bce_rx_ticks = 0;
 629 #else
 630 /* Generate an int. if 18us have elapsed since the last received frame. */
 631 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 632 #endif
 633 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 634 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 635     &bce_rx_ticks, 0, "Receive ticks count");
 636
 637
 638 /****************************************************************************/
 639 /* Device probe function.                                                   */
 640 /*                                                                          */
 641 /* Compares the device to the driver's list of supported devices and        */
 642 /* reports back to the OS whether this is the right driver for the device.  */
 643 /*                                                                          */
 644 /* Returns:                                                                 */
 645 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 646 /****************************************************************************/
 647 static int
 648 bce_probe(device_t dev)
 649 {
 650         const struct bce_type *t;
 651         struct bce_softc *sc;
 652         char *descbuf;
 653         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 654
 655         t = bce_devs;
 656
 657         sc = device_get_softc(dev);
 658         sc->bce_unit = device_get_unit(dev);
 659         sc->bce_dev = dev;
 660
 661         /* Get the data for the device to be probed. */
 662         vid  = pci_get_vendor(dev);
 663         did  = pci_get_device(dev);
 664         svid = pci_get_subvendor(dev);
 665         sdid = pci_get_subdevice(dev);
 666
 667         DBPRINT(sc, BCE_EXTREME_LOAD,
 668             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 669             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 670
 671         /* Look through the list of known devices for a match. */
 672         while(t->bce_name != NULL) {
 673
 674                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 675                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 676                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 677
 678                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 679
 680                         if (descbuf == NULL)
 681                                 return(ENOMEM);
 682
 683                         /* Print out the device identity. */
 684                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 685                             t->bce_name, (((pci_read_config(dev,
 686                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 687                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 688
 689                         device_set_desc_copy(dev, descbuf);
 690                         free(descbuf, M_TEMP);
 691                         return(BUS_PROBE_DEFAULT);
 692                 }
 693                 t++;
 694         }
 695
 696         return(ENXIO);
 697 }
 698
 699
 700 /****************************************************************************/
 701 /* PCI Capabilities Probe Function.                                         */
 702 /*                                                                          */
 703 /* Walks the PCI capabiites list for the device to find what features are   */
 704 /* supported.                                                               */
 705 /*                                                                          */
 706 /* Returns:                                                                 */
 707 /*   None.                                                                  */
 708 /****************************************************************************/
 709 static void
 710 bce_print_adapter_info(struct bce_softc *sc)
 711 {
 712         int i = 0;
 713
 714         DBENTER(BCE_VERBOSE_LOAD);
 715
 716         if (bce_verbose || bootverbose) {
 717                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 718                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 719                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 720
 721
 722                 /* Bus info. */
 723                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 724                         printf("Bus (PCIe x%d, ", sc->link_width);
 725                         switch (sc->link_speed) {
 726                         case 1: printf("2.5Gbps); "); break;
 727                         case 2: printf("5Gbps); "); break;
 728                         default: printf("Unknown link speed); ");
 729                         }
 730                 } else {
 731                         printf("Bus (PCI%s, %s, %dMHz); ",
 732                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 733                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 734                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 735                 }
 736
 737                 /* Firmware version and device features. */
 738                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 739                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 740                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 741
 742                 if (bce_hdr_split == TRUE) {
 743                         printf("SPLT");
 744                         i++;
 745                 }
 746
 747                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 748                         if (i > 0) printf("|");
 749                         printf("MSI"); i++;
 750                 }
 751
 752                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 753                         if (i > 0) printf("|");
 754                         printf("MSI-X"); i++;
 755                 }
 756
 757                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 758                         if (i > 0) printf("|");
 759                         printf("2.5G"); i++;
 760                 }
 761
 762                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 763                         if (i > 0) printf("|");
 764                         printf("Remote PHY(%s)",
 765                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 766                             "FIBER" : "TP"); i++;
 767                 }
 768
 769                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 770                         if (i > 0) printf("|");
 771                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 772                 } else {
 773                         printf(")\n");
 774                 }
 775
 776                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 777                     sc->bce_rx_quick_cons_trip_int,
 778                     sc->bce_rx_quick_cons_trip,
 779                     sc->bce_rx_ticks_int,
 780                     sc->bce_rx_ticks,
 781                     sc->bce_tx_quick_cons_trip_int,
 782                     sc->bce_tx_quick_cons_trip,
 783                     sc->bce_tx_ticks_int,
 784                     sc->bce_tx_ticks);
 785
 786         }
 787
 788         DBEXIT(BCE_VERBOSE_LOAD);
 789 }
 790
 791
 792 /****************************************************************************/
 793 /* PCI Capabilities Probe Function.                                         */
 794 /*                                                                          */
 795 /* Walks the PCI capabiites list for the device to find what features are   */
 796 /* supported.                                                               */
 797 /*                                                                          */
 798 /* Returns:                                                                 */
 799 /*   None.                                                                  */
 800 /****************************************************************************/
 801 static void
 802 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 803 {
 804         u32 reg;
 805
 806         DBENTER(BCE_VERBOSE_LOAD);
 807
 808         /* Check if PCI-X capability is enabled. */
 809         if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {
 810                 if (reg != 0)
 811                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 812         }
 813
 814         /* Check if PCIe capability is enabled. */
 815         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 816                 if (reg != 0) {
 817                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 818                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 819                             "0x%08X\n", link_status);
 820                         sc->link_speed = link_status & 0xf;
 821                         sc->link_width = (link_status >> 4) & 0x3f;
 822                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 823                         sc->bce_flags |= BCE_PCIE_FLAG;
 824                 }
 825         }
 826
 827         /* Check if MSI capability is enabled. */
 828         if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {
 829                 if (reg != 0)
 830                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 831         }
 832
 833         /* Check if MSI-X capability is enabled. */
 834         if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {
 835                 if (reg != 0)
 836                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 837         }
 838
 839         DBEXIT(BCE_VERBOSE_LOAD);
 840 }
 841
 842
 843 /****************************************************************************/
 844 /* Load and validate user tunable settings.                                 */
 845 /*                                                                          */
 846 /* Returns:                                                                 */
 847 /*   Nothing.                                                               */
 848 /****************************************************************************/
 849 static void
 850 bce_set_tunables(struct bce_softc *sc)
 851 {
 852         /* Set sysctl values for RX page count. */
 853         switch (bce_rx_pages) {
 854         case 1:
 855                 /* fall-through */
 856         case 2:
 857                 /* fall-through */
 858         case 4:
 859                 /* fall-through */
 860         case 8:
 861                 sc->rx_pages = bce_rx_pages;
 862                 break;
 863         default:
 864                 sc->rx_pages = DEFAULT_RX_PAGES;
 865                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 866                     "hw.bce.rx_pages!  Setting default of %d.\n",
 867                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 868         }
 869
 870         /* ToDo: Consider allowing user setting for pg_pages. */
 871         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 872
 873         /* Set sysctl values for TX page count. */
 874         switch (bce_tx_pages) {
 875         case 1:
 876                 /* fall-through */
 877         case 2:
 878                 /* fall-through */
 879         case 4:
 880                 /* fall-through */
 881         case 8:
 882                 sc->tx_pages = bce_tx_pages;
 883                 break;
 884         default:
 885                 sc->tx_pages = DEFAULT_TX_PAGES;
 886                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 887                     "hw.bce.tx_pages!  Setting default of %d.\n",
 888                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 889         }
 890
 891         /*
 892          * Validate the TX trip point (i.e. the number of
 893          * TX completions before a status block update is
 894          * generated and an interrupt is asserted.
 895          */
 896         if (bce_tx_quick_cons_trip_int <= 100) {
 897                 sc->bce_tx_quick_cons_trip_int =
 898                     bce_tx_quick_cons_trip_int;
 899         } else {
 900                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 901                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 902                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 903                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 904                 sc->bce_tx_quick_cons_trip_int =
 905                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 906         }
 907
 908         if (bce_tx_quick_cons_trip <= 100) {
 909                 sc->bce_tx_quick_cons_trip =
 910                     bce_tx_quick_cons_trip;
 911         } else {
 912                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 913                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 914                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 915                     DEFAULT_TX_QUICK_CONS_TRIP);
 916                 sc->bce_tx_quick_cons_trip =
 917                     DEFAULT_TX_QUICK_CONS_TRIP;
 918         }
 919
 920         /*
 921          * Validate the TX ticks count (i.e. the maximum amount
 922          * of time to wait after the last TX completion has
 923          * occurred before a status block update is generated
 924          * and an interrupt is asserted.
 925          */
 926         if (bce_tx_ticks_int <= 100) {
 927                 sc->bce_tx_ticks_int =
 928                     bce_tx_ticks_int;
 929         } else {
 930                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 931                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 932                     __FILE__, __LINE__, bce_tx_ticks_int,
 933                     DEFAULT_TX_TICKS_INT);
 934                 sc->bce_tx_ticks_int =
 935                     DEFAULT_TX_TICKS_INT;
 936            }
 937
 938         if (bce_tx_ticks <= 100) {
 939                 sc->bce_tx_ticks =
 940                     bce_tx_ticks;
 941         } else {
 942                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 943                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 944                     __FILE__, __LINE__, bce_tx_ticks,
 945                     DEFAULT_TX_TICKS);
 946                 sc->bce_tx_ticks =
 947                     DEFAULT_TX_TICKS;
 948         }
 949
 950         /*
 951          * Validate the RX trip point (i.e. the number of
 952          * RX frames received before a status block update is
 953          * generated and an interrupt is asserted.
 954          */
 955         if (bce_rx_quick_cons_trip_int <= 100) {
 956                 sc->bce_rx_quick_cons_trip_int =
 957                     bce_rx_quick_cons_trip_int;
 958         } else {
 959                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 960                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 961                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 962                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 963                 sc->bce_rx_quick_cons_trip_int =
 964                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 965         }
 966
 967         if (bce_rx_quick_cons_trip <= 100) {
 968                 sc->bce_rx_quick_cons_trip =
 969                     bce_rx_quick_cons_trip;
 970         } else {
 971                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 972                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
 973                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
 974                     DEFAULT_RX_QUICK_CONS_TRIP);
 975                 sc->bce_rx_quick_cons_trip =
 976                     DEFAULT_RX_QUICK_CONS_TRIP;
 977         }
 978
 979         /*
 980          * Validate the RX ticks count (i.e. the maximum amount
 981          * of time to wait after the last RX frame has been
 982          * received before a status block update is generated
 983          * and an interrupt is asserted.
 984          */
 985         if (bce_rx_ticks_int <= 100) {
 986                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
 987         } else {
 988                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 989                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
 990                     __FILE__, __LINE__, bce_rx_ticks_int,
 991                     DEFAULT_RX_TICKS_INT);
 992                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 993         }
 994
 995         if (bce_rx_ticks <= 100) {
 996                 sc->bce_rx_ticks = bce_rx_ticks;
 997         } else {
 998                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 999                     "hw.bce.rx_ticks!  Setting default of %d.\n",
1000                     __FILE__, __LINE__, bce_rx_ticks,
1001                     DEFAULT_RX_TICKS);
1002                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1003         }
1004
1005         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1006         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1007                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1008                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1009                    __FILE__, __LINE__);
1010                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1011                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1012         }
1013
1014         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1015         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1016                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1017                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1018                    __FILE__, __LINE__);
1019                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1020                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1021         }
1022
1023 }
1024
1025
1026 /****************************************************************************/
1027 /* Device attach function.                                                  */
1028 /*                                                                          */
1029 /* Allocates device resources, performs secondary chip identification,      */
1030 /* resets and initializes the hardware, and initializes driver instance     */
1031 /* variables.                                                               */
1032 /*                                                                          */
1033 /* Returns:                                                                 */
1034 /*   0 on success, positive value on failure.                               */
1035 /****************************************************************************/
1036 static int
1037 bce_attach(device_t dev)
1038 {
1039         struct bce_softc *sc;
1040         struct ifnet *ifp;
1041         u32 val;
1042         int count, error, rc = 0, rid;
1043
1044         sc = device_get_softc(dev);
1045         sc->bce_dev = dev;
1046
1047         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1048
1049         sc->bce_unit = device_get_unit(dev);
1050
1051         /* Set initial device and PHY flags */
1052         sc->bce_flags = 0;
1053         sc->bce_phy_flags = 0;
1054
1055         bce_set_tunables(sc);
1056
1057         pci_enable_busmaster(dev);
1058
1059         /* Allocate PCI memory resources. */
1060         rid = PCIR_BAR(0);
1061         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1062                 &rid, RF_ACTIVE);
1063
1064         if (sc->bce_res_mem == NULL) {
1065                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1066                     __FILE__, __LINE__);
1067                 rc = ENXIO;
1068                 goto bce_attach_fail;
1069         }
1070
1071         /* Get various resource handles. */
1072         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1073         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1074         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1075
1076         bce_probe_pci_caps(dev, sc);
1077
1078         rid = 1;
1079         count = 0;
1080 #if 0
1081         /* Try allocating MSI-X interrupts. */
1082         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1083                 (bce_msi_enable >= 2) &&
1084                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1085                 &rid, RF_ACTIVE)) != NULL)) {
1086
1087                 msi_needed = count = 1;
1088
1089                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1090                         (count != msi_needed)) {
1091                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1092                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1093                                 msi_needed, count, error);
1094                         count = 0;
1095                         pci_release_msi(dev);
1096                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1097                                 sc->bce_res_irq);
1098                         sc->bce_res_irq = NULL;
1099                 } else {
1100                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1101                                 __FUNCTION__);
1102                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1103                 }
1104         }
1105 #endif
1106
1107         /* Try allocating a MSI interrupt. */
1108         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1109                 (bce_msi_enable >= 1) && (count == 0)) {
1110                 count = 1;
1111                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1112                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1113                             "error = %d\n", __FILE__, __LINE__, error);
1114                         count = 0;
1115                         pci_release_msi(dev);
1116                 } else {
1117                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1118                             "interrupt.\n", __FUNCTION__);
1119                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1120                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1121                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1122                         rid = 1;
1123                 }
1124         }
1125
1126         /* Try allocating a legacy interrupt. */
1127         if (count == 0) {
1128                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1129                         __FUNCTION__);
1130                 rid = 0;
1131         }
1132
1133         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1134             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1135
1136         /* Report any IRQ allocation errors. */
1137         if (sc->bce_res_irq == NULL) {
1138                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1139                     __FILE__, __LINE__);
1140                 rc = ENXIO;
1141                 goto bce_attach_fail;
1142         }
1143
1144         /* Initialize mutex for the current device instance. */
1145         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1146
1147         /*
1148          * Configure byte swap and enable indirect register access.
1149          * Rely on CPU to do target byte swapping on big endian systems.
1150          * Access to registers outside of PCI configurtion space are not
1151          * valid until this is done.
1152          */
1153         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1154             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1155             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1156
1157         /* Save ASIC revsion info. */
1158         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1159
1160         /* Weed out any non-production controller revisions. */
1161         switch(BCE_CHIP_ID(sc)) {
1162         case BCE_CHIP_ID_5706_A0:
1163         case BCE_CHIP_ID_5706_A1:
1164         case BCE_CHIP_ID_5708_A0:
1165         case BCE_CHIP_ID_5708_B0:
1166         case BCE_CHIP_ID_5709_A0:
1167         case BCE_CHIP_ID_5709_B0:
1168         case BCE_CHIP_ID_5709_B1:
1169         case BCE_CHIP_ID_5709_B2:
1170                 BCE_PRINTF("%s(%d): Unsupported controller "
1171                     "revision (%c%d)!\n", __FILE__, __LINE__,
1172                     (((pci_read_config(dev, PCIR_REVID, 4) &
1173                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1174                     PCIR_REVID, 4) & 0xf));
1175                 rc = ENODEV;
1176                 goto bce_attach_fail;
1177         }
1178
1179         /*
1180          * The embedded PCIe to PCI-X bridge (EPB)
1181          * in the 5708 cannot address memory above
1182          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1183          */
1184         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1185                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1186         else
1187                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1188
1189         /*
1190          * Find the base address for shared memory access.
1191          * Newer versions of bootcode use a signature and offset
1192          * while older versions use a fixed address.
1193          */
1194         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1195         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1196                 /* Multi-port devices use different offsets in shared memory. */
1197                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1198                     (pci_get_function(sc->bce_dev) << 2));
1199         else
1200                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1201
1202         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1203             __FUNCTION__, sc->bce_shmem_base);
1204
1205         /* Fetch the bootcode revision. */
1206         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1207         for (int i = 0, j = 0; i < 3; i++) {
1208                 u8 num;
1209
1210                 num = (u8) (val >> (24 - (i * 8)));
1211                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1212                         if (num >= k || !skip0 || k == 1) {
1213                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1214                                 skip0 = 0;
1215                         }
1216                 }
1217
1218                 if (i != 2)
1219                         sc->bce_bc_ver[j++] = '.';
1220         }
1221
1222         /* Check if any management firwmare is enabled. */
1223         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1224         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1225                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1226
1227                 /* Allow time for firmware to enter the running state. */
1228                 for (int i = 0; i < 30; i++) {
1229                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1230                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1231                                 break;
1232                         DELAY(10000);
1233                 }
1234
1235                 /* Check if management firmware is running. */
1236                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1237                 val &= BCE_CONDITION_MFW_RUN_MASK;
1238                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1239                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1240                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1241                         int i = 0;
1242
1243                         /* Read the management firmware version string. */
1244                         for (int j = 0; j < 3; j++) {
1245                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1246                                 val = bswap32(val);
1247                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1248                                 i += 4;
1249                         }
1250                 } else {
1251                         /* May cause firmware synchronization timeouts. */
1252                         BCE_PRINTF("%s(%d): Management firmware enabled "
1253                             "but not running!\n", __FILE__, __LINE__);
1254                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1255
1256                         /* ToDo: Any action the driver should take? */
1257                 }
1258         }
1259
1260         /* Get PCI bus information (speed and type). */
1261         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1262         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1263                 u32 clkreg;
1264
1265                 sc->bce_flags |= BCE_PCIX_FLAG;
1266
1267                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1268
1269                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1270                 switch (clkreg) {
1271                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1272                         sc->bus_speed_mhz = 133;
1273                         break;
1274
1275                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1276                         sc->bus_speed_mhz = 100;
1277                         break;
1278
1279                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1280                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1281                         sc->bus_speed_mhz = 66;
1282                         break;
1283
1284                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1285                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1286                         sc->bus_speed_mhz = 50;
1287                         break;
1288
1289                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1290                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1291                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1292                         sc->bus_speed_mhz = 33;
1293                         break;
1294                 }
1295         } else {
1296                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1297                         sc->bus_speed_mhz = 66;
1298                 else
1299                         sc->bus_speed_mhz = 33;
1300         }
1301
1302         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1303                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1304
1305         /* Find the media type for the adapter. */
1306         bce_get_media(sc);
1307
1308         /* Reset controller and announce to bootcode that driver is present. */
1309         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1310                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1311                     __FILE__, __LINE__);
1312                 rc = ENXIO;
1313                 goto bce_attach_fail;
1314         }
1315
1316         /* Initialize the controller. */
1317         if (bce_chipinit(sc)) {
1318                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1319                     __FILE__, __LINE__);
1320                 rc = ENXIO;
1321                 goto bce_attach_fail;
1322         }
1323
1324         /* Perform NVRAM test. */
1325         if (bce_nvram_test(sc)) {
1326                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1327                     __FILE__, __LINE__);
1328                 rc = ENXIO;
1329                 goto bce_attach_fail;
1330         }
1331
1332         /* Fetch the permanent Ethernet MAC address. */
1333         bce_get_mac_addr(sc);
1334
1335         /*
1336          * Trip points control how many BDs
1337          * should be ready before generating an
1338          * interrupt while ticks control how long
1339          * a BD can sit in the chain before
1340          * generating an interrupt.  Set the default
1341          * values for the RX and TX chains.
1342          */
1343
1344         /* Not used for L2. */
1345         sc->bce_comp_prod_trip_int     = 0;
1346         sc->bce_comp_prod_trip         = 0;
1347         sc->bce_com_ticks_int          = 0;
1348         sc->bce_com_ticks              = 0;
1349         sc->bce_cmd_ticks_int          = 0;
1350         sc->bce_cmd_ticks              = 0;
1351
1352         /* Update statistics once every second. */
1353         sc->bce_stats_ticks = 1000000 & 0xffff00;
1354
1355         /* Store data needed by PHY driver for backplane applications */
1356         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1357         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1358
1359         /* Allocate DMA memory resources. */
1360         if (bce_dma_alloc(dev)) {
1361                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1362                     __FILE__, __LINE__);
1363                 rc = ENXIO;
1364                 goto bce_attach_fail;
1365         }
1366
1367         /* Allocate an ifnet structure. */
1368         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1369         if (ifp == NULL) {
1370                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1371                     __FILE__, __LINE__);
1372                 rc = ENXIO;
1373                 goto bce_attach_fail;
1374         }
1375
1376         /* Initialize the ifnet interface. */
1377         ifp->if_softc   = sc;
1378         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1379         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1380         ifp->if_ioctl   = bce_ioctl;
1381         ifp->if_start   = bce_start;
1382         ifp->if_init    = bce_init;
1383         ifp->if_mtu     = ETHERMTU;
1384
1385         if (bce_tso_enable) {
1386                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1387                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1388                     IFCAP_VLAN_HWTSO;
1389         } else {
1390                 ifp->if_hwassist = BCE_IF_HWASSIST;
1391                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1392         }
1393
1394 #if __FreeBSD_version >= 800505
1395         /*
1396          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1397          * so it's approximate value.
1398          */
1399         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1400                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1401 #endif
1402
1403         ifp->if_capenable = ifp->if_capabilities;
1404
1405         /*
1406          * Assume standard mbuf sizes for buffer allocation.
1407          * This may change later if the MTU size is set to
1408          * something other than 1500.
1409          */
1410         bce_get_rx_buffer_sizes(sc,
1411             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1412
1413         /* Recalculate our buffer allocation sizes. */
1414         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1415         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1416         IFQ_SET_READY(&ifp->if_snd);
1417
1418         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1419                 ifp->if_baudrate = IF_Mbps(2500ULL);
1420         else
1421                 ifp->if_baudrate = IF_Mbps(1000);
1422
1423         /* Handle any special PHY initialization for SerDes PHYs. */
1424         bce_init_media(sc);
1425
1426         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1427                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1428                     bce_ifmedia_sts);
1429                 /*
1430                  * We can't manually override remote PHY's link and assume
1431                  * PHY port configuration(Fiber or TP) is not changed after
1432                  * device attach.  This may not be correct though.
1433                  */
1434                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1435                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1436                                 ifmedia_add(&sc->bce_ifmedia,
1437                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1438                                 ifmedia_add(&sc->bce_ifmedia,
1439                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1440                         }
1441                         ifmedia_add(&sc->bce_ifmedia,
1442                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1443                         ifmedia_add(&sc->bce_ifmedia,
1444                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1445                 } else {
1446                         ifmedia_add(&sc->bce_ifmedia,
1447                             IFM_ETHER | IFM_10_T, 0, NULL);
1448                         ifmedia_add(&sc->bce_ifmedia,
1449                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1450                         ifmedia_add(&sc->bce_ifmedia,
1451                             IFM_ETHER | IFM_100_TX, 0, NULL);
1452                         ifmedia_add(&sc->bce_ifmedia,
1453                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1454                         ifmedia_add(&sc->bce_ifmedia,
1455                             IFM_ETHER | IFM_1000_T, 0, NULL);
1456                         ifmedia_add(&sc->bce_ifmedia,
1457                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1458                 }
1459                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1460                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1461                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1462         } else {
1463                 /* MII child bus by attaching the PHY. */
1464                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1465                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1466                     MII_OFFSET_ANY, MIIF_DOPAUSE);
1467                 if (rc != 0) {
1468                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1469                             __LINE__);
1470                         goto bce_attach_fail;
1471                 }
1472         }
1473
1474         /* Attach to the Ethernet interface list. */
1475         ether_ifattach(ifp, sc->eaddr);
1476
1477 #if __FreeBSD_version < 500000
1478         callout_init(&sc->bce_tick_callout);
1479         callout_init(&sc->bce_pulse_callout);
1480 #else
1481         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1482         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1483 #endif
1484
1485         /* Hookup IRQ last. */
1486         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1487                 NULL, bce_intr, sc, &sc->bce_intrhand);
1488
1489         if (rc) {
1490                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1491                     __FILE__, __LINE__);
1492                 bce_detach(dev);
1493                 goto bce_attach_exit;
1494         }
1495
1496         /*
1497          * At this point we've acquired all the resources
1498          * we need to run so there's no turning back, we're
1499          * cleared for launch.
1500          */
1501
1502         /* Print some important debugging info. */
1503         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1504
1505         /* Add the supported sysctls to the kernel. */
1506         bce_add_sysctls(sc);
1507
1508         BCE_LOCK(sc);
1509
1510         /*
1511          * The chip reset earlier notified the bootcode that
1512          * a driver is present.  We now need to start our pulse
1513          * routine so that the bootcode is reminded that we're
1514          * still running.
1515          */
1516         bce_pulse(sc);
1517
1518         bce_mgmt_init_locked(sc);
1519         BCE_UNLOCK(sc);
1520
1521         /* Finally, print some useful adapter info */
1522         bce_print_adapter_info(sc);
1523         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1524                 __FUNCTION__, sc);
1525
1526         goto bce_attach_exit;
1527
1528 bce_attach_fail:
1529         bce_release_resources(sc);
1530
1531 bce_attach_exit:
1532
1533         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1534
1535         return(rc);
1536 }
1537
1538
1539 /****************************************************************************/
1540 /* Device detach function.                                                  */
1541 /*                                                                          */
1542 /* Stops the controller, resets the controller, and releases resources.     */
1543 /*                                                                          */
1544 /* Returns:                                                                 */
1545 /*   0 on success, positive value on failure.                               */
1546 /****************************************************************************/
1547 static int
1548 bce_detach(device_t dev)
1549 {
1550         struct bce_softc *sc = device_get_softc(dev);
1551         struct ifnet *ifp;
1552         u32 msg;
1553
1554         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1555
1556         ifp = sc->bce_ifp;
1557
1558         /* Stop and reset the controller. */
1559         BCE_LOCK(sc);
1560
1561         /* Stop the pulse so the bootcode can go to driver absent state. */
1562         callout_stop(&sc->bce_pulse_callout);
1563
1564         bce_stop(sc);
1565         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1566                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1567         else
1568                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1569         bce_reset(sc, msg);
1570
1571         BCE_UNLOCK(sc);
1572
1573         ether_ifdetach(ifp);
1574
1575         /* If we have a child device on the MII bus remove it too. */
1576         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1577                 ifmedia_removeall(&sc->bce_ifmedia);
1578         else {
1579                 bus_generic_detach(dev);
1580                 device_delete_child(dev, sc->bce_miibus);
1581         }
1582
1583         /* Release all remaining resources. */
1584         bce_release_resources(sc);
1585
1586         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1587
1588         return(0);
1589 }
1590
1591
1592 /****************************************************************************/
1593 /* Device shutdown function.                                                */
1594 /*                                                                          */
1595 /* Stops and resets the controller.                                         */
1596 /*                                                                          */
1597 /* Returns:                                                                 */
1598 /*   0 on success, positive value on failure.                               */
1599 /****************************************************************************/
1600 static int
1601 bce_shutdown(device_t dev)
1602 {
1603         struct bce_softc *sc = device_get_softc(dev);
1604         u32 msg;
1605
1606         DBENTER(BCE_VERBOSE);
1607
1608         BCE_LOCK(sc);
1609         bce_stop(sc);
1610         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1611                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1612         else
1613                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1614         bce_reset(sc, msg);
1615         BCE_UNLOCK(sc);
1616
1617         DBEXIT(BCE_VERBOSE);
1618
1619         return (0);
1620 }
1621
1622
1623 #ifdef BCE_DEBUG
1624 /****************************************************************************/
1625 /* Register read.                                                           */
1626 /*                                                                          */
1627 /* Returns:                                                                 */
1628 /*   The value of the register.                                             */
1629 /****************************************************************************/
1630 static u32
1631 bce_reg_rd(struct bce_softc *sc, u32 offset)
1632 {
1633         u32 val = REG_RD(sc, offset);
1634         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1635                 __FUNCTION__, offset, val);
1636         return val;
1637 }
1638
1639
1640 /****************************************************************************/
1641 /* Register write (16 bit).                                                 */
1642 /*                                                                          */
1643 /* Returns:                                                                 */
1644 /*   Nothing.                                                               */
1645 /****************************************************************************/
1646 static void
1647 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1648 {
1649         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1650                 __FUNCTION__, offset, val);
1651         REG_WR16(sc, offset, val);
1652 }
1653
1654
1655 /****************************************************************************/
1656 /* Register write.                                                          */
1657 /*                                                                          */
1658 /* Returns:                                                                 */
1659 /*   Nothing.                                                               */
1660 /****************************************************************************/
1661 static void
1662 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1663 {
1664         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1665                 __FUNCTION__, offset, val);
1666         REG_WR(sc, offset, val);
1667 }
1668 #endif
1669
1670 /****************************************************************************/
1671 /* Indirect register read.                                                  */
1672 /*                                                                          */
1673 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1674 /* configuration space.  Using this mechanism avoids issues with posted     */
1675 /* reads but is much slower than memory-mapped I/O.                         */
1676 /*                                                                          */
1677 /* Returns:                                                                 */
1678 /*   The value of the register.                                             */
1679 /****************************************************************************/
1680 static u32
1681 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1682 {
1683         device_t dev;
1684         dev = sc->bce_dev;
1685
1686         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1687 #ifdef BCE_DEBUG
1688         {
1689                 u32 val;
1690                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1691                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1692                         __FUNCTION__, offset, val);
1693                 return val;
1694         }
1695 #else
1696         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1697 #endif
1698 }
1699
1700
1701 /****************************************************************************/
1702 /* Indirect register write.                                                 */
1703 /*                                                                          */
1704 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1705 /* configuration space.  Using this mechanism avoids issues with posted     */
1706 /* writes but is muchh slower than memory-mapped I/O.                       */
1707 /*                                                                          */
1708 /* Returns:                                                                 */
1709 /*   Nothing.                                                               */
1710 /****************************************************************************/
1711 static void
1712 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1713 {
1714         device_t dev;
1715         dev = sc->bce_dev;
1716
1717         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1718                 __FUNCTION__, offset, val);
1719
1720         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1721         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1722 }
1723
1724
1725 /****************************************************************************/
1726 /* Shared memory write.                                                     */
1727 /*                                                                          */
1728 /* Writes NetXtreme II shared memory region.                                */
1729 /*                                                                          */
1730 /* Returns:                                                                 */
1731 /*   Nothing.                                                               */
1732 /****************************************************************************/
1733 static void
1734 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1735 {
1736         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1737             "0x%08X\n", __FUNCTION__, val, offset);
1738
1739         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1740 }
1741
1742
1743 /****************************************************************************/
1744 /* Shared memory read.                                                      */
1745 /*                                                                          */
1746 /* Reads NetXtreme II shared memory region.                                 */
1747 /*                                                                          */
1748 /* Returns:                                                                 */
1749 /*   The 32 bit value read.                                                 */
1750 /****************************************************************************/
1751 static u32
1752 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1753 {
1754         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1755
1756         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1757             "0x%08X\n", __FUNCTION__, val, offset);
1758
1759         return val;
1760 }
1761
1762
1763 #ifdef BCE_DEBUG
1764 /****************************************************************************/
1765 /* Context memory read.                                                     */
1766 /*                                                                          */
1767 /* The NetXtreme II controller uses context memory to track connection      */
1768 /* information for L2 and higher network protocols.                         */
1769 /*                                                                          */
1770 /* Returns:                                                                 */
1771 /*   The requested 32 bit value of context memory.                          */
1772 /****************************************************************************/
1773 static u32
1774 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1775 {
1776         u32 idx, offset, retry_cnt = 5, val;
1777
1778         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1779             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1780             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1781
1782         offset = ctx_offset + cid_addr;
1783
1784         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1785
1786                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1787
1788                 for (idx = 0; idx < retry_cnt; idx++) {
1789                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1790                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1791                                 break;
1792                         DELAY(5);
1793                 }
1794
1795                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1796                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1797                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1798                             __FILE__, __LINE__, cid_addr, ctx_offset);
1799
1800                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1801         } else {
1802                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1803                 val = REG_RD(sc, BCE_CTX_DATA);
1804         }
1805
1806         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1807                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1808
1809         return(val);
1810 }
1811 #endif
1812
1813
1814 /****************************************************************************/
1815 /* Context memory write.                                                    */
1816 /*                                                                          */
1817 /* The NetXtreme II controller uses context memory to track connection      */
1818 /* information for L2 and higher network protocols.                         */
1819 /*                                                                          */
1820 /* Returns:                                                                 */
1821 /*   Nothing.                                                               */
1822 /****************************************************************************/
1823 static void
1824 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1825 {
1826         u32 idx, offset = ctx_offset + cid_addr;
1827         u32 val, retry_cnt = 5;
1828
1829         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1830                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1831
1832         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1833                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1834                     __FUNCTION__, cid_addr));
1835
1836         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1837
1838                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1839                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1840
1841                 for (idx = 0; idx < retry_cnt; idx++) {
1842                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1843                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1844                                 break;
1845                         DELAY(5);
1846                 }
1847
1848                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1849                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1850                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1851                             __FILE__, __LINE__, cid_addr, ctx_offset);
1852
1853         } else {
1854                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1855                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1856         }
1857 }
1858
1859
1860 /****************************************************************************/
1861 /* PHY register read.                                                       */
1862 /*                                                                          */
1863 /* Implements register reads on the MII bus.                                */
1864 /*                                                                          */
1865 /* Returns:                                                                 */
1866 /*   The value of the register.                                             */
1867 /****************************************************************************/
1868 static int
1869 bce_miibus_read_reg(device_t dev, int phy, int reg)
1870 {
1871         struct bce_softc *sc;
1872         u32 val;
1873         int i;
1874
1875         sc = device_get_softc(dev);
1876
1877     /*
1878      * The 5709S PHY is an IEEE Clause 45 PHY
1879      * with special mappings to work with IEEE
1880      * Clause 22 register accesses.
1881      */
1882         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1883                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1884                         reg += 0x10;
1885         }
1886
1887     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1888                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1889                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1890
1891                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1892                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1893
1894                 DELAY(40);
1895         }
1896
1897
1898         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1899             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1900             BCE_EMAC_MDIO_COMM_START_BUSY;
1901         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1902
1903         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1904                 DELAY(10);
1905
1906                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1907                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1908                         DELAY(5);
1909
1910                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1911                         val &= BCE_EMAC_MDIO_COMM_DATA;
1912
1913                         break;
1914                 }
1915         }
1916
1917         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1918                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1919                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1920                 val = 0x0;
1921         } else {
1922                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1923         }
1924
1925
1926         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1927                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1928                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1929
1930                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1931                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1932
1933                 DELAY(40);
1934         }
1935
1936         DB_PRINT_PHY_REG(reg, val);
1937         return (val & 0xffff);
1938
1939 }
1940
1941
1942 /****************************************************************************/
1943 /* PHY register write.                                                      */
1944 /*                                                                          */
1945 /* Implements register writes on the MII bus.                               */
1946 /*                                                                          */
1947 /* Returns:                                                                 */
1948 /*   The value of the register.                                             */
1949 /****************************************************************************/
1950 static int
1951 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1952 {
1953         struct bce_softc *sc;
1954         u32 val1;
1955         int i;
1956
1957         sc = device_get_softc(dev);
1958
1959         DB_PRINT_PHY_REG(reg, val);
1960
1961         /*
1962          * The 5709S PHY is an IEEE Clause 45 PHY
1963          * with special mappings to work with IEEE
1964          * Clause 22 register accesses.
1965          */
1966         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1967                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1968                         reg += 0x10;
1969         }
1970
1971         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1972                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1973                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1974
1975                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1976                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1977
1978                 DELAY(40);
1979         }
1980
1981         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1982             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1983             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1984         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1985
1986         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1987                 DELAY(10);
1988
1989                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1990                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1991                         DELAY(5);
1992                         break;
1993                 }
1994         }
1995
1996         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1997                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1998                     __FILE__, __LINE__);
1999
2000         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2001                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2002                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2003
2004                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2005                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2006
2007                 DELAY(40);
2008         }
2009
2010         return 0;
2011 }
2012
2013
2014 /****************************************************************************/
2015 /* MII bus status change.                                                   */
2016 /*                                                                          */
2017 /* Called by the MII bus driver when the PHY establishes link to set the    */
2018 /* MAC interface registers.                                                 */
2019 /*                                                                          */
2020 /* Returns:                                                                 */
2021 /*   Nothing.                                                               */
2022 /****************************************************************************/
2023 static void
2024 bce_miibus_statchg(device_t dev)
2025 {
2026         struct bce_softc *sc;
2027         struct mii_data *mii;
2028         struct ifmediareq ifmr;
2029         int media_active, media_status, val;
2030
2031         sc = device_get_softc(dev);
2032
2033         DBENTER(BCE_VERBOSE_PHY);
2034
2035         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2036                 bzero(&ifmr, sizeof(ifmr));
2037                 bce_ifmedia_sts_rphy(sc, &ifmr);
2038                 media_active = ifmr.ifm_active;
2039                 media_status = ifmr.ifm_status;
2040         } else {
2041                 mii = device_get_softc(sc->bce_miibus);
2042                 media_active = mii->mii_media_active;
2043                 media_status = mii->mii_media_status;
2044         }
2045
2046         /* Ignore invalid media status. */
2047         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2048             (IFM_ACTIVE | IFM_AVALID))
2049                 goto bce_miibus_statchg_exit;
2050
2051         val = REG_RD(sc, BCE_EMAC_MODE);
2052         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2053             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2054             BCE_EMAC_MODE_25G);
2055
2056         /* Set MII or GMII interface based on the PHY speed. */
2057         switch (IFM_SUBTYPE(media_active)) {
2058         case IFM_10_T:
2059                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2060                         DBPRINT(sc, BCE_INFO_PHY,
2061                             "Enabling 10Mb interface.\n");
2062                         val |= BCE_EMAC_MODE_PORT_MII_10;
2063                         break;
2064                 }
2065                 /* fall-through */
2066         case IFM_100_TX:
2067                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2068                 val |= BCE_EMAC_MODE_PORT_MII;
2069                 break;
2070         case IFM_2500_SX:
2071                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2072                 val |= BCE_EMAC_MODE_25G;
2073                 /* fall-through */
2074         case IFM_1000_T:
2075         case IFM_1000_SX:
2076                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2077                 val |= BCE_EMAC_MODE_PORT_GMII;
2078                 break;
2079         default:
2080                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2081                     "default GMII interface.\n");
2082                 val |= BCE_EMAC_MODE_PORT_GMII;
2083         }
2084
2085         /* Set half or full duplex based on PHY settings. */
2086         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2087                 DBPRINT(sc, BCE_INFO_PHY,
2088                     "Setting Half-Duplex interface.\n");
2089                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2090         } else
2091                 DBPRINT(sc, BCE_INFO_PHY,
2092                     "Setting Full-Duplex interface.\n");
2093
2094         REG_WR(sc, BCE_EMAC_MODE, val);
2095
2096         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2097                 DBPRINT(sc, BCE_INFO_PHY,
2098                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2099                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2100         } else {
2101                 DBPRINT(sc, BCE_INFO_PHY,
2102                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2103                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2104         }
2105
2106         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2107                 DBPRINT(sc, BCE_INFO_PHY,
2108                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2109                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2110                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2111         } else {
2112                 DBPRINT(sc, BCE_INFO_PHY,
2113                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2114                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2115                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2116         }
2117
2118         /* ToDo: Update watermarks in bce_init_rx_context(). */
2119
2120 bce_miibus_statchg_exit:
2121         DBEXIT(BCE_VERBOSE_PHY);
2122 }
2123
2124
2125 /****************************************************************************/
2126 /* Acquire NVRAM lock.                                                      */
2127 /*                                                                          */
2128 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2129 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2130 /* for use by the driver.                                                   */
2131 /*                                                                          */
2132 /* Returns:                                                                 */
2133 /*   0 on success, positive value on failure.                               */
2134 /****************************************************************************/
2135 static int
2136 bce_acquire_nvram_lock(struct bce_softc *sc)
2137 {
2138         u32 val;
2139         int j, rc = 0;
2140
2141         DBENTER(BCE_VERBOSE_NVRAM);
2142
2143         /* Request access to the flash interface. */
2144         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2145         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2146                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2147                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2148                         break;
2149
2150                 DELAY(5);
2151         }
2152
2153         if (j >= NVRAM_TIMEOUT_COUNT) {
2154                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2155                 rc = EBUSY;
2156         }
2157
2158         DBEXIT(BCE_VERBOSE_NVRAM);
2159         return (rc);
2160 }
2161
2162
2163 /****************************************************************************/
2164 /* Release NVRAM lock.                                                      */
2165 /*                                                                          */
2166 /* When the caller is finished accessing NVRAM the lock must be released.   */
2167 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2168 /* for use by the driver.                                                   */
2169 /*                                                                          */
2170 /* Returns:                                                                 */
2171 /*   0 on success, positive value on failure.                               */
2172 /****************************************************************************/
2173 static int
2174 bce_release_nvram_lock(struct bce_softc *sc)
2175 {
2176         u32 val;
2177         int j, rc = 0;
2178
2179         DBENTER(BCE_VERBOSE_NVRAM);
2180
2181         /*
2182          * Relinquish nvram interface.
2183          */
2184         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2185
2186         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2187                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2188                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2189                         break;
2190
2191                 DELAY(5);
2192         }
2193
2194         if (j >= NVRAM_TIMEOUT_COUNT) {
2195                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2196                 rc = EBUSY;
2197         }
2198
2199         DBEXIT(BCE_VERBOSE_NVRAM);
2200         return (rc);
2201 }
2202
2203
2204 #ifdef BCE_NVRAM_WRITE_SUPPORT
2205 /****************************************************************************/
2206 /* Enable NVRAM write access.                                               */
2207 /*                                                                          */
2208 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2209 /*                                                                          */
2210 /* Returns:                                                                 */
2211 /*   0 on success, positive value on failure.                               */
2212 /****************************************************************************/
2213 static int
2214 bce_enable_nvram_write(struct bce_softc *sc)
2215 {
2216         u32 val;
2217         int rc = 0;
2218
2219         DBENTER(BCE_VERBOSE_NVRAM);
2220
2221         val = REG_RD(sc, BCE_MISC_CFG);
2222         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2223
2224         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2225                 int j;
2226
2227                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2228                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2229
2230                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2231                         DELAY(5);
2232
2233                         val = REG_RD(sc, BCE_NVM_COMMAND);
2234                         if (val & BCE_NVM_COMMAND_DONE)
2235                                 break;
2236                 }
2237
2238                 if (j >= NVRAM_TIMEOUT_COUNT) {
2239                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2240                         rc = EBUSY;
2241                 }
2242         }
2243
2244         DBENTER(BCE_VERBOSE_NVRAM);
2245         return (rc);
2246 }
2247
2248
2249 /****************************************************************************/
2250 /* Disable NVRAM write access.                                              */
2251 /*                                                                          */
2252 /* When the caller is finished writing to NVRAM write access must be        */
2253 /* disabled.                                                                */
2254 /*                                                                          */
2255 /* Returns:                                                                 */
2256 /*   Nothing.                                                               */
2257 /****************************************************************************/
2258 static void
2259 bce_disable_nvram_write(struct bce_softc *sc)
2260 {
2261         u32 val;
2262
2263         DBENTER(BCE_VERBOSE_NVRAM);
2264
2265         val = REG_RD(sc, BCE_MISC_CFG);
2266         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2267
2268         DBEXIT(BCE_VERBOSE_NVRAM);
2269
2270 }
2271 #endif
2272
2273
2274 /****************************************************************************/
2275 /* Enable NVRAM access.                                                     */
2276 /*                                                                          */
2277 /* Before accessing NVRAM for read or write operations the caller must      */
2278 /* enabled NVRAM access.                                                    */
2279 /*                                                                          */
2280 /* Returns:                                                                 */
2281 /*   Nothing.                                                               */
2282 /****************************************************************************/
2283 static void
2284 bce_enable_nvram_access(struct bce_softc *sc)
2285 {
2286         u32 val;
2287
2288         DBENTER(BCE_VERBOSE_NVRAM);
2289
2290         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2291         /* Enable both bits, even on read. */
2292         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2293             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2294
2295         DBEXIT(BCE_VERBOSE_NVRAM);
2296 }
2297
2298
2299 /****************************************************************************/
2300 /* Disable NVRAM access.                                                    */
2301 /*                                                                          */
2302 /* When the caller is finished accessing NVRAM access must be disabled.     */
2303 /*                                                                          */
2304 /* Returns:                                                                 */
2305 /*   Nothing.                                                               */
2306 /****************************************************************************/
2307 static void
2308 bce_disable_nvram_access(struct bce_softc *sc)
2309 {
2310         u32 val;
2311
2312         DBENTER(BCE_VERBOSE_NVRAM);
2313
2314         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2315
2316         /* Disable both bits, even after read. */
2317         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2318             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2319
2320         DBEXIT(BCE_VERBOSE_NVRAM);
2321 }
2322
2323
2324 #ifdef BCE_NVRAM_WRITE_SUPPORT
2325 /****************************************************************************/
2326 /* Erase NVRAM page before writing.                                         */
2327 /*                                                                          */
2328 /* Non-buffered flash parts require that a page be erased before it is      */
2329 /* written.                                                                 */
2330 /*                                                                          */
2331 /* Returns:                                                                 */
2332 /*   0 on success, positive value on failure.                               */
2333 /****************************************************************************/
2334 static int
2335 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2336 {
2337         u32 cmd;
2338         int j, rc = 0;
2339
2340         DBENTER(BCE_VERBOSE_NVRAM);
2341
2342         /* Buffered flash doesn't require an erase. */
2343         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2344                 goto bce_nvram_erase_page_exit;
2345
2346         /* Build an erase command. */
2347         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2348             BCE_NVM_COMMAND_DOIT;
2349
2350         /*
2351          * Clear the DONE bit separately, set the NVRAM adress to erase,
2352          * and issue the erase command.
2353          */
2354         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2355         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2356         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2357
2358         /* Wait for completion. */
2359         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2360                 u32 val;
2361
2362                 DELAY(5);
2363
2364                 val = REG_RD(sc, BCE_NVM_COMMAND);
2365                 if (val & BCE_NVM_COMMAND_DONE)
2366                         break;
2367         }
2368
2369         if (j >= NVRAM_TIMEOUT_COUNT) {
2370                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2371                 rc = EBUSY;
2372         }
2373
2374 bce_nvram_erase_page_exit:
2375         DBEXIT(BCE_VERBOSE_NVRAM);
2376         return (rc);
2377 }
2378 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2379
2380
2381 /****************************************************************************/
2382 /* Read a dword (32 bits) from NVRAM.                                       */
2383 /*                                                                          */
2384 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2385 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2386 /*                                                                          */
2387 /* Returns:                                                                 */
2388 /*   0 on success and the 32 bit value read, positive value on failure.     */
2389 /****************************************************************************/
2390 static int
2391 bce_nvram_read_dword(struct bce_softc *sc,
2392     u32 offset, u8 *ret_val, u32 cmd_flags)
2393 {
2394         u32 cmd;
2395         int i, rc = 0;
2396
2397         DBENTER(BCE_EXTREME_NVRAM);
2398
2399         /* Build the command word. */
2400         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2401
2402         /* Calculate the offset for buffered flash if translation is used. */
2403         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2404                 offset = ((offset / sc->bce_flash_info->page_size) <<
2405                     sc->bce_flash_info->page_bits) +
2406                     (offset % sc->bce_flash_info->page_size);
2407         }
2408
2409         /*
2410          * Clear the DONE bit separately, set the address to read,
2411          * and issue the read.
2412          */
2413         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2414         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2415         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2416
2417         /* Wait for completion. */
2418         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2419                 u32 val;
2420
2421                 DELAY(5);
2422
2423                 val = REG_RD(sc, BCE_NVM_COMMAND);
2424                 if (val & BCE_NVM_COMMAND_DONE) {
2425                         val = REG_RD(sc, BCE_NVM_READ);
2426
2427                         val = bce_be32toh(val);
2428                         memcpy(ret_val, &val, 4);
2429                         break;
2430                 }
2431         }
2432
2433         /* Check for errors. */
2434         if (i >= NVRAM_TIMEOUT_COUNT) {
2435                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2436                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2437                 rc = EBUSY;
2438         }
2439
2440         DBEXIT(BCE_EXTREME_NVRAM);
2441         return(rc);
2442 }
2443
2444
2445 #ifdef BCE_NVRAM_WRITE_SUPPORT
2446 /****************************************************************************/
2447 /* Write a dword (32 bits) to NVRAM.                                        */
2448 /*                                                                          */
2449 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2450 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2451 /* enabled NVRAM write access.                                              */
2452 /*                                                                          */
2453 /* Returns:                                                                 */
2454 /*   0 on success, positive value on failure.                               */
2455 /****************************************************************************/
2456 static int
2457 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2458         u32 cmd_flags)
2459 {
2460         u32 cmd, val32;
2461         int j, rc = 0;
2462
2463         DBENTER(BCE_VERBOSE_NVRAM);
2464
2465         /* Build the command word. */
2466         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2467
2468         /* Calculate the offset for buffered flash if translation is used. */
2469         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2470                 offset = ((offset / sc->bce_flash_info->page_size) <<
2471                     sc->bce_flash_info->page_bits) +
2472                     (offset % sc->bce_flash_info->page_size);
2473         }
2474
2475         /*
2476          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2477          * set the NVRAM address to write, and issue the write command
2478          */
2479         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2480         memcpy(&val32, val, 4);
2481         val32 = htobe32(val32);
2482         REG_WR(sc, BCE_NVM_WRITE, val32);
2483         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2484         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2485
2486         /* Wait for completion. */
2487         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2488                 DELAY(5);
2489
2490                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2491                         break;
2492         }
2493         if (j >= NVRAM_TIMEOUT_COUNT) {
2494                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2495                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2496                 rc = EBUSY;
2497         }
2498
2499         DBEXIT(BCE_VERBOSE_NVRAM);
2500         return (rc);
2501 }
2502 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2503
2504
2505 /****************************************************************************/
2506 /* Initialize NVRAM access.                                                 */
2507 /*                                                                          */
2508 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2509 /* access that device.                                                      */
2510 /*                                                                          */
2511 /* Returns:                                                                 */
2512 /*   0 on success, positive value on failure.                               */
2513 /****************************************************************************/
2514 static int
2515 bce_init_nvram(struct bce_softc *sc)
2516 {
2517         u32 val;
2518         int j, entry_count, rc = 0;
2519         const struct flash_spec *flash;
2520
2521         DBENTER(BCE_VERBOSE_NVRAM);
2522
2523         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2524                 sc->bce_flash_info = &flash_5709;
2525                 goto bce_init_nvram_get_flash_size;
2526         }
2527
2528         /* Determine the selected interface. */
2529         val = REG_RD(sc, BCE_NVM_CFG1);
2530
2531         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2532
2533         /*
2534          * Flash reconfiguration is required to support additional
2535          * NVRAM devices not directly supported in hardware.
2536          * Check if the flash interface was reconfigured
2537          * by the bootcode.
2538          */
2539
2540         if (val & 0x40000000) {
2541                 /* Flash interface reconfigured by bootcode. */
2542
2543                 DBPRINT(sc,BCE_INFO_LOAD,
2544                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2545
2546                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2547                      j++, flash++) {
2548                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2549                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2550                                 sc->bce_flash_info = flash;
2551                                 break;
2552                         }
2553                 }
2554         } else {
2555                 /* Flash interface not yet reconfigured. */
2556                 u32 mask;
2557
2558                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2559                         __FUNCTION__);
2560
2561                 if (val & (1 << 23))
2562                         mask = FLASH_BACKUP_STRAP_MASK;
2563                 else
2564                         mask = FLASH_STRAP_MASK;
2565
2566                 /* Look for the matching NVRAM device configuration data. */
2567                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2568
2569                         /* Check if the device matches any of the known devices. */
2570                         if ((val & mask) == (flash->strapping & mask)) {
2571                                 /* Found a device match. */
2572                                 sc->bce_flash_info = flash;
2573
2574                                 /* Request access to the flash interface. */
2575                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2576                                         return rc;
2577
2578                                 /* Reconfigure the flash interface. */
2579                                 bce_enable_nvram_access(sc);
2580                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2581                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2582                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2583                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2584                                 bce_disable_nvram_access(sc);
2585                                 bce_release_nvram_lock(sc);
2586
2587                                 break;
2588                         }
2589                 }
2590         }
2591
2592         /* Check if a matching device was found. */
2593         if (j == entry_count) {
2594                 sc->bce_flash_info = NULL;
2595                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2596                     __FILE__, __LINE__);
2597                 DBEXIT(BCE_VERBOSE_NVRAM);
2598                 return (ENODEV);
2599         }
2600
2601 bce_init_nvram_get_flash_size:
2602         /* Write the flash config data to the shared memory interface. */
2603         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2604         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2605         if (val)
2606                 sc->bce_flash_size = val;
2607         else
2608                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2609
2610         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2611             __FUNCTION__, sc->bce_flash_info->name,
2612             sc->bce_flash_info->total_size);
2613
2614         DBEXIT(BCE_VERBOSE_NVRAM);
2615         return rc;
2616 }
2617
2618
2619 /****************************************************************************/
2620 /* Read an arbitrary range of data from NVRAM.                              */
2621 /*                                                                          */
2622 /* Prepares the NVRAM interface for access and reads the requested data     */
2623 /* into the supplied buffer.                                                */
2624 /*                                                                          */
2625 /* Returns:                                                                 */
2626 /*   0 on success and the data read, positive value on failure.             */
2627 /****************************************************************************/
2628 static int
2629 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2630         int buf_size)
2631 {
2632         int rc = 0;
2633         u32 cmd_flags, offset32, len32, extra;
2634
2635         DBENTER(BCE_VERBOSE_NVRAM);
2636
2637         if (buf_size == 0)
2638                 goto bce_nvram_read_exit;
2639
2640         /* Request access to the flash interface. */
2641         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2642                 goto bce_nvram_read_exit;
2643
2644         /* Enable access to flash interface */
2645         bce_enable_nvram_access(sc);
2646
2647         len32 = buf_size;
2648         offset32 = offset;
2649         extra = 0;
2650
2651         cmd_flags = 0;
2652
2653         if (offset32 & 3) {
2654                 u8 buf[4];
2655                 u32 pre_len;
2656
2657                 offset32 &= ~3;
2658                 pre_len = 4 - (offset & 3);
2659
2660                 if (pre_len >= len32) {
2661                         pre_len = len32;
2662                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2663                 }
2664                 else {
2665                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2666                 }
2667
2668                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2669
2670                 if (rc)
2671                         return rc;
2672
2673                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2674
2675                 offset32 += 4;
2676                 ret_buf += pre_len;
2677                 len32 -= pre_len;
2678         }
2679
2680         if (len32 & 3) {
2681                 extra = 4 - (len32 & 3);
2682                 len32 = (len32 + 4) & ~3;
2683         }
2684
2685         if (len32 == 4) {
2686                 u8 buf[4];
2687
2688                 if (cmd_flags)
2689                         cmd_flags = BCE_NVM_COMMAND_LAST;
2690                 else
2691                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2692                                     BCE_NVM_COMMAND_LAST;
2693
2694                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2695
2696                 memcpy(ret_buf, buf, 4 - extra);
2697         }
2698         else if (len32 > 0) {
2699                 u8 buf[4];
2700
2701                 /* Read the first word. */
2702                 if (cmd_flags)
2703                         cmd_flags = 0;
2704                 else
2705                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2706
2707                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2708
2709                 /* Advance to the next dword. */
2710                 offset32 += 4;
2711                 ret_buf += 4;
2712                 len32 -= 4;
2713
2714                 while (len32 > 4 && rc == 0) {
2715                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2716
2717                         /* Advance to the next dword. */
2718                         offset32 += 4;
2719                         ret_buf += 4;
2720                         len32 -= 4;
2721                 }
2722
2723                 if (rc)
2724                         goto bce_nvram_read_locked_exit;
2725
2726                 cmd_flags = BCE_NVM_COMMAND_LAST;
2727                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2728
2729                 memcpy(ret_buf, buf, 4 - extra);
2730         }
2731
2732 bce_nvram_read_locked_exit:
2733         /* Disable access to flash interface and release the lock. */
2734         bce_disable_nvram_access(sc);
2735         bce_release_nvram_lock(sc);
2736
2737 bce_nvram_read_exit:
2738         DBEXIT(BCE_VERBOSE_NVRAM);
2739         return rc;
2740 }
2741
2742
2743 #ifdef BCE_NVRAM_WRITE_SUPPORT
2744 /****************************************************************************/
2745 /* Write an arbitrary range of data from NVRAM.                             */
2746 /*                                                                          */
2747 /* Prepares the NVRAM interface for write access and writes the requested   */
2748 /* data from the supplied buffer.  The caller is responsible for            */
2749 /* calculating any appropriate CRCs.                                        */
2750 /*                                                                          */
2751 /* Returns:                                                                 */
2752 /*   0 on success, positive value on failure.                               */
2753 /****************************************************************************/
2754 static int
2755 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2756         int buf_size)
2757 {
2758         u32 written, offset32, len32;
2759         u8 *buf, start[4], end[4];
2760         int rc = 0;
2761         int align_start, align_end;
2762
2763         DBENTER(BCE_VERBOSE_NVRAM);
2764
2765         buf = data_buf;
2766         offset32 = offset;
2767         len32 = buf_size;
2768         align_start = align_end = 0;
2769
2770         if ((align_start = (offset32 & 3))) {
2771                 offset32 &= ~3;
2772                 len32 += align_start;
2773                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2774                         goto bce_nvram_write_exit;
2775         }
2776
2777         if (len32 & 3) {
2778                 if ((len32 > 4) || !align_start) {
2779                         align_end = 4 - (len32 & 3);
2780                         len32 += align_end;
2781                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2782                                 end, 4))) {
2783                                 goto bce_nvram_write_exit;
2784                         }
2785                 }
2786         }
2787
2788         if (align_start || align_end) {
2789                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2790                 if (buf == 0) {
2791                         rc = ENOMEM;
2792                         goto bce_nvram_write_exit;
2793                 }
2794
2795                 if (align_start) {
2796                         memcpy(buf, start, 4);
2797                 }
2798
2799                 if (align_end) {
2800                         memcpy(buf + len32 - 4, end, 4);
2801                 }
2802                 memcpy(buf + align_start, data_buf, buf_size);
2803         }
2804
2805         written = 0;
2806         while ((written < len32) && (rc == 0)) {
2807                 u32 page_start, page_end, data_start, data_end;
2808                 u32 addr, cmd_flags;
2809                 int i;
2810                 u8 flash_buffer[264];
2811
2812             /* Find the page_start addr */
2813                 page_start = offset32 + written;
2814                 page_start -= (page_start % sc->bce_flash_info->page_size);
2815                 /* Find the page_end addr */
2816                 page_end = page_start + sc->bce_flash_info->page_size;
2817                 /* Find the data_start addr */
2818                 data_start = (written == 0) ? offset32 : page_start;
2819                 /* Find the data_end addr */
2820                 data_end = (page_end > offset32 + len32) ?
2821                         (offset32 + len32) : page_end;
2822
2823                 /* Request access to the flash interface. */
2824                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2825                         goto bce_nvram_write_exit;
2826
2827                 /* Enable access to flash interface */
2828                 bce_enable_nvram_access(sc);
2829
2830                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2831                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2832                         int j;
2833
2834                         /* Read the whole page into the buffer
2835                          * (non-buffer flash only) */
2836                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2837                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2838                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2839                                 }
2840                                 rc = bce_nvram_read_dword(sc,
2841                                         page_start + j,
2842                                         &flash_buffer[j],
2843                                         cmd_flags);
2844
2845                                 if (rc)
2846                                         goto bce_nvram_write_locked_exit;
2847
2848                                 cmd_flags = 0;
2849                         }
2850                 }
2851
2852                 /* Enable writes to flash interface (unlock write-protect) */
2853                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2854                         goto bce_nvram_write_locked_exit;
2855
2856                 /* Erase the page */
2857                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2858                         goto bce_nvram_write_locked_exit;
2859
2860                 /* Re-enable the write again for the actual write */
2861                 bce_enable_nvram_write(sc);
2862
2863                 /* Loop to write back the buffer data from page_start to
2864                  * data_start */
2865                 i = 0;
2866                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2867                         for (addr = page_start; addr < data_start;
2868                                 addr += 4, i += 4) {
2869
2870                                 rc = bce_nvram_write_dword(sc, addr,
2871                                         &flash_buffer[i], cmd_flags);
2872
2873                                 if (rc != 0)
2874                                         goto bce_nvram_write_locked_exit;
2875
2876                                 cmd_flags = 0;
2877                         }
2878                 }
2879
2880                 /* Loop to write the new data from data_start to data_end */
2881                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2882                         if ((addr == page_end - 4) ||
2883                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2884                                 (addr == data_end - 4))) {
2885
2886                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2887                         }
2888                         rc = bce_nvram_write_dword(sc, addr, buf,
2889                                 cmd_flags);
2890
2891                         if (rc != 0)
2892                                 goto bce_nvram_write_locked_exit;
2893
2894                         cmd_flags = 0;
2895                         buf += 4;
2896                 }
2897
2898                 /* Loop to write back the buffer data from data_end
2899                  * to page_end */
2900                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2901                         for (addr = data_end; addr < page_end;
2902                                 addr += 4, i += 4) {
2903
2904                                 if (addr == page_end-4) {
2905                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2906                                 }
2907                                 rc = bce_nvram_write_dword(sc, addr,
2908                                         &flash_buffer[i], cmd_flags);
2909
2910                                 if (rc != 0)
2911                                         goto bce_nvram_write_locked_exit;
2912
2913                                 cmd_flags = 0;
2914                         }
2915                 }
2916
2917                 /* Disable writes to flash interface (lock write-protect) */
2918                 bce_disable_nvram_write(sc);
2919
2920                 /* Disable access to flash interface */
2921                 bce_disable_nvram_access(sc);
2922                 bce_release_nvram_lock(sc);
2923
2924                 /* Increment written */
2925                 written += data_end - data_start;
2926         }
2927
2928         goto bce_nvram_write_exit;
2929
2930 bce_nvram_write_locked_exit:
2931         bce_disable_nvram_write(sc);
2932         bce_disable_nvram_access(sc);
2933         bce_release_nvram_lock(sc);
2934
2935 bce_nvram_write_exit:
2936         if (align_start || align_end)
2937                 free(buf, M_DEVBUF);
2938
2939         DBEXIT(BCE_VERBOSE_NVRAM);
2940         return (rc);
2941 }
2942 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2943
2944
2945 /****************************************************************************/
2946 /* Verifies that NVRAM is accessible and contains valid data.               */
2947 /*                                                                          */
2948 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2949 /* correct.                                                                 */
2950 /*                                                                          */
2951 /* Returns:                                                                 */
2952 /*   0 on success, positive value on failure.                               */
2953 /****************************************************************************/
2954 static int
2955 bce_nvram_test(struct bce_softc *sc)
2956 {
2957         u32 buf[BCE_NVRAM_SIZE / 4];
2958         u8 *data = (u8 *) buf;
2959         int rc = 0;
2960         u32 magic, csum;
2961
2962         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2963
2964         /*
2965          * Check that the device NVRAM is valid by reading
2966          * the magic value at offset 0.
2967          */
2968         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2969                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2970                     __FILE__, __LINE__);
2971                 goto bce_nvram_test_exit;
2972         }
2973
2974         /*
2975          * Verify that offset 0 of the NVRAM contains
2976          * a valid magic number.
2977          */
2978         magic = bce_be32toh(buf[0]);
2979         if (magic != BCE_NVRAM_MAGIC) {
2980                 rc = ENODEV;
2981                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2982                     "Expected: 0x%08X, Found: 0x%08X\n",
2983                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2984                 goto bce_nvram_test_exit;
2985         }
2986
2987         /*
2988          * Verify that the device NVRAM includes valid
2989          * configuration data.
2990          */
2991         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2992                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2993                     "Information from  NVRAM!\n", __FILE__, __LINE__);
2994                 goto bce_nvram_test_exit;
2995         }
2996
2997         csum = ether_crc32_le(data, 0x100);
2998         if (csum != BCE_CRC32_RESIDUAL) {
2999                 rc = ENODEV;
3000                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3001                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3002                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3003                 goto bce_nvram_test_exit;
3004         }
3005
3006         csum = ether_crc32_le(data + 0x100, 0x100);
3007         if (csum != BCE_CRC32_RESIDUAL) {
3008                 rc = ENODEV;
3009                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3010                     "information NVRAM CRC! Expected: 0x%08X, "
3011                     "Found: 08%08X\n", __FILE__, __LINE__,
3012                     BCE_CRC32_RESIDUAL, csum);
3013         }
3014
3015 bce_nvram_test_exit:
3016         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3017         return rc;
3018 }
3019
3020
3021 /****************************************************************************/
3022 /* Calculates the size of the buffers to allocate based on the MTU.         */
3023 /*                                                                          */
3024 /* Returns:                                                                 */
3025 /*   Nothing.                                                               */
3026 /****************************************************************************/
3027 static void
3028 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3029 {
3030         DBENTER(BCE_VERBOSE_LOAD);
3031
3032         /* Use a single allocation type when header splitting enabled. */
3033         if (bce_hdr_split == TRUE) {
3034                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3035                 /* Make sure offset is 16 byte aligned for hardware. */
3036                 sc->rx_bd_mbuf_align_pad =
3037                         roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3038                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3039                         sc->rx_bd_mbuf_align_pad;
3040                 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
3041         } else {
3042                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3043                     ETHER_CRC_LEN) > MCLBYTES) {
3044                         /* Setup for jumbo RX buffer allocations. */
3045                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3046                         sc->rx_bd_mbuf_align_pad  =
3047                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3048                         sc->rx_bd_mbuf_data_len =
3049                             sc->rx_bd_mbuf_alloc_size -
3050                             sc->rx_bd_mbuf_align_pad;
3051                 } else {
3052                         /* Setup for standard RX buffer allocations. */
3053                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3054                         sc->rx_bd_mbuf_align_pad  =
3055                             roundup2(MCLBYTES, 16) - MCLBYTES;
3056                         sc->rx_bd_mbuf_data_len =
3057                             sc->rx_bd_mbuf_alloc_size -
3058                             sc->rx_bd_mbuf_align_pad;
3059                 }
3060         }
3061
3062 //      DBPRINT(sc, BCE_INFO_LOAD,
3063         DBPRINT(sc, BCE_WARN,
3064            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3065            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3066            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3067            sc->rx_bd_mbuf_align_pad);
3068
3069         DBEXIT(BCE_VERBOSE_LOAD);
3070
3071 }
3072
3073 /****************************************************************************/
3074 /* Identifies the current media type of the controller and sets the PHY     */
3075 /* address.                                                                 */
3076 /*                                                                          */
3077 /* Returns:                                                                 */
3078 /*   Nothing.                                                               */
3079 /****************************************************************************/
3080 static void
3081 bce_get_media(struct bce_softc *sc)
3082 {
3083         u32 val;
3084
3085         DBENTER(BCE_VERBOSE_PHY);
3086
3087         /* Assume PHY address for copper controllers. */
3088         sc->bce_phy_addr = 1;
3089
3090         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3091                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3092                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3093                 u32 strap;
3094
3095                 /*
3096                  * The BCM5709S is software configurable
3097                  * for Copper or SerDes operation.
3098                  */
3099                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3100                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3101                             "for copper.\n");
3102                         goto bce_get_media_exit;
3103                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3104                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3105                             "for dual media.\n");
3106                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3107                         goto bce_get_media_exit;
3108                 }
3109
3110                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3111                         strap = (val &
3112                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3113                 else
3114                         strap = (val &
3115                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3116
3117                 if (pci_get_function(sc->bce_dev) == 0) {
3118                         switch (strap) {
3119                         case 0x4:
3120                         case 0x5:
3121                         case 0x6:
3122                                 DBPRINT(sc, BCE_INFO_LOAD,
3123                                     "BCM5709 s/w configured for SerDes.\n");
3124                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3125                                 break;
3126                         default:
3127                                 DBPRINT(sc, BCE_INFO_LOAD,
3128                                     "BCM5709 s/w configured for Copper.\n");
3129                                 break;
3130                         }
3131                 } else {
3132                         switch (strap) {
3133                         case 0x1:
3134                         case 0x2:
3135                         case 0x4:
3136                                 DBPRINT(sc, BCE_INFO_LOAD,
3137                                     "BCM5709 s/w configured for SerDes.\n");
3138                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3139                                 break;
3140                         default:
3141                                 DBPRINT(sc, BCE_INFO_LOAD,
3142                                     "BCM5709 s/w configured for Copper.\n");
3143                                 break;
3144                         }
3145                 }
3146
3147         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3148                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3149
3150         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3151
3152                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3153
3154                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3155                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3156
3157                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3158                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3159                         sc->bce_phy_addr = 2;
3160
3161                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3162                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3163                                 sc->bce_phy_flags |=
3164                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3165                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3166                                     "capable adapter\n");
3167                         }
3168                 }
3169         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3170             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3171                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3172
3173 bce_get_media_exit:
3174         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3175                 "Using PHY address %d.\n", sc->bce_phy_addr);
3176
3177         DBEXIT(BCE_VERBOSE_PHY);
3178 }
3179
3180
3181 /****************************************************************************/
3182 /* Performs PHY initialization required before MII drivers access the       */
3183 /* device.                                                                  */
3184 /*                                                                          */
3185 /* Returns:                                                                 */
3186 /*   Nothing.                                                               */
3187 /****************************************************************************/
3188 static void
3189 bce_init_media(struct bce_softc *sc)
3190 {
3191         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3192             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3193                 /*
3194                  * Configure 5709S/5716S PHYs to use traditional IEEE
3195                  * Clause 22 method. Otherwise we have no way to attach
3196                  * the PHY in mii(4) layer. PHY specific configuration
3197                  * is done in mii layer.
3198                  */
3199
3200                 /* Select auto-negotiation MMD of the PHY. */
3201                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3202                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3203                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3204                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3205
3206                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3207                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3208                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3209         }
3210 }
3211
3212
3213 /****************************************************************************/
3214 /* Free any DMA memory owned by the driver.                                 */
3215 /*                                                                          */
3216 /* Scans through each data structre that requires DMA memory and frees      */
3217 /* the memory if allocated.                                                 */
3218 /*                                                                          */
3219 /* Returns:                                                                 */
3220 /*   Nothing.                                                               */
3221 /****************************************************************************/
3222 static void
3223 bce_dma_free(struct bce_softc *sc)
3224 {
3225         int i;
3226
3227         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3228
3229         /* Free, unmap, and destroy the status block. */
3230         if (sc->status_block != NULL) {
3231                 bus_dmamem_free(
3232                    sc->status_tag,
3233                     sc->status_block,
3234                     sc->status_map);
3235                 sc->status_block = NULL;
3236         }
3237
3238         if (sc->status_map != NULL) {
3239                 bus_dmamap_unload(
3240                     sc->status_tag,
3241                     sc->status_map);
3242                 bus_dmamap_destroy(sc->status_tag,
3243                     sc->status_map);
3244                 sc->status_map = NULL;
3245         }
3246
3247         if (sc->status_tag != NULL) {
3248                 bus_dma_tag_destroy(sc->status_tag);
3249                 sc->status_tag = NULL;
3250         }
3251
3252
3253         /* Free, unmap, and destroy the statistics block. */
3254         if (sc->stats_block != NULL) {
3255                 bus_dmamem_free(
3256                     sc->stats_tag,
3257                     sc->stats_block,
3258                     sc->stats_map);
3259                 sc->stats_block = NULL;
3260         }
3261
3262         if (sc->stats_map != NULL) {
3263                 bus_dmamap_unload(
3264                     sc->stats_tag,
3265                     sc->stats_map);
3266                 bus_dmamap_destroy(sc->stats_tag,
3267                     sc->stats_map);
3268                 sc->stats_map = NULL;
3269         }
3270
3271         if (sc->stats_tag != NULL) {
3272                 bus_dma_tag_destroy(sc->stats_tag);
3273                 sc->stats_tag = NULL;
3274         }
3275
3276
3277         /* Free, unmap and destroy all context memory pages. */
3278         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3279                 for (i = 0; i < sc->ctx_pages; i++ ) {
3280                         if (sc->ctx_block[i] != NULL) {
3281                                 bus_dmamem_free(
3282                                     sc->ctx_tag,
3283                                     sc->ctx_block[i],
3284                                     sc->ctx_map[i]);
3285                                 sc->ctx_block[i] = NULL;
3286                         }
3287
3288                         if (sc->ctx_map[i] != NULL) {
3289                                 bus_dmamap_unload(
3290                                     sc->ctx_tag,
3291                                     sc->ctx_map[i]);
3292                                 bus_dmamap_destroy(
3293                                     sc->ctx_tag,
3294                                     sc->ctx_map[i]);
3295                                 sc->ctx_map[i] = NULL;
3296                         }
3297                 }
3298
3299                 /* Destroy the context memory tag. */
3300                 if (sc->ctx_tag != NULL) {
3301                         bus_dma_tag_destroy(sc->ctx_tag);
3302                         sc->ctx_tag = NULL;
3303                 }
3304         }
3305
3306
3307         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3308         for (i = 0; i < sc->tx_pages; i++ ) {
3309                 if (sc->tx_bd_chain[i] != NULL) {
3310                         bus_dmamem_free(
3311                             sc->tx_bd_chain_tag,
3312                             sc->tx_bd_chain[i],
3313                             sc->tx_bd_chain_map[i]);
3314                         sc->tx_bd_chain[i] = NULL;
3315                 }
3316
3317                 if (sc->tx_bd_chain_map[i] != NULL) {
3318                         bus_dmamap_unload(
3319                             sc->tx_bd_chain_tag,
3320                             sc->tx_bd_chain_map[i]);
3321                         bus_dmamap_destroy(
3322                             sc->tx_bd_chain_tag,
3323                             sc->tx_bd_chain_map[i]);
3324                         sc->tx_bd_chain_map[i] = NULL;
3325                 }
3326         }
3327
3328         /* Destroy the TX buffer descriptor tag. */
3329         if (sc->tx_bd_chain_tag != NULL) {
3330                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3331                 sc->tx_bd_chain_tag = NULL;
3332         }
3333
3334
3335         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3336         for (i = 0; i < sc->rx_pages; i++ ) {
3337                 if (sc->rx_bd_chain[i] != NULL) {
3338                         bus_dmamem_free(
3339                             sc->rx_bd_chain_tag,
3340                             sc->rx_bd_chain[i],
3341                             sc->rx_bd_chain_map[i]);
3342                         sc->rx_bd_chain[i] = NULL;
3343                 }
3344
3345                 if (sc->rx_bd_chain_map[i] != NULL) {
3346                         bus_dmamap_unload(
3347                             sc->rx_bd_chain_tag,
3348                             sc->rx_bd_chain_map[i]);
3349                         bus_dmamap_destroy(
3350                             sc->rx_bd_chain_tag,
3351                             sc->rx_bd_chain_map[i]);
3352                         sc->rx_bd_chain_map[i] = NULL;
3353                 }
3354         }
3355
3356         /* Destroy the RX buffer descriptor tag. */
3357         if (sc->rx_bd_chain_tag != NULL) {
3358                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3359                 sc->rx_bd_chain_tag = NULL;
3360         }
3361
3362
3363         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3364         if (bce_hdr_split == TRUE) {
3365                 for (i = 0; i < sc->pg_pages; i++ ) {
3366                         if (sc->pg_bd_chain[i] != NULL) {
3367                                 bus_dmamem_free(
3368                                     sc->pg_bd_chain_tag,
3369                                     sc->pg_bd_chain[i],
3370                                     sc->pg_bd_chain_map[i]);
3371                                 sc->pg_bd_chain[i] = NULL;
3372                         }
3373
3374                         if (sc->pg_bd_chain_map[i] != NULL) {
3375                                 bus_dmamap_unload(
3376                                     sc->pg_bd_chain_tag,
3377                                     sc->pg_bd_chain_map[i]);
3378                                 bus_dmamap_destroy(
3379                                     sc->pg_bd_chain_tag,
3380                                     sc->pg_bd_chain_map[i]);
3381                                 sc->pg_bd_chain_map[i] = NULL;
3382                         }
3383                 }
3384
3385                 /* Destroy the page buffer descriptor tag. */
3386                 if (sc->pg_bd_chain_tag != NULL) {
3387                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3388                         sc->pg_bd_chain_tag = NULL;
3389                 }
3390         }
3391
3392
3393         /* Unload and destroy the TX mbuf maps. */
3394         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3395                 if (sc->tx_mbuf_map[i] != NULL) {
3396                         bus_dmamap_unload(sc->tx_mbuf_tag,
3397                             sc->tx_mbuf_map[i]);
3398                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3399                             sc->tx_mbuf_map[i]);
3400                         sc->tx_mbuf_map[i] = NULL;
3401                 }
3402         }
3403
3404         /* Destroy the TX mbuf tag. */
3405         if (sc->tx_mbuf_tag != NULL) {
3406                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3407                 sc->tx_mbuf_tag = NULL;
3408         }
3409
3410         /* Unload and destroy the RX mbuf maps. */
3411         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3412                 if (sc->rx_mbuf_map[i] != NULL) {
3413                         bus_dmamap_unload(sc->rx_mbuf_tag,
3414                             sc->rx_mbuf_map[i]);
3415                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3416                             sc->rx_mbuf_map[i]);
3417                         sc->rx_mbuf_map[i] = NULL;
3418                 }
3419         }
3420
3421         /* Destroy the RX mbuf tag. */
3422         if (sc->rx_mbuf_tag != NULL) {
3423                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3424                 sc->rx_mbuf_tag = NULL;
3425         }
3426
3427         /* Unload and destroy the page mbuf maps. */
3428         if (bce_hdr_split == TRUE) {
3429                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3430                         if (sc->pg_mbuf_map[i] != NULL) {
3431                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3432                                     sc->pg_mbuf_map[i]);
3433                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3434                                     sc->pg_mbuf_map[i]);
3435                                 sc->pg_mbuf_map[i] = NULL;
3436                         }
3437                 }
3438
3439                 /* Destroy the page mbuf tag. */
3440                 if (sc->pg_mbuf_tag != NULL) {
3441                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3442                         sc->pg_mbuf_tag = NULL;
3443                 }
3444         }
3445
3446         /* Destroy the parent tag */
3447         if (sc->parent_tag != NULL) {
3448                 bus_dma_tag_destroy(sc->parent_tag);
3449                 sc->parent_tag = NULL;
3450         }
3451
3452         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3453 }
3454
3455
3456 /****************************************************************************/
3457 /* Get DMA memory from the OS.                                              */
3458 /*                                                                          */
3459 /* Validates that the OS has provided DMA buffers in response to a          */
3460 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3461 /* When the callback is used the OS will return 0 for the mapping function  */
3462 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3463 /* failures back to the caller.                                             */
3464 /*                                                                          */
3465 /* Returns:                                                                 */
3466 /*   Nothing.                                                               */
3467 /****************************************************************************/
3468 static void
3469 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3470 {
3471         bus_addr_t *busaddr = arg;
3472
3473         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3474             __FUNCTION__, nseg));
3475         /* Simulate a mapping failure. */
3476         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3477             error = ENOMEM);
3478
3479         /* ToDo: How to increment debug sim_count variable here? */
3480
3481         /* Check for an error and signal the caller that an error occurred. */
3482         if (error) {
3483                 *busaddr = 0;
3484         } else {
3485                 *busaddr = segs->ds_addr;
3486         }
3487
3488         return;
3489 }
3490
3491
3492 /****************************************************************************/
3493 /* Allocate any DMA memory needed by the driver.                            */
3494 /*                                                                          */
3495 /* Allocates DMA memory needed for the various global structures needed by  */
3496 /* hardware.                                                                */
3497 /*                                                                          */
3498 /* Memory alignment requirements:                                           */
3499 /* +-----------------+----------+----------+----------+----------+          */
3500 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3501 /* +-----------------+----------+----------+----------+----------+          */
3502 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3503 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3504 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3505 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3506 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3507 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3508 /* |Context Memory   |          |          |          |          |          */
3509 /* +-----------------+----------+----------+----------+----------+          */
3510 /*                                                                          */
3511 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3512 /*                                                                          */
3513 /* Returns:                                                                 */
3514 /*   0 for success, positive value for failure.                             */
3515 /****************************************************************************/
3516 static int
3517 bce_dma_alloc(device_t dev)
3518 {
3519         struct bce_softc *sc;
3520         int i, error, rc = 0;
3521         bus_size_t max_size, max_seg_size;
3522         int max_segments;
3523
3524         sc = device_get_softc(dev);
3525
3526         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3527
3528         /*
3529          * Allocate the parent bus DMA tag appropriate for PCI.
3530          */
3531         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3532             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3533             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3534             &sc->parent_tag)) {
3535                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3536                     __FILE__, __LINE__);
3537                 rc = ENOMEM;
3538                 goto bce_dma_alloc_exit;
3539         }
3540
3541         /*
3542          * Create a DMA tag for the status block, allocate and clear the
3543          * memory, map the memory into DMA space, and fetch the physical
3544          * address of the block.
3545          */
3546         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3547             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3548             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3549             0, NULL, NULL, &sc->status_tag)) {
3550                 BCE_PRINTF("%s(%d): Could not allocate status block "
3551                     "DMA tag!\n", __FILE__, __LINE__);
3552                 rc = ENOMEM;
3553                 goto bce_dma_alloc_exit;
3554         }
3555
3556         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3557             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3558             &sc->status_map)) {
3559                 BCE_PRINTF("%s(%d): Could not allocate status block "
3560                     "DMA memory!\n", __FILE__, __LINE__);
3561                 rc = ENOMEM;
3562                 goto bce_dma_alloc_exit;
3563         }
3564
3565         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3566             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3567             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3568
3569         if (error) {
3570                 BCE_PRINTF("%s(%d): Could not map status block "
3571                     "DMA memory!\n", __FILE__, __LINE__);
3572                 rc = ENOMEM;
3573                 goto bce_dma_alloc_exit;
3574         }
3575
3576         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3577             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3578
3579         /*
3580          * Create a DMA tag for the statistics block, allocate and clear the
3581          * memory, map the memory into DMA space, and fetch the physical
3582          * address of the block.
3583          */
3584         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3585             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3586             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3587             0, NULL, NULL, &sc->stats_tag)) {
3588                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3589                     "DMA tag!\n", __FILE__, __LINE__);
3590                 rc = ENOMEM;
3591                 goto bce_dma_alloc_exit;
3592         }
3593
3594         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3595             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3596                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3597                     "DMA memory!\n", __FILE__, __LINE__);
3598                 rc = ENOMEM;
3599                 goto bce_dma_alloc_exit;
3600         }
3601
3602         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3603             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3604             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3605
3606         if(error) {
3607                 BCE_PRINTF("%s(%d): Could not map statistics block "
3608                     "DMA memory!\n", __FILE__, __LINE__);
3609                 rc = ENOMEM;
3610                 goto bce_dma_alloc_exit;
3611         }
3612
3613         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3614             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3615
3616         /* BCM5709 uses host memory as cache for context memory. */
3617         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3618                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3619                 if (sc->ctx_pages == 0)
3620                         sc->ctx_pages = 1;
3621
3622                 DBRUNIF((sc->ctx_pages > 512),
3623                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3624                     __FILE__, __LINE__, sc->ctx_pages));
3625
3626                 /*
3627                  * Create a DMA tag for the context pages,
3628                  * allocate and clear the memory, map the
3629                  * memory into DMA space, and fetch the
3630                  * physical address of the block.
3631                  */
3632                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3633                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3634                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3635                     0, NULL, NULL, &sc->ctx_tag)) {
3636                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3637                             "DMA tag!\n", __FILE__, __LINE__);
3638                         rc = ENOMEM;
3639                         goto bce_dma_alloc_exit;
3640                 }
3641
3642                 for (i = 0; i < sc->ctx_pages; i++) {
3643
3644                         if(bus_dmamem_alloc(sc->ctx_tag,
3645                             (void **)&sc->ctx_block[i],
3646                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3647                             &sc->ctx_map[i])) {
3648                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3649                                     "DMA memory!\n", __FILE__, __LINE__);
3650                                 rc = ENOMEM;
3651                                 goto bce_dma_alloc_exit;
3652                         }
3653
3654                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3655                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3656                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3657
3658                         if (error) {
3659                                 BCE_PRINTF("%s(%d): Could not map CTX "
3660                                     "DMA memory!\n", __FILE__, __LINE__);
3661                                 rc = ENOMEM;
3662                                 goto bce_dma_alloc_exit;
3663                         }
3664
3665                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3666                             "= 0x%jX\n", __FUNCTION__, i,
3667                             (uintmax_t) sc->ctx_paddr[i]);
3668                 }
3669         }
3670
3671         /*
3672          * Create a DMA tag for the TX buffer descriptor chain,
3673          * allocate and clear the  memory, and fetch the
3674          * physical address of the block.
3675          */
3676         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3677             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3678             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3679             NULL, NULL, &sc->tx_bd_chain_tag)) {
3680                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3681                     "chain DMA tag!\n", __FILE__, __LINE__);
3682                 rc = ENOMEM;
3683                 goto bce_dma_alloc_exit;
3684         }
3685
3686         for (i = 0; i < sc->tx_pages; i++) {
3687
3688                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3689                     (void **)&sc->tx_bd_chain[i],
3690                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3691                     &sc->tx_bd_chain_map[i])) {
3692                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3693                             "chain DMA memory!\n", __FILE__, __LINE__);
3694                         rc = ENOMEM;
3695                         goto bce_dma_alloc_exit;
3696                 }
3697
3698                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3699                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3700                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3701                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3702
3703                 if (error) {
3704                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3705                             "chain DMA memory!\n", __FILE__, __LINE__);
3706                         rc = ENOMEM;
3707                         goto bce_dma_alloc_exit;
3708                 }
3709
3710                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3711                     "0x%jX\n", __FUNCTION__, i,
3712                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3713         }
3714
3715         /* Check the required size before mapping to conserve resources. */
3716         if (bce_tso_enable) {
3717                 max_size     = BCE_TSO_MAX_SIZE;
3718                 max_segments = BCE_MAX_SEGMENTS;
3719                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3720         } else {
3721                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3722                 max_segments = BCE_MAX_SEGMENTS;
3723                 max_seg_size = MCLBYTES;
3724         }
3725
3726         /* Create a DMA tag for TX mbufs. */
3727         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3728             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3729             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3730                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3731                     __FILE__, __LINE__);
3732                 rc = ENOMEM;
3733                 goto bce_dma_alloc_exit;
3734         }
3735
3736         /* Create DMA maps for the TX mbufs clusters. */
3737         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3738                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3739                         &sc->tx_mbuf_map[i])) {
3740                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3741                             "map!\n", __FILE__, __LINE__);
3742                         rc = ENOMEM;
3743                         goto bce_dma_alloc_exit;
3744                 }
3745         }
3746
3747         /*
3748          * Create a DMA tag for the RX buffer descriptor chain,
3749          * allocate and clear the memory, and fetch the physical
3750          * address of the blocks.
3751          */
3752         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3753                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3754                         sc->max_bus_addr, NULL, NULL,
3755                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3756                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3757                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3758                     "DMA tag!\n", __FILE__, __LINE__);
3759                 rc = ENOMEM;
3760                 goto bce_dma_alloc_exit;
3761         }
3762
3763         for (i = 0; i < sc->rx_pages; i++) {
3764
3765                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3766                     (void **)&sc->rx_bd_chain[i],
3767                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3768                     &sc->rx_bd_chain_map[i])) {
3769                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3770                             "chain DMA memory!\n", __FILE__, __LINE__);
3771                         rc = ENOMEM;
3772                         goto bce_dma_alloc_exit;
3773                 }
3774
3775                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3776                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3777                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3778                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3779
3780                 if (error) {
3781                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3782                             "chain DMA memory!\n", __FILE__, __LINE__);
3783                         rc = ENOMEM;
3784                         goto bce_dma_alloc_exit;
3785                 }
3786
3787                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3788                     "0x%jX\n", __FUNCTION__, i,
3789                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3790         }
3791
3792         /*
3793          * Create a DMA tag for RX mbufs.
3794          */
3795         if (bce_hdr_split == TRUE)
3796                 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3797                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3798         else
3799                 max_size = max_seg_size = MJUM9BYTES;
3800         max_segments = 1;
3801
3802         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3803             "(max size = 0x%jX max segments = %d, max segment "
3804             "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3805              max_segments, (uintmax_t) max_seg_size);
3806
3807         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3808             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3809             max_size, max_segments, max_seg_size, 0, NULL, NULL,
3810             &sc->rx_mbuf_tag)) {
3811                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3812                     __FILE__, __LINE__);
3813                 rc = ENOMEM;
3814                 goto bce_dma_alloc_exit;
3815         }
3816
3817         /* Create DMA maps for the RX mbuf clusters. */
3818         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3819                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3820                     &sc->rx_mbuf_map[i])) {
3821                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3822                             "DMA map!\n", __FILE__, __LINE__);
3823                         rc = ENOMEM;
3824                         goto bce_dma_alloc_exit;
3825                 }
3826         }
3827
3828         if (bce_hdr_split == TRUE) {
3829                 /*
3830                  * Create a DMA tag for the page buffer descriptor chain,
3831                  * allocate and clear the memory, and fetch the physical
3832                  * address of the blocks.
3833                  */
3834                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3835                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3836                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3837                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3838                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3839                             "chain DMA tag!\n", __FILE__, __LINE__);
3840                         rc = ENOMEM;
3841                         goto bce_dma_alloc_exit;
3842                 }
3843
3844                 for (i = 0; i < sc->pg_pages; i++) {
3845                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3846                             (void **)&sc->pg_bd_chain[i],
3847                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3848                             &sc->pg_bd_chain_map[i])) {
3849                                 BCE_PRINTF("%s(%d): Could not allocate page "
3850                                     "descriptor chain DMA memory!\n",
3851                                     __FILE__, __LINE__);
3852                                 rc = ENOMEM;
3853                                 goto bce_dma_alloc_exit;
3854                         }
3855
3856                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3857                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3858                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3859                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3860
3861                         if (error) {
3862                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3863                                         "chain DMA memory!\n", __FILE__, __LINE__);
3864                                 rc = ENOMEM;
3865                                 goto bce_dma_alloc_exit;
3866                         }
3867
3868                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3869                                 "0x%jX\n", __FUNCTION__, i,
3870                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3871                 }
3872
3873                 /*
3874                  * Create a DMA tag for page mbufs.
3875                  */
3876                 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3877                         MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3878
3879                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3880                         sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3881                         max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3882                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3883                                 "DMA tag!\n", __FILE__, __LINE__);
3884                         rc = ENOMEM;
3885                         goto bce_dma_alloc_exit;
3886                 }
3887
3888                 /* Create DMA maps for the page mbuf clusters. */
3889                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3890                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3891                                 &sc->pg_mbuf_map[i])) {
3892                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3893                                         "DMA map!\n", __FILE__, __LINE__);
3894                                 rc = ENOMEM;
3895                                 goto bce_dma_alloc_exit;
3896                         }
3897                 }
3898         }
3899
3900 bce_dma_alloc_exit:
3901         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3902         return(rc);
3903 }
3904
3905
3906 /****************************************************************************/
3907 /* Release all resources used by the driver.                                */
3908 /*                                                                          */
3909 /* Releases all resources acquired by the driver including interrupts,      */
3910 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3911 /*                                                                          */
3912 /* Returns:                                                                 */
3913 /*   Nothing.                                                               */
3914 /****************************************************************************/
3915 static void
3916 bce_release_resources(struct bce_softc *sc)
3917 {
3918         device_t dev;
3919
3920         DBENTER(BCE_VERBOSE_RESET);
3921
3922         dev = sc->bce_dev;
3923
3924         bce_dma_free(sc);
3925
3926         if (sc->bce_intrhand != NULL) {
3927                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3928                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3929         }
3930
3931         if (sc->bce_res_irq != NULL) {
3932                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3933                 bus_release_resource(dev, SYS_RES_IRQ,
3934                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3935         }
3936
3937         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3938                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3939                 pci_release_msi(dev);
3940         }
3941
3942         if (sc->bce_res_mem != NULL) {
3943                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3944                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3945                     sc->bce_res_mem);
3946         }
3947
3948         if (sc->bce_ifp != NULL) {
3949                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3950                 if_free(sc->bce_ifp);
3951         }
3952
3953         if (mtx_initialized(&sc->bce_mtx))
3954                 BCE_LOCK_DESTROY(sc);
3955
3956         DBEXIT(BCE_VERBOSE_RESET);
3957 }
3958
3959
3960 /****************************************************************************/
3961 /* Firmware synchronization.                                                */
3962 /*                                                                          */
3963 /* Before performing certain events such as a chip reset, synchronize with  */
3964 /* the firmware first.                                                      */
3965 /*                                                                          */
3966 /* Returns:                                                                 */
3967 /*   0 for success, positive value for failure.                             */
3968 /****************************************************************************/
3969 static int
3970 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3971 {
3972         int i, rc = 0;
3973         u32 val;
3974
3975         DBENTER(BCE_VERBOSE_RESET);
3976
3977         /* Don't waste any time if we've timed out before. */
3978         if (sc->bce_fw_timed_out == TRUE) {
3979                 rc = EBUSY;
3980                 goto bce_fw_sync_exit;
3981         }
3982
3983         /* Increment the message sequence number. */
3984         sc->bce_fw_wr_seq++;
3985         msg_data |= sc->bce_fw_wr_seq;
3986
3987         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3988             "0x%08X\n", msg_data);
3989
3990         /* Send the message to the bootcode driver mailbox. */
3991         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3992
3993         /* Wait for the bootcode to acknowledge the message. */
3994         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3995                 /* Check for a response in the bootcode firmware mailbox. */
3996                 val = bce_shmem_rd(sc, BCE_FW_MB);
3997                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3998                         break;
3999                 DELAY(1000);
4000         }
4001
4002         /* If we've timed out, tell bootcode that we've stopped waiting. */
4003         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
4004             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
4005
4006                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
4007                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
4008
4009                 msg_data &= ~BCE_DRV_MSG_CODE;
4010                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4011
4012                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4013
4014                 sc->bce_fw_timed_out = TRUE;
4015                 rc = EBUSY;
4016         }
4017
4018 bce_fw_sync_exit:
4019         DBEXIT(BCE_VERBOSE_RESET);
4020         return (rc);
4021 }
4022
4023
4024 /****************************************************************************/
4025 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4026 /*                                                                          */
4027 /* Returns:                                                                 */
4028 /*   Nothing.                                                               */
4029 /****************************************************************************/
4030 static void
4031 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
4032         u32 rv2p_code_len, u32 rv2p_proc)
4033 {
4034         int i;
4035         u32 val;
4036
4037         DBENTER(BCE_VERBOSE_RESET);
4038
4039         /* Set the page size used by RV2P. */
4040         if (rv2p_proc == RV2P_PROC2) {
4041                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4042         }
4043
4044         for (i = 0; i < rv2p_code_len; i += 8) {
4045                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4046                 rv2p_code++;
4047                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4048                 rv2p_code++;
4049
4050                 if (rv2p_proc == RV2P_PROC1) {
4051                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4052                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4053                 }
4054                 else {
4055                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4056                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4057                 }
4058         }
4059
4060         /* Reset the processor, un-stall is done later. */
4061         if (rv2p_proc == RV2P_PROC1) {
4062                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4063         }
4064         else {
4065                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4066         }
4067
4068         DBEXIT(BCE_VERBOSE_RESET);
4069 }
4070
4071
4072 /****************************************************************************/
4073 /* Load RISC processor firmware.                                            */
4074 /*                                                                          */
4075 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4076 /* associated with a particular processor.                                  */
4077 /*                                                                          */
4078 /* Returns:                                                                 */
4079 /*   Nothing.                                                               */
4080 /****************************************************************************/
4081 static void
4082 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4083         struct fw_info *fw)
4084 {
4085         u32 offset;
4086
4087         DBENTER(BCE_VERBOSE_RESET);
4088
4089     bce_halt_cpu(sc, cpu_reg);
4090
4091         /* Load the Text area. */
4092         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4093         if (fw->text) {
4094                 int j;
4095
4096                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4097                         REG_WR_IND(sc, offset, fw->text[j]);
4098                 }
4099         }
4100
4101         /* Load the Data area. */
4102         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4103         if (fw->data) {
4104                 int j;
4105
4106                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4107                         REG_WR_IND(sc, offset, fw->data[j]);
4108                 }
4109         }
4110
4111         /* Load the SBSS area. */
4112         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4113         if (fw->sbss) {
4114                 int j;
4115
4116                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4117                         REG_WR_IND(sc, offset, fw->sbss[j]);
4118                 }
4119         }
4120
4121         /* Load the BSS area. */
4122         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4123         if (fw->bss) {
4124                 int j;
4125
4126                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4127                         REG_WR_IND(sc, offset, fw->bss[j]);
4128                 }
4129         }
4130
4131         /* Load the Read-Only area. */
4132         offset = cpu_reg->spad_base +
4133                 (fw->rodata_addr - cpu_reg->mips_view_base);
4134         if (fw->rodata) {
4135                 int j;
4136
4137                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4138                         REG_WR_IND(sc, offset, fw->rodata[j]);
4139                 }
4140         }
4141
4142         /* Clear the pre-fetch instruction and set the FW start address. */
4143         REG_WR_IND(sc, cpu_reg->inst, 0);
4144         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4145
4146         DBEXIT(BCE_VERBOSE_RESET);
4147 }
4148
4149
4150 /****************************************************************************/
4151 /* Starts the RISC processor.                                               */
4152 /*                                                                          */
4153 /* Assumes the CPU starting address has already been set.                   */
4154 /*                                                                          */
4155 /* Returns:                                                                 */
4156 /*   Nothing.                                                               */
4157 /****************************************************************************/
4158 static void
4159 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4160 {
4161         u32 val;
4162
4163         DBENTER(BCE_VERBOSE_RESET);
4164
4165         /* Start the CPU. */
4166         val = REG_RD_IND(sc, cpu_reg->mode);
4167         val &= ~cpu_reg->mode_value_halt;
4168         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4169         REG_WR_IND(sc, cpu_reg->mode, val);
4170
4171         DBEXIT(BCE_VERBOSE_RESET);
4172 }
4173
4174
4175 /****************************************************************************/
4176 /* Halts the RISC processor.                                                */
4177 /*                                                                          */
4178 /* Returns:                                                                 */
4179 /*   Nothing.                                                               */
4180 /****************************************************************************/
4181 static void
4182 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4183 {
4184         u32 val;
4185
4186         DBENTER(BCE_VERBOSE_RESET);
4187
4188         /* Halt the CPU. */
4189         val = REG_RD_IND(sc, cpu_reg->mode);
4190         val |= cpu_reg->mode_value_halt;
4191         REG_WR_IND(sc, cpu_reg->mode, val);
4192         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4193
4194         DBEXIT(BCE_VERBOSE_RESET);
4195 }
4196
4197
4198 /****************************************************************************/
4199 /* Initialize the RX CPU.                                                   */
4200 /*                                                                          */
4201 /* Returns:                                                                 */
4202 /*   Nothing.                                                               */
4203 /****************************************************************************/
4204 static void
4205 bce_start_rxp_cpu(struct bce_softc *sc)
4206 {
4207         struct cpu_reg cpu_reg;
4208
4209         DBENTER(BCE_VERBOSE_RESET);
4210
4211         cpu_reg.mode = BCE_RXP_CPU_MODE;
4212         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4213         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4214         cpu_reg.state = BCE_RXP_CPU_STATE;
4215         cpu_reg.state_value_clear = 0xffffff;
4216         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4217         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4218         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4219         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4220         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4221         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4222         cpu_reg.mips_view_base = 0x8000000;
4223
4224         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4225         bce_start_cpu(sc, &cpu_reg);
4226
4227         DBEXIT(BCE_VERBOSE_RESET);
4228 }
4229
4230
4231 /****************************************************************************/
4232 /* Initialize the RX CPU.                                                   */
4233 /*                                                                          */
4234 /* Returns:                                                                 */
4235 /*   Nothing.                                                               */
4236 /****************************************************************************/
4237 static void
4238 bce_init_rxp_cpu(struct bce_softc *sc)
4239 {
4240         struct cpu_reg cpu_reg;
4241         struct fw_info fw;
4242
4243         DBENTER(BCE_VERBOSE_RESET);
4244
4245         cpu_reg.mode = BCE_RXP_CPU_MODE;
4246         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4247         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4248         cpu_reg.state = BCE_RXP_CPU_STATE;
4249         cpu_reg.state_value_clear = 0xffffff;
4250         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4251         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4252         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4253         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4254         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4255         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4256         cpu_reg.mips_view_base = 0x8000000;
4257
4258         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4259                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4260                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4261                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4262                 fw.start_addr = bce_RXP_b09FwStartAddr;
4263
4264                 fw.text_addr = bce_RXP_b09FwTextAddr;
4265                 fw.text_len = bce_RXP_b09FwTextLen;
4266                 fw.text_index = 0;
4267                 fw.text = bce_RXP_b09FwText;
4268
4269                 fw.data_addr = bce_RXP_b09FwDataAddr;
4270                 fw.data_len = bce_RXP_b09FwDataLen;
4271                 fw.data_index = 0;
4272                 fw.data = bce_RXP_b09FwData;
4273
4274                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4275                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4276                 fw.sbss_index = 0;
4277                 fw.sbss = bce_RXP_b09FwSbss;
4278
4279                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4280                 fw.bss_len = bce_RXP_b09FwBssLen;
4281                 fw.bss_index = 0;
4282                 fw.bss = bce_RXP_b09FwBss;
4283
4284                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4285                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4286                 fw.rodata_index = 0;
4287                 fw.rodata = bce_RXP_b09FwRodata;
4288         } else {
4289                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4290                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4291                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4292                 fw.start_addr = bce_RXP_b06FwStartAddr;
4293
4294                 fw.text_addr = bce_RXP_b06FwTextAddr;
4295                 fw.text_len = bce_RXP_b06FwTextLen;
4296                 fw.text_index = 0;
4297                 fw.text = bce_RXP_b06FwText;
4298
4299                 fw.data_addr = bce_RXP_b06FwDataAddr;
4300                 fw.data_len = bce_RXP_b06FwDataLen;
4301                 fw.data_index = 0;
4302                 fw.data = bce_RXP_b06FwData;
4303
4304                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4305                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4306                 fw.sbss_index = 0;
4307                 fw.sbss = bce_RXP_b06FwSbss;
4308
4309                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4310                 fw.bss_len = bce_RXP_b06FwBssLen;
4311                 fw.bss_index = 0;
4312                 fw.bss = bce_RXP_b06FwBss;
4313
4314                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4315                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4316                 fw.rodata_index = 0;
4317                 fw.rodata = bce_RXP_b06FwRodata;
4318         }
4319
4320         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4321         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4322
4323     /* Delay RXP start until initialization is complete. */
4324
4325         DBEXIT(BCE_VERBOSE_RESET);
4326 }
4327
4328
4329 /****************************************************************************/
4330 /* Initialize the TX CPU.                                                   */
4331 /*                                                                          */
4332 /* Returns:                                                                 */
4333 /*   Nothing.                                                               */
4334 /****************************************************************************/
4335 static void
4336 bce_init_txp_cpu(struct bce_softc *sc)
4337 {
4338         struct cpu_reg cpu_reg;
4339         struct fw_info fw;
4340
4341         DBENTER(BCE_VERBOSE_RESET);
4342
4343         cpu_reg.mode = BCE_TXP_CPU_MODE;
4344         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4345         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4346         cpu_reg.state = BCE_TXP_CPU_STATE;
4347         cpu_reg.state_value_clear = 0xffffff;
4348         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4349         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4350         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4351         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4352         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4353         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4354         cpu_reg.mips_view_base = 0x8000000;
4355
4356         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4357                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4358                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4359                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4360                 fw.start_addr = bce_TXP_b09FwStartAddr;
4361
4362                 fw.text_addr = bce_TXP_b09FwTextAddr;
4363                 fw.text_len = bce_TXP_b09FwTextLen;
4364                 fw.text_index = 0;
4365                 fw.text = bce_TXP_b09FwText;
4366
4367                 fw.data_addr = bce_TXP_b09FwDataAddr;
4368                 fw.data_len = bce_TXP_b09FwDataLen;
4369                 fw.data_index = 0;
4370                 fw.data = bce_TXP_b09FwData;
4371
4372                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4373                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4374                 fw.sbss_index = 0;
4375                 fw.sbss = bce_TXP_b09FwSbss;
4376
4377                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4378                 fw.bss_len = bce_TXP_b09FwBssLen;
4379                 fw.bss_index = 0;
4380                 fw.bss = bce_TXP_b09FwBss;
4381
4382                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4383                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4384                 fw.rodata_index = 0;
4385                 fw.rodata = bce_TXP_b09FwRodata;
4386         } else {
4387                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4388                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4389                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4390                 fw.start_addr = bce_TXP_b06FwStartAddr;
4391
4392                 fw.text_addr = bce_TXP_b06FwTextAddr;
4393                 fw.text_len = bce_TXP_b06FwTextLen;
4394                 fw.text_index = 0;
4395                 fw.text = bce_TXP_b06FwText;
4396
4397                 fw.data_addr = bce_TXP_b06FwDataAddr;
4398                 fw.data_len = bce_TXP_b06FwDataLen;
4399                 fw.data_index = 0;
4400                 fw.data = bce_TXP_b06FwData;
4401
4402                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4403                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4404                 fw.sbss_index = 0;
4405                 fw.sbss = bce_TXP_b06FwSbss;
4406
4407                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4408                 fw.bss_len = bce_TXP_b06FwBssLen;
4409                 fw.bss_index = 0;
4410                 fw.bss = bce_TXP_b06FwBss;
4411
4412                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4413                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4414                 fw.rodata_index = 0;
4415                 fw.rodata = bce_TXP_b06FwRodata;
4416         }
4417
4418         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4419         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4420     bce_start_cpu(sc, &cpu_reg);
4421
4422         DBEXIT(BCE_VERBOSE_RESET);
4423 }
4424
4425
4426 /****************************************************************************/
4427 /* Initialize the TPAT CPU.                                                 */
4428 /*                                                                          */
4429 /* Returns:                                                                 */
4430 /*   Nothing.                                                               */
4431 /****************************************************************************/
4432 static void
4433 bce_init_tpat_cpu(struct bce_softc *sc)
4434 {
4435         struct cpu_reg cpu_reg;
4436         struct fw_info fw;
4437
4438         DBENTER(BCE_VERBOSE_RESET);
4439
4440         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4441         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4442         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4443         cpu_reg.state = BCE_TPAT_CPU_STATE;
4444         cpu_reg.state_value_clear = 0xffffff;
4445         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4446         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4447         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4448         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4449         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4450         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4451         cpu_reg.mips_view_base = 0x8000000;
4452
4453         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4454                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4455                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4456                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4457                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4458
4459                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4460                 fw.text_len = bce_TPAT_b09FwTextLen;
4461                 fw.text_index = 0;
4462                 fw.text = bce_TPAT_b09FwText;
4463
4464                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4465                 fw.data_len = bce_TPAT_b09FwDataLen;
4466                 fw.data_index = 0;
4467                 fw.data = bce_TPAT_b09FwData;
4468
4469                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4470                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4471                 fw.sbss_index = 0;
4472                 fw.sbss = bce_TPAT_b09FwSbss;
4473
4474                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4475                 fw.bss_len = bce_TPAT_b09FwBssLen;
4476                 fw.bss_index = 0;
4477                 fw.bss = bce_TPAT_b09FwBss;
4478
4479                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4480                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4481                 fw.rodata_index = 0;
4482                 fw.rodata = bce_TPAT_b09FwRodata;
4483         } else {
4484                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4485                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4486                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4487                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4488
4489                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4490                 fw.text_len = bce_TPAT_b06FwTextLen;
4491                 fw.text_index = 0;
4492                 fw.text = bce_TPAT_b06FwText;
4493
4494                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4495                 fw.data_len = bce_TPAT_b06FwDataLen;
4496                 fw.data_index = 0;
4497                 fw.data = bce_TPAT_b06FwData;
4498
4499                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4500                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4501                 fw.sbss_index = 0;
4502                 fw.sbss = bce_TPAT_b06FwSbss;
4503
4504                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4505                 fw.bss_len = bce_TPAT_b06FwBssLen;
4506                 fw.bss_index = 0;
4507                 fw.bss = bce_TPAT_b06FwBss;
4508
4509                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4510                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4511                 fw.rodata_index = 0;
4512                 fw.rodata = bce_TPAT_b06FwRodata;
4513         }
4514
4515         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4516         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4517         bce_start_cpu(sc, &cpu_reg);
4518
4519         DBEXIT(BCE_VERBOSE_RESET);
4520 }
4521
4522
4523 /****************************************************************************/
4524 /* Initialize the CP CPU.                                                   */
4525 /*                                                                          */
4526 /* Returns:                                                                 */
4527 /*   Nothing.                                                               */
4528 /****************************************************************************/
4529 static void
4530 bce_init_cp_cpu(struct bce_softc *sc)
4531 {
4532         struct cpu_reg cpu_reg;
4533         struct fw_info fw;
4534
4535         DBENTER(BCE_VERBOSE_RESET);
4536
4537         cpu_reg.mode = BCE_CP_CPU_MODE;
4538         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4539         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4540         cpu_reg.state = BCE_CP_CPU_STATE;
4541         cpu_reg.state_value_clear = 0xffffff;
4542         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4543         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4544         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4545         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4546         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4547         cpu_reg.spad_base = BCE_CP_SCRATCH;
4548         cpu_reg.mips_view_base = 0x8000000;
4549
4550         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4551                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4552                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4553                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4554                 fw.start_addr = bce_CP_b09FwStartAddr;
4555
4556                 fw.text_addr = bce_CP_b09FwTextAddr;
4557                 fw.text_len = bce_CP_b09FwTextLen;
4558                 fw.text_index = 0;
4559                 fw.text = bce_CP_b09FwText;
4560
4561                 fw.data_addr = bce_CP_b09FwDataAddr;
4562                 fw.data_len = bce_CP_b09FwDataLen;
4563                 fw.data_index = 0;
4564                 fw.data = bce_CP_b09FwData;
4565
4566                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4567                 fw.sbss_len = bce_CP_b09FwSbssLen;
4568                 fw.sbss_index = 0;
4569                 fw.sbss = bce_CP_b09FwSbss;
4570
4571                 fw.bss_addr = bce_CP_b09FwBssAddr;
4572                 fw.bss_len = bce_CP_b09FwBssLen;
4573                 fw.bss_index = 0;
4574                 fw.bss = bce_CP_b09FwBss;
4575
4576                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4577                 fw.rodata_len = bce_CP_b09FwRodataLen;
4578                 fw.rodata_index = 0;
4579                 fw.rodata = bce_CP_b09FwRodata;
4580         } else {
4581                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4582                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4583                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4584                 fw.start_addr = bce_CP_b06FwStartAddr;
4585
4586                 fw.text_addr = bce_CP_b06FwTextAddr;
4587                 fw.text_len = bce_CP_b06FwTextLen;
4588                 fw.text_index = 0;
4589                 fw.text = bce_CP_b06FwText;
4590
4591                 fw.data_addr = bce_CP_b06FwDataAddr;
4592                 fw.data_len = bce_CP_b06FwDataLen;
4593                 fw.data_index = 0;
4594                 fw.data = bce_CP_b06FwData;
4595
4596                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4597                 fw.sbss_len = bce_CP_b06FwSbssLen;
4598                 fw.sbss_index = 0;
4599                 fw.sbss = bce_CP_b06FwSbss;
4600
4601                 fw.bss_addr = bce_CP_b06FwBssAddr;
4602                 fw.bss_len = bce_CP_b06FwBssLen;
4603                 fw.bss_index = 0;
4604                 fw.bss = bce_CP_b06FwBss;
4605
4606                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4607                 fw.rodata_len = bce_CP_b06FwRodataLen;
4608                 fw.rodata_index = 0;
4609                 fw.rodata = bce_CP_b06FwRodata;
4610         }
4611
4612         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4613         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4614         bce_start_cpu(sc, &cpu_reg);
4615
4616         DBEXIT(BCE_VERBOSE_RESET);
4617 }
4618
4619
4620 /****************************************************************************/
4621 /* Initialize the COM CPU.                                                 */
4622 /*                                                                          */
4623 /* Returns:                                                                 */
4624 /*   Nothing.                                                               */
4625 /****************************************************************************/
4626 static void
4627 bce_init_com_cpu(struct bce_softc *sc)
4628 {
4629         struct cpu_reg cpu_reg;
4630         struct fw_info fw;
4631
4632         DBENTER(BCE_VERBOSE_RESET);
4633
4634         cpu_reg.mode = BCE_COM_CPU_MODE;
4635         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4636         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4637         cpu_reg.state = BCE_COM_CPU_STATE;
4638         cpu_reg.state_value_clear = 0xffffff;
4639         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4640         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4641         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4642         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4643         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4644         cpu_reg.spad_base = BCE_COM_SCRATCH;
4645         cpu_reg.mips_view_base = 0x8000000;
4646
4647         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4648                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4649                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4650                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4651                 fw.start_addr = bce_COM_b09FwStartAddr;
4652
4653                 fw.text_addr = bce_COM_b09FwTextAddr;
4654                 fw.text_len = bce_COM_b09FwTextLen;
4655                 fw.text_index = 0;
4656                 fw.text = bce_COM_b09FwText;
4657
4658                 fw.data_addr = bce_COM_b09FwDataAddr;
4659                 fw.data_len = bce_COM_b09FwDataLen;
4660                 fw.data_index = 0;
4661                 fw.data = bce_COM_b09FwData;
4662
4663                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4664                 fw.sbss_len = bce_COM_b09FwSbssLen;
4665                 fw.sbss_index = 0;
4666                 fw.sbss = bce_COM_b09FwSbss;
4667
4668                 fw.bss_addr = bce_COM_b09FwBssAddr;
4669                 fw.bss_len = bce_COM_b09FwBssLen;
4670                 fw.bss_index = 0;
4671                 fw.bss = bce_COM_b09FwBss;
4672
4673                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4674                 fw.rodata_len = bce_COM_b09FwRodataLen;
4675                 fw.rodata_index = 0;
4676                 fw.rodata = bce_COM_b09FwRodata;
4677         } else {
4678                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4679                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4680                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4681                 fw.start_addr = bce_COM_b06FwStartAddr;
4682
4683                 fw.text_addr = bce_COM_b06FwTextAddr;
4684                 fw.text_len = bce_COM_b06FwTextLen;
4685                 fw.text_index = 0;
4686                 fw.text = bce_COM_b06FwText;
4687
4688                 fw.data_addr = bce_COM_b06FwDataAddr;
4689                 fw.data_len = bce_COM_b06FwDataLen;
4690                 fw.data_index = 0;
4691                 fw.data = bce_COM_b06FwData;
4692
4693                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4694                 fw.sbss_len = bce_COM_b06FwSbssLen;
4695                 fw.sbss_index = 0;
4696                 fw.sbss = bce_COM_b06FwSbss;
4697
4698                 fw.bss_addr = bce_COM_b06FwBssAddr;
4699                 fw.bss_len = bce_COM_b06FwBssLen;
4700                 fw.bss_index = 0;
4701                 fw.bss = bce_COM_b06FwBss;
4702
4703                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4704                 fw.rodata_len = bce_COM_b06FwRodataLen;
4705                 fw.rodata_index = 0;
4706                 fw.rodata = bce_COM_b06FwRodata;
4707         }
4708
4709         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4710         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4711         bce_start_cpu(sc, &cpu_reg);
4712
4713         DBEXIT(BCE_VERBOSE_RESET);
4714 }
4715
4716
4717 /****************************************************************************/
4718 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4719 /*                                                                          */
4720 /* Loads the firmware for each CPU and starts the CPU.                      */
4721 /*                                                                          */
4722 /* Returns:                                                                 */
4723 /*   Nothing.                                                               */
4724 /****************************************************************************/
4725 static void
4726 bce_init_cpus(struct bce_softc *sc)
4727 {
4728         DBENTER(BCE_VERBOSE_RESET);
4729
4730         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4731
4732                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4733                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4734                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4735                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4736                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4737                 } else {
4738                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4739                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4740                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4741                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4742                 }
4743
4744         } else {
4745                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4746                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4747                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4748                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4749         }
4750
4751         bce_init_rxp_cpu(sc);
4752         bce_init_txp_cpu(sc);
4753         bce_init_tpat_cpu(sc);
4754         bce_init_com_cpu(sc);
4755         bce_init_cp_cpu(sc);
4756
4757         DBEXIT(BCE_VERBOSE_RESET);
4758 }
4759
4760
4761 /****************************************************************************/
4762 /* Initialize context memory.                                               */
4763 /*                                                                          */
4764 /* Clears the memory associated with each Context ID (CID).                 */
4765 /*                                                                          */
4766 /* Returns:                                                                 */
4767 /*   Nothing.                                                               */
4768 /****************************************************************************/
4769 static int
4770 bce_init_ctx(struct bce_softc *sc)
4771 {
4772         u32 offset, val, vcid_addr;
4773         int i, j, rc, retry_cnt;
4774
4775         rc = 0;
4776         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4777
4778         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4779                 retry_cnt = CTX_INIT_RETRY_COUNT;
4780
4781                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4782
4783                 /*
4784                  * BCM5709 context memory may be cached
4785                  * in host memory so prepare the host memory
4786                  * for access.
4787                  */
4788                 val = BCE_CTX_COMMAND_ENABLED |
4789                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4790                 val |= (BCM_PAGE_BITS - 8) << 16;
4791                 REG_WR(sc, BCE_CTX_COMMAND, val);
4792
4793                 /* Wait for mem init command to complete. */
4794                 for (i = 0; i < retry_cnt; i++) {
4795                         val = REG_RD(sc, BCE_CTX_COMMAND);
4796                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4797                                 break;
4798                         DELAY(2);
4799                 }
4800                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4801                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4802                             __FUNCTION__);
4803                         rc = EBUSY;
4804                         goto init_ctx_fail;
4805                 }
4806
4807                 for (i = 0; i < sc->ctx_pages; i++) {
4808                         /* Set the physical address of the context memory. */
4809                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4810                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4811                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4812                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4813                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4814                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4815                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4816
4817                         /* Verify the context memory write was successful. */
4818                         for (j = 0; j < retry_cnt; j++) {
4819                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4820                                 if ((val &
4821                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4822                                         break;
4823                                 DELAY(5);
4824                         }
4825                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4826                                 BCE_PRINTF("%s(): Failed to initialize "
4827                                     "context page %d!\n", __FUNCTION__, i);
4828                                 rc = EBUSY;
4829                                 goto init_ctx_fail;
4830                         }
4831                 }
4832         } else {
4833
4834                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4835
4836                 /*
4837                  * For the 5706/5708, context memory is local to
4838                  * the controller, so initialize the controller
4839                  * context memory.
4840                  */
4841
4842                 vcid_addr = GET_CID_ADDR(96);
4843                 while (vcid_addr) {
4844
4845                         vcid_addr -= PHY_CTX_SIZE;
4846
4847                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4848                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4849
4850                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4851                                 CTX_WR(sc, 0x00, offset, 0);
4852                         }
4853
4854                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4855                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4856                 }
4857
4858         }
4859 init_ctx_fail:
4860         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4861         return (rc);
4862 }
4863
4864
4865 /****************************************************************************/
4866 /* Fetch the permanent MAC address of the controller.                       */
4867 /*                                                                          */
4868 /* Returns:                                                                 */
4869 /*   Nothing.                                                               */
4870 /****************************************************************************/
4871 static void
4872 bce_get_mac_addr(struct bce_softc *sc)
4873 {
4874         u32 mac_lo = 0, mac_hi = 0;
4875
4876         DBENTER(BCE_VERBOSE_RESET);
4877
4878         /*
4879          * The NetXtreme II bootcode populates various NIC
4880          * power-on and runtime configuration items in a
4881          * shared memory area.  The factory configured MAC
4882          * address is available from both NVRAM and the
4883          * shared memory area so we'll read the value from
4884          * shared memory for speed.
4885          */
4886
4887         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4888         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4889
4890         if ((mac_lo == 0) && (mac_hi == 0)) {
4891                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4892                     __FILE__, __LINE__);
4893         } else {
4894                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4895                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4896                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4897                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4898                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4899                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4900         }
4901
4902         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4903             "address = %6D\n", sc->eaddr, ":");
4904         DBEXIT(BCE_VERBOSE_RESET);
4905 }
4906
4907
4908 /****************************************************************************/
4909 /* Program the MAC address.                                                 */
4910 /*                                                                          */
4911 /* Returns:                                                                 */
4912 /*   Nothing.                                                               */
4913 /****************************************************************************/
4914 static void
4915 bce_set_mac_addr(struct bce_softc *sc)
4916 {
4917         u32 val;
4918         u8 *mac_addr = sc->eaddr;
4919
4920         /* ToDo: Add support for setting multiple MAC addresses. */
4921
4922         DBENTER(BCE_VERBOSE_RESET);
4923         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4924             "%6D\n", sc->eaddr, ":");
4925
4926         val = (mac_addr[0] << 8) | mac_addr[1];
4927
4928         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4929
4930         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4931             (mac_addr[4] << 8) | mac_addr[5];
4932
4933         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4934
4935         DBEXIT(BCE_VERBOSE_RESET);
4936 }
4937
4938
4939 /****************************************************************************/
4940 /* Stop the controller.                                                     */
4941 /*                                                                          */
4942 /* Returns:                                                                 */
4943 /*   Nothing.                                                               */
4944 /****************************************************************************/
4945 static void
4946 bce_stop(struct bce_softc *sc)
4947 {
4948         struct ifnet *ifp;
4949
4950         DBENTER(BCE_VERBOSE_RESET);
4951
4952         BCE_LOCK_ASSERT(sc);
4953
4954         ifp = sc->bce_ifp;
4955
4956         callout_stop(&sc->bce_tick_callout);
4957
4958         /* Disable the transmit/receive blocks. */
4959         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4960         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4961         DELAY(20);
4962
4963         bce_disable_intr(sc);
4964
4965         /* Free RX buffers. */
4966         if (bce_hdr_split == TRUE) {
4967                 bce_free_pg_chain(sc);
4968         }
4969         bce_free_rx_chain(sc);
4970
4971         /* Free TX buffers. */
4972         bce_free_tx_chain(sc);
4973
4974         sc->watchdog_timer = 0;
4975
4976         sc->bce_link_up = FALSE;
4977
4978         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4979
4980         DBEXIT(BCE_VERBOSE_RESET);
4981 }
4982
4983
4984 static int
4985 bce_reset(struct bce_softc *sc, u32 reset_code)
4986 {
4987         u32 emac_mode_save, val;
4988         int i, rc = 0;
4989         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4990             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4991
4992         DBENTER(BCE_VERBOSE_RESET);
4993
4994         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4995             __FUNCTION__, reset_code);
4996
4997         /*
4998          * If ASF/IPMI is operational, then the EMAC Mode register already
4999          * contains appropriate values for the link settings that have
5000          * been auto-negotiated.  Resetting the chip will clobber those
5001          * values.  Save the important bits so we can restore them after
5002          * the reset.
5003          */
5004         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
5005
5006         /* Wait for pending PCI transactions to complete. */
5007         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
5008             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
5009             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
5010             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5011             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5012         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5013         DELAY(5);
5014
5015         /* Disable DMA */
5016         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5017                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5018                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5019                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5020         }
5021
5022         /* Assume bootcode is running. */
5023         sc->bce_fw_timed_out = FALSE;
5024         sc->bce_drv_cardiac_arrest = FALSE;
5025
5026         /* Give the firmware a chance to prepare for the reset. */
5027         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5028         if (rc)
5029                 goto bce_reset_exit;
5030
5031         /* Set a firmware reminder that this is a soft reset. */
5032         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5033
5034         /* Dummy read to force the chip to complete all current transactions. */
5035         val = REG_RD(sc, BCE_MISC_ID);
5036
5037         /* Chip reset. */
5038         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5039                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5040                 REG_RD(sc, BCE_MISC_COMMAND);
5041                 DELAY(5);
5042
5043                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5044                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5045
5046                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5047         } else {
5048                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5049                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5050                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5051                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5052
5053                 /* Allow up to 30us for reset to complete. */
5054                 for (i = 0; i < 10; i++) {
5055                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5056                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5057                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5058                                 break;
5059                         }
5060                         DELAY(10);
5061                 }
5062
5063                 /* Check that reset completed successfully. */
5064                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5065                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5066                         BCE_PRINTF("%s(%d): Reset failed!\n",
5067                             __FILE__, __LINE__);
5068                         rc = EBUSY;
5069                         goto bce_reset_exit;
5070                 }
5071         }
5072
5073         /* Make sure byte swapping is properly configured. */
5074         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5075         if (val != 0x01020304) {
5076                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5077                     __FILE__, __LINE__);
5078                 rc = ENODEV;
5079                 goto bce_reset_exit;
5080         }
5081
5082         /* Just completed a reset, assume that firmware is running again. */
5083         sc->bce_fw_timed_out = FALSE;
5084         sc->bce_drv_cardiac_arrest = FALSE;
5085
5086         /* Wait for the firmware to finish its initialization. */
5087         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5088         if (rc)
5089                 BCE_PRINTF("%s(%d): Firmware did not complete "
5090                     "initialization!\n", __FILE__, __LINE__);
5091         /* Get firmware capabilities. */
5092         bce_fw_cap_init(sc);
5093
5094 bce_reset_exit:
5095         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5096         val = REG_RD(sc, BCE_EMAC_MODE);
5097         val = (val & ~emac_mode_mask) | emac_mode_save;
5098         REG_WR(sc, BCE_EMAC_MODE, val);
5099
5100         DBEXIT(BCE_VERBOSE_RESET);
5101         return (rc);
5102 }
5103
5104
5105 static int
5106 bce_chipinit(struct bce_softc *sc)
5107 {
5108         u32 val;
5109         int rc = 0;
5110
5111         DBENTER(BCE_VERBOSE_RESET);
5112
5113         bce_disable_intr(sc);
5114
5115         /*
5116          * Initialize DMA byte/word swapping, configure the number of DMA
5117          * channels and PCI clock compensation delay.
5118          */
5119         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5120             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5121 #if BYTE_ORDER == BIG_ENDIAN
5122             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5123 #endif
5124             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5125             DMA_READ_CHANS << 12 |
5126             DMA_WRITE_CHANS << 16;
5127
5128         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5129
5130         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5131                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5132
5133         /*
5134          * This setting resolves a problem observed on certain Intel PCI
5135          * chipsets that cannot handle multiple outstanding DMA operations.
5136          * See errata E9_5706A1_65.
5137          */
5138         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5139             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5140             !(sc->bce_flags & BCE_PCIX_FLAG))
5141                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5142
5143         REG_WR(sc, BCE_DMA_CONFIG, val);
5144
5145         /* Enable the RX_V2P and Context state machines before access. */
5146         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5147             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5148             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5149             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5150
5151         /* Initialize context mapping and zero out the quick contexts. */
5152         if ((rc = bce_init_ctx(sc)) != 0)
5153                 goto bce_chipinit_exit;
5154
5155         /* Initialize the on-boards CPUs */
5156         bce_init_cpus(sc);
5157
5158         /* Enable management frames (NC-SI) to flow to the MCP. */
5159         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5160                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5161                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5162         }
5163
5164         /* Prepare NVRAM for access. */
5165         if ((rc = bce_init_nvram(sc)) != 0)
5166                 goto bce_chipinit_exit;
5167
5168         /* Set the kernel bypass block size */
5169         val = REG_RD(sc, BCE_MQ_CONFIG);
5170         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5171         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5172
5173         /* Enable bins used on the 5709. */
5174         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5175                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5176                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5177                         val |= BCE_MQ_CONFIG_HALT_DIS;
5178         }
5179
5180         REG_WR(sc, BCE_MQ_CONFIG, val);
5181
5182         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5183         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5184         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5185
5186         /* Set the page size and clear the RV2P processor stall bits. */
5187         val = (BCM_PAGE_BITS - 8) << 24;
5188         REG_WR(sc, BCE_RV2P_CONFIG, val);
5189
5190         /* Configure page size. */
5191         val = REG_RD(sc, BCE_TBDR_CONFIG);
5192         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5193         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5194         REG_WR(sc, BCE_TBDR_CONFIG, val);
5195
5196         /* Set the perfect match control register to default. */
5197         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5198
5199 bce_chipinit_exit:
5200         DBEXIT(BCE_VERBOSE_RESET);
5201
5202         return(rc);
5203 }
5204
5205
5206 /****************************************************************************/
5207 /* Initialize the controller in preparation to send/receive traffic.        */
5208 /*                                                                          */
5209 /* Returns:                                                                 */
5210 /*   0 for success, positive value for failure.                             */
5211 /****************************************************************************/
5212 static int
5213 bce_blockinit(struct bce_softc *sc)
5214 {
5215         u32 reg, val;
5216         int rc = 0;
5217
5218         DBENTER(BCE_VERBOSE_RESET);
5219
5220         /* Load the hardware default MAC address. */
5221         bce_set_mac_addr(sc);
5222
5223         /* Set the Ethernet backoff seed value */
5224         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5225               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5226               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5227         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5228
5229         sc->last_status_idx = 0;
5230         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5231
5232         /* Set up link change interrupt generation. */
5233         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5234
5235         /* Program the physical address of the status block. */
5236         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5237             BCE_ADDR_LO(sc->status_block_paddr));
5238         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5239             BCE_ADDR_HI(sc->status_block_paddr));
5240
5241         /* Program the physical address of the statistics block. */
5242         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5243             BCE_ADDR_LO(sc->stats_block_paddr));
5244         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5245             BCE_ADDR_HI(sc->stats_block_paddr));
5246
5247         /* Program various host coalescing parameters. */
5248         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5249             (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
5250         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5251             (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
5252         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
5253             (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
5254         REG_WR(sc, BCE_HC_TX_TICKS,
5255             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5256         REG_WR(sc, BCE_HC_RX_TICKS,
5257             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5258         REG_WR(sc, BCE_HC_COM_TICKS,
5259             (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
5260         REG_WR(sc, BCE_HC_CMD_TICKS,
5261             (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
5262         REG_WR(sc, BCE_HC_STATS_TICKS,
5263             (sc->bce_stats_ticks & 0xffff00));
5264         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5265
5266         /* Configure the Host Coalescing block. */
5267         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5268             BCE_HC_CONFIG_COLLECT_STATS;
5269
5270 #if 0
5271         /* ToDo: Add MSI-X support. */
5272         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5273                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5274                     BCE_HC_SB_CONFIG_1;
5275
5276                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5277
5278                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5279                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5280
5281                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5282                     (sc->tx_quick_cons_trip_int << 16) |
5283                      sc->tx_quick_cons_trip);
5284
5285                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5286                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5287
5288                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5289         }
5290
5291         /*
5292          * Tell the HC block to automatically set the
5293          * INT_MASK bit after an MSI/MSI-X interrupt
5294          * is generated so the driver doesn't have to.
5295          */
5296         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5297                 val |= BCE_HC_CONFIG_ONE_SHOT;
5298
5299         /* Set the MSI-X status blocks to 128 byte boundaries. */
5300         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5301                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5302 #endif
5303
5304         REG_WR(sc, BCE_HC_CONFIG, val);
5305
5306         /* Clear the internal statistics counters. */
5307         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5308
5309         /* Verify that bootcode is running. */
5310         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5311
5312         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5313             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5314             __FILE__, __LINE__);
5315             reg = 0);
5316
5317         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5318             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5319                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5320                     "Expected: 08%08X\n", __FILE__, __LINE__,
5321                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5322                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5323                 rc = ENODEV;
5324                 goto bce_blockinit_exit;
5325         }
5326
5327         /* Enable DMA */
5328         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5329                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5330                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5331                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5332         }
5333
5334         /* Allow bootcode to apply additional fixes before enabling MAC. */
5335         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5336             BCE_DRV_MSG_CODE_RESET);
5337
5338         /* Enable link state change interrupt generation. */
5339         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5340
5341         /* Enable the RXP. */
5342         bce_start_rxp_cpu(sc);
5343
5344         /* Disable management frames (NC-SI) from flowing to the MCP. */
5345         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5346                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5347                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5348                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5349         }
5350
5351         /* Enable all remaining blocks in the MAC. */
5352         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5353                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5354                     BCE_MISC_ENABLE_DEFAULT_XI);
5355         else
5356                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5357                     BCE_MISC_ENABLE_DEFAULT);
5358
5359         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5360         DELAY(20);
5361
5362         /* Save the current host coalescing block settings. */
5363         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5364
5365 bce_blockinit_exit:
5366         DBEXIT(BCE_VERBOSE_RESET);
5367
5368         return (rc);
5369 }
5370
5371
5372 /****************************************************************************/
5373 /* Encapsulate an mbuf into the rx_bd chain.                                */
5374 /*                                                                          */
5375 /* Returns:                                                                 */
5376 /*   0 for success, positive value for failure.                             */
5377 /****************************************************************************/
5378 static int
5379 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5380     u16 *chain_prod, u32 *prod_bseq)
5381 {
5382         bus_dmamap_t map;
5383         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
5384         struct mbuf *m_new = NULL;
5385         struct rx_bd *rxbd;
5386         int nsegs, error, rc = 0;
5387 #ifdef BCE_DEBUG
5388         u16 debug_chain_prod = *chain_prod;
5389 #endif
5390
5391         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5392
5393         /* Make sure the inputs are valid. */
5394         DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC),
5395             BCE_PRINTF("%s(%d): RX producer out of range: "
5396             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5397             *chain_prod, (u16) MAX_RX_BD_ALLOC));
5398
5399         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5400             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5401             *prod, *chain_prod, *prod_bseq);
5402
5403         /* Update some debug statistic counters */
5404         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5405             sc->rx_low_watermark = sc->free_rx_bd);
5406         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5407             sc->rx_empty_count++);
5408
5409         /* Check whether this is a new mbuf allocation. */
5410         if (m == NULL) {
5411
5412                 /* Simulate an mbuf allocation failure. */
5413                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5414                     sc->mbuf_alloc_failed_count++;
5415                     sc->mbuf_alloc_failed_sim_count++;
5416                     rc = ENOBUFS;
5417                     goto bce_get_rx_buf_exit);
5418
5419                 /* This is a new mbuf allocation. */
5420                 if (bce_hdr_split == TRUE)
5421                         MGETHDR(m_new, M_NOWAIT, MT_DATA);
5422                 else
5423                         m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5424                             sc->rx_bd_mbuf_alloc_size);
5425
5426                 if (m_new == NULL) {
5427                         sc->mbuf_alloc_failed_count++;
5428                         rc = ENOBUFS;
5429                         goto bce_get_rx_buf_exit;
5430                 }
5431
5432                 DBRUN(sc->debug_rx_mbuf_alloc++);
5433         } else {
5434                 /* Reuse an existing mbuf. */
5435                 m_new = m;
5436         }
5437
5438         /* Make sure we have a valid packet header. */
5439         M_ASSERTPKTHDR(m_new);
5440
5441         /* Initialize the mbuf size and pad if necessary for alignment. */
5442         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5443         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5444
5445         /* ToDo: Consider calling m_fragment() to test error handling. */
5446
5447         /* Map the mbuf cluster into device memory. */
5448         map = sc->rx_mbuf_map[*chain_prod];
5449         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
5450             segs, &nsegs, BUS_DMA_NOWAIT);
5451
5452         /* Handle any mapping errors. */
5453         if (error) {
5454                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5455                     "chain (%d)!\n", __FILE__, __LINE__, error);
5456
5457                 sc->dma_map_addr_rx_failed_count++;
5458                 m_freem(m_new);
5459
5460                 DBRUN(sc->debug_rx_mbuf_alloc--);
5461
5462                 rc = ENOBUFS;
5463                 goto bce_get_rx_buf_exit;
5464         }
5465
5466         /* All mbufs must map to a single segment. */
5467         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5468             __FUNCTION__, nsegs));
5469
5470         /* Setup the rx_bd for the segment. */
5471         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
5472
5473         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5474         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5475         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5476         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5477         *prod_bseq += segs[0].ds_len;
5478
5479         /* Save the mbuf and update our counter. */
5480         sc->rx_mbuf_ptr[*chain_prod] = m_new;
5481         sc->free_rx_bd -= nsegs;
5482
5483         DBRUNMSG(BCE_INSANE_RECV,
5484             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5485
5486         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5487             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n",
5488             __FUNCTION__, *prod, *chain_prod, *prod_bseq);
5489
5490 bce_get_rx_buf_exit:
5491         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5492
5493         return(rc);
5494 }
5495
5496
5497 /****************************************************************************/
5498 /* Encapsulate an mbuf cluster into the page chain.                         */
5499 /*                                                                          */
5500 /* Returns:                                                                 */
5501 /*   0 for success, positive value for failure.                             */
5502 /****************************************************************************/
5503 static int
5504 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5505         u16 *prod_idx)
5506 {
5507         bus_dmamap_t map;
5508         bus_addr_t busaddr;
5509         struct mbuf *m_new = NULL;
5510         struct rx_bd *pgbd;
5511         int error, rc = 0;
5512 #ifdef BCE_DEBUG
5513         u16 debug_prod_idx = *prod_idx;
5514 #endif
5515
5516         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5517
5518         /* Make sure the inputs are valid. */
5519         DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC),
5520             BCE_PRINTF("%s(%d): page producer out of range: "
5521             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5522             *prod_idx, (u16) MAX_PG_BD_ALLOC));
5523
5524         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5525             "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5526
5527         /* Update counters if we've hit a new low or run out of pages. */
5528         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5529             sc->pg_low_watermark = sc->free_pg_bd);
5530         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5531
5532         /* Check whether this is a new mbuf allocation. */
5533         if (m == NULL) {
5534
5535                 /* Simulate an mbuf allocation failure. */
5536                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5537                     sc->mbuf_alloc_failed_count++;
5538                     sc->mbuf_alloc_failed_sim_count++;
5539                     rc = ENOBUFS;
5540                     goto bce_get_pg_buf_exit);
5541
5542                 /* This is a new mbuf allocation. */
5543                 m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5544                 if (m_new == NULL) {
5545                         sc->mbuf_alloc_failed_count++;
5546                         rc = ENOBUFS;
5547                         goto bce_get_pg_buf_exit;
5548                 }
5549
5550                 DBRUN(sc->debug_pg_mbuf_alloc++);
5551         } else {
5552                 /* Reuse an existing mbuf. */
5553                 m_new = m;
5554                 m_new->m_data = m_new->m_ext.ext_buf;
5555         }
5556
5557         m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5558
5559         /* ToDo: Consider calling m_fragment() to test error handling. */
5560
5561         /* Map the mbuf cluster into device memory. */
5562         map = sc->pg_mbuf_map[*prod_idx];
5563         error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5564             sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5565             &busaddr, BUS_DMA_NOWAIT);
5566
5567         /* Handle any mapping errors. */
5568         if (error) {
5569                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5570                     __FILE__, __LINE__);
5571
5572                 m_freem(m_new);
5573                 DBRUN(sc->debug_pg_mbuf_alloc--);
5574
5575                 rc = ENOBUFS;
5576                 goto bce_get_pg_buf_exit;
5577         }
5578
5579         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5580
5581         /*
5582          * The page chain uses the same rx_bd data structure
5583          * as the receive chain but doesn't require a byte sequence (bseq).
5584          */
5585         pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5586
5587         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5588         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5589         pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
5590         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5591
5592         /* Save the mbuf and update our counter. */
5593         sc->pg_mbuf_ptr[*prod_idx] = m_new;
5594         sc->free_pg_bd--;
5595
5596         DBRUNMSG(BCE_INSANE_RECV,
5597             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5598
5599         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5600             "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5601
5602 bce_get_pg_buf_exit:
5603         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5604
5605         return(rc);
5606 }
5607
5608
5609 /****************************************************************************/
5610 /* Initialize the TX context memory.                                        */
5611 /*                                                                          */
5612 /* Returns:                                                                 */
5613 /*   Nothing                                                                */
5614 /****************************************************************************/
5615 static void
5616 bce_init_tx_context(struct bce_softc *sc)
5617 {
5618         u32 val;
5619
5620         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5621
5622         /* Initialize the context ID for an L2 TX chain. */
5623         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5624                 /* Set the CID type to support an L2 connection. */
5625                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5626                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5627                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5628                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5629                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5630                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5631
5632                 /* Point the hardware to the first page in the chain. */
5633                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5634                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5635                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5636                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5637                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5638                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5639         } else {
5640                 /* Set the CID type to support an L2 connection. */
5641                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5642                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5643                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5644                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5645
5646                 /* Point the hardware to the first page in the chain. */
5647                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5648                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5649                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5650                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5651                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5652                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5653         }
5654
5655         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5656 }
5657
5658
5659 /****************************************************************************/
5660 /* Allocate memory and initialize the TX data structures.                   */
5661 /*                                                                          */
5662 /* Returns:                                                                 */
5663 /*   0 for success, positive value for failure.                             */
5664 /****************************************************************************/
5665 static int
5666 bce_init_tx_chain(struct bce_softc *sc)
5667 {
5668         struct tx_bd *txbd;
5669         int i, rc = 0;
5670
5671         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5672
5673         /* Set the initial TX producer/consumer indices. */
5674         sc->tx_prod        = 0;
5675         sc->tx_cons        = 0;
5676         sc->tx_prod_bseq   = 0;
5677         sc->used_tx_bd     = 0;
5678         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5679         DBRUN(sc->tx_hi_watermark = 0);
5680         DBRUN(sc->tx_full_count = 0);
5681
5682         /*
5683          * The NetXtreme II supports a linked-list structre called
5684          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5685          * consists of a series of 1 or more chain pages, each of which
5686          * consists of a fixed number of BD entries.
5687          * The last BD entry on each page is a pointer to the next page
5688          * in the chain, and the last pointer in the BD chain
5689          * points back to the beginning of the chain.
5690          */
5691
5692         /* Set the TX next pointer chain entries. */
5693         for (i = 0; i < sc->tx_pages; i++) {
5694                 int j;
5695
5696                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5697
5698                 /* Check if we've reached the last page. */
5699                 if (i == (sc->tx_pages - 1))
5700                         j = 0;
5701                 else
5702                         j = i + 1;
5703
5704                 txbd->tx_bd_haddr_hi =
5705                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5706                 txbd->tx_bd_haddr_lo =
5707                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5708         }
5709
5710         bce_init_tx_context(sc);
5711
5712         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5713         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5714
5715         return(rc);
5716 }
5717
5718
5719 /****************************************************************************/
5720 /* Free memory and clear the TX data structures.                            */
5721 /*                                                                          */
5722 /* Returns:                                                                 */
5723 /*   Nothing.                                                               */
5724 /****************************************************************************/
5725 static void
5726 bce_free_tx_chain(struct bce_softc *sc)
5727 {
5728         int i;
5729
5730         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5731
5732         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5733         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5734                 if (sc->tx_mbuf_ptr[i] != NULL) {
5735                         if (sc->tx_mbuf_map[i] != NULL)
5736                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5737                                     sc->tx_mbuf_map[i],
5738                                     BUS_DMASYNC_POSTWRITE);
5739                         m_freem(sc->tx_mbuf_ptr[i]);
5740                         sc->tx_mbuf_ptr[i] = NULL;
5741                         DBRUN(sc->debug_tx_mbuf_alloc--);
5742                 }
5743         }
5744
5745         /* Clear each TX chain page. */
5746         for (i = 0; i < sc->tx_pages; i++)
5747                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5748
5749         sc->used_tx_bd = 0;
5750
5751         /* Check if we lost any mbufs in the process. */
5752         DBRUNIF((sc->debug_tx_mbuf_alloc),
5753             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5754             "from tx chain!\n", __FILE__, __LINE__,
5755             sc->debug_tx_mbuf_alloc));
5756
5757         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5758 }
5759
5760
5761 /****************************************************************************/
5762 /* Initialize the RX context memory.                                        */
5763 /*                                                                          */
5764 /* Returns:                                                                 */
5765 /*   Nothing                                                                */
5766 /****************************************************************************/
5767 static void
5768 bce_init_rx_context(struct bce_softc *sc)
5769 {
5770         u32 val;
5771
5772         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5773
5774         /* Init the type, size, and BD cache levels for the RX context. */
5775         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5776             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5777             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5778
5779         /*
5780          * Set the level for generating pause frames
5781          * when the number of available rx_bd's gets
5782          * too low (the low watermark) and the level
5783          * when pause frames can be stopped (the high
5784          * watermark).
5785          */
5786         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5787                 u32 lo_water, hi_water;
5788
5789                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5790                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5791                 } else {
5792                         lo_water = 0;
5793                 }
5794
5795                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5796                         lo_water = 0;
5797                 }
5798
5799                 hi_water = USABLE_RX_BD_ALLOC / 4;
5800
5801                 if (hi_water <= lo_water) {
5802                         lo_water = 0;
5803                 }
5804
5805                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5806                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5807
5808                 if (hi_water > 0xf)
5809                         hi_water = 0xf;
5810                 else if (hi_water == 0)
5811                         lo_water = 0;
5812
5813                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5814                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5815         }
5816
5817         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5818
5819         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5820         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5821                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5822                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5823         }
5824
5825         /* Point the hardware to the first page in the chain. */
5826         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5827         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5828         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5829         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5830
5831         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5832 }
5833
5834
5835 /****************************************************************************/
5836 /* Allocate memory and initialize the RX data structures.                   */
5837 /*                                                                          */
5838 /* Returns:                                                                 */
5839 /*   0 for success, positive value for failure.                             */
5840 /****************************************************************************/
5841 static int
5842 bce_init_rx_chain(struct bce_softc *sc)
5843 {
5844         struct rx_bd *rxbd;
5845         int i, rc = 0;
5846
5847         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5848             BCE_VERBOSE_CTX);
5849
5850         /* Initialize the RX producer and consumer indices. */
5851         sc->rx_prod        = 0;
5852         sc->rx_cons        = 0;
5853         sc->rx_prod_bseq   = 0;
5854         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5855         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5856
5857         /* Initialize the RX next pointer chain entries. */
5858         for (i = 0; i < sc->rx_pages; i++) {
5859                 int j;
5860
5861                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5862
5863                 /* Check if we've reached the last page. */
5864                 if (i == (sc->rx_pages - 1))
5865                         j = 0;
5866                 else
5867                         j = i + 1;
5868
5869                 /* Setup the chain page pointers. */
5870                 rxbd->rx_bd_haddr_hi =
5871                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5872                 rxbd->rx_bd_haddr_lo =
5873                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5874         }
5875
5876         /* Fill up the RX chain. */
5877         bce_fill_rx_chain(sc);
5878
5879         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5880         DBRUN(sc->rx_empty_count = 0);
5881         for (i = 0; i < sc->rx_pages; i++) {
5882                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5883                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5884         }
5885
5886         bce_init_rx_context(sc);
5887
5888         DBRUNMSG(BCE_EXTREME_RECV,
5889             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5890         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5891             BCE_VERBOSE_CTX);
5892
5893         /* ToDo: Are there possible failure modes here? */
5894
5895         return(rc);
5896 }
5897
5898
5899 /****************************************************************************/
5900 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5901 /* occurs.                                                                  */
5902 /*                                                                          */
5903 /* Returns:                                                                 */
5904 /*   Nothing                                                                */
5905 /****************************************************************************/
5906 static void
5907 bce_fill_rx_chain(struct bce_softc *sc)
5908 {
5909         u16 prod, prod_idx;
5910         u32 prod_bseq;
5911
5912         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5913             BCE_VERBOSE_CTX);
5914
5915         /* Get the RX chain producer indices. */
5916         prod      = sc->rx_prod;
5917         prod_bseq = sc->rx_prod_bseq;
5918
5919         /* Keep filling the RX chain until it's full. */
5920         while (sc->free_rx_bd > 0) {
5921                 prod_idx = RX_CHAIN_IDX(prod);
5922                 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5923                         /* Bail out if we can't add an mbuf to the chain. */
5924                         break;
5925                 }
5926                 prod = NEXT_RX_BD(prod);
5927         }
5928
5929         /* Save the RX chain producer indices. */
5930         sc->rx_prod      = prod;
5931         sc->rx_prod_bseq = prod_bseq;
5932
5933         /* We should never end up pointing to a next page pointer. */
5934         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5935             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5936             __FUNCTION__, sc->rx_prod));
5937
5938         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5939         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5940             BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod);
5941         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) +
5942             BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq);
5943
5944         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5945             BCE_VERBOSE_CTX);
5946 }
5947
5948
5949 /****************************************************************************/
5950 /* Free memory and clear the RX data structures.                            */
5951 /*                                                                          */
5952 /* Returns:                                                                 */
5953 /*   Nothing.                                                               */
5954 /****************************************************************************/
5955 static void
5956 bce_free_rx_chain(struct bce_softc *sc)
5957 {
5958         int i;
5959
5960         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5961
5962         /* Free any mbufs still in the RX mbuf chain. */
5963         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5964                 if (sc->rx_mbuf_ptr[i] != NULL) {
5965                         if (sc->rx_mbuf_map[i] != NULL)
5966                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5967                                     sc->rx_mbuf_map[i],
5968                                     BUS_DMASYNC_POSTREAD);
5969                         m_freem(sc->rx_mbuf_ptr[i]);
5970                         sc->rx_mbuf_ptr[i] = NULL;
5971                         DBRUN(sc->debug_rx_mbuf_alloc--);
5972                 }
5973         }
5974
5975         /* Clear each RX chain page. */
5976         for (i = 0; i < sc->rx_pages; i++)
5977                 if (sc->rx_bd_chain[i] != NULL) {
5978                         bzero((char *)sc->rx_bd_chain[i],
5979                             BCE_RX_CHAIN_PAGE_SZ);
5980                 }
5981
5982         sc->free_rx_bd = sc->max_rx_bd;
5983
5984         /* Check if we lost any mbufs in the process. */
5985         DBRUNIF((sc->debug_rx_mbuf_alloc),
5986             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5987             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5988
5989         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5990 }
5991
5992
5993 /****************************************************************************/
5994 /* Allocate memory and initialize the page data structures.                 */
5995 /* Assumes that bce_init_rx_chain() has not already been called.            */
5996 /*                                                                          */
5997 /* Returns:                                                                 */
5998 /*   0 for success, positive value for failure.                             */
5999 /****************************************************************************/
6000 static int
6001 bce_init_pg_chain(struct bce_softc *sc)
6002 {
6003         struct rx_bd *pgbd;
6004         int i, rc = 0;
6005         u32 val;
6006
6007         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6008                 BCE_VERBOSE_CTX);
6009
6010         /* Initialize the page producer and consumer indices. */
6011         sc->pg_prod        = 0;
6012         sc->pg_cons        = 0;
6013         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
6014         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
6015         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
6016         DBRUN(sc->pg_empty_count = 0);
6017
6018         /* Initialize the page next pointer chain entries. */
6019         for (i = 0; i < sc->pg_pages; i++) {
6020                 int j;
6021
6022                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
6023
6024                 /* Check if we've reached the last page. */
6025                 if (i == (sc->pg_pages - 1))
6026                         j = 0;
6027                 else
6028                         j = i + 1;
6029
6030                 /* Setup the chain page pointers. */
6031                 pgbd->rx_bd_haddr_hi =
6032                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6033                 pgbd->rx_bd_haddr_lo =
6034                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6035         }
6036
6037         /* Setup the MQ BIN mapping for host_pg_bidx. */
6038         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6039                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6040
6041         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6042
6043         /* Configure the rx_bd and page chain mbuf cluster size. */
6044         val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
6045         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6046
6047         /* Configure the context reserved for jumbo support. */
6048         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6049                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6050
6051         /* Point the hardware to the first page in the page chain. */
6052         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6053         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6054         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6055         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6056
6057         /* Fill up the page chain. */
6058         bce_fill_pg_chain(sc);
6059
6060         for (i = 0; i < sc->pg_pages; i++) {
6061                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6062                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6063         }
6064
6065         DBRUNMSG(BCE_EXTREME_RECV,
6066             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6067         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6068                 BCE_VERBOSE_CTX);
6069         return(rc);
6070 }
6071
6072
6073 /****************************************************************************/
6074 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6075 /* occurs.                                                                  */
6076 /*                                                                          */
6077 /* Returns:                                                                 */
6078 /*   Nothing                                                                */
6079 /****************************************************************************/
6080 static void
6081 bce_fill_pg_chain(struct bce_softc *sc)
6082 {
6083         u16 prod, prod_idx;
6084
6085         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6086             BCE_VERBOSE_CTX);
6087
6088         /* Get the page chain prodcuer index. */
6089         prod = sc->pg_prod;
6090
6091         /* Keep filling the page chain until it's full. */
6092         while (sc->free_pg_bd > 0) {
6093                 prod_idx = PG_CHAIN_IDX(prod);
6094                 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
6095                         /* Bail out if we can't add an mbuf to the chain. */
6096                         break;
6097                 }
6098                 prod = NEXT_PG_BD(prod);
6099         }
6100
6101         /* Save the page chain producer index. */
6102         sc->pg_prod = prod;
6103
6104         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6105             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6106             __FUNCTION__, sc->pg_prod));
6107
6108         /*
6109          * Write the mailbox and tell the chip about
6110          * the new rx_bd's in the page chain.
6111          */
6112         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
6113             BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod);
6114
6115         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6116             BCE_VERBOSE_CTX);
6117 }
6118
6119
6120 /****************************************************************************/
6121 /* Free memory and clear the RX data structures.                            */
6122 /*                                                                          */
6123 /* Returns:                                                                 */
6124 /*   Nothing.                                                               */
6125 /****************************************************************************/
6126 static void
6127 bce_free_pg_chain(struct bce_softc *sc)
6128 {
6129         int i;
6130
6131         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6132
6133         /* Free any mbufs still in the mbuf page chain. */
6134         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6135                 if (sc->pg_mbuf_ptr[i] != NULL) {
6136                         if (sc->pg_mbuf_map[i] != NULL)
6137                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6138                                     sc->pg_mbuf_map[i],
6139                                     BUS_DMASYNC_POSTREAD);
6140                         m_freem(sc->pg_mbuf_ptr[i]);
6141                         sc->pg_mbuf_ptr[i] = NULL;
6142                         DBRUN(sc->debug_pg_mbuf_alloc--);
6143                 }
6144         }
6145
6146         /* Clear each page chain pages. */
6147         for (i = 0; i < sc->pg_pages; i++)
6148                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6149
6150         sc->free_pg_bd = sc->max_pg_bd;
6151
6152         /* Check if we lost any mbufs in the process. */
6153         DBRUNIF((sc->debug_pg_mbuf_alloc),
6154             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6155             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6156
6157         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6158 }
6159
6160
6161 static u32
6162 bce_get_rphy_link(struct bce_softc *sc)
6163 {
6164         u32 advertise, link;
6165         int fdpx;
6166
6167         advertise = 0;
6168         fdpx = 0;
6169         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6170                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6171         else
6172                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6173         if (link & BCE_NETLINK_ANEG_ENB)
6174                 advertise |= BCE_NETLINK_ANEG_ENB;
6175         if (link & BCE_NETLINK_SPEED_10HALF)
6176                 advertise |= BCE_NETLINK_SPEED_10HALF;
6177         if (link & BCE_NETLINK_SPEED_10FULL) {
6178                 advertise |= BCE_NETLINK_SPEED_10FULL;
6179                 fdpx++;
6180         }
6181         if (link & BCE_NETLINK_SPEED_100HALF)
6182                 advertise |= BCE_NETLINK_SPEED_100HALF;
6183         if (link & BCE_NETLINK_SPEED_100FULL) {
6184                 advertise |= BCE_NETLINK_SPEED_100FULL;
6185                 fdpx++;
6186         }
6187         if (link & BCE_NETLINK_SPEED_1000HALF)
6188                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6189         if (link & BCE_NETLINK_SPEED_1000FULL) {
6190                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6191                 fdpx++;
6192         }
6193         if (link & BCE_NETLINK_SPEED_2500HALF)
6194                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6195         if (link & BCE_NETLINK_SPEED_2500FULL) {
6196                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6197                 fdpx++;
6198         }
6199         if (fdpx)
6200                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6201                     BCE_NETLINK_FC_PAUSE_ASYM;
6202         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6203                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6204                     BCE_NETLINK_ETH_AT_WIRESPEED;
6205
6206         return (advertise);
6207 }
6208
6209
6210 /****************************************************************************/
6211 /* Set media options.                                                       */
6212 /*                                                                          */
6213 /* Returns:                                                                 */
6214 /*   0 for success, positive value for failure.                             */
6215 /****************************************************************************/
6216 static int
6217 bce_ifmedia_upd(struct ifnet *ifp)
6218 {
6219         struct bce_softc *sc = ifp->if_softc;
6220         int error;
6221
6222         DBENTER(BCE_VERBOSE);
6223
6224         BCE_LOCK(sc);
6225         error = bce_ifmedia_upd_locked(ifp);
6226         BCE_UNLOCK(sc);
6227
6228         DBEXIT(BCE_VERBOSE);
6229         return (error);
6230 }
6231
6232
6233 /****************************************************************************/
6234 /* Set media options.                                                       */
6235 /*                                                                          */
6236 /* Returns:                                                                 */
6237 /*   Nothing.                                                               */
6238 /****************************************************************************/
6239 static int
6240 bce_ifmedia_upd_locked(struct ifnet *ifp)
6241 {
6242         struct bce_softc *sc = ifp->if_softc;
6243         struct mii_data *mii;
6244         struct mii_softc *miisc;
6245         struct ifmedia *ifm;
6246         u32 link;
6247         int error, fdx;
6248
6249         DBENTER(BCE_VERBOSE_PHY);
6250
6251         error = 0;
6252         BCE_LOCK_ASSERT(sc);
6253
6254         sc->bce_link_up = FALSE;
6255         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6256                 ifm = &sc->bce_ifmedia;
6257                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6258                         return (EINVAL);
6259                 link = 0;
6260                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6261                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6262                 case IFM_AUTO:
6263                         /*
6264                          * Check advertised link of remote PHY by reading
6265                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6266                          * Always use the same link type of remote PHY.
6267                          */
6268                         link = bce_get_rphy_link(sc);
6269                         break;
6270                 case IFM_2500_SX:
6271                         if ((sc->bce_phy_flags &
6272                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6273                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6274                                 return (EINVAL);
6275                         /*
6276                          * XXX
6277                          * Have to enable forced 2.5Gbps configuration.
6278                          */
6279                         if (fdx != 0)
6280                                 link |= BCE_NETLINK_SPEED_2500FULL;
6281                         else
6282                                 link |= BCE_NETLINK_SPEED_2500HALF;
6283                         break;
6284                 case IFM_1000_SX:
6285                         if ((sc->bce_phy_flags &
6286                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6287                                 return (EINVAL);
6288                         /*
6289                          * XXX
6290                          * Have to disable 2.5Gbps configuration.
6291                          */
6292                         if (fdx != 0)
6293                                 link = BCE_NETLINK_SPEED_1000FULL;
6294                         else
6295                                 link = BCE_NETLINK_SPEED_1000HALF;
6296                         break;
6297                 case IFM_1000_T:
6298                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6299                                 return (EINVAL);
6300                         if (fdx != 0)
6301                                 link = BCE_NETLINK_SPEED_1000FULL;
6302                         else
6303                                 link = BCE_NETLINK_SPEED_1000HALF;
6304                         break;
6305                 case IFM_100_TX:
6306                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6307                                 return (EINVAL);
6308                         if (fdx != 0)
6309                                 link = BCE_NETLINK_SPEED_100FULL;
6310                         else
6311                                 link = BCE_NETLINK_SPEED_100HALF;
6312                         break;
6313                 case IFM_10_T:
6314                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6315                                 return (EINVAL);
6316                         if (fdx != 0)
6317                                 link = BCE_NETLINK_SPEED_10FULL;
6318                         else
6319                                 link = BCE_NETLINK_SPEED_10HALF;
6320                         break;
6321                 default:
6322                         return (EINVAL);
6323                 }
6324                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6325                         /*
6326                          * XXX
6327                          * Advertise pause capability for full-duplex media.
6328                          */
6329                         if (fdx != 0)
6330                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6331                                     BCE_NETLINK_FC_PAUSE_ASYM;
6332                         if ((sc->bce_phy_flags &
6333                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6334                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6335                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6336                 }
6337
6338                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6339                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6340         } else {
6341                 mii = device_get_softc(sc->bce_miibus);
6342
6343                 /* Make sure the MII bus has been enumerated. */
6344                 if (mii) {
6345                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6346                                 PHY_RESET(miisc);
6347                         error = mii_mediachg(mii);
6348                 }
6349         }
6350
6351         DBEXIT(BCE_VERBOSE_PHY);
6352         return (error);
6353 }
6354
6355
6356 static void
6357 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6358 {
6359         struct ifnet *ifp;
6360         u32 link;
6361
6362         ifp = sc->bce_ifp;
6363         BCE_LOCK_ASSERT(sc);
6364
6365         ifmr->ifm_status = IFM_AVALID;
6366         ifmr->ifm_active = IFM_ETHER;
6367         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6368         /* XXX Handle heart beat status? */
6369         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6370                 ifmr->ifm_status |= IFM_ACTIVE;
6371         else {
6372                 ifmr->ifm_active |= IFM_NONE;
6373                 ifp->if_baudrate = 0;
6374                 return;
6375         }
6376         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6377         case BCE_LINK_STATUS_10HALF:
6378                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6379                 ifp->if_baudrate = IF_Mbps(10UL);
6380                 break;
6381         case BCE_LINK_STATUS_10FULL:
6382                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6383                 ifp->if_baudrate = IF_Mbps(10UL);
6384                 break;
6385         case BCE_LINK_STATUS_100HALF:
6386                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6387                 ifp->if_baudrate = IF_Mbps(100UL);
6388                 break;
6389         case BCE_LINK_STATUS_100FULL:
6390                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6391                 ifp->if_baudrate = IF_Mbps(100UL);
6392                 break;
6393         case BCE_LINK_STATUS_1000HALF:
6394                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6395                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6396                 else
6397                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6398                 ifp->if_baudrate = IF_Mbps(1000UL);
6399                 break;
6400         case BCE_LINK_STATUS_1000FULL:
6401                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6402                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6403                 else
6404                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6405                 ifp->if_baudrate = IF_Mbps(1000UL);
6406                 break;
6407         case BCE_LINK_STATUS_2500HALF:
6408                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6409                         ifmr->ifm_active |= IFM_NONE;
6410                         return;
6411                 } else
6412                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6413                 ifp->if_baudrate = IF_Mbps(2500UL);
6414                 break;
6415         case BCE_LINK_STATUS_2500FULL:
6416                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6417                         ifmr->ifm_active |= IFM_NONE;
6418                         return;
6419                 } else
6420                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6421                 ifp->if_baudrate = IF_Mbps(2500UL);
6422                 break;
6423         default:
6424                 ifmr->ifm_active |= IFM_NONE;
6425                 return;
6426         }
6427
6428         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6429                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6430         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6431                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6432 }
6433
6434
6435 /****************************************************************************/
6436 /* Reports current media status.                                            */
6437 /*                                                                          */
6438 /* Returns:                                                                 */
6439 /*   Nothing.                                                               */
6440 /****************************************************************************/
6441 static void
6442 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6443 {
6444         struct bce_softc *sc = ifp->if_softc;
6445         struct mii_data *mii;
6446
6447         DBENTER(BCE_VERBOSE_PHY);
6448
6449         BCE_LOCK(sc);
6450
6451         if ((ifp->if_flags & IFF_UP) == 0) {
6452                 BCE_UNLOCK(sc);
6453                 return;
6454         }
6455
6456         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6457                 bce_ifmedia_sts_rphy(sc, ifmr);
6458         else {
6459                 mii = device_get_softc(sc->bce_miibus);
6460                 mii_pollstat(mii);
6461                 ifmr->ifm_active = mii->mii_media_active;
6462                 ifmr->ifm_status = mii->mii_media_status;
6463         }
6464
6465         BCE_UNLOCK(sc);
6466
6467         DBEXIT(BCE_VERBOSE_PHY);
6468 }
6469
6470
6471 /****************************************************************************/
6472 /* Handles PHY generated interrupt events.                                  */
6473 /*                                                                          */
6474 /* Returns:                                                                 */
6475 /*   Nothing.                                                               */
6476 /****************************************************************************/
6477 static void
6478 bce_phy_intr(struct bce_softc *sc)
6479 {
6480         u32 new_link_state, old_link_state;
6481
6482         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6483
6484         DBRUN(sc->phy_interrupts++);
6485
6486         new_link_state = sc->status_block->status_attn_bits &
6487             STATUS_ATTN_BITS_LINK_STATE;
6488         old_link_state = sc->status_block->status_attn_bits_ack &
6489             STATUS_ATTN_BITS_LINK_STATE;
6490
6491         /* Handle any changes if the link state has changed. */
6492         if (new_link_state != old_link_state) {
6493
6494                 /* Update the status_attn_bits_ack field. */
6495                 if (new_link_state) {
6496                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6497                             STATUS_ATTN_BITS_LINK_STATE);
6498                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6499                             __FUNCTION__);
6500                 } else {
6501                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6502                             STATUS_ATTN_BITS_LINK_STATE);
6503                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6504                             __FUNCTION__);
6505                 }
6506
6507                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6508                         if (new_link_state) {
6509                                 if (bootverbose)
6510                                         if_printf(sc->bce_ifp, "link UP\n");
6511                                 if_link_state_change(sc->bce_ifp,
6512                                     LINK_STATE_UP);
6513                         } else {
6514                                 if (bootverbose)
6515                                         if_printf(sc->bce_ifp, "link DOWN\n");
6516                                 if_link_state_change(sc->bce_ifp,
6517                                     LINK_STATE_DOWN);
6518                         }
6519                 }
6520                 /*
6521                  * Assume link is down and allow
6522                  * tick routine to update the state
6523                  * based on the actual media state.
6524                  */
6525                 sc->bce_link_up = FALSE;
6526                 callout_stop(&sc->bce_tick_callout);
6527                 bce_tick(sc);
6528         }
6529
6530         /* Acknowledge the link change interrupt. */
6531         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6532
6533         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6534 }
6535
6536
6537 /****************************************************************************/
6538 /* Reads the receive consumer value from the status block (skipping over    */
6539 /* chain page pointer if necessary).                                        */
6540 /*                                                                          */
6541 /* Returns:                                                                 */
6542 /*   hw_cons                                                                */
6543 /****************************************************************************/
6544 static inline u16
6545 bce_get_hw_rx_cons(struct bce_softc *sc)
6546 {
6547         u16 hw_cons;
6548
6549         rmb();
6550         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6551         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6552                 hw_cons++;
6553
6554         return hw_cons;
6555 }
6556
6557 /****************************************************************************/
6558 /* Handles received frame interrupt events.                                 */
6559 /*                                                                          */
6560 /* Returns:                                                                 */
6561 /*   Nothing.                                                               */
6562 /****************************************************************************/
6563 static void
6564 bce_rx_intr(struct bce_softc *sc)
6565 {
6566         struct ifnet *ifp = sc->bce_ifp;
6567         struct l2_fhdr *l2fhdr;
6568         struct ether_vlan_header *vh;
6569         unsigned int pkt_len;
6570         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6571         u32 status;
6572         unsigned int rem_len;
6573         u16 sw_pg_cons, sw_pg_cons_idx;
6574
6575         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6576         DBRUN(sc->interrupts_rx++);
6577         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6578             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6579             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6580
6581         /* Prepare the RX chain pages to be accessed by the host CPU. */
6582         for (int i = 0; i < sc->rx_pages; i++)
6583                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6584                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6585
6586         /* Prepare the page chain pages to be accessed by the host CPU. */
6587         if (bce_hdr_split == TRUE) {
6588                 for (int i = 0; i < sc->pg_pages; i++)
6589                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6590                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6591         }
6592
6593         /* Get the hardware's view of the RX consumer index. */
6594         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6595
6596         /* Get working copies of the driver's view of the consumer indices. */
6597         sw_rx_cons = sc->rx_cons;
6598         sw_pg_cons = sc->pg_cons;
6599
6600         /* Update some debug statistics counters */
6601         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6602             sc->rx_low_watermark = sc->free_rx_bd);
6603         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6604             sc->rx_empty_count++);
6605
6606         /* Scan through the receive chain as long as there is work to do */
6607         /* ToDo: Consider setting a limit on the number of packets processed. */
6608         rmb();
6609         while (sw_rx_cons != hw_rx_cons) {
6610                 struct mbuf *m0;
6611
6612                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6613                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6614
6615                 /* Unmap the mbuf from DMA space. */
6616                 bus_dmamap_sync(sc->rx_mbuf_tag,
6617                     sc->rx_mbuf_map[sw_rx_cons_idx],
6618                     BUS_DMASYNC_POSTREAD);
6619                 bus_dmamap_unload(sc->rx_mbuf_tag,
6620                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6621
6622                 /* Remove the mbuf from the RX chain. */
6623                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6624                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6625                 DBRUN(sc->debug_rx_mbuf_alloc--);
6626                 sc->free_rx_bd++;
6627
6628                 if(m0 == NULL) {
6629                         DBPRINT(sc, BCE_EXTREME_RECV,
6630                             "%s(): Oops! Empty mbuf pointer "
6631                             "found in sc->rx_mbuf_ptr[0x%04X]!\n",
6632                             __FUNCTION__, sw_rx_cons_idx);
6633                         goto bce_rx_int_next_rx;
6634                 }
6635
6636                 /*
6637                  * Frames received on the NetXteme II are prepended
6638                  * with an l2_fhdr structure which provides status
6639                  * information about the received frame (including
6640                  * VLAN tags and checksum info).  The frames are
6641                  * also automatically adjusted to word align the IP
6642                  * header (i.e. two null bytes are inserted before
6643                  * the Ethernet header).  As a result the data
6644                  * DMA'd by the controller into the mbuf looks
6645                  * like this:
6646                  *
6647                  * +---------+-----+---------------------+-----+
6648                  * | l2_fhdr | pad | packet data         | FCS |
6649                  * +---------+-----+---------------------+-----+
6650                  *
6651                  * The l2_fhdr needs to be checked and skipped and
6652                  * the FCS needs to be stripped before sending the
6653                  * packet up the stack.
6654                  */
6655                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6656
6657                 /* Get the packet data + FCS length and the status. */
6658                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6659                 status  = l2fhdr->l2_fhdr_status;
6660
6661                 /*
6662                  * Skip over the l2_fhdr and pad, resulting in the
6663                  * following data in the mbuf:
6664                  * +---------------------+-----+
6665                  * | packet data         | FCS |
6666                  * +---------------------+-----+
6667                  */
6668                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6669
6670                 /*
6671                  * When split header mode is used, an ethernet frame
6672                  * may be split across the receive chain and the
6673                  * page chain. If that occurs an mbuf cluster must be
6674                  * reassembled from the individual mbuf pieces.
6675                  */
6676                 if (bce_hdr_split == TRUE) {
6677                         /*
6678                          * Check whether the received frame fits in a single
6679                          * mbuf or not (i.e. packet data + FCS <=
6680                          * sc->rx_bd_mbuf_data_len bytes).
6681                          */
6682                         if (pkt_len > m0->m_len) {
6683                                 /*
6684                                  * The received frame is larger than a single mbuf.
6685                                  * If the frame was a TCP frame then only the TCP
6686                                  * header is placed in the mbuf, the remaining
6687                                  * payload (including FCS) is placed in the page
6688                                  * chain, the SPLIT flag is set, and the header
6689                                  * length is placed in the IP checksum field.
6690                                  * If the frame is not a TCP frame then the mbuf
6691                                  * is filled and the remaining bytes are placed
6692                                  * in the page chain.
6693                                  */
6694
6695                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6696                                         "packet.\n", __FUNCTION__);
6697                                 DBRUN(sc->split_header_frames_rcvd++);
6698
6699                                 /*
6700                                  * When the page chain is enabled and the TCP
6701                                  * header has been split from the TCP payload,
6702                                  * the ip_xsum structure will reflect the length
6703                                  * of the TCP header, not the IP checksum.  Set
6704                                  * the packet length of the mbuf accordingly.
6705                                  */
6706                                 if (status & L2_FHDR_STATUS_SPLIT) {
6707                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6708                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6709                                 }
6710
6711                                 rem_len = pkt_len - m0->m_len;
6712
6713                                 /* Pull mbufs off the page chain for any remaining data. */
6714                                 while (rem_len > 0) {
6715                                         struct mbuf *m_pg;
6716
6717                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6718
6719                                         /* Remove the mbuf from the page chain. */
6720                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6721                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6722                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6723                                         sc->free_pg_bd++;
6724
6725                                         /* Unmap the page chain mbuf from DMA space. */
6726                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6727                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6728                                                 BUS_DMASYNC_POSTREAD);
6729                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6730                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6731
6732                                         /* Adjust the mbuf length. */
6733                                         if (rem_len < m_pg->m_len) {
6734                                                 /* The mbuf chain is complete. */
6735                                                 m_pg->m_len = rem_len;
6736                                                 rem_len = 0;
6737                                         } else {
6738                                                 /* More packet data is waiting. */
6739                                                 rem_len -= m_pg->m_len;
6740                                         }
6741
6742                                         /* Concatenate the mbuf cluster to the mbuf. */
6743                                         m_cat(m0, m_pg);
6744
6745                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6746                                 }
6747
6748                                 /* Set the total packet length. */
6749                                 m0->m_pkthdr.len = pkt_len;
6750
6751                         } else {
6752                                 /*
6753                                  * The received packet is small and fits in a
6754                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6755                                  * FCS <= MHLEN).  In other words, the packet is
6756                                  * 154 bytes or less in size.
6757                                  */
6758
6759                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6760                                         "packet.\n", __FUNCTION__);
6761
6762                                 /* Set the total packet length. */
6763                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6764                         }
6765                 } else
6766                         /* Set the total packet length. */
6767                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6768
6769                 /* Remove the trailing Ethernet FCS. */
6770                 m_adj(m0, -ETHER_CRC_LEN);
6771
6772                 /* Check that the resulting mbuf chain is valid. */
6773                 DBRUN(m_sanity(m0, FALSE));
6774                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6775                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6776                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6777                     m_print(m0, 128));
6778
6779                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6780                     sc->l2fhdr_error_sim_count++;
6781                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6782
6783                 /* Check the received frame for errors. */
6784                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6785                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6786                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6787
6788                         /* Log the error and release the mbuf. */
6789                         ifp->if_ierrors++;
6790                         sc->l2fhdr_error_count++;
6791
6792                         m_freem(m0);
6793                         m0 = NULL;
6794                         goto bce_rx_int_next_rx;
6795                 }
6796
6797                 /* Send the packet to the appropriate interface. */
6798                 m0->m_pkthdr.rcvif = ifp;
6799
6800                 /* Assume no hardware checksum. */
6801                 m0->m_pkthdr.csum_flags = 0;
6802
6803                 /* Validate the checksum if offload enabled. */
6804                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6805
6806                         /* Check for an IP datagram. */
6807                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6808                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6809                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6810                                 DBRUN(sc->csum_offload_ip++);
6811                                 /* Check if the IP checksum is valid. */
6812                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6813                                         m0->m_pkthdr.csum_flags |=
6814                                             CSUM_IP_VALID;
6815                         }
6816
6817                         /* Check for a valid TCP/UDP frame. */
6818                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6819                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6820
6821                                 /* Check for a good TCP/UDP checksum. */
6822                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6823                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6824                                         DBRUN(sc->csum_offload_tcp_udp++);
6825                                         m0->m_pkthdr.csum_data =
6826                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6827                                         m0->m_pkthdr.csum_flags |=
6828                                             (CSUM_DATA_VALID
6829                                             | CSUM_PSEUDO_HDR);
6830                                 }
6831                         }
6832                 }
6833
6834                 /* Attach the VLAN tag. */
6835                 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
6836                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6837                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6838                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6839 #if __FreeBSD_version < 700000
6840                                 VLAN_INPUT_TAG(ifp, m0,
6841                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6842 #else
6843                                 m0->m_pkthdr.ether_vtag =
6844                                     l2fhdr->l2_fhdr_vlan_tag;
6845                                 m0->m_flags |= M_VLANTAG;
6846 #endif
6847                         } else {
6848                                 /*
6849                                  * bce(4) controllers can't disable VLAN
6850                                  * tag stripping if management firmware
6851                                  * (ASF/IPMI/UMP) is running. So we always
6852                                  * strip VLAN tag and manually reconstruct
6853                                  * the VLAN frame by appending stripped
6854                                  * VLAN tag in driver if VLAN tag stripping
6855                                  * was disabled.
6856                                  *
6857                                  * TODO: LLC SNAP handling.
6858                                  */
6859                                 bcopy(mtod(m0, uint8_t *),
6860                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6861                                     ETHER_ADDR_LEN * 2);
6862                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6863                                 vh = mtod(m0, struct ether_vlan_header *);
6864                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6865                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6866                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6867                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6868                         }
6869                 }
6870
6871                 /* Increment received packet statistics. */
6872                 ifp->if_ipackets++;
6873
6874 bce_rx_int_next_rx:
6875                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6876
6877                 /* If we have a packet, pass it up the stack */
6878                 if (m0) {
6879                         /* Make sure we don't lose our place when we release the lock. */
6880                         sc->rx_cons = sw_rx_cons;
6881                         sc->pg_cons = sw_pg_cons;
6882
6883                         BCE_UNLOCK(sc);
6884                         (*ifp->if_input)(ifp, m0);
6885                         BCE_LOCK(sc);
6886
6887                         /* Recover our place. */
6888                         sw_rx_cons = sc->rx_cons;
6889                         sw_pg_cons = sc->pg_cons;
6890                 }
6891
6892                 /* Refresh hw_cons to see if there's new work */
6893                 if (sw_rx_cons == hw_rx_cons)
6894                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6895         }
6896
6897         /* No new packets.  Refill the page chain. */
6898         if (bce_hdr_split == TRUE) {
6899                 sc->pg_cons = sw_pg_cons;
6900                 bce_fill_pg_chain(sc);
6901         }
6902
6903         /* No new packets.  Refill the RX chain. */
6904         sc->rx_cons = sw_rx_cons;
6905         bce_fill_rx_chain(sc);
6906
6907         /* Prepare the page chain pages to be accessed by the NIC. */
6908         for (int i = 0; i < sc->rx_pages; i++)
6909                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6910                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6911
6912         if (bce_hdr_split == TRUE) {
6913                 for (int i = 0; i < sc->pg_pages; i++)
6914                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6915                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6916         }
6917
6918         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6919             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6920             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6921         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6922 }
6923
6924
6925 /****************************************************************************/
6926 /* Reads the transmit consumer value from the status block (skipping over   */
6927 /* chain page pointer if necessary).                                        */
6928 /*                                                                          */
6929 /* Returns:                                                                 */
6930 /*   hw_cons                                                                */
6931 /****************************************************************************/
6932 static inline u16
6933 bce_get_hw_tx_cons(struct bce_softc *sc)
6934 {
6935         u16 hw_cons;
6936
6937         mb();
6938         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6939         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6940                 hw_cons++;
6941
6942         return hw_cons;
6943 }
6944
6945
6946 /****************************************************************************/
6947 /* Handles transmit completion interrupt events.                            */
6948 /*                                                                          */
6949 /* Returns:                                                                 */
6950 /*   Nothing.                                                               */
6951 /****************************************************************************/
6952 static void
6953 bce_tx_intr(struct bce_softc *sc)
6954 {
6955         struct ifnet *ifp = sc->bce_ifp;
6956         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6957
6958         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6959         DBRUN(sc->interrupts_tx++);
6960         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6961             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6962             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6963
6964         BCE_LOCK_ASSERT(sc);
6965
6966         /* Get the hardware's view of the TX consumer index. */
6967         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6968         sw_tx_cons = sc->tx_cons;
6969
6970         /* Prevent speculative reads of the status block. */
6971         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6972             BUS_SPACE_BARRIER_READ);
6973
6974         /* Cycle through any completed TX chain page entries. */
6975         while (sw_tx_cons != hw_tx_cons) {
6976 #ifdef BCE_DEBUG
6977                 struct tx_bd *txbd = NULL;
6978 #endif
6979                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6980
6981                 DBPRINT(sc, BCE_INFO_SEND,
6982                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6983                     "sw_tx_chain_cons = 0x%04X\n",
6984                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6985
6986                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6987                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6988                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6989                     (int) MAX_TX_BD_ALLOC);
6990                     bce_breakpoint(sc));
6991
6992                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6993                     [TX_IDX(sw_tx_chain_cons)]);
6994
6995                 DBRUNIF((txbd == NULL),
6996                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6997                     __FILE__, __LINE__, sw_tx_chain_cons);
6998                     bce_breakpoint(sc));
6999
7000                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
7001                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
7002
7003                 /*
7004                  * Free the associated mbuf. Remember
7005                  * that only the last tx_bd of a packet
7006                  * has an mbuf pointer and DMA map.
7007                  */
7008                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
7009
7010                         /* Validate that this is the last tx_bd. */
7011                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
7012                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
7013                             "txmbuf == NULL!\n", __FILE__, __LINE__);
7014                             bce_breakpoint(sc));
7015
7016                         DBRUNMSG(BCE_INFO_SEND,
7017                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
7018                             "from tx_bd[0x%04X]\n", __FUNCTION__,
7019                             sw_tx_chain_cons));
7020
7021                         /* Unmap the mbuf. */
7022                         bus_dmamap_unload(sc->tx_mbuf_tag,
7023                             sc->tx_mbuf_map[sw_tx_chain_cons]);
7024
7025                         /* Free the mbuf. */
7026                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
7027                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
7028                         DBRUN(sc->debug_tx_mbuf_alloc--);
7029
7030                         ifp->if_opackets++;
7031                 }
7032
7033                 sc->used_tx_bd--;
7034                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
7035
7036                 /* Refresh hw_cons to see if there's new work. */
7037                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7038
7039                 /* Prevent speculative reads of the status block. */
7040                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7041                     BUS_SPACE_BARRIER_READ);
7042         }
7043
7044         /* Clear the TX timeout timer. */
7045         sc->watchdog_timer = 0;
7046
7047         /* Clear the tx hardware queue full flag. */
7048         if (sc->used_tx_bd < sc->max_tx_bd) {
7049                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7050                     DBPRINT(sc, BCE_INFO_SEND,
7051                     "%s(): Open TX chain! %d/%d (used/total)\n",
7052                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7053                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7054         }
7055
7056         sc->tx_cons = sw_tx_cons;
7057
7058         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7059             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7060             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7061         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7062 }
7063
7064
7065 /****************************************************************************/
7066 /* Disables interrupt generation.                                           */
7067 /*                                                                          */
7068 /* Returns:                                                                 */
7069 /*   Nothing.                                                               */
7070 /****************************************************************************/
7071 static void
7072 bce_disable_intr(struct bce_softc *sc)
7073 {
7074         DBENTER(BCE_VERBOSE_INTR);
7075
7076         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7077         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7078
7079         DBEXIT(BCE_VERBOSE_INTR);
7080 }
7081
7082
7083 /****************************************************************************/
7084 /* Enables interrupt generation.                                            */
7085 /*                                                                          */
7086 /* Returns:                                                                 */
7087 /*   Nothing.                                                               */
7088 /****************************************************************************/
7089 static void
7090 bce_enable_intr(struct bce_softc *sc, int coal_now)
7091 {
7092         DBENTER(BCE_VERBOSE_INTR);
7093
7094         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7095             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7096             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7097
7098         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7099             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7100
7101         /* Force an immediate interrupt (whether there is new data or not). */
7102         if (coal_now)
7103                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7104
7105         DBEXIT(BCE_VERBOSE_INTR);
7106 }
7107
7108
7109 /****************************************************************************/
7110 /* Handles controller initialization.                                       */
7111 /*                                                                          */
7112 /* Returns:                                                                 */
7113 /*   Nothing.                                                               */
7114 /****************************************************************************/
7115 static void
7116 bce_init_locked(struct bce_softc *sc)
7117 {
7118         struct ifnet *ifp;
7119         u32 ether_mtu = 0;
7120
7121         DBENTER(BCE_VERBOSE_RESET);
7122
7123         BCE_LOCK_ASSERT(sc);
7124
7125         ifp = sc->bce_ifp;
7126
7127         /* Check if the driver is still running and bail out if it is. */
7128         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7129                 goto bce_init_locked_exit;
7130
7131         bce_stop(sc);
7132
7133         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7134                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7135                     __FILE__, __LINE__);
7136                 goto bce_init_locked_exit;
7137         }
7138
7139         if (bce_chipinit(sc)) {
7140                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7141                     __FILE__, __LINE__);
7142                 goto bce_init_locked_exit;
7143         }
7144
7145         if (bce_blockinit(sc)) {
7146                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7147                     __FILE__, __LINE__);
7148                 goto bce_init_locked_exit;
7149         }
7150
7151         /* Load our MAC address. */
7152         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7153         bce_set_mac_addr(sc);
7154
7155         if (bce_hdr_split == FALSE)
7156                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7157         /*
7158          * Calculate and program the hardware Ethernet MTU
7159          * size. Be generous on the receive if we have room
7160          * and allowed by the user.
7161          */
7162         if (bce_strict_rx_mtu == TRUE)
7163                 ether_mtu = ifp->if_mtu;
7164         else {
7165                 if (bce_hdr_split == TRUE) {
7166                         if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
7167                                    sc->pg_bd_mbuf_alloc_size))
7168                                         ether_mtu = sc->rx_bd_mbuf_data_len +
7169                                            sc->pg_bd_mbuf_alloc_size;
7170                         else
7171                                 ether_mtu = ifp->if_mtu;
7172                 } else {
7173                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7174                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7175                         else
7176                                 ether_mtu = ifp->if_mtu;
7177                 }
7178         }
7179
7180         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7181
7182         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7183             __FUNCTION__, ether_mtu);
7184
7185         /* Program the mtu, enabling jumbo frame support if necessary. */
7186         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7187                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7188                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7189                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7190         else
7191                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7192
7193         /* Program appropriate promiscuous/multicast filtering. */
7194         bce_set_rx_mode(sc);
7195
7196         if (bce_hdr_split == TRUE) {
7197                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
7198                         __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
7199
7200                 /* Init page buffer descriptor chain. */
7201                 bce_init_pg_chain(sc);
7202         }
7203
7204         /* Init RX buffer descriptor chain. */
7205         bce_init_rx_chain(sc);
7206
7207         /* Init TX buffer descriptor chain. */
7208         bce_init_tx_chain(sc);
7209
7210         /* Enable host interrupts. */
7211         bce_enable_intr(sc, 1);
7212
7213         bce_ifmedia_upd_locked(ifp);
7214
7215         /* Let the OS know the driver is up and running. */
7216         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7217         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7218
7219         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7220
7221 bce_init_locked_exit:
7222         DBEXIT(BCE_VERBOSE_RESET);
7223 }
7224
7225
7226 /****************************************************************************/
7227 /* Initialize the controller just enough so that any management firmware    */
7228 /* running on the device will continue to operate correctly.                */
7229 /*                                                                          */
7230 /* Returns:                                                                 */
7231 /*   Nothing.                                                               */
7232 /****************************************************************************/
7233 static void
7234 bce_mgmt_init_locked(struct bce_softc *sc)
7235 {
7236         struct ifnet *ifp;
7237
7238         DBENTER(BCE_VERBOSE_RESET);
7239
7240         BCE_LOCK_ASSERT(sc);
7241
7242         /* Bail out if management firmware is not running. */
7243         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7244                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7245                     "No management firmware running...\n");
7246                 goto bce_mgmt_init_locked_exit;
7247         }
7248
7249         ifp = sc->bce_ifp;
7250
7251         /* Enable all critical blocks in the MAC. */
7252         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7253         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7254         DELAY(20);
7255
7256         bce_ifmedia_upd_locked(ifp);
7257
7258 bce_mgmt_init_locked_exit:
7259         DBEXIT(BCE_VERBOSE_RESET);
7260 }
7261
7262
7263 /****************************************************************************/
7264 /* Handles controller initialization when called from an unlocked routine.  */
7265 /*                                                                          */
7266 /* Returns:                                                                 */
7267 /*   Nothing.                                                               */
7268 /****************************************************************************/
7269 static void
7270 bce_init(void *xsc)
7271 {
7272         struct bce_softc *sc = xsc;
7273
7274         DBENTER(BCE_VERBOSE_RESET);
7275
7276         BCE_LOCK(sc);
7277         bce_init_locked(sc);
7278         BCE_UNLOCK(sc);
7279
7280         DBEXIT(BCE_VERBOSE_RESET);
7281 }
7282
7283
7284 /****************************************************************************/
7285 /* Modifies an mbuf for TSO on the hardware.                                */
7286 /*                                                                          */
7287 /* Returns:                                                                 */
7288 /*   Pointer to a modified mbuf.                                            */
7289 /****************************************************************************/
7290 static struct mbuf *
7291 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7292 {
7293         struct mbuf *m;
7294         struct ether_header *eh;
7295         struct ip *ip;
7296         struct tcphdr *th;
7297         u16 etype;
7298         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7299
7300         DBRUN(sc->tso_frames_requested++);
7301
7302         /* Controller may modify mbuf chains. */
7303         if (M_WRITABLE(*m_head) == 0) {
7304                 m = m_dup(*m_head, M_NOWAIT);
7305                 m_freem(*m_head);
7306                 if (m == NULL) {
7307                         sc->mbuf_alloc_failed_count++;
7308                         *m_head = NULL;
7309                         return (NULL);
7310                 }
7311                 *m_head = m;
7312         }
7313
7314         /*
7315          * For TSO the controller needs two pieces of info,
7316          * the MSS and the IP+TCP options length.
7317          */
7318         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7319         if (m == NULL) {
7320                 *m_head = NULL;
7321                 return (NULL);
7322         }
7323         eh = mtod(m, struct ether_header *);
7324         etype = ntohs(eh->ether_type);
7325
7326         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7327         switch (etype) {
7328         case ETHERTYPE_IP:
7329                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7330                 /* TSO only supported for TCP protocol. */
7331                 if (ip->ip_p != IPPROTO_TCP) {
7332                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7333                             __FILE__, __LINE__);
7334                         m_freem(*m_head);
7335                         *m_head = NULL;
7336                         return (NULL);
7337                 }
7338
7339                 /* Get IP header length in bytes (min 20) */
7340                 ip_hlen = ip->ip_hl << 2;
7341                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7342                     sizeof(struct tcphdr));
7343                 if (m == NULL) {
7344                         *m_head = NULL;
7345                         return (NULL);
7346                 }
7347
7348                 /* Get the TCP header length in bytes (min 20) */
7349                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7350                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7351                 tcp_hlen = (th->th_off << 2);
7352
7353                 /* Make sure all IP/TCP options live in the same buffer. */
7354                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7355                     tcp_hlen);
7356                 if (m == NULL) {
7357                         *m_head = NULL;
7358                         return (NULL);
7359                 }
7360
7361                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7362                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7363                 ip_len = ip->ip_len;
7364                 ip->ip_len = 0;
7365                 ip->ip_sum = 0;
7366                 break;
7367         case ETHERTYPE_IPV6:
7368                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7369                     __FILE__, __LINE__);
7370                 m_freem(*m_head);
7371                 *m_head = NULL;
7372                 return (NULL);
7373                 /* NOT REACHED */
7374         default:
7375                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7376                     __FILE__, __LINE__);
7377                 m_freem(*m_head);
7378                 *m_head = NULL;
7379                 return (NULL);
7380         }
7381
7382         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7383
7384         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7385             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7386             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7387             tcp_hlen, ip_len);
7388
7389         /* Set the LSO flag in the TX BD */
7390         *flags |= TX_BD_FLAGS_SW_LSO;
7391
7392         /* Set the length of IP + TCP options (in 32 bit words) */
7393         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7394             sizeof(struct tcphdr)) >> 2) << 8);
7395
7396         DBRUN(sc->tso_frames_completed++);
7397         return (*m_head);
7398 }
7399
7400
7401 /****************************************************************************/
7402 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7403 /* memory visible to the controller.                                        */
7404 /*                                                                          */
7405 /* Returns:                                                                 */
7406 /*   0 for success, positive value for failure.                             */
7407 /* Modified:                                                                */
7408 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7409 /****************************************************************************/
7410 static int
7411 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7412 {
7413         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7414         bus_dmamap_t map;
7415         struct tx_bd *txbd = NULL;
7416         struct mbuf *m0;
7417         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7418         u32 prod_bseq;
7419
7420 #ifdef BCE_DEBUG
7421         u16 debug_prod;
7422 #endif
7423
7424         int i, error, nsegs, rc = 0;
7425
7426         DBENTER(BCE_VERBOSE_SEND);
7427
7428         /* Make sure we have room in the TX chain. */
7429         if (sc->used_tx_bd >= sc->max_tx_bd)
7430                 goto bce_tx_encap_exit;
7431
7432         /* Transfer any checksum offload flags to the bd. */
7433         m0 = *m_head;
7434         if (m0->m_pkthdr.csum_flags) {
7435                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7436                         m0 = bce_tso_setup(sc, m_head, &flags);
7437                         if (m0 == NULL) {
7438                                 DBRUN(sc->tso_frames_failed++);
7439                                 goto bce_tx_encap_exit;
7440                         }
7441                         mss = htole16(m0->m_pkthdr.tso_segsz);
7442                 } else {
7443                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7444                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7445                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7446                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7447                 }
7448         }
7449
7450         /* Transfer any VLAN tags to the bd. */
7451         if (m0->m_flags & M_VLANTAG) {
7452                 flags |= TX_BD_FLAGS_VLAN_TAG;
7453                 vlan_tag = m0->m_pkthdr.ether_vtag;
7454         }
7455
7456         /* Map the mbuf into DMAable memory. */
7457         prod = sc->tx_prod;
7458         chain_prod = TX_CHAIN_IDX(prod);
7459         map = sc->tx_mbuf_map[chain_prod];
7460
7461         /* Map the mbuf into our DMA address space. */
7462         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7463             segs, &nsegs, BUS_DMA_NOWAIT);
7464
7465         /* Check if the DMA mapping was successful */
7466         if (error == EFBIG) {
7467                 sc->mbuf_frag_count++;
7468
7469                 /* Try to defrag the mbuf. */
7470                 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7471                 if (m0 == NULL) {
7472                         /* Defrag was unsuccessful */
7473                         m_freem(*m_head);
7474                         *m_head = NULL;
7475                         sc->mbuf_alloc_failed_count++;
7476                         rc = ENOBUFS;
7477                         goto bce_tx_encap_exit;
7478                 }
7479
7480                 /* Defrag was successful, try mapping again */
7481                 *m_head = m0;
7482                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7483                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7484
7485                 /* Still getting an error after a defrag. */
7486                 if (error == ENOMEM) {
7487                         /* Insufficient DMA buffers available. */
7488                         sc->dma_map_addr_tx_failed_count++;
7489                         rc = error;
7490                         goto bce_tx_encap_exit;
7491                 } else if (error != 0) {
7492                         /* Release it and return an error. */
7493                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7494                             "TX chain!\n", __FILE__, __LINE__);
7495                         m_freem(m0);
7496                         *m_head = NULL;
7497                         sc->dma_map_addr_tx_failed_count++;
7498                         rc = ENOBUFS;
7499                         goto bce_tx_encap_exit;
7500                 }
7501         } else if (error == ENOMEM) {
7502                 /* Insufficient DMA buffers available. */
7503                 sc->dma_map_addr_tx_failed_count++;
7504                 rc = error;
7505                 goto bce_tx_encap_exit;
7506         } else if (error != 0) {
7507                 m_freem(m0);
7508                 *m_head = NULL;
7509                 sc->dma_map_addr_tx_failed_count++;
7510                 rc = error;
7511                 goto bce_tx_encap_exit;
7512         }
7513
7514         /* Make sure there's room in the chain */
7515         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7516                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7517                 rc = ENOBUFS;
7518                 goto bce_tx_encap_exit;
7519         }
7520
7521         /* prod points to an empty tx_bd at this point. */
7522         prod_bseq  = sc->tx_prod_bseq;
7523
7524 #ifdef BCE_DEBUG
7525         debug_prod = chain_prod;
7526 #endif
7527
7528         DBPRINT(sc, BCE_INFO_SEND,
7529             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7530             "prod_bseq = 0x%08X\n",
7531             __FUNCTION__, prod, chain_prod, prod_bseq);
7532
7533         /*
7534          * Cycle through each mbuf segment that makes up
7535          * the outgoing frame, gathering the mapping info
7536          * for that segment and creating a tx_bd for
7537          * the mbuf.
7538          */
7539         for (i = 0; i < nsegs ; i++) {
7540
7541                 chain_prod = TX_CHAIN_IDX(prod);
7542                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7543                     [TX_IDX(chain_prod)];
7544
7545                 txbd->tx_bd_haddr_lo =
7546                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7547                 txbd->tx_bd_haddr_hi =
7548                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7549                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7550                     htole16(segs[i].ds_len);
7551                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7552                 txbd->tx_bd_flags = htole16(flags);
7553                 prod_bseq += segs[i].ds_len;
7554                 if (i == 0)
7555                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7556                 prod = NEXT_TX_BD(prod);
7557         }
7558
7559         /* Set the END flag on the last TX buffer descriptor. */
7560         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7561
7562         DBRUNMSG(BCE_EXTREME_SEND,
7563             bce_dump_tx_chain(sc, debug_prod, nsegs));
7564
7565         /*
7566          * Ensure that the mbuf pointer for this transmission
7567          * is placed at the array index of the last
7568          * descriptor in this chain.  This is done
7569          * because a single map is used for all
7570          * segments of the mbuf and we don't want to
7571          * unload the map before all of the segments
7572          * have been freed.
7573          */
7574         sc->tx_mbuf_ptr[chain_prod] = m0;
7575         sc->used_tx_bd += nsegs;
7576
7577         /* Update some debug statistic counters */
7578         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7579             sc->tx_hi_watermark = sc->used_tx_bd);
7580         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7581         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7582
7583         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7584
7585         /* prod points to the next free tx_bd at this point. */
7586         sc->tx_prod = prod;
7587         sc->tx_prod_bseq = prod_bseq;
7588
7589         /* Tell the chip about the waiting TX frames. */
7590         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7591             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7592         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7593             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7594
7595 bce_tx_encap_exit:
7596         DBEXIT(BCE_VERBOSE_SEND);
7597         return(rc);
7598 }
7599
7600
7601 /****************************************************************************/
7602 /* Main transmit routine when called from another routine with a lock.      */
7603 /*                                                                          */
7604 /* Returns:                                                                 */
7605 /*   Nothing.                                                               */
7606 /****************************************************************************/
7607 static void
7608 bce_start_locked(struct ifnet *ifp)
7609 {
7610         struct bce_softc *sc = ifp->if_softc;
7611         struct mbuf *m_head = NULL;
7612         int count = 0;
7613         u16 tx_prod, tx_chain_prod;
7614
7615         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7616
7617         BCE_LOCK_ASSERT(sc);
7618
7619         /* prod points to the next free tx_bd. */
7620         tx_prod = sc->tx_prod;
7621         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7622
7623         DBPRINT(sc, BCE_INFO_SEND,
7624             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7625             "tx_prod_bseq = 0x%08X\n",
7626             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7627
7628         /* If there's no link or the transmit queue is empty then just exit. */
7629         if (sc->bce_link_up == FALSE) {
7630                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7631                     __FUNCTION__);
7632                 goto bce_start_locked_exit;
7633         }
7634
7635         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7636                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7637                     __FUNCTION__);
7638                 goto bce_start_locked_exit;
7639         }
7640
7641         /*
7642          * Keep adding entries while there is space in the ring.
7643          */
7644         while (sc->used_tx_bd < sc->max_tx_bd) {
7645
7646                 /* Check for any frames to send. */
7647                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7648
7649                 /* Stop when the transmit queue is empty. */
7650                 if (m_head == NULL)
7651                         break;
7652
7653                 /*
7654                  * Pack the data into the transmit ring. If we
7655                  * don't have room, place the mbuf back at the
7656                  * head of the queue and set the OACTIVE flag
7657                  * to wait for the NIC to drain the chain.
7658                  */
7659                 if (bce_tx_encap(sc, &m_head)) {
7660                         if (m_head != NULL)
7661                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7662                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7663                         DBPRINT(sc, BCE_INFO_SEND,
7664                             "TX chain is closed for business! Total "
7665                             "tx_bd used = %d\n", sc->used_tx_bd);
7666                         break;
7667                 }
7668
7669                 count++;
7670
7671                 /* Send a copy of the frame to any BPF listeners. */
7672                 ETHER_BPF_MTAP(ifp, m_head);
7673         }
7674
7675         /* Exit if no packets were dequeued. */
7676         if (count == 0) {
7677                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7678                     "dequeued\n", __FUNCTION__);
7679                 goto bce_start_locked_exit;
7680         }
7681
7682         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7683             "send queue.\n", __FUNCTION__, count);
7684
7685         /* Set the tx timeout. */
7686         sc->watchdog_timer = BCE_TX_TIMEOUT;
7687
7688         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7689         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7690
7691 bce_start_locked_exit:
7692         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7693         return;
7694 }
7695
7696
7697 /****************************************************************************/
7698 /* Main transmit routine when called from another routine without a lock.   */
7699 /*                                                                          */
7700 /* Returns:                                                                 */
7701 /*   Nothing.                                                               */
7702 /****************************************************************************/
7703 static void
7704 bce_start(struct ifnet *ifp)
7705 {
7706         struct bce_softc *sc = ifp->if_softc;
7707
7708         DBENTER(BCE_VERBOSE_SEND);
7709
7710         BCE_LOCK(sc);
7711         bce_start_locked(ifp);
7712         BCE_UNLOCK(sc);
7713
7714         DBEXIT(BCE_VERBOSE_SEND);
7715 }
7716
7717
7718 /****************************************************************************/
7719 /* Handles any IOCTL calls from the operating system.                       */
7720 /*                                                                          */
7721 /* Returns:                                                                 */
7722 /*   0 for success, positive value for failure.                             */
7723 /****************************************************************************/
7724 static int
7725 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7726 {
7727         struct bce_softc *sc = ifp->if_softc;
7728         struct ifreq *ifr = (struct ifreq *) data;
7729         struct mii_data *mii;
7730         int mask, error = 0;
7731
7732         DBENTER(BCE_VERBOSE_MISC);
7733
7734         switch(command) {
7735
7736         /* Set the interface MTU. */
7737         case SIOCSIFMTU:
7738                 /* Check that the MTU setting is supported. */
7739                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7740                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7741                         error = EINVAL;
7742                         break;
7743                 }
7744
7745                 DBPRINT(sc, BCE_INFO_MISC,
7746                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7747                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7748
7749                 BCE_LOCK(sc);
7750                 ifp->if_mtu = ifr->ifr_mtu;
7751                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7752                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7753                         bce_init_locked(sc);
7754                 }
7755                 BCE_UNLOCK(sc);
7756                 break;
7757
7758         /* Set interface flags. */
7759         case SIOCSIFFLAGS:
7760                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7761
7762                 BCE_LOCK(sc);
7763
7764                 /* Check if the interface is up. */
7765                 if (ifp->if_flags & IFF_UP) {
7766                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7767                                 /* Change promiscuous/multicast flags as necessary. */
7768                                 bce_set_rx_mode(sc);
7769                         } else {
7770                                 /* Start the HW */
7771                                 bce_init_locked(sc);
7772                         }
7773                 } else {
7774                         /* The interface is down, check if driver is running. */
7775                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7776                                 bce_stop(sc);
7777
7778                                 /* If MFW is running, restart the controller a bit. */
7779                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7780                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7781                                         bce_chipinit(sc);
7782                                         bce_mgmt_init_locked(sc);
7783                                 }
7784                         }
7785                 }
7786
7787                 BCE_UNLOCK(sc);
7788                 break;
7789
7790         /* Add/Delete multicast address */
7791         case SIOCADDMULTI:
7792         case SIOCDELMULTI:
7793                 DBPRINT(sc, BCE_VERBOSE_MISC,
7794                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7795
7796                 BCE_LOCK(sc);
7797                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7798                         bce_set_rx_mode(sc);
7799                 BCE_UNLOCK(sc);
7800
7801                 break;
7802
7803         /* Set/Get Interface media */
7804         case SIOCSIFMEDIA:
7805         case SIOCGIFMEDIA:
7806                 DBPRINT(sc, BCE_VERBOSE_MISC,
7807                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7808                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7809                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7810                             command);
7811                 else {
7812                         mii = device_get_softc(sc->bce_miibus);
7813                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7814                             command);
7815                 }
7816                 break;
7817
7818         /* Set interface capability */
7819         case SIOCSIFCAP:
7820                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7821                 DBPRINT(sc, BCE_INFO_MISC,
7822                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7823
7824                 /* Toggle the TX checksum capabilities enable flag. */
7825                 if (mask & IFCAP_TXCSUM &&
7826                     ifp->if_capabilities & IFCAP_TXCSUM) {
7827                         ifp->if_capenable ^= IFCAP_TXCSUM;
7828                         if (IFCAP_TXCSUM & ifp->if_capenable)
7829                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7830                         else
7831                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7832                 }
7833
7834                 /* Toggle the RX checksum capabilities enable flag. */
7835                 if (mask & IFCAP_RXCSUM &&
7836                     ifp->if_capabilities & IFCAP_RXCSUM)
7837                         ifp->if_capenable ^= IFCAP_RXCSUM;
7838
7839                 /* Toggle the TSO capabilities enable flag. */
7840                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7841                     ifp->if_capabilities & IFCAP_TSO4) {
7842                         ifp->if_capenable ^= IFCAP_TSO4;
7843                         if (IFCAP_TSO4 & ifp->if_capenable)
7844                                 ifp->if_hwassist |= CSUM_TSO;
7845                         else
7846                                 ifp->if_hwassist &= ~CSUM_TSO;
7847                 }
7848
7849                 if (mask & IFCAP_VLAN_HWCSUM &&
7850                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7851                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7852
7853                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7854                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7855                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7856                 /*
7857                  * Don't actually disable VLAN tag stripping as
7858                  * management firmware (ASF/IPMI/UMP) requires the
7859                  * feature. If VLAN tag stripping is disabled driver
7860                  * will manually reconstruct the VLAN frame by
7861                  * appending stripped VLAN tag.
7862                  */
7863                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7864                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7865                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7866                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7867                             == 0)
7868                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7869                 }
7870                 VLAN_CAPABILITIES(ifp);
7871                 break;
7872         default:
7873                 /* We don't know how to handle the IOCTL, pass it on. */
7874                 error = ether_ioctl(ifp, command, data);
7875                 break;
7876         }
7877
7878         DBEXIT(BCE_VERBOSE_MISC);
7879         return(error);
7880 }
7881
7882
7883 /****************************************************************************/
7884 /* Transmit timeout handler.                                                */
7885 /*                                                                          */
7886 /* Returns:                                                                 */
7887 /*   Nothing.                                                               */
7888 /****************************************************************************/
7889 static void
7890 bce_watchdog(struct bce_softc *sc)
7891 {
7892         DBENTER(BCE_EXTREME_SEND);
7893
7894         BCE_LOCK_ASSERT(sc);
7895
7896         /* If the watchdog timer hasn't expired then just exit. */
7897         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7898                 goto bce_watchdog_exit;
7899
7900         /* If pause frames are active then don't reset the hardware. */
7901         /* ToDo: Should we reset the timer here? */
7902         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
7903                 goto bce_watchdog_exit;
7904
7905         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7906             __FILE__, __LINE__);
7907
7908         DBRUNMSG(BCE_INFO,
7909             bce_dump_driver_state(sc);
7910             bce_dump_status_block(sc);
7911             bce_dump_stats_block(sc);
7912             bce_dump_ftqs(sc);
7913             bce_dump_txp_state(sc, 0);
7914             bce_dump_rxp_state(sc, 0);
7915             bce_dump_tpat_state(sc, 0);
7916             bce_dump_cp_state(sc, 0);
7917             bce_dump_com_state(sc, 0));
7918
7919         DBRUN(bce_breakpoint(sc));
7920
7921         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7922
7923         bce_init_locked(sc);
7924         sc->bce_ifp->if_oerrors++;
7925
7926 bce_watchdog_exit:
7927         DBEXIT(BCE_EXTREME_SEND);
7928 }
7929
7930
7931 /*
7932  * Interrupt handler.
7933  */
7934 /****************************************************************************/
7935 /* Main interrupt entry point.  Verifies that the controller generated the  */
7936 /* interrupt and then calls a separate routine for handle the various       */
7937 /* interrupt causes (PHY, TX, RX).                                          */
7938 /*                                                                          */
7939 /* Returns:                                                                 */
7940 /*   0 for success, positive value for failure.                             */
7941 /****************************************************************************/
7942 static void
7943 bce_intr(void *xsc)
7944 {
7945         struct bce_softc *sc;
7946         struct ifnet *ifp;
7947         u32 status_attn_bits;
7948         u16 hw_rx_cons, hw_tx_cons;
7949
7950         sc = xsc;
7951         ifp = sc->bce_ifp;
7952
7953         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7954         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7955         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7956
7957         BCE_LOCK(sc);
7958
7959         DBRUN(sc->interrupts_generated++);
7960
7961         /* Synchnorize before we read from interface's status block */
7962         bus_dmamap_sync(sc->status_tag, sc->status_map,
7963             BUS_DMASYNC_POSTREAD);
7964
7965         /*
7966          * If the hardware status block index
7967          * matches the last value read by the
7968          * driver and we haven't asserted our
7969          * interrupt then there's nothing to do.
7970          */
7971         if ((sc->status_block->status_idx == sc->last_status_idx) &&
7972             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7973              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7974                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7975                     __FUNCTION__);
7976                 goto bce_intr_exit;
7977         }
7978
7979         /* Ack the interrupt and stop others from occuring. */
7980         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7981             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7982             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7983
7984         /* Check if the hardware has finished any work. */
7985         hw_rx_cons = bce_get_hw_rx_cons(sc);
7986         hw_tx_cons = bce_get_hw_tx_cons(sc);
7987
7988         /* Keep processing data as long as there is work to do. */
7989         for (;;) {
7990
7991                 status_attn_bits = sc->status_block->status_attn_bits;
7992
7993                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7994                     BCE_PRINTF("Simulating unexpected status attention "
7995                     "bit set.");
7996                     sc->unexpected_attention_sim_count++;
7997                     status_attn_bits = status_attn_bits |
7998                     STATUS_ATTN_BITS_PARITY_ERROR);
7999
8000                 /* Was it a link change interrupt? */
8001                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
8002                     (sc->status_block->status_attn_bits_ack &
8003                      STATUS_ATTN_BITS_LINK_STATE)) {
8004                         bce_phy_intr(sc);
8005
8006                         /* Clear transient updates during link state change. */
8007                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
8008                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
8009                         REG_RD(sc, BCE_HC_COMMAND);
8010                 }
8011
8012                 /* If any other attention is asserted, the chip is toast. */
8013                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
8014                     (sc->status_block->status_attn_bits_ack &
8015                     ~STATUS_ATTN_BITS_LINK_STATE))) {
8016
8017                         sc->unexpected_attention_count++;
8018
8019                         BCE_PRINTF("%s(%d): Fatal attention detected: "
8020                             "0x%08X\n", __FILE__, __LINE__,
8021                             sc->status_block->status_attn_bits);
8022
8023                         DBRUNMSG(BCE_FATAL,
8024                             if (unexpected_attention_sim_control == 0)
8025                                 bce_breakpoint(sc));
8026
8027                         bce_init_locked(sc);
8028                         goto bce_intr_exit;
8029                 }
8030
8031                 /* Check for any completed RX frames. */
8032                 if (hw_rx_cons != sc->hw_rx_cons)
8033                         bce_rx_intr(sc);
8034
8035                 /* Check for any completed TX frames. */
8036                 if (hw_tx_cons != sc->hw_tx_cons)
8037                         bce_tx_intr(sc);
8038
8039                 /* Save status block index value for the next interrupt. */
8040                 sc->last_status_idx = sc->status_block->status_idx;
8041
8042                 /*
8043                  * Prevent speculative reads from getting
8044                  * ahead of the status block.
8045                  */
8046                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8047                     BUS_SPACE_BARRIER_READ);
8048
8049                 /*
8050                  * If there's no work left then exit the
8051                  * interrupt service routine.
8052                  */
8053                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8054                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8055
8056                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8057                     (hw_tx_cons == sc->hw_tx_cons))
8058                         break;
8059
8060         }
8061
8062         bus_dmamap_sync(sc->status_tag, sc->status_map,
8063             BUS_DMASYNC_PREREAD);
8064
8065         /* Re-enable interrupts. */
8066         bce_enable_intr(sc, 0);
8067
8068         /* Handle any frames that arrived while handling the interrupt. */
8069         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8070             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8071                 bce_start_locked(ifp);
8072
8073 bce_intr_exit:
8074         BCE_UNLOCK(sc);
8075
8076         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8077 }
8078
8079
8080 /****************************************************************************/
8081 /* Programs the various packet receive modes (broadcast and multicast).     */
8082 /*                                                                          */
8083 /* Returns:                                                                 */
8084 /*   Nothing.                                                               */
8085 /****************************************************************************/
8086 static void
8087 bce_set_rx_mode(struct bce_softc *sc)
8088 {
8089         struct ifnet *ifp;
8090         struct ifmultiaddr *ifma;
8091         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8092         u32 rx_mode, sort_mode;
8093         int h, i;
8094
8095         DBENTER(BCE_VERBOSE_MISC);
8096
8097         BCE_LOCK_ASSERT(sc);
8098
8099         ifp = sc->bce_ifp;
8100
8101         /* Initialize receive mode default settings. */
8102         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8103             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8104         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8105
8106         /*
8107          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8108          * be enbled.
8109          */
8110         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8111             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8112                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8113
8114         /*
8115          * Check for promiscuous, all multicast, or selected
8116          * multicast address filtering.
8117          */
8118         if (ifp->if_flags & IFF_PROMISC) {
8119                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8120
8121                 /* Enable promiscuous mode. */
8122                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8123                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8124         } else if (ifp->if_flags & IFF_ALLMULTI) {
8125                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8126
8127                 /* Enable all multicast addresses. */
8128                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8129                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
8130         }
8131                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8132         } else {
8133                 /* Accept one or more multicast(s). */
8134                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8135
8136                 if_maddr_rlock(ifp);
8137                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8138                         if (ifma->ifma_addr->sa_family != AF_LINK)
8139                                 continue;
8140                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8141                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8142                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8143                 }
8144                 if_maddr_runlock(ifp);
8145
8146                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8147                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8148
8149                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8150         }
8151
8152         /* Only make changes if the recive mode has actually changed. */
8153         if (rx_mode != sc->rx_mode) {
8154                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8155                     "0x%08X\n", rx_mode);
8156
8157                 sc->rx_mode = rx_mode;
8158                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8159         }
8160
8161         /* Disable and clear the exisitng sort before enabling a new sort. */
8162         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8163         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8164         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8165
8166         DBEXIT(BCE_VERBOSE_MISC);
8167 }
8168
8169
8170 /****************************************************************************/
8171 /* Called periodically to updates statistics from the controllers           */
8172 /* statistics block.                                                        */
8173 /*                                                                          */
8174 /* Returns:                                                                 */
8175 /*   Nothing.                                                               */
8176 /****************************************************************************/
8177 static void
8178 bce_stats_update(struct bce_softc *sc)
8179 {
8180         struct ifnet *ifp;
8181         struct statistics_block *stats;
8182
8183         DBENTER(BCE_EXTREME_MISC);
8184
8185         ifp = sc->bce_ifp;
8186
8187         stats = (struct statistics_block *) sc->stats_block;
8188
8189         /*
8190          * Certain controllers don't report
8191          * carrier sense errors correctly.
8192          * See errata E11_5708CA0_1165.
8193          */
8194         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8195             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8196                 ifp->if_oerrors +=
8197                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8198
8199         /*
8200          * Update the sysctl statistics from the
8201          * hardware statistics.
8202          */
8203         sc->stat_IfHCInOctets =
8204             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8205              (u64) stats->stat_IfHCInOctets_lo;
8206
8207         sc->stat_IfHCInBadOctets =
8208             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8209              (u64) stats->stat_IfHCInBadOctets_lo;
8210
8211         sc->stat_IfHCOutOctets =
8212             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8213              (u64) stats->stat_IfHCOutOctets_lo;
8214
8215         sc->stat_IfHCOutBadOctets =
8216             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8217              (u64) stats->stat_IfHCOutBadOctets_lo;
8218
8219         sc->stat_IfHCInUcastPkts =
8220             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8221              (u64) stats->stat_IfHCInUcastPkts_lo;
8222
8223         sc->stat_IfHCInMulticastPkts =
8224             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8225              (u64) stats->stat_IfHCInMulticastPkts_lo;
8226
8227         sc->stat_IfHCInBroadcastPkts =
8228             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8229              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8230
8231         sc->stat_IfHCOutUcastPkts =
8232             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8233              (u64) stats->stat_IfHCOutUcastPkts_lo;
8234
8235         sc->stat_IfHCOutMulticastPkts =
8236             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8237              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8238
8239         sc->stat_IfHCOutBroadcastPkts =
8240             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8241              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8242
8243         /* ToDo: Preserve counters beyond 32 bits? */
8244         /* ToDo: Read the statistics from auto-clear regs? */
8245
8246         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8247             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8248
8249         sc->stat_Dot3StatsCarrierSenseErrors =
8250             stats->stat_Dot3StatsCarrierSenseErrors;
8251
8252         sc->stat_Dot3StatsFCSErrors =
8253             stats->stat_Dot3StatsFCSErrors;
8254
8255         sc->stat_Dot3StatsAlignmentErrors =
8256             stats->stat_Dot3StatsAlignmentErrors;
8257
8258         sc->stat_Dot3StatsSingleCollisionFrames =
8259             stats->stat_Dot3StatsSingleCollisionFrames;
8260
8261         sc->stat_Dot3StatsMultipleCollisionFrames =
8262             stats->stat_Dot3StatsMultipleCollisionFrames;
8263
8264         sc->stat_Dot3StatsDeferredTransmissions =
8265             stats->stat_Dot3StatsDeferredTransmissions;
8266
8267         sc->stat_Dot3StatsExcessiveCollisions =
8268             stats->stat_Dot3StatsExcessiveCollisions;
8269
8270         sc->stat_Dot3StatsLateCollisions =
8271             stats->stat_Dot3StatsLateCollisions;
8272
8273         sc->stat_EtherStatsCollisions =
8274             stats->stat_EtherStatsCollisions;
8275
8276         sc->stat_EtherStatsFragments =
8277             stats->stat_EtherStatsFragments;
8278
8279         sc->stat_EtherStatsJabbers =
8280             stats->stat_EtherStatsJabbers;
8281
8282         sc->stat_EtherStatsUndersizePkts =
8283             stats->stat_EtherStatsUndersizePkts;
8284
8285         sc->stat_EtherStatsOversizePkts =
8286              stats->stat_EtherStatsOversizePkts;
8287
8288         sc->stat_EtherStatsPktsRx64Octets =
8289             stats->stat_EtherStatsPktsRx64Octets;
8290
8291         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8292             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8293
8294         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8295             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8296
8297         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8298             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8299
8300         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8301             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8302
8303         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8304             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8305
8306         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8307             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8308
8309         sc->stat_EtherStatsPktsTx64Octets =
8310             stats->stat_EtherStatsPktsTx64Octets;
8311
8312         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8313             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8314
8315         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8316             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8317
8318         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8319             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8320
8321         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8322             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8323
8324         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8325             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8326
8327         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8328             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8329
8330         sc->stat_XonPauseFramesReceived =
8331             stats->stat_XonPauseFramesReceived;
8332
8333         sc->stat_XoffPauseFramesReceived =
8334             stats->stat_XoffPauseFramesReceived;
8335
8336         sc->stat_OutXonSent =
8337             stats->stat_OutXonSent;
8338
8339         sc->stat_OutXoffSent =
8340             stats->stat_OutXoffSent;
8341
8342         sc->stat_FlowControlDone =
8343             stats->stat_FlowControlDone;
8344
8345         sc->stat_MacControlFramesReceived =
8346             stats->stat_MacControlFramesReceived;
8347
8348         sc->stat_XoffStateEntered =
8349             stats->stat_XoffStateEntered;
8350
8351         sc->stat_IfInFramesL2FilterDiscards =
8352             stats->stat_IfInFramesL2FilterDiscards;
8353
8354         sc->stat_IfInRuleCheckerDiscards =
8355             stats->stat_IfInRuleCheckerDiscards;
8356
8357         sc->stat_IfInFTQDiscards =
8358             stats->stat_IfInFTQDiscards;
8359
8360         sc->stat_IfInMBUFDiscards =
8361             stats->stat_IfInMBUFDiscards;
8362
8363         sc->stat_IfInRuleCheckerP4Hit =
8364             stats->stat_IfInRuleCheckerP4Hit;
8365
8366         sc->stat_CatchupInRuleCheckerDiscards =
8367             stats->stat_CatchupInRuleCheckerDiscards;
8368
8369         sc->stat_CatchupInFTQDiscards =
8370             stats->stat_CatchupInFTQDiscards;
8371
8372         sc->stat_CatchupInMBUFDiscards =
8373             stats->stat_CatchupInMBUFDiscards;
8374
8375         sc->stat_CatchupInRuleCheckerP4Hit =
8376             stats->stat_CatchupInRuleCheckerP4Hit;
8377
8378         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8379
8380         /*
8381          * Update the interface statistics from the
8382          * hardware statistics.
8383          */
8384         ifp->if_collisions =
8385             (u_long) sc->stat_EtherStatsCollisions;
8386
8387         /* ToDo: This method loses soft errors. */
8388         ifp->if_ierrors =
8389             (u_long) sc->stat_EtherStatsUndersizePkts +
8390             (u_long) sc->stat_EtherStatsOversizePkts +
8391             (u_long) sc->stat_IfInMBUFDiscards +
8392             (u_long) sc->stat_Dot3StatsAlignmentErrors +
8393             (u_long) sc->stat_Dot3StatsFCSErrors +
8394             (u_long) sc->stat_IfInRuleCheckerDiscards +
8395             (u_long) sc->stat_IfInFTQDiscards +
8396             (u_long) sc->com_no_buffers;
8397
8398         /* ToDo: This method loses soft errors. */
8399         ifp->if_oerrors =
8400             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8401             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8402             (u_long) sc->stat_Dot3StatsLateCollisions;
8403
8404         /* ToDo: Add additional statistics? */
8405
8406         DBEXIT(BCE_EXTREME_MISC);
8407 }
8408
8409
8410 /****************************************************************************/
8411 /* Periodic function to notify the bootcode that the driver is still        */
8412 /* present.                                                                 */
8413 /*                                                                          */
8414 /* Returns:                                                                 */
8415 /*   Nothing.                                                               */
8416 /****************************************************************************/
8417 static void
8418 bce_pulse(void *xsc)
8419 {
8420         struct bce_softc *sc = xsc;
8421         u32 msg;
8422
8423         DBENTER(BCE_EXTREME_MISC);
8424
8425         BCE_LOCK_ASSERT(sc);
8426
8427         /* Tell the firmware that the driver is still running. */
8428         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8429         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8430
8431         /* Update the bootcode condition. */
8432         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8433
8434         /* Report whether the bootcode still knows the driver is running. */
8435         if (bce_verbose || bootverbose) {
8436                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8437                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8438                                 sc->bce_drv_cardiac_arrest = TRUE;
8439                                 BCE_PRINTF("%s(): Warning: bootcode "
8440                                     "thinks driver is absent! "
8441                                     "(bc_state = 0x%08X)\n",
8442                                     __FUNCTION__, sc->bc_state);
8443                         }
8444                 } else {
8445                         /*
8446                          * Not supported by all bootcode versions.
8447                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8448                          * will require the driver to reset the
8449                          * controller to clear this condition.
8450                          */
8451                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8452                                 sc->bce_drv_cardiac_arrest = FALSE;
8453                                 BCE_PRINTF("%s(): Bootcode found the "
8454                                     "driver pulse! (bc_state = 0x%08X)\n",
8455                                     __FUNCTION__, sc->bc_state);
8456                         }
8457                 }
8458         }
8459
8460
8461         /* Schedule the next pulse. */
8462         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8463
8464         DBEXIT(BCE_EXTREME_MISC);
8465 }
8466
8467
8468 /****************************************************************************/
8469 /* Periodic function to perform maintenance tasks.                          */
8470 /*                                                                          */
8471 /* Returns:                                                                 */
8472 /*   Nothing.                                                               */
8473 /****************************************************************************/
8474 static void
8475 bce_tick(void *xsc)
8476 {
8477         struct bce_softc *sc = xsc;
8478         struct mii_data *mii;
8479         struct ifnet *ifp;
8480         struct ifmediareq ifmr;
8481
8482         ifp = sc->bce_ifp;
8483
8484         DBENTER(BCE_EXTREME_MISC);
8485
8486         BCE_LOCK_ASSERT(sc);
8487
8488         /* Schedule the next tick. */
8489         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8490
8491         /* Update the statistics from the hardware statistics block. */
8492         bce_stats_update(sc);
8493
8494         /*
8495          * ToDo: This is a safety measure.  Need to re-evaluate
8496          * high level processing logic and eliminate this code.
8497          */
8498         /* Top off the receive and page chains. */
8499         if (bce_hdr_split == TRUE)
8500                 bce_fill_pg_chain(sc);
8501         bce_fill_rx_chain(sc);
8502
8503         /* Check that chip hasn't hung. */
8504         bce_watchdog(sc);
8505
8506         /* If link is up already up then we're done. */
8507         if (sc->bce_link_up == TRUE)
8508                 goto bce_tick_exit;
8509
8510         /* Link is down.  Check what the PHY's doing. */
8511         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8512                 bzero(&ifmr, sizeof(ifmr));
8513                 bce_ifmedia_sts_rphy(sc, &ifmr);
8514                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8515                     (IFM_ACTIVE | IFM_AVALID)) {
8516                         sc->bce_link_up = TRUE;
8517                         bce_miibus_statchg(sc->bce_dev);
8518                 }
8519         } else {
8520                 mii = device_get_softc(sc->bce_miibus);
8521                 mii_tick(mii);
8522                 /* Check if the link has come up. */
8523                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8524                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8525                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8526                             __FUNCTION__);
8527                         sc->bce_link_up = TRUE;
8528                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8529                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8530                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8531                             (bce_verbose || bootverbose))
8532                                 BCE_PRINTF("Gigabit link up!\n");
8533                 }
8534
8535         }
8536         if (sc->bce_link_up == TRUE) {
8537                 /* Now that link is up, handle any outstanding TX traffic. */
8538                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8539                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8540                             "pending TX traffic.\n", __FUNCTION__);
8541                         bce_start_locked(ifp);
8542                 }
8543         }
8544
8545 bce_tick_exit:
8546         DBEXIT(BCE_EXTREME_MISC);
8547         return;
8548 }
8549
8550 static void
8551 bce_fw_cap_init(struct bce_softc *sc)
8552 {
8553         u32 ack, cap, link;
8554
8555         ack = 0;
8556         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8557         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8558             BCE_FW_CAP_SIGNATURE_MAGIC)
8559                 return;
8560         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8561             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8562                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8563                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8564         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8565             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8566                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8567                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8568                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8569                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8570                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8571                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8572                     BCE_FW_CAP_REMOTE_PHY_CAP;
8573         }
8574
8575         if (ack != 0)
8576                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8577 }
8578
8579
8580 #ifdef BCE_DEBUG
8581 /****************************************************************************/
8582 /* Allows the driver state to be dumped through the sysctl interface.       */
8583 /*                                                                          */
8584 /* Returns:                                                                 */
8585 /*   0 for success, positive value for failure.                             */
8586 /****************************************************************************/
8587 static int
8588 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8589 {
8590         int error;
8591         int result;
8592         struct bce_softc *sc;
8593
8594         result = -1;
8595         error = sysctl_handle_int(oidp, &result, 0, req);
8596
8597         if (error || !req->newptr)
8598                 return (error);
8599
8600         if (result == 1) {
8601                 sc = (struct bce_softc *)arg1;
8602                 bce_dump_driver_state(sc);
8603         }
8604
8605         return error;
8606 }
8607
8608
8609 /****************************************************************************/
8610 /* Allows the hardware state to be dumped through the sysctl interface.     */
8611 /*                                                                          */
8612 /* Returns:                                                                 */
8613 /*   0 for success, positive value for failure.                             */
8614 /****************************************************************************/
8615 static int
8616 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8617 {
8618         int error;
8619         int result;
8620         struct bce_softc *sc;
8621
8622         result = -1;
8623         error = sysctl_handle_int(oidp, &result, 0, req);
8624
8625         if (error || !req->newptr)
8626                 return (error);
8627
8628         if (result == 1) {
8629                 sc = (struct bce_softc *)arg1;
8630                 bce_dump_hw_state(sc);
8631         }
8632
8633         return error;
8634 }
8635
8636
8637 /****************************************************************************/
8638 /* Allows the status block to be dumped through the sysctl interface.       */
8639 /*                                                                          */
8640 /* Returns:                                                                 */
8641 /*   0 for success, positive value for failure.                             */
8642 /****************************************************************************/
8643 static int
8644 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8645 {
8646         int error;
8647         int result;
8648         struct bce_softc *sc;
8649
8650         result = -1;
8651         error = sysctl_handle_int(oidp, &result, 0, req);
8652
8653         if (error || !req->newptr)
8654                 return (error);
8655
8656         if (result == 1) {
8657                 sc = (struct bce_softc *)arg1;
8658                 bce_dump_status_block(sc);
8659         }
8660
8661         return error;
8662 }
8663
8664
8665 /****************************************************************************/
8666 /* Allows the stats block to be dumped through the sysctl interface.        */
8667 /*                                                                          */
8668 /* Returns:                                                                 */
8669 /*   0 for success, positive value for failure.                             */
8670 /****************************************************************************/
8671 static int
8672 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8673 {
8674         int error;
8675         int result;
8676         struct bce_softc *sc;
8677
8678         result = -1;
8679         error = sysctl_handle_int(oidp, &result, 0, req);
8680
8681         if (error || !req->newptr)
8682                 return (error);
8683
8684         if (result == 1) {
8685                 sc = (struct bce_softc *)arg1;
8686                 bce_dump_stats_block(sc);
8687         }
8688
8689         return error;
8690 }
8691
8692
8693 /****************************************************************************/
8694 /* Allows the stat counters to be cleared without unloading/reloading the   */
8695 /* driver.                                                                  */
8696 /*                                                                          */
8697 /* Returns:                                                                 */
8698 /*   0 for success, positive value for failure.                             */
8699 /****************************************************************************/
8700 static int
8701 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8702 {
8703         int error;
8704         int result;
8705         struct bce_softc *sc;
8706
8707         result = -1;
8708         error = sysctl_handle_int(oidp, &result, 0, req);
8709
8710         if (error || !req->newptr)
8711                 return (error);
8712
8713         if (result == 1) {
8714                 sc = (struct bce_softc *)arg1;
8715                 struct statistics_block *stats;
8716
8717                 stats = (struct statistics_block *) sc->stats_block;
8718                 bzero(stats, sizeof(struct statistics_block));
8719
8720                 /* Clear the internal H/W statistics counters. */
8721                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8722
8723                 /* Reset the driver maintained statistics. */
8724                 sc->interrupts_rx =
8725                     sc->interrupts_tx = 0;
8726                 sc->tso_frames_requested =
8727                     sc->tso_frames_completed =
8728                     sc->tso_frames_failed = 0;
8729                 sc->rx_empty_count =
8730                     sc->tx_full_count = 0;
8731                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8732                 sc->tx_hi_watermark = 0;
8733                 sc->l2fhdr_error_count =
8734                     sc->l2fhdr_error_sim_count = 0;
8735                 sc->mbuf_alloc_failed_count =
8736                     sc->mbuf_alloc_failed_sim_count = 0;
8737                 sc->dma_map_addr_rx_failed_count =
8738                     sc->dma_map_addr_tx_failed_count = 0;
8739                 sc->mbuf_frag_count = 0;
8740                 sc->csum_offload_tcp_udp =
8741                     sc->csum_offload_ip = 0;
8742                 sc->vlan_tagged_frames_rcvd =
8743                     sc->vlan_tagged_frames_stripped = 0;
8744                 sc->split_header_frames_rcvd =
8745                     sc->split_header_tcp_frames_rcvd = 0;
8746
8747                 /* Clear firmware maintained statistics. */
8748                 REG_WR_IND(sc, 0x120084, 0);
8749         }
8750
8751         return error;
8752 }
8753
8754
8755 /****************************************************************************/
8756 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8757 /* interface.                                                               */
8758 /*                                                                          */
8759 /* Returns:                                                                 */
8760 /*   0 for success, positive value for failure.                             */
8761 /****************************************************************************/
8762 static int
8763 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8764 {
8765         int error;
8766         int result;
8767         struct bce_softc *sc;
8768
8769         result = -1;
8770         error = sysctl_handle_int(oidp, &result, 0, req);
8771
8772         if (error || !req->newptr)
8773                 return (error);
8774
8775         if (result == 1) {
8776                 sc = (struct bce_softc *)arg1;
8777                 bce_dump_shmem_state(sc);
8778         }
8779
8780         return error;
8781 }
8782
8783
8784 /****************************************************************************/
8785 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8786 /*                                                                          */
8787 /* Returns:                                                                 */
8788 /*   0 for success, positive value for failure.                             */
8789 /****************************************************************************/
8790 static int
8791 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8792 {
8793         int error;
8794         int result;
8795         struct bce_softc *sc;
8796
8797         result = -1;
8798         error = sysctl_handle_int(oidp, &result, 0, req);
8799
8800         if (error || !req->newptr)
8801                 return (error);
8802
8803         if (result == 1) {
8804                 sc = (struct bce_softc *)arg1;
8805                 bce_dump_bc_state(sc);
8806         }
8807
8808         return error;
8809 }
8810
8811
8812 /****************************************************************************/
8813 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8814 /*                                                                          */
8815 /* Returns:                                                                 */
8816 /*   0 for success, positive value for failure.                             */
8817 /****************************************************************************/
8818 static int
8819 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8820 {
8821         int error;
8822         int result;
8823         struct bce_softc *sc;
8824
8825         result = -1;
8826         error = sysctl_handle_int(oidp, &result, 0, req);
8827
8828         if (error || !req->newptr)
8829                 return (error);
8830
8831         if (result == 1) {
8832                 sc = (struct bce_softc *)arg1;
8833                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8834         }
8835
8836         return error;
8837 }
8838
8839
8840 /****************************************************************************/
8841 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8842 /*                                                                          */
8843 /* Returns:                                                                 */
8844 /*   0 for success, positive value for failure.                             */
8845 /****************************************************************************/
8846 static int
8847 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8848 {
8849         int error;
8850         int result;
8851         struct bce_softc *sc;
8852
8853         result = -1;
8854         error = sysctl_handle_int(oidp, &result, 0, req);
8855
8856         if (error || !req->newptr)
8857                 return (error);
8858
8859         if (result == 1) {
8860                 sc = (struct bce_softc *)arg1;
8861                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8862         }
8863
8864         return error;
8865 }
8866
8867
8868 /****************************************************************************/
8869 /* Provides a sysctl interface to allow dumping the TX chain.               */
8870 /*                                                                          */
8871 /* Returns:                                                                 */
8872 /*   0 for success, positive value for failure.                             */
8873 /****************************************************************************/
8874 static int
8875 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8876 {
8877         int error;
8878         int result;
8879         struct bce_softc *sc;
8880
8881         result = -1;
8882         error = sysctl_handle_int(oidp, &result, 0, req);
8883
8884         if (error || !req->newptr)
8885                 return (error);
8886
8887         if (result == 1) {
8888                 sc = (struct bce_softc *)arg1;
8889                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8890         }
8891
8892         return error;
8893 }
8894
8895
8896 /****************************************************************************/
8897 /* Provides a sysctl interface to allow dumping the page chain.             */
8898 /*                                                                          */
8899 /* Returns:                                                                 */
8900 /*   0 for success, positive value for failure.                             */
8901 /****************************************************************************/
8902 static int
8903 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8904 {
8905         int error;
8906         int result;
8907         struct bce_softc *sc;
8908
8909         result = -1;
8910         error = sysctl_handle_int(oidp, &result, 0, req);
8911
8912         if (error || !req->newptr)
8913                 return (error);
8914
8915         if (result == 1) {
8916                 sc = (struct bce_softc *)arg1;
8917                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8918         }
8919
8920         return error;
8921 }
8922
8923 /****************************************************************************/
8924 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8925 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8926 /*                                                                          */
8927 /* Returns:                                                                 */
8928 /*   0 for success, positive value for failure.                             */
8929 /****************************************************************************/
8930 static int
8931 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8932 {
8933         struct bce_softc *sc = (struct bce_softc *)arg1;
8934         int error;
8935         u32 result;
8936         u32 val[1];
8937         u8 *data = (u8 *) val;
8938
8939         result = -1;
8940         error = sysctl_handle_int(oidp, &result, 0, req);
8941         if (error || (req->newptr == NULL))
8942                 return (error);
8943
8944         error = bce_nvram_read(sc, result, data, 4);
8945
8946         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8947
8948         return (error);
8949 }
8950
8951
8952 /****************************************************************************/
8953 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8954 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8955 /*                                                                          */
8956 /* Returns:                                                                 */
8957 /*   0 for success, positive value for failure.                             */
8958 /****************************************************************************/
8959 static int
8960 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8961 {
8962         struct bce_softc *sc = (struct bce_softc *)arg1;
8963         int error;
8964         u32 val, result;
8965
8966         result = -1;
8967         error = sysctl_handle_int(oidp, &result, 0, req);
8968         if (error || (req->newptr == NULL))
8969                 return (error);
8970
8971         /* Make sure the register is accessible. */
8972         if (result < 0x8000) {
8973                 val = REG_RD(sc, result);
8974                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8975         } else if (result < 0x0280000) {
8976                 val = REG_RD_IND(sc, result);
8977                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8978         }
8979
8980         return (error);
8981 }
8982
8983
8984 /****************************************************************************/
8985 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8986 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8987 /*                                                                          */
8988 /* Returns:                                                                 */
8989 /*   0 for success, positive value for failure.                             */
8990 /****************************************************************************/
8991 static int
8992 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8993 {
8994         struct bce_softc *sc;
8995         device_t dev;
8996         int error, result;
8997         u16 val;
8998
8999         result = -1;
9000         error = sysctl_handle_int(oidp, &result, 0, req);
9001         if (error || (req->newptr == NULL))
9002                 return (error);
9003
9004         /* Make sure the register is accessible. */
9005         if (result < 0x20) {
9006                 sc = (struct bce_softc *)arg1;
9007                 dev = sc->bce_dev;
9008                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
9009                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9010         }
9011         return (error);
9012 }
9013
9014
9015 /****************************************************************************/
9016 /* Provides a sysctl interface for dumping the nvram contents.              */
9017 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9018 /*                                                                          */
9019 /* Returns:                                                                 */
9020 /*   0 for success, positive errno for failure.                             */
9021 /****************************************************************************/
9022 static int
9023 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9024 {
9025         struct bce_softc *sc = (struct bce_softc *)arg1;
9026         int error, i;
9027
9028         if (sc->nvram_buf == NULL)
9029                 sc->nvram_buf = malloc(sc->bce_flash_size,
9030                                     M_TEMP, M_ZERO | M_WAITOK);
9031
9032         error = 0;
9033         if (req->oldlen == sc->bce_flash_size) {
9034                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9035                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9036         }
9037
9038         if (error == 0)
9039                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9040
9041         return error;
9042 }
9043
9044 #ifdef BCE_NVRAM_WRITE_SUPPORT
9045 /****************************************************************************/
9046 /* Provides a sysctl interface for writing to nvram.                        */
9047 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9048 /*                                                                          */
9049 /* Returns:                                                                 */
9050 /*   0 for success, positive errno for failure.                             */
9051 /****************************************************************************/
9052 static int
9053 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9054 {
9055         struct bce_softc *sc = (struct bce_softc *)arg1;
9056         int error;
9057
9058         if (sc->nvram_buf == NULL)
9059                 sc->nvram_buf = malloc(sc->bce_flash_size,
9060                                     M_TEMP, M_ZERO | M_WAITOK);
9061         else
9062                 bzero(sc->nvram_buf, sc->bce_flash_size);
9063
9064         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9065         if (error == 0)
9066                 return (error);
9067
9068         if (req->newlen == sc->bce_flash_size)
9069                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9070                             sc->bce_flash_size);
9071
9072
9073         return error;
9074 }
9075 #endif
9076
9077
9078 /****************************************************************************/
9079 /* Provides a sysctl interface to allow reading a CID.                      */
9080 /*                                                                          */
9081 /* Returns:                                                                 */
9082 /*   0 for success, positive value for failure.                             */
9083 /****************************************************************************/
9084 static int
9085 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9086 {
9087         struct bce_softc *sc;
9088         int error, result;
9089
9090         result = -1;
9091         error = sysctl_handle_int(oidp, &result, 0, req);
9092         if (error || (req->newptr == NULL))
9093                 return (error);
9094
9095         /* Make sure the register is accessible. */
9096         if (result <= TX_CID) {
9097                 sc = (struct bce_softc *)arg1;
9098                 bce_dump_ctx(sc, result);
9099         }
9100
9101         return (error);
9102 }
9103
9104
9105 /****************************************************************************/
9106 /* Provides a sysctl interface to forcing the driver to dump state and      */
9107 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9108 /*                                                                          */
9109 /* Returns:                                                                 */
9110 /*   0 for success, positive value for failure.                             */
9111 /****************************************************************************/
9112 static int
9113 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9114 {
9115         int error;
9116         int result;
9117         struct bce_softc *sc;
9118
9119         result = -1;
9120         error = sysctl_handle_int(oidp, &result, 0, req);
9121
9122         if (error || !req->newptr)
9123                 return (error);
9124
9125         if (result == 1) {
9126                 sc = (struct bce_softc *)arg1;
9127                 bce_breakpoint(sc);
9128         }
9129
9130         return error;
9131 }
9132 #endif
9133
9134 /****************************************************************************/
9135 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9136 /*                                                                          */
9137 /* Returns:                                                                 */
9138 /*   0 for success, positive value for failure.                             */
9139 /****************************************************************************/
9140 static void
9141 bce_add_sysctls(struct bce_softc *sc)
9142 {
9143         struct sysctl_ctx_list *ctx;
9144         struct sysctl_oid_list *children;
9145
9146         DBENTER(BCE_VERBOSE_MISC);
9147
9148         ctx = device_get_sysctl_ctx(sc->bce_dev);
9149         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9150
9151 #ifdef BCE_DEBUG
9152         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9153             "l2fhdr_error_sim_control",
9154             CTLFLAG_RW, &l2fhdr_error_sim_control,
9155             0, "Debug control to force l2fhdr errors");
9156
9157         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9158             "l2fhdr_error_sim_count",
9159             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9160             0, "Number of simulated l2_fhdr errors");
9161 #endif
9162
9163         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9164             "l2fhdr_error_count",
9165             CTLFLAG_RD, &sc->l2fhdr_error_count,
9166             0, "Number of l2_fhdr errors");
9167
9168 #ifdef BCE_DEBUG
9169         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9170             "mbuf_alloc_failed_sim_control",
9171             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9172             0, "Debug control to force mbuf allocation failures");
9173
9174         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9175             "mbuf_alloc_failed_sim_count",
9176             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9177             0, "Number of simulated mbuf cluster allocation failures");
9178 #endif
9179
9180         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9181             "mbuf_alloc_failed_count",
9182             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9183             0, "Number of mbuf allocation failures");
9184
9185         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9186             "mbuf_frag_count",
9187             CTLFLAG_RD, &sc->mbuf_frag_count,
9188             0, "Number of fragmented mbufs");
9189
9190 #ifdef BCE_DEBUG
9191         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9192             "dma_map_addr_failed_sim_control",
9193             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9194             0, "Debug control to force DMA mapping failures");
9195
9196         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9197         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9198             "dma_map_addr_failed_sim_count",
9199             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9200             0, "Number of simulated DMA mapping failures");
9201
9202 #endif
9203
9204         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9205             "dma_map_addr_rx_failed_count",
9206             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9207             0, "Number of RX DMA mapping failures");
9208
9209         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9210             "dma_map_addr_tx_failed_count",
9211             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9212             0, "Number of TX DMA mapping failures");
9213
9214 #ifdef BCE_DEBUG
9215         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9216             "unexpected_attention_sim_control",
9217             CTLFLAG_RW, &unexpected_attention_sim_control,
9218             0, "Debug control to simulate unexpected attentions");
9219
9220         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9221             "unexpected_attention_sim_count",
9222             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9223             0, "Number of simulated unexpected attentions");
9224 #endif
9225
9226         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9227             "unexpected_attention_count",
9228             CTLFLAG_RW, &sc->unexpected_attention_count,
9229             0, "Number of unexpected attentions");
9230
9231 #ifdef BCE_DEBUG
9232         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9233             "debug_bootcode_running_failure",
9234             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9235             0, "Debug control to force bootcode running failures");
9236
9237         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9238             "rx_low_watermark",
9239             CTLFLAG_RD, &sc->rx_low_watermark,
9240             0, "Lowest level of free rx_bd's");
9241
9242         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9243             "rx_empty_count",
9244             CTLFLAG_RD, &sc->rx_empty_count,
9245             "Number of times the RX chain was empty");
9246
9247         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9248             "tx_hi_watermark",
9249             CTLFLAG_RD, &sc->tx_hi_watermark,
9250             0, "Highest level of used tx_bd's");
9251
9252         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9253             "tx_full_count",
9254             CTLFLAG_RD, &sc->tx_full_count,
9255             "Number of times the TX chain was full");
9256
9257         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9258             "tso_frames_requested",
9259             CTLFLAG_RD, &sc->tso_frames_requested,
9260             "Number of TSO frames requested");
9261
9262         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9263             "tso_frames_completed",
9264             CTLFLAG_RD, &sc->tso_frames_completed,
9265             "Number of TSO frames completed");
9266
9267         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9268             "tso_frames_failed",
9269             CTLFLAG_RD, &sc->tso_frames_failed,
9270             "Number of TSO frames failed");
9271
9272         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9273             "csum_offload_ip",
9274             CTLFLAG_RD, &sc->csum_offload_ip,
9275             "Number of IP checksum offload frames");
9276
9277         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9278             "csum_offload_tcp_udp",
9279             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9280             "Number of TCP/UDP checksum offload frames");
9281
9282         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9283             "vlan_tagged_frames_rcvd",
9284             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9285             "Number of VLAN tagged frames received");
9286
9287         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9288             "vlan_tagged_frames_stripped",
9289             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9290             "Number of VLAN tagged frames stripped");
9291
9292         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9293             "interrupts_rx",
9294             CTLFLAG_RD, &sc->interrupts_rx,
9295             "Number of RX interrupts");
9296
9297         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9298             "interrupts_tx",
9299             CTLFLAG_RD, &sc->interrupts_tx,
9300             "Number of TX interrupts");
9301
9302         if (bce_hdr_split == TRUE) {
9303                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9304                     "split_header_frames_rcvd",
9305                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9306                     "Number of split header frames received");
9307
9308                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9309                     "split_header_tcp_frames_rcvd",
9310                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9311                     "Number of split header TCP frames received");
9312         }
9313
9314         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9315             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9316             (void *)sc, 0,
9317             bce_sysctl_nvram_dump, "S", "");
9318
9319 #ifdef BCE_NVRAM_WRITE_SUPPORT
9320         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9321             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9322             (void *)sc, 0,
9323             bce_sysctl_nvram_write, "S", "");
9324 #endif
9325 #endif /* BCE_DEBUG */
9326
9327         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9328             "stat_IfHcInOctets",
9329             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9330             "Bytes received");
9331
9332         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9333             "stat_IfHCInBadOctets",
9334             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9335             "Bad bytes received");
9336
9337         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9338             "stat_IfHCOutOctets",
9339             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9340             "Bytes sent");
9341
9342         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9343             "stat_IfHCOutBadOctets",
9344             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9345             "Bad bytes sent");
9346
9347         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9348             "stat_IfHCInUcastPkts",
9349             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9350             "Unicast packets received");
9351
9352         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9353             "stat_IfHCInMulticastPkts",
9354             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9355             "Multicast packets received");
9356
9357         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9358             "stat_IfHCInBroadcastPkts",
9359             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9360             "Broadcast packets received");
9361
9362         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9363             "stat_IfHCOutUcastPkts",
9364             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9365             "Unicast packets sent");
9366
9367         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9368             "stat_IfHCOutMulticastPkts",
9369             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9370             "Multicast packets sent");
9371
9372         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9373             "stat_IfHCOutBroadcastPkts",
9374             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9375             "Broadcast packets sent");
9376
9377         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9378             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9379             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9380             0, "Internal MAC transmit errors");
9381
9382         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9383             "stat_Dot3StatsCarrierSenseErrors",
9384             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9385             0, "Carrier sense errors");
9386
9387         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9388             "stat_Dot3StatsFCSErrors",
9389             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9390             0, "Frame check sequence errors");
9391
9392         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9393             "stat_Dot3StatsAlignmentErrors",
9394             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9395             0, "Alignment errors");
9396
9397         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9398             "stat_Dot3StatsSingleCollisionFrames",
9399             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9400             0, "Single Collision Frames");
9401
9402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9403             "stat_Dot3StatsMultipleCollisionFrames",
9404             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9405             0, "Multiple Collision Frames");
9406
9407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9408             "stat_Dot3StatsDeferredTransmissions",
9409             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9410             0, "Deferred Transmissions");
9411
9412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9413             "stat_Dot3StatsExcessiveCollisions",
9414             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9415             0, "Excessive Collisions");
9416
9417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9418             "stat_Dot3StatsLateCollisions",
9419             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9420             0, "Late Collisions");
9421
9422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9423             "stat_EtherStatsCollisions",
9424             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9425             0, "Collisions");
9426
9427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9428             "stat_EtherStatsFragments",
9429             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9430             0, "Fragments");
9431
9432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9433             "stat_EtherStatsJabbers",
9434             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9435             0, "Jabbers");
9436
9437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9438             "stat_EtherStatsUndersizePkts",
9439             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9440             0, "Undersize packets");
9441
9442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9443             "stat_EtherStatsOversizePkts",
9444             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9445             0, "stat_EtherStatsOversizePkts");
9446
9447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9448             "stat_EtherStatsPktsRx64Octets",
9449             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9450             0, "Bytes received in 64 byte packets");
9451
9452         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9453             "stat_EtherStatsPktsRx65Octetsto127Octets",
9454             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9455             0, "Bytes received in 65 to 127 byte packets");
9456
9457         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9458             "stat_EtherStatsPktsRx128Octetsto255Octets",
9459             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9460             0, "Bytes received in 128 to 255 byte packets");
9461
9462         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9463             "stat_EtherStatsPktsRx256Octetsto511Octets",
9464             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9465             0, "Bytes received in 256 to 511 byte packets");
9466
9467         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9468             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9469             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9470             0, "Bytes received in 512 to 1023 byte packets");
9471
9472         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9473             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9474             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9475             0, "Bytes received in 1024 t0 1522 byte packets");
9476
9477         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9478             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9479             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9480             0, "Bytes received in 1523 to 9022 byte packets");
9481
9482         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9483             "stat_EtherStatsPktsTx64Octets",
9484             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9485             0, "Bytes sent in 64 byte packets");
9486
9487         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9488             "stat_EtherStatsPktsTx65Octetsto127Octets",
9489             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9490             0, "Bytes sent in 65 to 127 byte packets");
9491
9492         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9493             "stat_EtherStatsPktsTx128Octetsto255Octets",
9494             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9495             0, "Bytes sent in 128 to 255 byte packets");
9496
9497         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9498             "stat_EtherStatsPktsTx256Octetsto511Octets",
9499             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9500             0, "Bytes sent in 256 to 511 byte packets");
9501
9502         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9503             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9504             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9505             0, "Bytes sent in 512 to 1023 byte packets");
9506
9507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9508             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9509             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9510             0, "Bytes sent in 1024 to 1522 byte packets");
9511
9512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9513             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9514             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9515             0, "Bytes sent in 1523 to 9022 byte packets");
9516
9517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9518             "stat_XonPauseFramesReceived",
9519             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9520             0, "XON pause frames receved");
9521
9522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9523             "stat_XoffPauseFramesReceived",
9524             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9525             0, "XOFF pause frames received");
9526
9527         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9528             "stat_OutXonSent",
9529             CTLFLAG_RD, &sc->stat_OutXonSent,
9530             0, "XON pause frames sent");
9531
9532         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9533             "stat_OutXoffSent",
9534             CTLFLAG_RD, &sc->stat_OutXoffSent,
9535             0, "XOFF pause frames sent");
9536
9537         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9538             "stat_FlowControlDone",
9539             CTLFLAG_RD, &sc->stat_FlowControlDone,
9540             0, "Flow control done");
9541
9542         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9543             "stat_MacControlFramesReceived",
9544             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9545             0, "MAC control frames received");
9546
9547         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9548             "stat_XoffStateEntered",
9549             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9550             0, "XOFF state entered");
9551
9552         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9553             "stat_IfInFramesL2FilterDiscards",
9554             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9555             0, "Received L2 packets discarded");
9556
9557         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9558             "stat_IfInRuleCheckerDiscards",
9559             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9560             0, "Received packets discarded by rule");
9561
9562         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9563             "stat_IfInFTQDiscards",
9564             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9565             0, "Received packet FTQ discards");
9566
9567         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9568             "stat_IfInMBUFDiscards",
9569             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9570             0, "Received packets discarded due to lack "
9571             "of controller buffer memory");
9572
9573         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9574             "stat_IfInRuleCheckerP4Hit",
9575             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9576             0, "Received packets rule checker hits");
9577
9578         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9579             "stat_CatchupInRuleCheckerDiscards",
9580             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9581             0, "Received packets discarded in Catchup path");
9582
9583         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9584             "stat_CatchupInFTQDiscards",
9585             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9586             0, "Received packets discarded in FTQ in Catchup path");
9587
9588         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9589             "stat_CatchupInMBUFDiscards",
9590             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9591             0, "Received packets discarded in controller "
9592             "buffer memory in Catchup path");
9593
9594         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9595             "stat_CatchupInRuleCheckerP4Hit",
9596             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9597             0, "Received packets rule checker hits in Catchup path");
9598
9599         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9600             "com_no_buffers",
9601             CTLFLAG_RD, &sc->com_no_buffers,
9602             0, "Valid packets received but no RX buffers available");
9603
9604 #ifdef BCE_DEBUG
9605         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9606             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9607             (void *)sc, 0,
9608             bce_sysctl_driver_state, "I", "Drive state information");
9609
9610         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9611             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9612             (void *)sc, 0,
9613             bce_sysctl_hw_state, "I", "Hardware state information");
9614
9615         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9616             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9617             (void *)sc, 0,
9618             bce_sysctl_status_block, "I", "Dump status block");
9619
9620         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9621             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9622             (void *)sc, 0,
9623             bce_sysctl_stats_block, "I", "Dump statistics block");
9624
9625         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9626             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9627             (void *)sc, 0,
9628             bce_sysctl_stats_clear, "I", "Clear statistics block");
9629
9630         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9631             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9632             (void *)sc, 0,
9633             bce_sysctl_shmem_state, "I", "Shared memory state information");
9634
9635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9636             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9637             (void *)sc, 0,
9638             bce_sysctl_bc_state, "I", "Bootcode state information");
9639
9640         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9641             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9642             (void *)sc, 0,
9643             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9644
9645         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9646             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9647             (void *)sc, 0,
9648             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9649
9650         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9651             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9652             (void *)sc, 0,
9653             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9654
9655         if (bce_hdr_split == TRUE) {
9656                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9657                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9658                     (void *)sc, 0,
9659                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9660         }
9661
9662         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9663             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9664             (void *)sc, 0,
9665             bce_sysctl_dump_ctx, "I", "Dump context memory");
9666
9667         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9668             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9669             (void *)sc, 0,
9670             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9671
9672         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9673             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9674             (void *)sc, 0,
9675             bce_sysctl_reg_read, "I", "Register read");
9676
9677         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9678             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9679             (void *)sc, 0,
9680             bce_sysctl_nvram_read, "I", "NVRAM read");
9681
9682         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9683             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9684             (void *)sc, 0,
9685             bce_sysctl_phy_read, "I", "PHY register read");
9686
9687 #endif
9688
9689         DBEXIT(BCE_VERBOSE_MISC);
9690 }
9691
9692
9693 /****************************************************************************/
9694 /* BCE Debug Routines                                                       */
9695 /****************************************************************************/
9696 #ifdef BCE_DEBUG
9697
9698 /****************************************************************************/
9699 /* Freezes the controller to allow for a cohesive state dump.               */
9700 /*                                                                          */
9701 /* Returns:                                                                 */
9702 /*   Nothing.                                                               */
9703 /****************************************************************************/
9704 static __attribute__ ((noinline)) void
9705 bce_freeze_controller(struct bce_softc *sc)
9706 {
9707         u32 val;
9708         val = REG_RD(sc, BCE_MISC_COMMAND);
9709         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9710         REG_WR(sc, BCE_MISC_COMMAND, val);
9711 }
9712
9713
9714 /****************************************************************************/
9715 /* Unfreezes the controller after a freeze operation.  This may not always  */
9716 /* work and the controller will require a reset!                            */
9717 /*                                                                          */
9718 /* Returns:                                                                 */
9719 /*   Nothing.                                                               */
9720 /****************************************************************************/
9721 static __attribute__ ((noinline)) void
9722 bce_unfreeze_controller(struct bce_softc *sc)
9723 {
9724         u32 val;
9725         val = REG_RD(sc, BCE_MISC_COMMAND);
9726         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9727         REG_WR(sc, BCE_MISC_COMMAND, val);
9728 }
9729
9730
9731 /****************************************************************************/
9732 /* Prints out Ethernet frame information from an mbuf.                      */
9733 /*                                                                          */
9734 /* Partially decode an Ethernet frame to look at some important headers.    */
9735 /*                                                                          */
9736 /* Returns:                                                                 */
9737 /*   Nothing.                                                               */
9738 /****************************************************************************/
9739 static __attribute__ ((noinline)) void
9740 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9741 {
9742         struct ether_vlan_header *eh;
9743         u16 etype;
9744         int ehlen;
9745         struct ip *ip;
9746         struct tcphdr *th;
9747         struct udphdr *uh;
9748         struct arphdr *ah;
9749
9750         BCE_PRINTF(
9751             "-----------------------------"
9752             " Frame Decode "
9753             "-----------------------------\n");
9754
9755         eh = mtod(m, struct ether_vlan_header *);
9756
9757         /* Handle VLAN encapsulation if present. */
9758         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9759                 etype = ntohs(eh->evl_proto);
9760                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9761         } else {
9762                 etype = ntohs(eh->evl_encap_proto);
9763                 ehlen = ETHER_HDR_LEN;
9764         }
9765
9766         /* ToDo: Add VLAN output. */
9767         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9768             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9769
9770         switch (etype) {
9771         case ETHERTYPE_IP:
9772                 ip = (struct ip *)(m->m_data + ehlen);
9773                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9774                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9775                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9776                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9777
9778                 switch (ip->ip_p) {
9779                 case IPPROTO_TCP:
9780                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9781                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9782                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9783                             ntohs(th->th_dport), ntohs(th->th_sport),
9784                             (th->th_off << 2), th->th_flags,
9785                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9786                             "\02SYN\01FIN", ntohs(th->th_sum));
9787                         break;
9788                 case IPPROTO_UDP:
9789                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9790                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9791                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9792                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9793                             ntohs(uh->uh_sum));
9794                         break;
9795                 case IPPROTO_ICMP:
9796                         BCE_PRINTF("icmp:\n");
9797                         break;
9798                 default:
9799                         BCE_PRINTF("----: Other IP protocol.\n");
9800                         }
9801                 break;
9802         case ETHERTYPE_IPV6:
9803                 BCE_PRINTF("ipv6: No decode supported.\n");
9804                 break;
9805         case ETHERTYPE_ARP:
9806                 BCE_PRINTF("-arp: ");
9807                 ah = (struct arphdr *) (m->m_data + ehlen);
9808                 switch (ntohs(ah->ar_op)) {
9809                 case ARPOP_REVREQUEST:
9810                         printf("reverse ARP request\n");
9811                         break;
9812                 case ARPOP_REVREPLY:
9813                         printf("reverse ARP reply\n");
9814                         break;
9815                 case ARPOP_REQUEST:
9816                         printf("ARP request\n");
9817                         break;
9818                 case ARPOP_REPLY:
9819                         printf("ARP reply\n");
9820                         break;
9821                 default:
9822                         printf("other ARP operation\n");
9823                 }
9824                 break;
9825         default:
9826                 BCE_PRINTF("----: Other protocol.\n");
9827         }
9828
9829         BCE_PRINTF(
9830                 "-----------------------------"
9831                 "--------------"
9832                 "-----------------------------\n");
9833 }
9834
9835
9836 /****************************************************************************/
9837 /* Prints out information about an mbuf.                                    */
9838 /*                                                                          */
9839 /* Returns:                                                                 */
9840 /*   Nothing.                                                               */
9841 /****************************************************************************/
9842 static __attribute__ ((noinline)) void
9843 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9844 {
9845         struct mbuf *mp = m;
9846
9847         if (m == NULL) {
9848                 BCE_PRINTF("mbuf: null pointer\n");
9849                 return;
9850         }
9851
9852         while (mp) {
9853                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9854                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9855                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9856
9857                 if (mp->m_flags & M_PKTHDR) {
9858                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9859                             "csum_flags = %b\n", mp->m_pkthdr.len,
9860                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9861                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9862                             "\22M_PROMISC\23M_NOFREE",
9863                             mp->m_pkthdr.csum_flags,
9864                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9865                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9866                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9867                             "\14CSUM_PSEUDO_HDR");
9868                 }
9869
9870                 if (mp->m_flags & M_EXT) {
9871                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9872                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9873                         switch (mp->m_ext.ext_type) {
9874                         case EXT_CLUSTER:
9875                                 printf("EXT_CLUSTER\n"); break;
9876                         case EXT_SFBUF:
9877                                 printf("EXT_SFBUF\n"); break;
9878                         case EXT_JUMBO9:
9879                                 printf("EXT_JUMBO9\n"); break;
9880                         case EXT_JUMBO16:
9881                                 printf("EXT_JUMBO16\n"); break;
9882                         case EXT_PACKET:
9883                                 printf("EXT_PACKET\n"); break;
9884                         case EXT_MBUF:
9885                                 printf("EXT_MBUF\n"); break;
9886                         case EXT_NET_DRV:
9887                                 printf("EXT_NET_DRV\n"); break;
9888                         case EXT_MOD_TYPE:
9889                                 printf("EXT_MDD_TYPE\n"); break;
9890                         case EXT_DISPOSABLE:
9891                                 printf("EXT_DISPOSABLE\n"); break;
9892                         case EXT_EXTREF:
9893                                 printf("EXT_EXTREF\n"); break;
9894                         default:
9895                                 printf("UNKNOWN\n");
9896                         }
9897                 }
9898
9899                 mp = mp->m_next;
9900         }
9901 }
9902
9903
9904 /****************************************************************************/
9905 /* Prints out the mbufs in the TX mbuf chain.                               */
9906 /*                                                                          */
9907 /* Returns:                                                                 */
9908 /*   Nothing.                                                               */
9909 /****************************************************************************/
9910 static __attribute__ ((noinline)) void
9911 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9912 {
9913         struct mbuf *m;
9914
9915         BCE_PRINTF(
9916                 "----------------------------"
9917                 "  tx mbuf data  "
9918                 "----------------------------\n");
9919
9920         for (int i = 0; i < count; i++) {
9921                 m = sc->tx_mbuf_ptr[chain_prod];
9922                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9923                 bce_dump_mbuf(sc, m);
9924                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9925         }
9926
9927         BCE_PRINTF(
9928                 "----------------------------"
9929                 "----------------"
9930                 "----------------------------\n");
9931 }
9932
9933
9934 /****************************************************************************/
9935 /* Prints out the mbufs in the RX mbuf chain.                               */
9936 /*                                                                          */
9937 /* Returns:                                                                 */
9938 /*   Nothing.                                                               */
9939 /****************************************************************************/
9940 static __attribute__ ((noinline)) void
9941 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9942 {
9943         struct mbuf *m;
9944
9945         BCE_PRINTF(
9946                 "----------------------------"
9947                 "  rx mbuf data  "
9948                 "----------------------------\n");
9949
9950         for (int i = 0; i < count; i++) {
9951                 m = sc->rx_mbuf_ptr[chain_prod];
9952                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9953                 bce_dump_mbuf(sc, m);
9954                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9955         }
9956
9957
9958         BCE_PRINTF(
9959                 "----------------------------"
9960                 "----------------"
9961                 "----------------------------\n");
9962 }
9963
9964
9965 /****************************************************************************/
9966 /* Prints out the mbufs in the mbuf page chain.                             */
9967 /*                                                                          */
9968 /* Returns:                                                                 */
9969 /*   Nothing.                                                               */
9970 /****************************************************************************/
9971 static __attribute__ ((noinline)) void
9972 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9973 {
9974         struct mbuf *m;
9975
9976         BCE_PRINTF(
9977                 "----------------------------"
9978                 "  pg mbuf data  "
9979                 "----------------------------\n");
9980
9981         for (int i = 0; i < count; i++) {
9982                 m = sc->pg_mbuf_ptr[chain_prod];
9983                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9984                 bce_dump_mbuf(sc, m);
9985                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9986         }
9987
9988
9989         BCE_PRINTF(
9990                 "----------------------------"
9991                 "----------------"
9992                 "----------------------------\n");
9993 }
9994
9995
9996 /****************************************************************************/
9997 /* Prints out a tx_bd structure.                                            */
9998 /*                                                                          */
9999 /* Returns:                                                                 */
10000 /*   Nothing.                                                               */
10001 /****************************************************************************/
10002 static __attribute__ ((noinline)) void
10003 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
10004 {
10005         int i = 0;
10006
10007         if (idx > MAX_TX_BD_ALLOC)
10008                 /* Index out of range. */
10009                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
10010         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
10011                 /* TX Chain page pointer. */
10012                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10013                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
10014                     txbd->tx_bd_haddr_lo);
10015         else {
10016                 /* Normal tx_bd entry. */
10017                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
10018                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
10019                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
10020                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10021                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10022
10023                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10024                         if (i>0)
10025                                 printf("|");
10026                         printf("CONN_FAULT");
10027                         i++;
10028                 }
10029
10030                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10031                         if (i>0)
10032                                 printf("|");
10033                         printf("TCP_UDP_CKSUM");
10034                         i++;
10035                 }
10036
10037                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10038                         if (i>0)
10039                                 printf("|");
10040                         printf("IP_CKSUM");
10041                         i++;
10042                 }
10043
10044                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10045                         if (i>0)
10046                                 printf("|");
10047                         printf("VLAN");
10048                         i++;
10049                 }
10050
10051                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10052                         if (i>0)
10053                                 printf("|");
10054                         printf("COAL_NOW");
10055                         i++;
10056                 }
10057
10058                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10059                         if (i>0)
10060                                 printf("|");
10061                         printf("DONT_GEN_CRC");
10062                         i++;
10063                 }
10064
10065                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10066                         if (i>0)
10067                                 printf("|");
10068                         printf("START");
10069                         i++;
10070                 }
10071
10072                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10073                         if (i>0)
10074                                 printf("|");
10075                         printf("END");
10076                         i++;
10077                 }
10078
10079                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10080                         if (i>0)
10081                                 printf("|");
10082                         printf("LSO");
10083                         i++;
10084                 }
10085
10086                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10087                         if (i>0)
10088                                 printf("|");
10089                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10090                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10091                 }
10092
10093                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10094                         if (i>0)
10095                                 printf("|");
10096                         printf("SW_FLAGS");
10097                         i++;
10098                 }
10099
10100                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10101                         if (i>0)
10102                                 printf("|");
10103                         printf("SNAP)");
10104                 } else {
10105                         printf(")\n");
10106                 }
10107         }
10108 }
10109
10110
10111 /****************************************************************************/
10112 /* Prints out a rx_bd structure.                                            */
10113 /*                                                                          */
10114 /* Returns:                                                                 */
10115 /*   Nothing.                                                               */
10116 /****************************************************************************/
10117 static __attribute__ ((noinline)) void
10118 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10119 {
10120         if (idx > MAX_RX_BD_ALLOC)
10121                 /* Index out of range. */
10122                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10123         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10124                 /* RX Chain page pointer. */
10125                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10126                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10127                     rxbd->rx_bd_haddr_lo);
10128         else
10129                 /* Normal rx_bd entry. */
10130                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10131                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10132                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10133                     rxbd->rx_bd_flags);
10134 }
10135
10136
10137 /****************************************************************************/
10138 /* Prints out a rx_bd structure in the page chain.                          */
10139 /*                                                                          */
10140 /* Returns:                                                                 */
10141 /*   Nothing.                                                               */
10142 /****************************************************************************/
10143 static __attribute__ ((noinline)) void
10144 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10145 {
10146         if (idx > MAX_PG_BD_ALLOC)
10147                 /* Index out of range. */
10148                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10149         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10150                 /* Page Chain page pointer. */
10151                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10152                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10153         else
10154                 /* Normal rx_bd entry. */
10155                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10156                         "flags = 0x%08X\n", idx,
10157                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10158                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10159 }
10160
10161
10162 /****************************************************************************/
10163 /* Prints out a l2_fhdr structure.                                          */
10164 /*                                                                          */
10165 /* Returns:                                                                 */
10166 /*   Nothing.                                                               */
10167 /****************************************************************************/
10168 static __attribute__ ((noinline)) void
10169 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10170 {
10171         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10172                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10173                 "tcp_udp_xsum = 0x%04X\n", idx,
10174                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10175                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10176                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10177 }
10178
10179
10180 /****************************************************************************/
10181 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10182 /*                                                                          */
10183 /* Returns:                                                                 */
10184 /*   Nothing.                                                               */
10185 /****************************************************************************/
10186 static __attribute__ ((noinline)) void
10187 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10188 {
10189         if (cid > TX_CID) {
10190                 BCE_PRINTF(" Unknown CID\n");
10191                 return;
10192         }
10193
10194         BCE_PRINTF(
10195             "----------------------------"
10196             "    CTX Data    "
10197             "----------------------------\n");
10198
10199         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10200
10201         if (cid == RX_CID) {
10202                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10203                    "producer index\n",
10204                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10205                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10206                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10207                     BCE_L2CTX_RX_HOST_BSEQ));
10208                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10209                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10210                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10211                     "descriptor address\n",
10212                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10213                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10214                     "descriptor address\n",
10215                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10216                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10217                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10218                     BCE_L2CTX_RX_NX_BDIDX));
10219                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10220                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10221                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10222                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10223                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10224                     BCE_L2CTX_RX_PG_BUF_SIZE));
10225                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10226                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10227                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10228                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10229                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10230                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10231                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10232                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10233                     BCE_L2CTX_RX_NX_PG_BDIDX));
10234         } else if (cid == TX_CID) {
10235                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10236                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10237                             CTX_RD(sc, GET_CID_ADDR(cid),
10238                             BCE_L2CTX_TX_TYPE_XI));
10239                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10240                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10241                             BCE_L2CTX_TX_CMD_TYPE_XI));
10242                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10243                             "h/w buffer descriptor address\n",
10244                             CTX_RD(sc, GET_CID_ADDR(cid),
10245                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10246                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10247                             "h/w buffer descriptor address\n",
10248                             CTX_RD(sc, GET_CID_ADDR(cid),
10249                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10250                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10251                             "host producer index\n",
10252                             CTX_RD(sc, GET_CID_ADDR(cid),
10253                             BCE_L2CTX_TX_HOST_BIDX_XI));
10254                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10255                             "host byte sequence\n",
10256                             CTX_RD(sc, GET_CID_ADDR(cid),
10257                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10258                 } else {
10259                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10260                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10261                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10262                             CTX_RD(sc, GET_CID_ADDR(cid),
10263                             BCE_L2CTX_TX_CMD_TYPE));
10264                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10265                             "h/w buffer descriptor address\n",
10266                             CTX_RD(sc, GET_CID_ADDR(cid),
10267                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10268                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10269                             "h/w buffer descriptor address\n",
10270                             CTX_RD(sc, GET_CID_ADDR(cid),
10271                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10272                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10273                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10274                             BCE_L2CTX_TX_HOST_BIDX));
10275                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10276                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10277                             BCE_L2CTX_TX_HOST_BSEQ));
10278                 }
10279         }
10280
10281         BCE_PRINTF(
10282            "----------------------------"
10283            "    Raw CTX     "
10284            "----------------------------\n");
10285
10286         for (int i = 0x0; i < 0x300; i += 0x10) {
10287                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10288                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10289                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10290                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10291                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10292         }
10293
10294
10295         BCE_PRINTF(
10296            "----------------------------"
10297            "----------------"
10298            "----------------------------\n");
10299 }
10300
10301
10302 /****************************************************************************/
10303 /* Prints out the FTQ data.                                                 */
10304 /*                                                                          */
10305 /* Returns:                                                                */
10306 /*   Nothing.                                                               */
10307 /****************************************************************************/
10308 static __attribute__ ((noinline)) void
10309 bce_dump_ftqs(struct bce_softc *sc)
10310 {
10311         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10312
10313         BCE_PRINTF(
10314             "----------------------------"
10315             "    FTQ Data    "
10316             "----------------------------\n");
10317
10318         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10319             "Max_Depth  Valid_Cnt \n");
10320         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10321             "---------- ----------\n");
10322
10323         /* Setup the generic statistic counters for the FTQ valid count. */
10324         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10325             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10326             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10327             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10328         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10329
10330         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10331             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10332             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10333             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10334         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10335
10336         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10337             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10338             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10339             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10340         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10341
10342         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10343             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10344             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10345             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10346         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10347
10348         /* Input queue to the Receive Lookup state machine */
10349         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10350         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10351         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10352         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10353         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10354         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10355             cmd, ctl, cur_depth, max_depth, valid_cnt);
10356
10357         /* Input queue to the Receive Processor */
10358         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10359         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10360         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10361         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10362         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10363         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10364             cmd, ctl, cur_depth, max_depth, valid_cnt);
10365
10366         /* Input queue to the Recevie Processor */
10367         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10368         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10369         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10370         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10371         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10372         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10373             cmd, ctl, cur_depth, max_depth, valid_cnt);
10374
10375         /* Input queue to the Receive Virtual to Physical state machine */
10376         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10377         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10378         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10379         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10380         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10381         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10382             cmd, ctl, cur_depth, max_depth, valid_cnt);
10383
10384         /* Input queue to the Recevie Virtual to Physical state machine */
10385         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10386         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10387         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10388         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10389         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10390         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10391             cmd, ctl, cur_depth, max_depth, valid_cnt);
10392
10393         /* Input queue to the Receive Virtual to Physical state machine */
10394         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10395         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10396         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10397         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10398         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10399         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10400             cmd, ctl, cur_depth, max_depth, valid_cnt);
10401
10402         /* Input queue to the Receive DMA state machine */
10403         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10404         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10405         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10406         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10407         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10408         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10409             cmd, ctl, cur_depth, max_depth, valid_cnt);
10410
10411         /* Input queue to the Transmit Scheduler state machine */
10412         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10413         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10414         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10415         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10416         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10417         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10418             cmd, ctl, cur_depth, max_depth, valid_cnt);
10419
10420         /* Input queue to the Transmit Buffer Descriptor state machine */
10421         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10422         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10423         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10424         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10425         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10426         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10427             cmd, ctl, cur_depth, max_depth, valid_cnt);
10428
10429         /* Input queue to the Transmit Processor */
10430         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10431         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10432         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10433         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10434         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10435         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10436             cmd, ctl, cur_depth, max_depth, valid_cnt);
10437
10438         /* Input queue to the Transmit DMA state machine */
10439         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10440         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10441         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10442         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10443         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10444         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10445             cmd, ctl, cur_depth, max_depth, valid_cnt);
10446
10447         /* Input queue to the Transmit Patch-Up Processor */
10448         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10449         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10450         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10451         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10452         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10453         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10454             cmd, ctl, cur_depth, max_depth, valid_cnt);
10455
10456         /* Input queue to the Transmit Assembler state machine */
10457         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10458         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10459         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10460         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10461         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10462         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10463             cmd, ctl, cur_depth, max_depth, valid_cnt);
10464
10465         /* Input queue to the Completion Processor */
10466         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10467         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10468         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10469         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10470         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10471         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10472             cmd, ctl, cur_depth, max_depth, valid_cnt);
10473
10474         /* Input queue to the Completion Processor */
10475         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10476         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10477         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10478         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10479         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10480         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10481             cmd, ctl, cur_depth, max_depth, valid_cnt);
10482
10483         /* Input queue to the Completion Processor */
10484         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10485         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10486         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10487         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10488         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10489         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10490             cmd, ctl, cur_depth, max_depth, valid_cnt);
10491
10492         /* Setup the generic statistic counters for the FTQ valid count. */
10493         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10494             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10495             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10496
10497         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10498                 val = val |
10499                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10500                      24);
10501         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10502
10503         /* Input queue to the Management Control Processor */
10504         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10505         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10506         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10507         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10508         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10509         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10510             cmd, ctl, cur_depth, max_depth, valid_cnt);
10511
10512         /* Input queue to the Command Processor */
10513         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10514         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10515         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10516         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10517         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10518         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10519             cmd, ctl, cur_depth, max_depth, valid_cnt);
10520
10521         /* Input queue to the Completion Scheduler state machine */
10522         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10523         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10524         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10525         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10526         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10527         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10528             cmd, ctl, cur_depth, max_depth, valid_cnt);
10529
10530         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10531                 /* Input queue to the RV2P Command Scheduler */
10532                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10533                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10534                 cur_depth = (ctl & 0xFFC00000) >> 22;
10535                 max_depth = (ctl & 0x003FF000) >> 12;
10536                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10537                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10538                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10539         }
10540
10541         BCE_PRINTF(
10542             "----------------------------"
10543             "----------------"
10544             "----------------------------\n");
10545 }
10546
10547
10548 /****************************************************************************/
10549 /* Prints out the TX chain.                                                 */
10550 /*                                                                          */
10551 /* Returns:                                                                 */
10552 /*   Nothing.                                                               */
10553 /****************************************************************************/
10554 static __attribute__ ((noinline)) void
10555 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10556 {
10557         struct tx_bd *txbd;
10558
10559         /* First some info about the tx_bd chain structure. */
10560         BCE_PRINTF(
10561             "----------------------------"
10562             "  tx_bd  chain  "
10563             "----------------------------\n");
10564
10565         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10566             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10567         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10568             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10569         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10570
10571         BCE_PRINTF(
10572             "----------------------------"
10573             "   tx_bd data   "
10574             "----------------------------\n");
10575
10576         /* Now print out a decoded list of TX buffer descriptors. */
10577         for (int i = 0; i < count; i++) {
10578                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10579                 bce_dump_txbd(sc, tx_prod, txbd);
10580                 tx_prod++;
10581         }
10582
10583         BCE_PRINTF(
10584             "----------------------------"
10585             "----------------"
10586             "----------------------------\n");
10587 }
10588
10589
10590 /****************************************************************************/
10591 /* Prints out the RX chain.                                                 */
10592 /*                                                                          */
10593 /* Returns:                                                                 */
10594 /*   Nothing.                                                               */
10595 /****************************************************************************/
10596 static __attribute__ ((noinline)) void
10597 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10598 {
10599         struct rx_bd *rxbd;
10600
10601         /* First some info about the rx_bd chain structure. */
10602         BCE_PRINTF(
10603             "----------------------------"
10604             "  rx_bd  chain  "
10605             "----------------------------\n");
10606
10607         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10608             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10609
10610         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10611             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10612
10613         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10614
10615         BCE_PRINTF(
10616             "----------------------------"
10617             "   rx_bd data   "
10618             "----------------------------\n");
10619
10620         /* Now print out the rx_bd's themselves. */
10621         for (int i = 0; i < count; i++) {
10622                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10623                 bce_dump_rxbd(sc, rx_prod, rxbd);
10624                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10625         }
10626
10627         BCE_PRINTF(
10628             "----------------------------"
10629             "----------------"
10630             "----------------------------\n");
10631 }
10632
10633
10634 /****************************************************************************/
10635 /* Prints out the page chain.                                               */
10636 /*                                                                          */
10637 /* Returns:                                                                 */
10638 /*   Nothing.                                                               */
10639 /****************************************************************************/
10640 static __attribute__ ((noinline)) void
10641 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10642 {
10643         struct rx_bd *pgbd;
10644
10645         /* First some info about the page chain structure. */
10646         BCE_PRINTF(
10647             "----------------------------"
10648             "   page chain   "
10649             "----------------------------\n");
10650
10651         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10652             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10653
10654         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10655             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10656
10657         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10658
10659         BCE_PRINTF(
10660             "----------------------------"
10661             "   page data    "
10662             "----------------------------\n");
10663
10664         /* Now print out the rx_bd's themselves. */
10665         for (int i = 0; i < count; i++) {
10666                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10667                 bce_dump_pgbd(sc, pg_prod, pgbd);
10668                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10669         }
10670
10671         BCE_PRINTF(
10672             "----------------------------"
10673             "----------------"
10674             "----------------------------\n");
10675 }
10676
10677
10678 #define BCE_PRINT_RX_CONS(arg)                                          \
10679 if (sblk->status_rx_quick_consumer_index##arg)                          \
10680         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10681             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10682             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10683             arg);
10684
10685
10686 #define BCE_PRINT_TX_CONS(arg)                                          \
10687 if (sblk->status_tx_quick_consumer_index##arg)                          \
10688         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10689             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10690             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10691             arg);
10692
10693 /****************************************************************************/
10694 /* Prints out the status block from host memory.                            */
10695 /*                                                                          */
10696 /* Returns:                                                                 */
10697 /*   Nothing.                                                               */
10698 /****************************************************************************/
10699 static __attribute__ ((noinline)) void
10700 bce_dump_status_block(struct bce_softc *sc)
10701 {
10702         struct status_block *sblk;
10703
10704         sblk = sc->status_block;
10705
10706         BCE_PRINTF(
10707             "----------------------------"
10708             "  Status Block  "
10709             "----------------------------\n");
10710
10711         /* Theses indices are used for normal L2 drivers. */
10712         BCE_PRINTF("    0x%08X - attn_bits\n",
10713             sblk->status_attn_bits);
10714
10715         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10716             sblk->status_attn_bits_ack);
10717
10718         BCE_PRINT_RX_CONS(0);
10719         BCE_PRINT_TX_CONS(0)
10720
10721         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10722
10723         /* Theses indices are not used for normal L2 drivers. */
10724         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10725         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10726         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10727         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10728         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10729
10730         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10731
10732         if (sblk->status_completion_producer_index ||
10733             sblk->status_cmd_consumer_index)
10734                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10735                     sblk->status_completion_producer_index,
10736                     sblk->status_cmd_consumer_index);
10737
10738         BCE_PRINTF(
10739             "----------------------------"
10740             "----------------"
10741             "----------------------------\n");
10742 }
10743
10744
10745 #define BCE_PRINT_64BIT_STAT(arg)                               \
10746 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10747         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10748             sblk->arg##_lo, #arg);
10749
10750 #define BCE_PRINT_32BIT_STAT(arg)                               \
10751 if (sblk->arg)                                                  \
10752         BCE_PRINTF("         0x%08X : %s\n",                    \
10753             sblk->arg, #arg);
10754
10755 /****************************************************************************/
10756 /* Prints out the statistics block from host memory.                        */
10757 /*                                                                          */
10758 /* Returns:                                                                 */
10759 /*   Nothing.                                                               */
10760 /****************************************************************************/
10761 static __attribute__ ((noinline)) void
10762 bce_dump_stats_block(struct bce_softc *sc)
10763 {
10764         struct statistics_block *sblk;
10765
10766         sblk = sc->stats_block;
10767
10768         BCE_PRINTF(
10769             "---------------"
10770             " Stats Block  (All Stats Not Shown Are 0) "
10771             "---------------\n");
10772
10773         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10774         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10775         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10776         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10777         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10778         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10779         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10780         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10781         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10782         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10783         BCE_PRINT_32BIT_STAT(
10784             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10785         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10786         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10787         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10788         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10789         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10790         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10791         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10792         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10793         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10794         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10795         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10796         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10797         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10798         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10799         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10800         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10801         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10802         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10803         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10804         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10805         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10806         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10807         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10808         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10809         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10810         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10811         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10812         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10813         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10814         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10815         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10816         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10817         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10818         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10819         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10820         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10821         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10822         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10823         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10824         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10825         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10826         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10827         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10828
10829         BCE_PRINTF(
10830             "----------------------------"
10831             "----------------"
10832             "----------------------------\n");
10833 }
10834
10835
10836 /****************************************************************************/
10837 /* Prints out a summary of the driver state.                                */
10838 /*                                                                          */
10839 /* Returns:                                                                 */
10840 /*   Nothing.                                                               */
10841 /****************************************************************************/
10842 static __attribute__ ((noinline)) void
10843 bce_dump_driver_state(struct bce_softc *sc)
10844 {
10845         u32 val_hi, val_lo;
10846
10847         BCE_PRINTF(
10848             "-----------------------------"
10849             " Driver State "
10850             "-----------------------------\n");
10851
10852         val_hi = BCE_ADDR_HI(sc);
10853         val_lo = BCE_ADDR_LO(sc);
10854         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10855             "address\n", val_hi, val_lo);
10856
10857         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10858         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10859         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10860             "address\n", val_hi, val_lo);
10861
10862         val_hi = BCE_ADDR_HI(sc->status_block);
10863         val_lo = BCE_ADDR_LO(sc->status_block);
10864         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10865             "virtual address\n",        val_hi, val_lo);
10866
10867         val_hi = BCE_ADDR_HI(sc->stats_block);
10868         val_lo = BCE_ADDR_LO(sc->stats_block);
10869         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10870             "virtual address\n", val_hi, val_lo);
10871
10872         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10873         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10874         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10875             "virtual adddress\n", val_hi, val_lo);
10876
10877         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10878         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10879         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10880             "virtual address\n", val_hi, val_lo);
10881
10882         if (bce_hdr_split == TRUE) {
10883                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10884                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10885                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10886                     "virtual address\n", val_hi, val_lo);
10887         }
10888
10889         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10890         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10891         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10892             "virtual address\n",        val_hi, val_lo);
10893
10894         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10895         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10896         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10897             "virtual address\n", val_hi, val_lo);
10898
10899         if (bce_hdr_split == TRUE) {
10900                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10901                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10902                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10903                     "virtual address\n", val_hi, val_lo);
10904         }
10905
10906         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10907             "h/w intrs\n",
10908             (long long unsigned int) sc->interrupts_generated);
10909
10910         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10911             "rx interrupts handled\n",
10912             (long long unsigned int) sc->interrupts_rx);
10913
10914         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10915             "tx interrupts handled\n",
10916             (long long unsigned int) sc->interrupts_tx);
10917
10918         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10919             "phy interrupts handled\n",
10920             (long long unsigned int) sc->phy_interrupts);
10921
10922         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10923             "status block index\n", sc->last_status_idx);
10924
10925         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10926             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10927
10928         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10929             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10930
10931         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10932             "byte seq index\n", sc->tx_prod_bseq);
10933
10934         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10935             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10936
10937         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10938             "tx_bd's\n", sc->used_tx_bd);
10939
10940         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10941             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10942
10943         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10944             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10945
10946         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10947             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10948
10949         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10950             "byte seq index\n", sc->rx_prod_bseq);
10951
10952         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10953                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10954
10955         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10956             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10957
10958         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10959             "rx_bd's\n", sc->free_rx_bd);
10960
10961         if (bce_hdr_split == TRUE) {
10962                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10963                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10964
10965                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10966                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10967
10968                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10969                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10970         }
10971
10972         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10973             "rx_bd's\n", sc->free_pg_bd);
10974
10975         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10976             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10977
10978         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10979             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10980
10981         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10982             "bce mac flags\n", sc->bce_flags);
10983
10984         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10985             "bce phy flags\n", sc->bce_phy_flags);
10986
10987         BCE_PRINTF(
10988             "----------------------------"
10989             "----------------"
10990             "----------------------------\n");
10991 }
10992
10993
10994 /****************************************************************************/
10995 /* Prints out the hardware state through a summary of important register,   */
10996 /* followed by a complete register dump.                                    */
10997 /*                                                                          */
10998 /* Returns:                                                                 */
10999 /*   Nothing.                                                               */
11000 /****************************************************************************/
11001 static __attribute__ ((noinline)) void
11002 bce_dump_hw_state(struct bce_softc *sc)
11003 {
11004         u32 val;
11005
11006         BCE_PRINTF(
11007             "----------------------------"
11008             " Hardware State "
11009             "----------------------------\n");
11010
11011         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11012
11013         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
11014         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
11015             val, BCE_MISC_ENABLE_STATUS_BITS);
11016
11017         val = REG_RD(sc, BCE_DMA_STATUS);
11018         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11019             val, BCE_DMA_STATUS);
11020
11021         val = REG_RD(sc, BCE_CTX_STATUS);
11022         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11023             val, BCE_CTX_STATUS);
11024
11025         val = REG_RD(sc, BCE_EMAC_STATUS);
11026         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11027             val, BCE_EMAC_STATUS);
11028
11029         val = REG_RD(sc, BCE_RPM_STATUS);
11030         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11031             val, BCE_RPM_STATUS);
11032
11033         /* ToDo: Create a #define for this constant. */
11034         val = REG_RD(sc, 0x2004);
11035         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11036             val, 0x2004);
11037
11038         val = REG_RD(sc, BCE_RV2P_STATUS);
11039         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11040             val, BCE_RV2P_STATUS);
11041
11042         /* ToDo: Create a #define for this constant. */
11043         val = REG_RD(sc, 0x2c04);
11044         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11045             val, 0x2c04);
11046
11047         val = REG_RD(sc, BCE_TBDR_STATUS);
11048         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11049             val, BCE_TBDR_STATUS);
11050
11051         val = REG_RD(sc, BCE_TDMA_STATUS);
11052         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11053             val, BCE_TDMA_STATUS);
11054
11055         val = REG_RD(sc, BCE_HC_STATUS);
11056         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11057             val, BCE_HC_STATUS);
11058
11059         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11060         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11061             val, BCE_TXP_CPU_STATE);
11062
11063         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11064         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11065             val, BCE_TPAT_CPU_STATE);
11066
11067         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11068         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11069             val, BCE_RXP_CPU_STATE);
11070
11071         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11072         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11073             val, BCE_COM_CPU_STATE);
11074
11075         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11076         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11077             val, BCE_MCP_CPU_STATE);
11078
11079         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11080         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11081             val, BCE_CP_CPU_STATE);
11082
11083         BCE_PRINTF(
11084             "----------------------------"
11085             "----------------"
11086             "----------------------------\n");
11087
11088         BCE_PRINTF(
11089             "----------------------------"
11090             " Register  Dump "
11091             "----------------------------\n");
11092
11093         for (int i = 0x400; i < 0x8000; i += 0x10) {
11094                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11095                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11096                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11097         }
11098
11099         BCE_PRINTF(
11100             "----------------------------"
11101             "----------------"
11102             "----------------------------\n");
11103 }
11104
11105
11106 /****************************************************************************/
11107 /* Prints out the contentst of shared memory which is used for host driver  */
11108 /* to bootcode firmware communication.                                      */
11109 /*                                                                          */
11110 /* Returns:                                                                 */
11111 /*   Nothing.                                                               */
11112 /****************************************************************************/
11113 static __attribute__ ((noinline)) void
11114 bce_dump_shmem_state(struct bce_softc *sc)
11115 {
11116         BCE_PRINTF(
11117             "----------------------------"
11118             " Hardware State "
11119             "----------------------------\n");
11120
11121         BCE_PRINTF("0x%08X - Shared memory base address\n",
11122             sc->bce_shmem_base);
11123         BCE_PRINTF("%s - bootcode version\n",
11124             sc->bce_bc_ver);
11125
11126         BCE_PRINTF(
11127             "----------------------------"
11128             "   Shared Mem   "
11129             "----------------------------\n");
11130
11131         for (int i = 0x0; i < 0x200; i += 0x10) {
11132                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11133                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11134                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11135         }
11136
11137         BCE_PRINTF(
11138             "----------------------------"
11139             "----------------"
11140             "----------------------------\n");
11141 }
11142
11143
11144 /****************************************************************************/
11145 /* Prints out the mailbox queue registers.                                  */
11146 /*                                                                          */
11147 /* Returns:                                                                 */
11148 /*   Nothing.                                                               */
11149 /****************************************************************************/
11150 static __attribute__ ((noinline)) void
11151 bce_dump_mq_regs(struct bce_softc *sc)
11152 {
11153         BCE_PRINTF(
11154             "----------------------------"
11155             "    MQ Regs     "
11156             "----------------------------\n");
11157
11158         BCE_PRINTF(
11159             "----------------------------"
11160             "----------------"
11161             "----------------------------\n");
11162
11163         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11164                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11165                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11166                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11167         }
11168
11169         BCE_PRINTF(
11170             "----------------------------"
11171             "----------------"
11172             "----------------------------\n");
11173 }
11174
11175
11176 /****************************************************************************/
11177 /* Prints out the bootcode state.                                           */
11178 /*                                                                          */
11179 /* Returns:                                                                 */
11180 /*   Nothing.                                                               */
11181 /****************************************************************************/
11182 static __attribute__ ((noinline)) void
11183 bce_dump_bc_state(struct bce_softc *sc)
11184 {
11185         u32 val;
11186
11187         BCE_PRINTF(
11188             "----------------------------"
11189             " Bootcode State "
11190             "----------------------------\n");
11191
11192         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11193
11194         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11195         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11196             val, BCE_BC_RESET_TYPE);
11197
11198         val = bce_shmem_rd(sc, BCE_BC_STATE);
11199         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11200             val, BCE_BC_STATE);
11201
11202         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11203         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11204             val, BCE_BC_STATE_CONDITION);
11205
11206         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11207         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11208             val, BCE_BC_STATE_DEBUG_CMD);
11209
11210         BCE_PRINTF(
11211             "----------------------------"
11212             "----------------"
11213             "----------------------------\n");
11214 }
11215
11216
11217 /****************************************************************************/
11218 /* Prints out the TXP processor state.                                      */
11219 /*                                                                          */
11220 /* Returns:                                                                 */
11221 /*   Nothing.                                                               */
11222 /****************************************************************************/
11223 static __attribute__ ((noinline)) void
11224 bce_dump_txp_state(struct bce_softc *sc, int regs)
11225 {
11226         u32 val;
11227         u32 fw_version[3];
11228
11229         BCE_PRINTF(
11230             "----------------------------"
11231             "   TXP  State   "
11232             "----------------------------\n");
11233
11234         for (int i = 0; i < 3; i++)
11235                 fw_version[i] = htonl(REG_RD_IND(sc,
11236                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11237         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11238
11239         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11240         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11241             val, BCE_TXP_CPU_MODE);
11242
11243         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11244         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11245             val, BCE_TXP_CPU_STATE);
11246
11247         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11248         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11249             val, BCE_TXP_CPU_EVENT_MASK);
11250
11251         if (regs) {
11252                 BCE_PRINTF(
11253                     "----------------------------"
11254                     " Register  Dump "
11255                     "----------------------------\n");
11256
11257                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11258                         /* Skip the big blank spaces */
11259                         if (i < 0x454000 && i > 0x5ffff)
11260                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11261                                     "0x%08X 0x%08X\n", i,
11262                                     REG_RD_IND(sc, i),
11263                                     REG_RD_IND(sc, i + 0x4),
11264                                     REG_RD_IND(sc, i + 0x8),
11265                                     REG_RD_IND(sc, i + 0xC));
11266                 }
11267         }
11268
11269         BCE_PRINTF(
11270             "----------------------------"
11271             "----------------"
11272             "----------------------------\n");
11273 }
11274
11275
11276 /****************************************************************************/
11277 /* Prints out the RXP processor state.                                      */
11278 /*                                                                          */
11279 /* Returns:                                                                 */
11280 /*   Nothing.                                                               */
11281 /****************************************************************************/
11282 static __attribute__ ((noinline)) void
11283 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11284 {
11285         u32 val;
11286         u32 fw_version[3];
11287
11288         BCE_PRINTF(
11289             "----------------------------"
11290             "   RXP  State   "
11291             "----------------------------\n");
11292
11293         for (int i = 0; i < 3; i++)
11294                 fw_version[i] = htonl(REG_RD_IND(sc,
11295                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11296
11297         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11298
11299         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11300         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11301             val, BCE_RXP_CPU_MODE);
11302
11303         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11304         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11305             val, BCE_RXP_CPU_STATE);
11306
11307         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11308         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11309             val, BCE_RXP_CPU_EVENT_MASK);
11310
11311         if (regs) {
11312                 BCE_PRINTF(
11313                     "----------------------------"
11314                     " Register  Dump "
11315                     "----------------------------\n");
11316
11317                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11318                         /* Skip the big blank sapces */
11319                         if (i < 0xc5400 && i > 0xdffff)
11320                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11321                                     "0x%08X 0x%08X\n", i,
11322                                     REG_RD_IND(sc, i),
11323                                     REG_RD_IND(sc, i + 0x4),
11324                                     REG_RD_IND(sc, i + 0x8),
11325                                     REG_RD_IND(sc, i + 0xC));
11326                 }
11327         }
11328
11329         BCE_PRINTF(
11330             "----------------------------"
11331             "----------------"
11332             "----------------------------\n");
11333 }
11334
11335
11336 /****************************************************************************/
11337 /* Prints out the TPAT processor state.                                     */
11338 /*                                                                          */
11339 /* Returns:                                                                 */
11340 /*   Nothing.                                                               */
11341 /****************************************************************************/
11342 static __attribute__ ((noinline)) void
11343 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11344 {
11345         u32 val;
11346         u32 fw_version[3];
11347
11348         BCE_PRINTF(
11349             "----------------------------"
11350             "   TPAT State   "
11351             "----------------------------\n");
11352
11353         for (int i = 0; i < 3; i++)
11354                 fw_version[i] = htonl(REG_RD_IND(sc,
11355                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11356
11357         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11358
11359         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11360         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11361             val, BCE_TPAT_CPU_MODE);
11362
11363         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11364         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11365             val, BCE_TPAT_CPU_STATE);
11366
11367         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11368         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11369             val, BCE_TPAT_CPU_EVENT_MASK);
11370
11371         if (regs) {
11372                 BCE_PRINTF(
11373                     "----------------------------"
11374                     " Register  Dump "
11375                     "----------------------------\n");
11376
11377                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11378                         /* Skip the big blank spaces */
11379                         if (i < 0x854000 && i > 0x9ffff)
11380                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11381                                     "0x%08X 0x%08X\n", i,
11382                                     REG_RD_IND(sc, i),
11383                                     REG_RD_IND(sc, i + 0x4),
11384                                     REG_RD_IND(sc, i + 0x8),
11385                                     REG_RD_IND(sc, i + 0xC));
11386                 }
11387         }
11388
11389         BCE_PRINTF(
11390                 "----------------------------"
11391                 "----------------"
11392                 "----------------------------\n");
11393 }
11394
11395
11396 /****************************************************************************/
11397 /* Prints out the Command Procesor (CP) state.                              */
11398 /*                                                                          */
11399 /* Returns:                                                                 */
11400 /*   Nothing.                                                               */
11401 /****************************************************************************/
11402 static __attribute__ ((noinline)) void
11403 bce_dump_cp_state(struct bce_softc *sc, int regs)
11404 {
11405         u32 val;
11406         u32 fw_version[3];
11407
11408         BCE_PRINTF(
11409             "----------------------------"
11410             "    CP State    "
11411             "----------------------------\n");
11412
11413         for (int i = 0; i < 3; i++)
11414                 fw_version[i] = htonl(REG_RD_IND(sc,
11415                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11416
11417         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11418
11419         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11420         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11421             val, BCE_CP_CPU_MODE);
11422
11423         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11424         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11425             val, BCE_CP_CPU_STATE);
11426
11427         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11428         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11429             BCE_CP_CPU_EVENT_MASK);
11430
11431         if (regs) {
11432                 BCE_PRINTF(
11433                     "----------------------------"
11434                     " Register  Dump "
11435                     "----------------------------\n");
11436
11437                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11438                         /* Skip the big blank spaces */
11439                         if (i < 0x185400 && i > 0x19ffff)
11440                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11441                                     "0x%08X 0x%08X\n", i,
11442                                     REG_RD_IND(sc, i),
11443                                     REG_RD_IND(sc, i + 0x4),
11444                                     REG_RD_IND(sc, i + 0x8),
11445                                     REG_RD_IND(sc, i + 0xC));
11446                 }
11447         }
11448
11449         BCE_PRINTF(
11450             "----------------------------"
11451             "----------------"
11452             "----------------------------\n");
11453 }
11454
11455
11456 /****************************************************************************/
11457 /* Prints out the Completion Procesor (COM) state.                          */
11458 /*                                                                          */
11459 /* Returns:                                                                 */
11460 /*   Nothing.                                                               */
11461 /****************************************************************************/
11462 static __attribute__ ((noinline)) void
11463 bce_dump_com_state(struct bce_softc *sc, int regs)
11464 {
11465         u32 val;
11466         u32 fw_version[4];
11467
11468         BCE_PRINTF(
11469             "----------------------------"
11470             "   COM State    "
11471             "----------------------------\n");
11472
11473         for (int i = 0; i < 3; i++)
11474                 fw_version[i] = htonl(REG_RD_IND(sc,
11475                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11476
11477         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11478
11479         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11480         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11481             val, BCE_COM_CPU_MODE);
11482
11483         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11484         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11485             val, BCE_COM_CPU_STATE);
11486
11487         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11488         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11489             BCE_COM_CPU_EVENT_MASK);
11490
11491         if (regs) {
11492                 BCE_PRINTF(
11493                     "----------------------------"
11494                     " Register  Dump "
11495                     "----------------------------\n");
11496
11497                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11498                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11499                             "0x%08X 0x%08X\n", i,
11500                             REG_RD_IND(sc, i),
11501                             REG_RD_IND(sc, i + 0x4),
11502                             REG_RD_IND(sc, i + 0x8),
11503                             REG_RD_IND(sc, i + 0xC));
11504                 }
11505         }
11506
11507         BCE_PRINTF(
11508                 "----------------------------"
11509                 "----------------"
11510                 "----------------------------\n");
11511 }
11512
11513
11514 /****************************************************************************/
11515 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11516 /*                                                                          */
11517 /* Returns:                                                                 */
11518 /*   Nothing.                                                               */
11519 /****************************************************************************/
11520 static __attribute__ ((noinline)) void
11521 bce_dump_rv2p_state(struct bce_softc *sc)
11522 {
11523         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11524
11525         BCE_PRINTF(
11526             "----------------------------"
11527             "   RV2P State   "
11528             "----------------------------\n");
11529
11530         /* Stall the RV2P processors. */
11531         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11532         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11533         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11534
11535         /* Read the firmware version. */
11536         val = 0x00000001;
11537         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11538         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11539         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11540             BCE_RV2P_INSTR_HIGH_HIGH;
11541         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11542             fw_ver_high, fw_ver_low);
11543
11544         val = 0x00000001;
11545         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11546         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11547         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11548             BCE_RV2P_INSTR_HIGH_HIGH;
11549         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11550             fw_ver_high, fw_ver_low);
11551
11552         /* Resume the RV2P processors. */
11553         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11554         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11555         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11556
11557         /* Fetch the program counter value. */
11558         val = 0x68007800;
11559         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11560         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11561         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11562         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11563         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11564         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11565
11566         /* Fetch the program counter value again to see if it is advancing. */
11567         val = 0x68007800;
11568         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11569         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11570         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11571         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11572         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11573         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11574
11575         BCE_PRINTF(
11576             "----------------------------"
11577             "----------------"
11578             "----------------------------\n");
11579 }
11580
11581
11582 /****************************************************************************/
11583 /* Prints out the driver state and then enters the debugger.                */
11584 /*                                                                          */
11585 /* Returns:                                                                 */
11586 /*   Nothing.                                                               */
11587 /****************************************************************************/
11588 static __attribute__ ((noinline)) void
11589 bce_breakpoint(struct bce_softc *sc)
11590 {
11591
11592         /*
11593          * Unreachable code to silence compiler warnings
11594          * about unused functions.
11595          */
11596         if (0) {
11597                 bce_freeze_controller(sc);
11598                 bce_unfreeze_controller(sc);
11599                 bce_dump_enet(sc, NULL);
11600                 bce_dump_txbd(sc, 0, NULL);
11601                 bce_dump_rxbd(sc, 0, NULL);
11602                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11603                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11604                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11605                 bce_dump_l2fhdr(sc, 0, NULL);
11606                 bce_dump_ctx(sc, RX_CID);
11607                 bce_dump_ftqs(sc);
11608                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11609                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11610                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11611                 bce_dump_status_block(sc);
11612                 bce_dump_stats_block(sc);
11613                 bce_dump_driver_state(sc);
11614                 bce_dump_hw_state(sc);
11615                 bce_dump_bc_state(sc);
11616                 bce_dump_txp_state(sc, 0);
11617                 bce_dump_rxp_state(sc, 0);
11618                 bce_dump_tpat_state(sc, 0);
11619                 bce_dump_cp_state(sc, 0);
11620                 bce_dump_com_state(sc, 0);
11621                 bce_dump_rv2p_state(sc);
11622                 bce_dump_pgbd(sc, 0, NULL);
11623         }
11624
11625         bce_dump_status_block(sc);
11626         bce_dump_driver_state(sc);
11627
11628         /* Call the debugger. */
11629         breakpoint();
11630
11631         return;
11632 }
11633 #endif