sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2014 QLogic Corporation
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  18  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  19  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  20  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  21  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  22  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  23  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  24  * THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 /*
  31  * The following controllers are supported by this driver:
  32  *   BCM5706C A2, A3
  33  *   BCM5706S A2, A3
  34  *   BCM5708C B1, B2
  35  *   BCM5708S B1, B2
  36  *   BCM5709C A1, C0
  37  *   BCM5709S A1, C0
  38  *   BCM5716C C0
  39  *   BCM5716S C0
  40  *
  41  * The following controllers are not supported by this driver:
  42  *   BCM5706C A0, A1 (pre-production)
  43  *   BCM5706S A0, A1 (pre-production)
  44  *   BCM5708C A0, B0 (pre-production)
  45  *   BCM5708S A0, B0 (pre-production)
  46  *   BCM5709C A0  B0, B1, B2 (pre-production)
  47  *   BCM5709S A0, B0, B1, B2 (pre-production)
  48  */
  49
  50 #include "opt_bce.h"
  51
  52 #include <dev/bce/if_bcereg.h>
  53 #include <dev/bce/if_bcefw.h>
  54
  55 /****************************************************************************/
  56 /* BCE Debug Options                                                        */
  57 /****************************************************************************/
  58 #ifdef BCE_DEBUG
  59         u32 bce_debug = BCE_WARN;
  60
  61         /*          0 = Never              */
  62         /*          1 = 1 in 2,147,483,648 */
  63         /*        256 = 1 in     8,388,608 */
  64         /*       2048 = 1 in     1,048,576 */
  65         /*      65536 = 1 in        32,768 */
  66         /*    1048576 = 1 in         2,048 */
  67         /*  268435456 = 1 in             8 */
  68         /*  536870912 = 1 in             4 */
  69         /* 1073741824 = 1 in             2 */
  70
  71         /* Controls how often the l2_fhdr frame error check will fail. */
  72         int l2fhdr_error_sim_control = 0;
  73
  74         /* Controls how often the unexpected attention check will fail. */
  75         int unexpected_attention_sim_control = 0;
  76
  77         /* Controls how often to simulate an mbuf allocation failure. */
  78         int mbuf_alloc_failed_sim_control = 0;
  79
  80         /* Controls how often to simulate a DMA mapping failure. */
  81         int dma_map_addr_failed_sim_control = 0;
  82
  83         /* Controls how often to simulate a bootcode failure. */
  84         int bootcode_running_failure_sim_control = 0;
  85 #endif
  86
  87 /****************************************************************************/
  88 /* PCI Device ID Table                                                      */
  89 /*                                                                          */
  90 /* Used by bce_probe() to identify the devices supported by this driver.    */
  91 /****************************************************************************/
  92 #define BCE_DEVDESC_MAX         64
  93
  94 static const struct bce_type bce_devs[] = {
  95         /* BCM5706C Controllers and OEM boards. */
  96         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
  97                 "HP NC370T Multifunction Gigabit Server Adapter" },
  98         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
  99                 "HP NC370i Multifunction Gigabit Server Adapter" },
 100         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 101                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 102         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 103                 "HP NC371i Multifunction Gigabit Server Adapter" },
 104         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 105                 "QLogic NetXtreme II BCM5706 1000Base-T" },
 106
 107         /* BCM5706S controllers and OEM boards. */
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 109                 "HP NC370F Multifunction Gigabit Server Adapter" },
 110         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 111                 "QLogic NetXtreme II BCM5706 1000Base-SX" },
 112
 113         /* BCM5708C controllers and OEM boards. */
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 115                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 116         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 117                 "HP NC373i Multifunction Gigabit Server Adapter" },
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 119                 "HP NC374m PCIe Multifunction Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 121                 "QLogic NetXtreme II BCM5708 1000Base-T" },
 122
 123         /* BCM5708S controllers and OEM boards. */
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 125                 "HP NC373m Multifunction Gigabit Server Adapter" },
 126         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 127                 "HP NC373i Multifunction Gigabit Server Adapter" },
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 129                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 131                 "QLogic NetXtreme II BCM5708 1000Base-SX" },
 132
 133         /* BCM5709C controllers and OEM boards. */
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 135                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 136         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 137                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 139                 "QLogic NetXtreme II BCM5709 1000Base-T" },
 140
 141         /* BCM5709S controllers and OEM boards. */
 142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 143                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 145                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 147                 "QLogic NetXtreme II BCM5709 1000Base-SX" },
 148
 149         /* BCM5716 controllers and OEM boards. */
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 151                 "QLogic NetXtreme II BCM5716 1000Base-T" },
 152
 153         { 0, 0, 0, 0, NULL }
 154 };
 155
 156
 157 /****************************************************************************/
 158 /* Supported Flash NVRAM device data.                                       */
 159 /****************************************************************************/
 160 static const struct flash_spec flash_table[] =
 161 {
 162 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 163 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 164
 165         /* Slow EEPROM */
 166         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 167          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 168          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 169          "EEPROM - slow"},
 170         /* Expansion entry 0001 */
 171         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 172          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 173          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 174          "Entry 0001"},
 175         /* Saifun SA25F010 (non-buffered flash) */
 176         /* strap, cfg1, & write1 need updates */
 177         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 178          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 179          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 180          "Non-buffered flash (128kB)"},
 181         /* Saifun SA25F020 (non-buffered flash) */
 182         /* strap, cfg1, & write1 need updates */
 183         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 184          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 185          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 186          "Non-buffered flash (256kB)"},
 187         /* Expansion entry 0100 */
 188         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 189          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 190          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 191          "Entry 0100"},
 192         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 193         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 194          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 195          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 196          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 197         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 198         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 199          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 200          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 201          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 202         /* Saifun SA25F005 (non-buffered flash) */
 203         /* strap, cfg1, & write1 need updates */
 204         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 205          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 206          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 207          "Non-buffered flash (64kB)"},
 208         /* Fast EEPROM */
 209         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 210          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 211          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 212          "EEPROM - fast"},
 213         /* Expansion entry 1001 */
 214         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 215          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 216          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 217          "Entry 1001"},
 218         /* Expansion entry 1010 */
 219         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 1010"},
 223         /* ATMEL AT45DB011B (buffered flash) */
 224         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 225          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 226          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 227          "Buffered flash (128kB)"},
 228         /* Expansion entry 1100 */
 229         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 231          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 232          "Entry 1100"},
 233         /* Expansion entry 1101 */
 234         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 235          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 236          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 237          "Entry 1101"},
 238         /* Ateml Expansion entry 1110 */
 239         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 240          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 241          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 242          "Entry 1110 (Atmel)"},
 243         /* ATMEL AT45DB021B (buffered flash) */
 244         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 245          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 246          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 247          "Buffered flash (256kB)"},
 248 };
 249
 250 /*
 251  * The BCM5709 controllers transparently handle the
 252  * differences between Atmel 264 byte pages and all
 253  * flash devices which use 256 byte pages, so no
 254  * logical-to-physical mapping is required in the
 255  * driver.
 256  */
 257 static const struct flash_spec flash_5709 = {
 258         .flags          = BCE_NV_BUFFERED,
 259         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 260         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 261         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 262         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 263         .name           = "5709/5716 buffered flash (256kB)",
 264 };
 265
 266
 267 /****************************************************************************/
 268 /* FreeBSD device entry points.                                             */
 269 /****************************************************************************/
 270 static int  bce_probe                   (device_t);
 271 static int  bce_attach                  (device_t);
 272 static int  bce_detach                  (device_t);
 273 static int  bce_shutdown                (device_t);
 274
 275
 276 /****************************************************************************/
 277 /* BCE Debug Data Structure Dump Routines                                   */
 278 /****************************************************************************/
 279 #ifdef BCE_DEBUG
 280 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 281 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 282 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 283 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 284 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 285 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 286 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 287 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 288 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 289 static void bce_dump_txbd                       (struct bce_softc *,
 290     int, struct tx_bd *);
 291 static void bce_dump_rxbd                       (struct bce_softc *,
 292     int, struct rx_bd *);
 293 static void bce_dump_pgbd                       (struct bce_softc *,
 294     int, struct rx_bd *);
 295 static void bce_dump_l2fhdr             (struct bce_softc *,
 296     int, struct l2_fhdr *);
 297 static void bce_dump_ctx                        (struct bce_softc *, u16);
 298 static void bce_dump_ftqs                       (struct bce_softc *);
 299 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 300 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 301 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 302 static void bce_dump_status_block       (struct bce_softc *);
 303 static void bce_dump_stats_block        (struct bce_softc *);
 304 static void bce_dump_driver_state       (struct bce_softc *);
 305 static void bce_dump_hw_state           (struct bce_softc *);
 306 static void bce_dump_shmem_state        (struct bce_softc *);
 307 static void bce_dump_mq_regs            (struct bce_softc *);
 308 static void bce_dump_bc_state           (struct bce_softc *);
 309 static void bce_dump_txp_state          (struct bce_softc *, int);
 310 static void bce_dump_rxp_state          (struct bce_softc *, int);
 311 static void bce_dump_tpat_state (struct bce_softc *, int);
 312 static void bce_dump_cp_state           (struct bce_softc *, int);
 313 static void bce_dump_com_state          (struct bce_softc *, int);
 314 static void bce_dump_rv2p_state (struct bce_softc *);
 315 static void bce_breakpoint                      (struct bce_softc *);
 316 #endif /*BCE_DEBUG */
 317
 318
 319 /****************************************************************************/
 320 /* BCE Register/Memory Access Routines                                      */
 321 /****************************************************************************/
 322 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 323 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 324 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 325 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 326 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 327 static int  bce_miibus_read_reg         (device_t, int, int);
 328 static int  bce_miibus_write_reg        (device_t, int, int, int);
 329 static void bce_miibus_statchg          (device_t);
 330
 331 #ifdef BCE_DEBUG
 332 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 333 #ifdef BCE_NVRAM_WRITE_SUPPORT
 334 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 335 #endif
 336 #endif
 337
 338 /****************************************************************************/
 339 /* BCE NVRAM Access Routines                                                */
 340 /****************************************************************************/
 341 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 342 static int  bce_release_nvram_lock      (struct bce_softc *);
 343 static void bce_enable_nvram_access(struct bce_softc *);
 344 static void bce_disable_nvram_access(struct bce_softc *);
 345 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 346 static int  bce_init_nvram                      (struct bce_softc *);
 347 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 348 static int  bce_nvram_test                      (struct bce_softc *);
 349 #ifdef BCE_NVRAM_WRITE_SUPPORT
 350 static int  bce_enable_nvram_write      (struct bce_softc *);
 351 static void bce_disable_nvram_write(struct bce_softc *);
 352 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 353 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 354 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 355 #endif
 356
 357 /****************************************************************************/
 358 /*                                                                          */
 359 /****************************************************************************/
 360 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 361 static void bce_get_media                       (struct bce_softc *);
 362 static void bce_init_media                      (struct bce_softc *);
 363 static u32 bce_get_rphy_link            (struct bce_softc *);
 364 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 365 static int  bce_dma_alloc                       (device_t);
 366 static void bce_dma_free                        (struct bce_softc *);
 367 static void bce_release_resources       (struct bce_softc *);
 368
 369 /****************************************************************************/
 370 /* BCE Firmware Synchronization and Load                                    */
 371 /****************************************************************************/
 372 static void bce_fw_cap_init                     (struct bce_softc *);
 373 static int  bce_fw_sync                 (struct bce_softc *, u32);
 374 static void bce_load_rv2p_fw            (struct bce_softc *, u32 *, u32, u32);
 375 static void bce_load_cpu_fw             (struct bce_softc *,
 376     struct cpu_reg *, struct fw_info *);
 377 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 378 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 379 static void bce_start_rxp_cpu           (struct bce_softc *);
 380 static void bce_init_rxp_cpu            (struct bce_softc *);
 381 static void bce_init_txp_cpu            (struct bce_softc *);
 382 static void bce_init_tpat_cpu           (struct bce_softc *);
 383 static void bce_init_cp_cpu             (struct bce_softc *);
 384 static void bce_init_com_cpu            (struct bce_softc *);
 385 static void bce_init_cpus                       (struct bce_softc *);
 386
 387 static void bce_print_adapter_info      (struct bce_softc *);
 388 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 389 static void bce_stop                            (struct bce_softc *);
 390 static int  bce_reset                           (struct bce_softc *, u32);
 391 static int  bce_chipinit                        (struct bce_softc *);
 392 static int  bce_blockinit                       (struct bce_softc *);
 393
 394 static int  bce_init_tx_chain           (struct bce_softc *);
 395 static void bce_free_tx_chain           (struct bce_softc *);
 396
 397 static int  bce_get_rx_buf                      (struct bce_softc *,
 398     struct mbuf *, u16 *, u16 *, u32 *);
 399 static int  bce_init_rx_chain           (struct bce_softc *);
 400 static void bce_fill_rx_chain           (struct bce_softc *);
 401 static void bce_free_rx_chain           (struct bce_softc *);
 402
 403 static int  bce_get_pg_buf                      (struct bce_softc *,
 404     struct mbuf *, u16 *, u16 *);
 405 static int  bce_init_pg_chain           (struct bce_softc *);
 406 static void bce_fill_pg_chain           (struct bce_softc *);
 407 static void bce_free_pg_chain           (struct bce_softc *);
 408
 409 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 410     struct mbuf **, u16 *);
 411 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 412 static void bce_start_locked            (struct ifnet *);
 413 static void bce_start                           (struct ifnet *);
 414 static int  bce_ioctl                           (struct ifnet *, u_long, caddr_t);
 415 static void bce_watchdog                        (struct bce_softc *);
 416 static int  bce_ifmedia_upd             (struct ifnet *);
 417 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 418 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 419 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 420 static void bce_init_locked             (struct bce_softc *);
 421 static void bce_init                            (void *);
 422 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 423
 424 static int  bce_init_ctx                        (struct bce_softc *);
 425 static void bce_get_mac_addr            (struct bce_softc *);
 426 static void bce_set_mac_addr            (struct bce_softc *);
 427 static void bce_phy_intr                        (struct bce_softc *);
 428 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 429 static void bce_rx_intr                 (struct bce_softc *);
 430 static void bce_tx_intr                 (struct bce_softc *);
 431 static void bce_disable_intr            (struct bce_softc *);
 432 static void bce_enable_intr             (struct bce_softc *, int);
 433
 434 static void bce_intr                            (void *);
 435 static void bce_set_rx_mode             (struct bce_softc *);
 436 static void bce_stats_update            (struct bce_softc *);
 437 static void bce_tick                            (void *);
 438 static void bce_pulse                           (void *);
 439 static void bce_add_sysctls             (struct bce_softc *);
 440
 441
 442 /****************************************************************************/
 443 /* FreeBSD device dispatch table.                                           */
 444 /****************************************************************************/
 445 static device_method_t bce_methods[] = {
 446         /* Device interface (device_if.h) */
 447         DEVMETHOD(device_probe,         bce_probe),
 448         DEVMETHOD(device_attach,        bce_attach),
 449         DEVMETHOD(device_detach,        bce_detach),
 450         DEVMETHOD(device_shutdown,      bce_shutdown),
 451 /* Supported by device interface but not used here. */
 452 /*      DEVMETHOD(device_identify,      bce_identify),      */
 453 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 454 /*      DEVMETHOD(device_resume,        bce_resume),        */
 455 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 456
 457         /* MII interface (miibus_if.h) */
 458         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 459         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 460         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 461 /* Supported by MII interface but not used here.       */
 462 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 463 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 464
 465         DEVMETHOD_END
 466 };
 467
 468 static driver_t bce_driver = {
 469         "bce",
 470         bce_methods,
 471         sizeof(struct bce_softc)
 472 };
 473
 474 static devclass_t bce_devclass;
 475
 476 MODULE_DEPEND(bce, pci, 1, 1, 1);
 477 MODULE_DEPEND(bce, ether, 1, 1, 1);
 478 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 479
 480 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 481 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 482
 483
 484 /****************************************************************************/
 485 /* Tunable device values                                                    */
 486 /****************************************************************************/
 487 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 488
 489 /* Allowable values are TRUE or FALSE */
 490 static int bce_verbose = TRUE;
 491 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
 492 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 493     "Verbose output enable/disable");
 494
 495 /* Allowable values are TRUE or FALSE */
 496 static int bce_tso_enable = TRUE;
 497 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 498 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 499     "TSO Enable/Disable");
 500
 501 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 502 /* ToDo: Add MSI-X support. */
 503 static int bce_msi_enable = 1;
 504 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 505 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 506     "MSI-X|MSI|INTx selector");
 507
 508 /* Allowable values are 1, 2, 4, 8. */
 509 static int bce_rx_pages = DEFAULT_RX_PAGES;
 510 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 511 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 512     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 513
 514 /* Allowable values are 1, 2, 4, 8. */
 515 static int bce_tx_pages = DEFAULT_TX_PAGES;
 516 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 517 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 518     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 519
 520 /* Allowable values are TRUE or FALSE. */
 521 static int bce_hdr_split = TRUE;
 522 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
 523 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 524     "Frame header/payload splitting Enable/Disable");
 525
 526 /* Allowable values are TRUE or FALSE. */
 527 static int bce_strict_rx_mtu = FALSE;
 528 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
 529 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN,
 530     &bce_strict_rx_mtu, 0,
 531     "Enable/Disable strict RX frame size checking");
 532
 533 /* Allowable values are 0 ... 100 */
 534 #ifdef BCE_DEBUG
 535 /* Generate 1 interrupt for every transmit completion. */
 536 static int bce_tx_quick_cons_trip_int = 1;
 537 #else
 538 /* Generate 1 interrupt for every 20 transmit completions. */
 539 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 540 #endif
 541 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
 542 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 543     &bce_tx_quick_cons_trip_int, 0,
 544     "Transmit BD trip point during interrupts");
 545
 546 /* Allowable values are 0 ... 100 */
 547 /* Generate 1 interrupt for every transmit completion. */
 548 #ifdef BCE_DEBUG
 549 static int bce_tx_quick_cons_trip = 1;
 550 #else
 551 /* Generate 1 interrupt for every 20 transmit completions. */
 552 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 553 #endif
 554 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
 555 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 556     &bce_tx_quick_cons_trip, 0,
 557     "Transmit BD trip point");
 558
 559 /* Allowable values are 0 ... 100 */
 560 #ifdef BCE_DEBUG
 561 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 562 static int bce_tx_ticks_int = 0;
 563 #else
 564 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 565 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 566 #endif
 567 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 568 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 569     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 570
 571 /* Allowable values are 0 ... 100 */
 572 #ifdef BCE_DEBUG
 573 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 574 static int bce_tx_ticks = 0;
 575 #else
 576 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 577 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 578 #endif
 579 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 580 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 581     &bce_tx_ticks, 0, "Transmit ticks count");
 582
 583 /* Allowable values are 1 ... 100 */
 584 #ifdef BCE_DEBUG
 585 /* Generate 1 interrupt for every received frame. */
 586 static int bce_rx_quick_cons_trip_int = 1;
 587 #else
 588 /* Generate 1 interrupt for every 6 received frames. */
 589 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 590 #endif
 591 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
 592 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 593     &bce_rx_quick_cons_trip_int, 0,
 594     "Receive BD trip point duirng interrupts");
 595
 596 /* Allowable values are 1 ... 100 */
 597 #ifdef BCE_DEBUG
 598 /* Generate 1 interrupt for every received frame. */
 599 static int bce_rx_quick_cons_trip = 1;
 600 #else
 601 /* Generate 1 interrupt for every 6 received frames. */
 602 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 603 #endif
 604 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
 605 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 606     &bce_rx_quick_cons_trip, 0,
 607     "Receive BD trip point");
 608
 609 /* Allowable values are 0 ... 100 */
 610 #ifdef BCE_DEBUG
 611 /* Generate an int. if 0us have elapsed since the last received frame. */
 612 static int bce_rx_ticks_int = 0;
 613 #else
 614 /* Generate an int. if 18us have elapsed since the last received frame. */
 615 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 616 #endif
 617 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 618 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 619     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 620
 621 /* Allowable values are 0 ... 100 */
 622 #ifdef BCE_DEBUG
 623 /* Generate an int. if 0us have elapsed since the last received frame. */
 624 static int bce_rx_ticks = 0;
 625 #else
 626 /* Generate an int. if 18us have elapsed since the last received frame. */
 627 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 628 #endif
 629 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 630 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 631     &bce_rx_ticks, 0, "Receive ticks count");
 632
 633
 634 /****************************************************************************/
 635 /* Device probe function.                                                   */
 636 /*                                                                          */
 637 /* Compares the device to the driver's list of supported devices and        */
 638 /* reports back to the OS whether this is the right driver for the device.  */
 639 /*                                                                          */
 640 /* Returns:                                                                 */
 641 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 642 /****************************************************************************/
 643 static int
 644 bce_probe(device_t dev)
 645 {
 646         const struct bce_type *t;
 647         struct bce_softc *sc;
 648         char *descbuf;
 649         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 650
 651         t = bce_devs;
 652
 653         sc = device_get_softc(dev);
 654         sc->bce_unit = device_get_unit(dev);
 655         sc->bce_dev = dev;
 656
 657         /* Get the data for the device to be probed. */
 658         vid  = pci_get_vendor(dev);
 659         did  = pci_get_device(dev);
 660         svid = pci_get_subvendor(dev);
 661         sdid = pci_get_subdevice(dev);
 662
 663         DBPRINT(sc, BCE_EXTREME_LOAD,
 664             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 665             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 666
 667         /* Look through the list of known devices for a match. */
 668         while(t->bce_name != NULL) {
 669
 670                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 671                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 672                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 673
 674                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 675
 676                         if (descbuf == NULL)
 677                                 return(ENOMEM);
 678
 679                         /* Print out the device identity. */
 680                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 681                             t->bce_name, (((pci_read_config(dev,
 682                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 683                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 684
 685                         device_set_desc_copy(dev, descbuf);
 686                         free(descbuf, M_TEMP);
 687                         return(BUS_PROBE_DEFAULT);
 688                 }
 689                 t++;
 690         }
 691
 692         return(ENXIO);
 693 }
 694
 695
 696 /****************************************************************************/
 697 /* PCI Capabilities Probe Function.                                         */
 698 /*                                                                          */
 699 /* Walks the PCI capabiites list for the device to find what features are   */
 700 /* supported.                                                               */
 701 /*                                                                          */
 702 /* Returns:                                                                 */
 703 /*   None.                                                                  */
 704 /****************************************************************************/
 705 static void
 706 bce_print_adapter_info(struct bce_softc *sc)
 707 {
 708         int i = 0;
 709
 710         DBENTER(BCE_VERBOSE_LOAD);
 711
 712         if (bce_verbose || bootverbose) {
 713                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 714                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 715                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 716
 717
 718                 /* Bus info. */
 719                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 720                         printf("Bus (PCIe x%d, ", sc->link_width);
 721                         switch (sc->link_speed) {
 722                         case 1: printf("2.5Gbps); "); break;
 723                         case 2: printf("5Gbps); "); break;
 724                         default: printf("Unknown link speed); ");
 725                         }
 726                 } else {
 727                         printf("Bus (PCI%s, %s, %dMHz); ",
 728                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 729                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 730                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 731                 }
 732
 733                 /* Firmware version and device features. */
 734                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 735                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 736                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 737
 738                 if (bce_hdr_split == TRUE) {
 739                         printf("SPLT");
 740                         i++;
 741                 }
 742
 743                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 744                         if (i > 0) printf("|");
 745                         printf("MSI"); i++;
 746                 }
 747
 748                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 749                         if (i > 0) printf("|");
 750                         printf("MSI-X"); i++;
 751                 }
 752
 753                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 754                         if (i > 0) printf("|");
 755                         printf("2.5G"); i++;
 756                 }
 757
 758                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 759                         if (i > 0) printf("|");
 760                         printf("Remote PHY(%s)",
 761                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 762                             "FIBER" : "TP"); i++;
 763                 }
 764
 765                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 766                         if (i > 0) printf("|");
 767                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 768                 } else {
 769                         printf(")\n");
 770                 }
 771
 772                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 773                     sc->bce_rx_quick_cons_trip_int,
 774                     sc->bce_rx_quick_cons_trip,
 775                     sc->bce_rx_ticks_int,
 776                     sc->bce_rx_ticks,
 777                     sc->bce_tx_quick_cons_trip_int,
 778                     sc->bce_tx_quick_cons_trip,
 779                     sc->bce_tx_ticks_int,
 780                     sc->bce_tx_ticks);
 781
 782         }
 783
 784         DBEXIT(BCE_VERBOSE_LOAD);
 785 }
 786
 787
 788 /****************************************************************************/
 789 /* PCI Capabilities Probe Function.                                         */
 790 /*                                                                          */
 791 /* Walks the PCI capabiites list for the device to find what features are   */
 792 /* supported.                                                               */
 793 /*                                                                          */
 794 /* Returns:                                                                 */
 795 /*   None.                                                                  */
 796 /****************************************************************************/
 797 static void
 798 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 799 {
 800         u32 reg;
 801
 802         DBENTER(BCE_VERBOSE_LOAD);
 803
 804         /* Check if PCI-X capability is enabled. */
 805         if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
 806                 if (reg != 0)
 807                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 808         }
 809
 810         /* Check if PCIe capability is enabled. */
 811         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
 812                 if (reg != 0) {
 813                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 814                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 815                             "0x%08X\n", link_status);
 816                         sc->link_speed = link_status & 0xf;
 817                         sc->link_width = (link_status >> 4) & 0x3f;
 818                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 819                         sc->bce_flags |= BCE_PCIE_FLAG;
 820                 }
 821         }
 822
 823         /* Check if MSI capability is enabled. */
 824         if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
 825                 if (reg != 0)
 826                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 827         }
 828
 829         /* Check if MSI-X capability is enabled. */
 830         if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
 831                 if (reg != 0)
 832                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 833         }
 834
 835         DBEXIT(BCE_VERBOSE_LOAD);
 836 }
 837
 838
 839 /****************************************************************************/
 840 /* Load and validate user tunable settings.                                 */
 841 /*                                                                          */
 842 /* Returns:                                                                 */
 843 /*   Nothing.                                                               */
 844 /****************************************************************************/
 845 static void
 846 bce_set_tunables(struct bce_softc *sc)
 847 {
 848         /* Set sysctl values for RX page count. */
 849         switch (bce_rx_pages) {
 850         case 1:
 851                 /* fall-through */
 852         case 2:
 853                 /* fall-through */
 854         case 4:
 855                 /* fall-through */
 856         case 8:
 857                 sc->rx_pages = bce_rx_pages;
 858                 break;
 859         default:
 860                 sc->rx_pages = DEFAULT_RX_PAGES;
 861                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 862                     "hw.bce.rx_pages!  Setting default of %d.\n",
 863                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 864         }
 865
 866         /* ToDo: Consider allowing user setting for pg_pages. */
 867         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 868
 869         /* Set sysctl values for TX page count. */
 870         switch (bce_tx_pages) {
 871         case 1:
 872                 /* fall-through */
 873         case 2:
 874                 /* fall-through */
 875         case 4:
 876                 /* fall-through */
 877         case 8:
 878                 sc->tx_pages = bce_tx_pages;
 879                 break;
 880         default:
 881                 sc->tx_pages = DEFAULT_TX_PAGES;
 882                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 883                     "hw.bce.tx_pages!  Setting default of %d.\n",
 884                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 885         }
 886
 887         /*
 888          * Validate the TX trip point (i.e. the number of
 889          * TX completions before a status block update is
 890          * generated and an interrupt is asserted.
 891          */
 892         if (bce_tx_quick_cons_trip_int <= 100) {
 893                 sc->bce_tx_quick_cons_trip_int =
 894                     bce_tx_quick_cons_trip_int;
 895         } else {
 896                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 897                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 898                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 899                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 900                 sc->bce_tx_quick_cons_trip_int =
 901                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 902         }
 903
 904         if (bce_tx_quick_cons_trip <= 100) {
 905                 sc->bce_tx_quick_cons_trip =
 906                     bce_tx_quick_cons_trip;
 907         } else {
 908                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 909                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 910                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 911                     DEFAULT_TX_QUICK_CONS_TRIP);
 912                 sc->bce_tx_quick_cons_trip =
 913                     DEFAULT_TX_QUICK_CONS_TRIP;
 914         }
 915
 916         /*
 917          * Validate the TX ticks count (i.e. the maximum amount
 918          * of time to wait after the last TX completion has
 919          * occurred before a status block update is generated
 920          * and an interrupt is asserted.
 921          */
 922         if (bce_tx_ticks_int <= 100) {
 923                 sc->bce_tx_ticks_int =
 924                     bce_tx_ticks_int;
 925         } else {
 926                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 927                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 928                     __FILE__, __LINE__, bce_tx_ticks_int,
 929                     DEFAULT_TX_TICKS_INT);
 930                 sc->bce_tx_ticks_int =
 931                     DEFAULT_TX_TICKS_INT;
 932            }
 933
 934         if (bce_tx_ticks <= 100) {
 935                 sc->bce_tx_ticks =
 936                     bce_tx_ticks;
 937         } else {
 938                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 939                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 940                     __FILE__, __LINE__, bce_tx_ticks,
 941                     DEFAULT_TX_TICKS);
 942                 sc->bce_tx_ticks =
 943                     DEFAULT_TX_TICKS;
 944         }
 945
 946         /*
 947          * Validate the RX trip point (i.e. the number of
 948          * RX frames received before a status block update is
 949          * generated and an interrupt is asserted.
 950          */
 951         if (bce_rx_quick_cons_trip_int <= 100) {
 952                 sc->bce_rx_quick_cons_trip_int =
 953                     bce_rx_quick_cons_trip_int;
 954         } else {
 955                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 956                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 957                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 958                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 959                 sc->bce_rx_quick_cons_trip_int =
 960                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 961         }
 962
 963         if (bce_rx_quick_cons_trip <= 100) {
 964                 sc->bce_rx_quick_cons_trip =
 965                     bce_rx_quick_cons_trip;
 966         } else {
 967                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 968                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
 969                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
 970                     DEFAULT_RX_QUICK_CONS_TRIP);
 971                 sc->bce_rx_quick_cons_trip =
 972                     DEFAULT_RX_QUICK_CONS_TRIP;
 973         }
 974
 975         /*
 976          * Validate the RX ticks count (i.e. the maximum amount
 977          * of time to wait after the last RX frame has been
 978          * received before a status block update is generated
 979          * and an interrupt is asserted.
 980          */
 981         if (bce_rx_ticks_int <= 100) {
 982                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
 983         } else {
 984                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 985                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
 986                     __FILE__, __LINE__, bce_rx_ticks_int,
 987                     DEFAULT_RX_TICKS_INT);
 988                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 989         }
 990
 991         if (bce_rx_ticks <= 100) {
 992                 sc->bce_rx_ticks = bce_rx_ticks;
 993         } else {
 994                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 995                     "hw.bce.rx_ticks!  Setting default of %d.\n",
 996                     __FILE__, __LINE__, bce_rx_ticks,
 997                     DEFAULT_RX_TICKS);
 998                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
 999         }
1000
1001         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1002         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1003                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1004                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1005                    __FILE__, __LINE__);
1006                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1007                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1008         }
1009
1010         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1011         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1012                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1013                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1014                    __FILE__, __LINE__);
1015                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1016                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1017         }
1018
1019 }
1020
1021
1022 /****************************************************************************/
1023 /* Device attach function.                                                  */
1024 /*                                                                          */
1025 /* Allocates device resources, performs secondary chip identification,      */
1026 /* resets and initializes the hardware, and initializes driver instance     */
1027 /* variables.                                                               */
1028 /*                                                                          */
1029 /* Returns:                                                                 */
1030 /*   0 on success, positive value on failure.                               */
1031 /****************************************************************************/
1032 static int
1033 bce_attach(device_t dev)
1034 {
1035         struct bce_softc *sc;
1036         struct ifnet *ifp;
1037         u32 val;
1038         int count, error, rc = 0, rid;
1039
1040         sc = device_get_softc(dev);
1041         sc->bce_dev = dev;
1042
1043         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1044
1045         sc->bce_unit = device_get_unit(dev);
1046
1047         /* Set initial device and PHY flags */
1048         sc->bce_flags = 0;
1049         sc->bce_phy_flags = 0;
1050
1051         bce_set_tunables(sc);
1052
1053         pci_enable_busmaster(dev);
1054
1055         /* Allocate PCI memory resources. */
1056         rid = PCIR_BAR(0);
1057         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1058                 &rid, RF_ACTIVE);
1059
1060         if (sc->bce_res_mem == NULL) {
1061                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1062                     __FILE__, __LINE__);
1063                 rc = ENXIO;
1064                 goto bce_attach_fail;
1065         }
1066
1067         /* Get various resource handles. */
1068         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1069         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1070         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1071
1072         bce_probe_pci_caps(dev, sc);
1073
1074         rid = 1;
1075         count = 0;
1076 #if 0
1077         /* Try allocating MSI-X interrupts. */
1078         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1079                 (bce_msi_enable >= 2) &&
1080                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1081                 &rid, RF_ACTIVE)) != NULL)) {
1082
1083                 msi_needed = count = 1;
1084
1085                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1086                         (count != msi_needed)) {
1087                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1088                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1089                                 msi_needed, count, error);
1090                         count = 0;
1091                         pci_release_msi(dev);
1092                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1093                                 sc->bce_res_irq);
1094                         sc->bce_res_irq = NULL;
1095                 } else {
1096                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1097                                 __FUNCTION__);
1098                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1099                 }
1100         }
1101 #endif
1102
1103         /* Try allocating a MSI interrupt. */
1104         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1105                 (bce_msi_enable >= 1) && (count == 0)) {
1106                 count = 1;
1107                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1108                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1109                             "error = %d\n", __FILE__, __LINE__, error);
1110                         count = 0;
1111                         pci_release_msi(dev);
1112                 } else {
1113                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1114                             "interrupt.\n", __FUNCTION__);
1115                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1116                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1117                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1118                         rid = 1;
1119                 }
1120         }
1121
1122         /* Try allocating a legacy interrupt. */
1123         if (count == 0) {
1124                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1125                         __FUNCTION__);
1126                 rid = 0;
1127         }
1128
1129         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1130             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1131
1132         /* Report any IRQ allocation errors. */
1133         if (sc->bce_res_irq == NULL) {
1134                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1135                     __FILE__, __LINE__);
1136                 rc = ENXIO;
1137                 goto bce_attach_fail;
1138         }
1139
1140         /* Initialize mutex for the current device instance. */
1141         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1142
1143         /*
1144          * Configure byte swap and enable indirect register access.
1145          * Rely on CPU to do target byte swapping on big endian systems.
1146          * Access to registers outside of PCI configurtion space are not
1147          * valid until this is done.
1148          */
1149         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1150             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1151             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1152
1153         /* Save ASIC revsion info. */
1154         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1155
1156         /* Weed out any non-production controller revisions. */
1157         switch(BCE_CHIP_ID(sc)) {
1158         case BCE_CHIP_ID_5706_A0:
1159         case BCE_CHIP_ID_5706_A1:
1160         case BCE_CHIP_ID_5708_A0:
1161         case BCE_CHIP_ID_5708_B0:
1162         case BCE_CHIP_ID_5709_A0:
1163         case BCE_CHIP_ID_5709_B0:
1164         case BCE_CHIP_ID_5709_B1:
1165         case BCE_CHIP_ID_5709_B2:
1166                 BCE_PRINTF("%s(%d): Unsupported controller "
1167                     "revision (%c%d)!\n", __FILE__, __LINE__,
1168                     (((pci_read_config(dev, PCIR_REVID, 4) &
1169                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1170                     PCIR_REVID, 4) & 0xf));
1171                 rc = ENODEV;
1172                 goto bce_attach_fail;
1173         }
1174
1175         /*
1176          * The embedded PCIe to PCI-X bridge (EPB)
1177          * in the 5708 cannot address memory above
1178          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1179          */
1180         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1181                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1182         else
1183                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1184
1185         /*
1186          * Find the base address for shared memory access.
1187          * Newer versions of bootcode use a signature and offset
1188          * while older versions use a fixed address.
1189          */
1190         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1191         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1192                 /* Multi-port devices use different offsets in shared memory. */
1193                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1194                     (pci_get_function(sc->bce_dev) << 2));
1195         else
1196                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1197
1198         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1199             __FUNCTION__, sc->bce_shmem_base);
1200
1201         /* Fetch the bootcode revision. */
1202         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1203         for (int i = 0, j = 0; i < 3; i++) {
1204                 u8 num;
1205
1206                 num = (u8) (val >> (24 - (i * 8)));
1207                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1208                         if (num >= k || !skip0 || k == 1) {
1209                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1210                                 skip0 = 0;
1211                         }
1212                 }
1213
1214                 if (i != 2)
1215                         sc->bce_bc_ver[j++] = '.';
1216         }
1217
1218         /* Check if any management firwmare is enabled. */
1219         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1220         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1221                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1222
1223                 /* Allow time for firmware to enter the running state. */
1224                 for (int i = 0; i < 30; i++) {
1225                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1226                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1227                                 break;
1228                         DELAY(10000);
1229                 }
1230
1231                 /* Check if management firmware is running. */
1232                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1233                 val &= BCE_CONDITION_MFW_RUN_MASK;
1234                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1235                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1236                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1237                         int i = 0;
1238
1239                         /* Read the management firmware version string. */
1240                         for (int j = 0; j < 3; j++) {
1241                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1242                                 val = bswap32(val);
1243                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1244                                 i += 4;
1245                         }
1246                 } else {
1247                         /* May cause firmware synchronization timeouts. */
1248                         BCE_PRINTF("%s(%d): Management firmware enabled "
1249                             "but not running!\n", __FILE__, __LINE__);
1250                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1251
1252                         /* ToDo: Any action the driver should take? */
1253                 }
1254         }
1255
1256         /* Get PCI bus information (speed and type). */
1257         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1258         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1259                 u32 clkreg;
1260
1261                 sc->bce_flags |= BCE_PCIX_FLAG;
1262
1263                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1264
1265                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1266                 switch (clkreg) {
1267                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1268                         sc->bus_speed_mhz = 133;
1269                         break;
1270
1271                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1272                         sc->bus_speed_mhz = 100;
1273                         break;
1274
1275                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1276                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1277                         sc->bus_speed_mhz = 66;
1278                         break;
1279
1280                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1281                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1282                         sc->bus_speed_mhz = 50;
1283                         break;
1284
1285                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1286                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1287                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1288                         sc->bus_speed_mhz = 33;
1289                         break;
1290                 }
1291         } else {
1292                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1293                         sc->bus_speed_mhz = 66;
1294                 else
1295                         sc->bus_speed_mhz = 33;
1296         }
1297
1298         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1299                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1300
1301         /* Find the media type for the adapter. */
1302         bce_get_media(sc);
1303
1304         /* Reset controller and announce to bootcode that driver is present. */
1305         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1306                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1307                     __FILE__, __LINE__);
1308                 rc = ENXIO;
1309                 goto bce_attach_fail;
1310         }
1311
1312         /* Initialize the controller. */
1313         if (bce_chipinit(sc)) {
1314                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1315                     __FILE__, __LINE__);
1316                 rc = ENXIO;
1317                 goto bce_attach_fail;
1318         }
1319
1320         /* Perform NVRAM test. */
1321         if (bce_nvram_test(sc)) {
1322                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1323                     __FILE__, __LINE__);
1324                 rc = ENXIO;
1325                 goto bce_attach_fail;
1326         }
1327
1328         /* Fetch the permanent Ethernet MAC address. */
1329         bce_get_mac_addr(sc);
1330
1331         /*
1332          * Trip points control how many BDs
1333          * should be ready before generating an
1334          * interrupt while ticks control how long
1335          * a BD can sit in the chain before
1336          * generating an interrupt.  Set the default
1337          * values for the RX and TX chains.
1338          */
1339
1340         /* Not used for L2. */
1341         sc->bce_comp_prod_trip_int     = 0;
1342         sc->bce_comp_prod_trip         = 0;
1343         sc->bce_com_ticks_int          = 0;
1344         sc->bce_com_ticks              = 0;
1345         sc->bce_cmd_ticks_int          = 0;
1346         sc->bce_cmd_ticks              = 0;
1347
1348         /* Update statistics once every second. */
1349         sc->bce_stats_ticks = 1000000 & 0xffff00;
1350
1351         /* Store data needed by PHY driver for backplane applications */
1352         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1353         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1354
1355         /* Allocate DMA memory resources. */
1356         if (bce_dma_alloc(dev)) {
1357                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1358                     __FILE__, __LINE__);
1359                 rc = ENXIO;
1360                 goto bce_attach_fail;
1361         }
1362
1363         /* Allocate an ifnet structure. */
1364         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1365         if (ifp == NULL) {
1366                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1367                     __FILE__, __LINE__);
1368                 rc = ENXIO;
1369                 goto bce_attach_fail;
1370         }
1371
1372         /* Initialize the ifnet interface. */
1373         ifp->if_softc   = sc;
1374         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1375         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1376         ifp->if_ioctl   = bce_ioctl;
1377         ifp->if_start   = bce_start;
1378         ifp->if_init    = bce_init;
1379         ifp->if_mtu     = ETHERMTU;
1380
1381         if (bce_tso_enable) {
1382                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1383                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1384                     IFCAP_VLAN_HWTSO;
1385         } else {
1386                 ifp->if_hwassist = BCE_IF_HWASSIST;
1387                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1388         }
1389
1390 #if __FreeBSD_version >= 800505
1391         /*
1392          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1393          * so it's approximate value.
1394          */
1395         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1396                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1397 #endif
1398
1399         ifp->if_capenable = ifp->if_capabilities;
1400
1401         /*
1402          * Assume standard mbuf sizes for buffer allocation.
1403          * This may change later if the MTU size is set to
1404          * something other than 1500.
1405          */
1406         bce_get_rx_buffer_sizes(sc,
1407             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1408
1409         /* Recalculate our buffer allocation sizes. */
1410         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1411         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1412         IFQ_SET_READY(&ifp->if_snd);
1413
1414         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1415                 ifp->if_baudrate = IF_Mbps(2500ULL);
1416         else
1417                 ifp->if_baudrate = IF_Mbps(1000);
1418
1419         /* Handle any special PHY initialization for SerDes PHYs. */
1420         bce_init_media(sc);
1421
1422         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1423                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1424                     bce_ifmedia_sts);
1425                 /*
1426                  * We can't manually override remote PHY's link and assume
1427                  * PHY port configuration(Fiber or TP) is not changed after
1428                  * device attach.  This may not be correct though.
1429                  */
1430                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1431                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1432                                 ifmedia_add(&sc->bce_ifmedia,
1433                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1434                                 ifmedia_add(&sc->bce_ifmedia,
1435                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1436                         }
1437                         ifmedia_add(&sc->bce_ifmedia,
1438                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1439                         ifmedia_add(&sc->bce_ifmedia,
1440                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1441                 } else {
1442                         ifmedia_add(&sc->bce_ifmedia,
1443                             IFM_ETHER | IFM_10_T, 0, NULL);
1444                         ifmedia_add(&sc->bce_ifmedia,
1445                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1446                         ifmedia_add(&sc->bce_ifmedia,
1447                             IFM_ETHER | IFM_100_TX, 0, NULL);
1448                         ifmedia_add(&sc->bce_ifmedia,
1449                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1450                         ifmedia_add(&sc->bce_ifmedia,
1451                             IFM_ETHER | IFM_1000_T, 0, NULL);
1452                         ifmedia_add(&sc->bce_ifmedia,
1453                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1454                 }
1455                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1456                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1457                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1458         } else {
1459                 /* MII child bus by attaching the PHY. */
1460                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1461                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1462                     MII_OFFSET_ANY, MIIF_DOPAUSE | MIIF_FORCEPAUSE);
1463                 if (rc != 0) {
1464                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1465                             __LINE__);
1466                         goto bce_attach_fail;
1467                 }
1468         }
1469
1470         /* Attach to the Ethernet interface list. */
1471         ether_ifattach(ifp, sc->eaddr);
1472
1473 #if __FreeBSD_version < 500000
1474         callout_init(&sc->bce_tick_callout);
1475         callout_init(&sc->bce_pulse_callout);
1476 #else
1477         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1478         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1479 #endif
1480
1481         /* Hookup IRQ last. */
1482         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1483                 NULL, bce_intr, sc, &sc->bce_intrhand);
1484
1485         if (rc) {
1486                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1487                     __FILE__, __LINE__);
1488                 bce_detach(dev);
1489                 goto bce_attach_exit;
1490         }
1491
1492         /*
1493          * At this point we've acquired all the resources
1494          * we need to run so there's no turning back, we're
1495          * cleared for launch.
1496          */
1497
1498         /* Print some important debugging info. */
1499         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1500
1501         /* Add the supported sysctls to the kernel. */
1502         bce_add_sysctls(sc);
1503
1504         BCE_LOCK(sc);
1505
1506         /*
1507          * The chip reset earlier notified the bootcode that
1508          * a driver is present.  We now need to start our pulse
1509          * routine so that the bootcode is reminded that we're
1510          * still running.
1511          */
1512         bce_pulse(sc);
1513
1514         bce_mgmt_init_locked(sc);
1515         BCE_UNLOCK(sc);
1516
1517         /* Finally, print some useful adapter info */
1518         bce_print_adapter_info(sc);
1519         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1520                 __FUNCTION__, sc);
1521
1522         goto bce_attach_exit;
1523
1524 bce_attach_fail:
1525         bce_release_resources(sc);
1526
1527 bce_attach_exit:
1528
1529         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1530
1531         return(rc);
1532 }
1533
1534
1535 /****************************************************************************/
1536 /* Device detach function.                                                  */
1537 /*                                                                          */
1538 /* Stops the controller, resets the controller, and releases resources.     */
1539 /*                                                                          */
1540 /* Returns:                                                                 */
1541 /*   0 on success, positive value on failure.                               */
1542 /****************************************************************************/
1543 static int
1544 bce_detach(device_t dev)
1545 {
1546         struct bce_softc *sc = device_get_softc(dev);
1547         struct ifnet *ifp;
1548         u32 msg;
1549
1550         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1551
1552         ifp = sc->bce_ifp;
1553
1554         /* Stop and reset the controller. */
1555         BCE_LOCK(sc);
1556
1557         /* Stop the pulse so the bootcode can go to driver absent state. */
1558         callout_stop(&sc->bce_pulse_callout);
1559
1560         bce_stop(sc);
1561         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1562                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1563         else
1564                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1565         bce_reset(sc, msg);
1566
1567         BCE_UNLOCK(sc);
1568
1569         ether_ifdetach(ifp);
1570
1571         /* If we have a child device on the MII bus remove it too. */
1572         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1573                 ifmedia_removeall(&sc->bce_ifmedia);
1574         else {
1575                 bus_generic_detach(dev);
1576                 device_delete_child(dev, sc->bce_miibus);
1577         }
1578
1579         /* Release all remaining resources. */
1580         bce_release_resources(sc);
1581
1582         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1583
1584         return(0);
1585 }
1586
1587
1588 /****************************************************************************/
1589 /* Device shutdown function.                                                */
1590 /*                                                                          */
1591 /* Stops and resets the controller.                                         */
1592 /*                                                                          */
1593 /* Returns:                                                                 */
1594 /*   0 on success, positive value on failure.                               */
1595 /****************************************************************************/
1596 static int
1597 bce_shutdown(device_t dev)
1598 {
1599         struct bce_softc *sc = device_get_softc(dev);
1600         u32 msg;
1601
1602         DBENTER(BCE_VERBOSE);
1603
1604         BCE_LOCK(sc);
1605         bce_stop(sc);
1606         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1607                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1608         else
1609                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1610         bce_reset(sc, msg);
1611         BCE_UNLOCK(sc);
1612
1613         DBEXIT(BCE_VERBOSE);
1614
1615         return (0);
1616 }
1617
1618
1619 #ifdef BCE_DEBUG
1620 /****************************************************************************/
1621 /* Register read.                                                           */
1622 /*                                                                          */
1623 /* Returns:                                                                 */
1624 /*   The value of the register.                                             */
1625 /****************************************************************************/
1626 static u32
1627 bce_reg_rd(struct bce_softc *sc, u32 offset)
1628 {
1629         u32 val = REG_RD(sc, offset);
1630         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1631                 __FUNCTION__, offset, val);
1632         return val;
1633 }
1634
1635
1636 /****************************************************************************/
1637 /* Register write (16 bit).                                                 */
1638 /*                                                                          */
1639 /* Returns:                                                                 */
1640 /*   Nothing.                                                               */
1641 /****************************************************************************/
1642 static void
1643 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1644 {
1645         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1646                 __FUNCTION__, offset, val);
1647         REG_WR16(sc, offset, val);
1648 }
1649
1650
1651 /****************************************************************************/
1652 /* Register write.                                                          */
1653 /*                                                                          */
1654 /* Returns:                                                                 */
1655 /*   Nothing.                                                               */
1656 /****************************************************************************/
1657 static void
1658 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1659 {
1660         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1661                 __FUNCTION__, offset, val);
1662         REG_WR(sc, offset, val);
1663 }
1664 #endif
1665
1666 /****************************************************************************/
1667 /* Indirect register read.                                                  */
1668 /*                                                                          */
1669 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1670 /* configuration space.  Using this mechanism avoids issues with posted     */
1671 /* reads but is much slower than memory-mapped I/O.                         */
1672 /*                                                                          */
1673 /* Returns:                                                                 */
1674 /*   The value of the register.                                             */
1675 /****************************************************************************/
1676 static u32
1677 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1678 {
1679         device_t dev;
1680         dev = sc->bce_dev;
1681
1682         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1683 #ifdef BCE_DEBUG
1684         {
1685                 u32 val;
1686                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1687                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1688                         __FUNCTION__, offset, val);
1689                 return val;
1690         }
1691 #else
1692         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1693 #endif
1694 }
1695
1696
1697 /****************************************************************************/
1698 /* Indirect register write.                                                 */
1699 /*                                                                          */
1700 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1701 /* configuration space.  Using this mechanism avoids issues with posted     */
1702 /* writes but is muchh slower than memory-mapped I/O.                       */
1703 /*                                                                          */
1704 /* Returns:                                                                 */
1705 /*   Nothing.                                                               */
1706 /****************************************************************************/
1707 static void
1708 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1709 {
1710         device_t dev;
1711         dev = sc->bce_dev;
1712
1713         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1714                 __FUNCTION__, offset, val);
1715
1716         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1717         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1718 }
1719
1720
1721 /****************************************************************************/
1722 /* Shared memory write.                                                     */
1723 /*                                                                          */
1724 /* Writes NetXtreme II shared memory region.                                */
1725 /*                                                                          */
1726 /* Returns:                                                                 */
1727 /*   Nothing.                                                               */
1728 /****************************************************************************/
1729 static void
1730 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1731 {
1732         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1733             "0x%08X\n", __FUNCTION__, val, offset);
1734
1735         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1736 }
1737
1738
1739 /****************************************************************************/
1740 /* Shared memory read.                                                      */
1741 /*                                                                          */
1742 /* Reads NetXtreme II shared memory region.                                 */
1743 /*                                                                          */
1744 /* Returns:                                                                 */
1745 /*   The 32 bit value read.                                                 */
1746 /****************************************************************************/
1747 static u32
1748 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1749 {
1750         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1751
1752         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1753             "0x%08X\n", __FUNCTION__, val, offset);
1754
1755         return val;
1756 }
1757
1758
1759 #ifdef BCE_DEBUG
1760 /****************************************************************************/
1761 /* Context memory read.                                                     */
1762 /*                                                                          */
1763 /* The NetXtreme II controller uses context memory to track connection      */
1764 /* information for L2 and higher network protocols.                         */
1765 /*                                                                          */
1766 /* Returns:                                                                 */
1767 /*   The requested 32 bit value of context memory.                          */
1768 /****************************************************************************/
1769 static u32
1770 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1771 {
1772         u32 idx, offset, retry_cnt = 5, val;
1773
1774         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1775             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1776             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1777
1778         offset = ctx_offset + cid_addr;
1779
1780         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1781
1782                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1783
1784                 for (idx = 0; idx < retry_cnt; idx++) {
1785                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1786                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1787                                 break;
1788                         DELAY(5);
1789                 }
1790
1791                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1792                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1793                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1794                             __FILE__, __LINE__, cid_addr, ctx_offset);
1795
1796                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1797         } else {
1798                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1799                 val = REG_RD(sc, BCE_CTX_DATA);
1800         }
1801
1802         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1803                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1804
1805         return(val);
1806 }
1807 #endif
1808
1809
1810 /****************************************************************************/
1811 /* Context memory write.                                                    */
1812 /*                                                                          */
1813 /* The NetXtreme II controller uses context memory to track connection      */
1814 /* information for L2 and higher network protocols.                         */
1815 /*                                                                          */
1816 /* Returns:                                                                 */
1817 /*   Nothing.                                                               */
1818 /****************************************************************************/
1819 static void
1820 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1821 {
1822         u32 idx, offset = ctx_offset + cid_addr;
1823         u32 val, retry_cnt = 5;
1824
1825         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1826                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1827
1828         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1829                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1830                     __FUNCTION__, cid_addr));
1831
1832         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1833
1834                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1835                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1836
1837                 for (idx = 0; idx < retry_cnt; idx++) {
1838                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1839                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1840                                 break;
1841                         DELAY(5);
1842                 }
1843
1844                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1845                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1846                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1847                             __FILE__, __LINE__, cid_addr, ctx_offset);
1848
1849         } else {
1850                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1851                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1852         }
1853 }
1854
1855
1856 /****************************************************************************/
1857 /* PHY register read.                                                       */
1858 /*                                                                          */
1859 /* Implements register reads on the MII bus.                                */
1860 /*                                                                          */
1861 /* Returns:                                                                 */
1862 /*   The value of the register.                                             */
1863 /****************************************************************************/
1864 static int
1865 bce_miibus_read_reg(device_t dev, int phy, int reg)
1866 {
1867         struct bce_softc *sc;
1868         u32 val;
1869         int i;
1870
1871         sc = device_get_softc(dev);
1872
1873     /*
1874      * The 5709S PHY is an IEEE Clause 45 PHY
1875      * with special mappings to work with IEEE
1876      * Clause 22 register accesses.
1877      */
1878         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1879                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1880                         reg += 0x10;
1881         }
1882
1883     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1884                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1885                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1886
1887                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1888                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1889
1890                 DELAY(40);
1891         }
1892
1893
1894         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1895             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1896             BCE_EMAC_MDIO_COMM_START_BUSY;
1897         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1898
1899         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1900                 DELAY(10);
1901
1902                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1903                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1904                         DELAY(5);
1905
1906                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1907                         val &= BCE_EMAC_MDIO_COMM_DATA;
1908
1909                         break;
1910                 }
1911         }
1912
1913         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1914                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1915                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1916                 val = 0x0;
1917         } else {
1918                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1919         }
1920
1921
1922         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1923                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1924                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1925
1926                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1927                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1928
1929                 DELAY(40);
1930         }
1931
1932         DB_PRINT_PHY_REG(reg, val);
1933         return (val & 0xffff);
1934
1935 }
1936
1937
1938 /****************************************************************************/
1939 /* PHY register write.                                                      */
1940 /*                                                                          */
1941 /* Implements register writes on the MII bus.                               */
1942 /*                                                                          */
1943 /* Returns:                                                                 */
1944 /*   The value of the register.                                             */
1945 /****************************************************************************/
1946 static int
1947 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1948 {
1949         struct bce_softc *sc;
1950         u32 val1;
1951         int i;
1952
1953         sc = device_get_softc(dev);
1954
1955         DB_PRINT_PHY_REG(reg, val);
1956
1957         /*
1958          * The 5709S PHY is an IEEE Clause 45 PHY
1959          * with special mappings to work with IEEE
1960          * Clause 22 register accesses.
1961          */
1962         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1963                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1964                         reg += 0x10;
1965         }
1966
1967         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1968                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1969                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1970
1971                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1972                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1973
1974                 DELAY(40);
1975         }
1976
1977         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1978             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1979             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1980         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1981
1982         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1983                 DELAY(10);
1984
1985                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1986                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1987                         DELAY(5);
1988                         break;
1989                 }
1990         }
1991
1992         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1993                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1994                     __FILE__, __LINE__);
1995
1996         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1997                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1998                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1999
2000                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2001                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2002
2003                 DELAY(40);
2004         }
2005
2006         return 0;
2007 }
2008
2009
2010 /****************************************************************************/
2011 /* MII bus status change.                                                   */
2012 /*                                                                          */
2013 /* Called by the MII bus driver when the PHY establishes link to set the    */
2014 /* MAC interface registers.                                                 */
2015 /*                                                                          */
2016 /* Returns:                                                                 */
2017 /*   Nothing.                                                               */
2018 /****************************************************************************/
2019 static void
2020 bce_miibus_statchg(device_t dev)
2021 {
2022         struct bce_softc *sc;
2023         struct mii_data *mii;
2024         struct ifmediareq ifmr;
2025         int media_active, media_status, val;
2026
2027         sc = device_get_softc(dev);
2028
2029         DBENTER(BCE_VERBOSE_PHY);
2030
2031         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2032                 bzero(&ifmr, sizeof(ifmr));
2033                 bce_ifmedia_sts_rphy(sc, &ifmr);
2034                 media_active = ifmr.ifm_active;
2035                 media_status = ifmr.ifm_status;
2036         } else {
2037                 mii = device_get_softc(sc->bce_miibus);
2038                 media_active = mii->mii_media_active;
2039                 media_status = mii->mii_media_status;
2040         }
2041
2042         /* Ignore invalid media status. */
2043         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2044             (IFM_ACTIVE | IFM_AVALID))
2045                 goto bce_miibus_statchg_exit;
2046
2047         val = REG_RD(sc, BCE_EMAC_MODE);
2048         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2049             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2050             BCE_EMAC_MODE_25G);
2051
2052         /* Set MII or GMII interface based on the PHY speed. */
2053         switch (IFM_SUBTYPE(media_active)) {
2054         case IFM_10_T:
2055                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2056                         DBPRINT(sc, BCE_INFO_PHY,
2057                             "Enabling 10Mb interface.\n");
2058                         val |= BCE_EMAC_MODE_PORT_MII_10;
2059                         break;
2060                 }
2061                 /* fall-through */
2062         case IFM_100_TX:
2063                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2064                 val |= BCE_EMAC_MODE_PORT_MII;
2065                 break;
2066         case IFM_2500_SX:
2067                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2068                 val |= BCE_EMAC_MODE_25G;
2069                 /* fall-through */
2070         case IFM_1000_T:
2071         case IFM_1000_SX:
2072                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2073                 val |= BCE_EMAC_MODE_PORT_GMII;
2074                 break;
2075         default:
2076                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2077                     "default GMII interface.\n");
2078                 val |= BCE_EMAC_MODE_PORT_GMII;
2079         }
2080
2081         /* Set half or full duplex based on PHY settings. */
2082         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2083                 DBPRINT(sc, BCE_INFO_PHY,
2084                     "Setting Half-Duplex interface.\n");
2085                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2086         } else
2087                 DBPRINT(sc, BCE_INFO_PHY,
2088                     "Setting Full-Duplex interface.\n");
2089
2090         REG_WR(sc, BCE_EMAC_MODE, val);
2091
2092         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2093                 DBPRINT(sc, BCE_INFO_PHY,
2094                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2095                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2096                 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2097         } else {
2098                 DBPRINT(sc, BCE_INFO_PHY,
2099                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2100                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2101                 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2102         }
2103
2104         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2105                 DBPRINT(sc, BCE_INFO_PHY,
2106                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2107                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2108                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2109         } else {
2110                 DBPRINT(sc, BCE_INFO_PHY,
2111                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2112                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2113                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2114         }
2115
2116         /* ToDo: Update watermarks in bce_init_rx_context(). */
2117
2118 bce_miibus_statchg_exit:
2119         DBEXIT(BCE_VERBOSE_PHY);
2120 }
2121
2122
2123 /****************************************************************************/
2124 /* Acquire NVRAM lock.                                                      */
2125 /*                                                                          */
2126 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2127 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2128 /* for use by the driver.                                                   */
2129 /*                                                                          */
2130 /* Returns:                                                                 */
2131 /*   0 on success, positive value on failure.                               */
2132 /****************************************************************************/
2133 static int
2134 bce_acquire_nvram_lock(struct bce_softc *sc)
2135 {
2136         u32 val;
2137         int j, rc = 0;
2138
2139         DBENTER(BCE_VERBOSE_NVRAM);
2140
2141         /* Request access to the flash interface. */
2142         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2143         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2144                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2145                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2146                         break;
2147
2148                 DELAY(5);
2149         }
2150
2151         if (j >= NVRAM_TIMEOUT_COUNT) {
2152                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2153                 rc = EBUSY;
2154         }
2155
2156         DBEXIT(BCE_VERBOSE_NVRAM);
2157         return (rc);
2158 }
2159
2160
2161 /****************************************************************************/
2162 /* Release NVRAM lock.                                                      */
2163 /*                                                                          */
2164 /* When the caller is finished accessing NVRAM the lock must be released.   */
2165 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2166 /* for use by the driver.                                                   */
2167 /*                                                                          */
2168 /* Returns:                                                                 */
2169 /*   0 on success, positive value on failure.                               */
2170 /****************************************************************************/
2171 static int
2172 bce_release_nvram_lock(struct bce_softc *sc)
2173 {
2174         u32 val;
2175         int j, rc = 0;
2176
2177         DBENTER(BCE_VERBOSE_NVRAM);
2178
2179         /*
2180          * Relinquish nvram interface.
2181          */
2182         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2183
2184         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2185                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2186                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2187                         break;
2188
2189                 DELAY(5);
2190         }
2191
2192         if (j >= NVRAM_TIMEOUT_COUNT) {
2193                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2194                 rc = EBUSY;
2195         }
2196
2197         DBEXIT(BCE_VERBOSE_NVRAM);
2198         return (rc);
2199 }
2200
2201
2202 #ifdef BCE_NVRAM_WRITE_SUPPORT
2203 /****************************************************************************/
2204 /* Enable NVRAM write access.                                               */
2205 /*                                                                          */
2206 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2207 /*                                                                          */
2208 /* Returns:                                                                 */
2209 /*   0 on success, positive value on failure.                               */
2210 /****************************************************************************/
2211 static int
2212 bce_enable_nvram_write(struct bce_softc *sc)
2213 {
2214         u32 val;
2215         int rc = 0;
2216
2217         DBENTER(BCE_VERBOSE_NVRAM);
2218
2219         val = REG_RD(sc, BCE_MISC_CFG);
2220         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2221
2222         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2223                 int j;
2224
2225                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2226                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2227
2228                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2229                         DELAY(5);
2230
2231                         val = REG_RD(sc, BCE_NVM_COMMAND);
2232                         if (val & BCE_NVM_COMMAND_DONE)
2233                                 break;
2234                 }
2235
2236                 if (j >= NVRAM_TIMEOUT_COUNT) {
2237                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2238                         rc = EBUSY;
2239                 }
2240         }
2241
2242         DBENTER(BCE_VERBOSE_NVRAM);
2243         return (rc);
2244 }
2245
2246
2247 /****************************************************************************/
2248 /* Disable NVRAM write access.                                              */
2249 /*                                                                          */
2250 /* When the caller is finished writing to NVRAM write access must be        */
2251 /* disabled.                                                                */
2252 /*                                                                          */
2253 /* Returns:                                                                 */
2254 /*   Nothing.                                                               */
2255 /****************************************************************************/
2256 static void
2257 bce_disable_nvram_write(struct bce_softc *sc)
2258 {
2259         u32 val;
2260
2261         DBENTER(BCE_VERBOSE_NVRAM);
2262
2263         val = REG_RD(sc, BCE_MISC_CFG);
2264         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2265
2266         DBEXIT(BCE_VERBOSE_NVRAM);
2267
2268 }
2269 #endif
2270
2271
2272 /****************************************************************************/
2273 /* Enable NVRAM access.                                                     */
2274 /*                                                                          */
2275 /* Before accessing NVRAM for read or write operations the caller must      */
2276 /* enabled NVRAM access.                                                    */
2277 /*                                                                          */
2278 /* Returns:                                                                 */
2279 /*   Nothing.                                                               */
2280 /****************************************************************************/
2281 static void
2282 bce_enable_nvram_access(struct bce_softc *sc)
2283 {
2284         u32 val;
2285
2286         DBENTER(BCE_VERBOSE_NVRAM);
2287
2288         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2289         /* Enable both bits, even on read. */
2290         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2291             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2292
2293         DBEXIT(BCE_VERBOSE_NVRAM);
2294 }
2295
2296
2297 /****************************************************************************/
2298 /* Disable NVRAM access.                                                    */
2299 /*                                                                          */
2300 /* When the caller is finished accessing NVRAM access must be disabled.     */
2301 /*                                                                          */
2302 /* Returns:                                                                 */
2303 /*   Nothing.                                                               */
2304 /****************************************************************************/
2305 static void
2306 bce_disable_nvram_access(struct bce_softc *sc)
2307 {
2308         u32 val;
2309
2310         DBENTER(BCE_VERBOSE_NVRAM);
2311
2312         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2313
2314         /* Disable both bits, even after read. */
2315         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2316             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2317
2318         DBEXIT(BCE_VERBOSE_NVRAM);
2319 }
2320
2321
2322 #ifdef BCE_NVRAM_WRITE_SUPPORT
2323 /****************************************************************************/
2324 /* Erase NVRAM page before writing.                                         */
2325 /*                                                                          */
2326 /* Non-buffered flash parts require that a page be erased before it is      */
2327 /* written.                                                                 */
2328 /*                                                                          */
2329 /* Returns:                                                                 */
2330 /*   0 on success, positive value on failure.                               */
2331 /****************************************************************************/
2332 static int
2333 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2334 {
2335         u32 cmd;
2336         int j, rc = 0;
2337
2338         DBENTER(BCE_VERBOSE_NVRAM);
2339
2340         /* Buffered flash doesn't require an erase. */
2341         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2342                 goto bce_nvram_erase_page_exit;
2343
2344         /* Build an erase command. */
2345         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2346             BCE_NVM_COMMAND_DOIT;
2347
2348         /*
2349          * Clear the DONE bit separately, set the NVRAM adress to erase,
2350          * and issue the erase command.
2351          */
2352         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2353         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2354         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2355
2356         /* Wait for completion. */
2357         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2358                 u32 val;
2359
2360                 DELAY(5);
2361
2362                 val = REG_RD(sc, BCE_NVM_COMMAND);
2363                 if (val & BCE_NVM_COMMAND_DONE)
2364                         break;
2365         }
2366
2367         if (j >= NVRAM_TIMEOUT_COUNT) {
2368                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2369                 rc = EBUSY;
2370         }
2371
2372 bce_nvram_erase_page_exit:
2373         DBEXIT(BCE_VERBOSE_NVRAM);
2374         return (rc);
2375 }
2376 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2377
2378
2379 /****************************************************************************/
2380 /* Read a dword (32 bits) from NVRAM.                                       */
2381 /*                                                                          */
2382 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2383 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2384 /*                                                                          */
2385 /* Returns:                                                                 */
2386 /*   0 on success and the 32 bit value read, positive value on failure.     */
2387 /****************************************************************************/
2388 static int
2389 bce_nvram_read_dword(struct bce_softc *sc,
2390     u32 offset, u8 *ret_val, u32 cmd_flags)
2391 {
2392         u32 cmd;
2393         int i, rc = 0;
2394
2395         DBENTER(BCE_EXTREME_NVRAM);
2396
2397         /* Build the command word. */
2398         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2399
2400         /* Calculate the offset for buffered flash if translation is used. */
2401         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2402                 offset = ((offset / sc->bce_flash_info->page_size) <<
2403                     sc->bce_flash_info->page_bits) +
2404                     (offset % sc->bce_flash_info->page_size);
2405         }
2406
2407         /*
2408          * Clear the DONE bit separately, set the address to read,
2409          * and issue the read.
2410          */
2411         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2412         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2413         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2414
2415         /* Wait for completion. */
2416         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2417                 u32 val;
2418
2419                 DELAY(5);
2420
2421                 val = REG_RD(sc, BCE_NVM_COMMAND);
2422                 if (val & BCE_NVM_COMMAND_DONE) {
2423                         val = REG_RD(sc, BCE_NVM_READ);
2424
2425                         val = bce_be32toh(val);
2426                         memcpy(ret_val, &val, 4);
2427                         break;
2428                 }
2429         }
2430
2431         /* Check for errors. */
2432         if (i >= NVRAM_TIMEOUT_COUNT) {
2433                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2434                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2435                 rc = EBUSY;
2436         }
2437
2438         DBEXIT(BCE_EXTREME_NVRAM);
2439         return(rc);
2440 }
2441
2442
2443 #ifdef BCE_NVRAM_WRITE_SUPPORT
2444 /****************************************************************************/
2445 /* Write a dword (32 bits) to NVRAM.                                        */
2446 /*                                                                          */
2447 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2448 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2449 /* enabled NVRAM write access.                                              */
2450 /*                                                                          */
2451 /* Returns:                                                                 */
2452 /*   0 on success, positive value on failure.                               */
2453 /****************************************************************************/
2454 static int
2455 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2456         u32 cmd_flags)
2457 {
2458         u32 cmd, val32;
2459         int j, rc = 0;
2460
2461         DBENTER(BCE_VERBOSE_NVRAM);
2462
2463         /* Build the command word. */
2464         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2465
2466         /* Calculate the offset for buffered flash if translation is used. */
2467         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2468                 offset = ((offset / sc->bce_flash_info->page_size) <<
2469                     sc->bce_flash_info->page_bits) +
2470                     (offset % sc->bce_flash_info->page_size);
2471         }
2472
2473         /*
2474          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2475          * set the NVRAM address to write, and issue the write command
2476          */
2477         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2478         memcpy(&val32, val, 4);
2479         val32 = htobe32(val32);
2480         REG_WR(sc, BCE_NVM_WRITE, val32);
2481         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2482         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2483
2484         /* Wait for completion. */
2485         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2486                 DELAY(5);
2487
2488                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2489                         break;
2490         }
2491         if (j >= NVRAM_TIMEOUT_COUNT) {
2492                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2493                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2494                 rc = EBUSY;
2495         }
2496
2497         DBEXIT(BCE_VERBOSE_NVRAM);
2498         return (rc);
2499 }
2500 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2501
2502
2503 /****************************************************************************/
2504 /* Initialize NVRAM access.                                                 */
2505 /*                                                                          */
2506 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2507 /* access that device.                                                      */
2508 /*                                                                          */
2509 /* Returns:                                                                 */
2510 /*   0 on success, positive value on failure.                               */
2511 /****************************************************************************/
2512 static int
2513 bce_init_nvram(struct bce_softc *sc)
2514 {
2515         u32 val;
2516         int j, entry_count, rc = 0;
2517         const struct flash_spec *flash;
2518
2519         DBENTER(BCE_VERBOSE_NVRAM);
2520
2521         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2522                 sc->bce_flash_info = &flash_5709;
2523                 goto bce_init_nvram_get_flash_size;
2524         }
2525
2526         /* Determine the selected interface. */
2527         val = REG_RD(sc, BCE_NVM_CFG1);
2528
2529         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2530
2531         /*
2532          * Flash reconfiguration is required to support additional
2533          * NVRAM devices not directly supported in hardware.
2534          * Check if the flash interface was reconfigured
2535          * by the bootcode.
2536          */
2537
2538         if (val & 0x40000000) {
2539                 /* Flash interface reconfigured by bootcode. */
2540
2541                 DBPRINT(sc,BCE_INFO_LOAD,
2542                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2543
2544                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2545                      j++, flash++) {
2546                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2547                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2548                                 sc->bce_flash_info = flash;
2549                                 break;
2550                         }
2551                 }
2552         } else {
2553                 /* Flash interface not yet reconfigured. */
2554                 u32 mask;
2555
2556                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2557                         __FUNCTION__);
2558
2559                 if (val & (1 << 23))
2560                         mask = FLASH_BACKUP_STRAP_MASK;
2561                 else
2562                         mask = FLASH_STRAP_MASK;
2563
2564                 /* Look for the matching NVRAM device configuration data. */
2565                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2566
2567                         /* Check if the device matches any of the known devices. */
2568                         if ((val & mask) == (flash->strapping & mask)) {
2569                                 /* Found a device match. */
2570                                 sc->bce_flash_info = flash;
2571
2572                                 /* Request access to the flash interface. */
2573                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2574                                         return rc;
2575
2576                                 /* Reconfigure the flash interface. */
2577                                 bce_enable_nvram_access(sc);
2578                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2579                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2580                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2581                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2582                                 bce_disable_nvram_access(sc);
2583                                 bce_release_nvram_lock(sc);
2584
2585                                 break;
2586                         }
2587                 }
2588         }
2589
2590         /* Check if a matching device was found. */
2591         if (j == entry_count) {
2592                 sc->bce_flash_info = NULL;
2593                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2594                     __FILE__, __LINE__);
2595                 DBEXIT(BCE_VERBOSE_NVRAM);
2596                 return (ENODEV);
2597         }
2598
2599 bce_init_nvram_get_flash_size:
2600         /* Write the flash config data to the shared memory interface. */
2601         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2602         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2603         if (val)
2604                 sc->bce_flash_size = val;
2605         else
2606                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2607
2608         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2609             __FUNCTION__, sc->bce_flash_info->name,
2610             sc->bce_flash_info->total_size);
2611
2612         DBEXIT(BCE_VERBOSE_NVRAM);
2613         return rc;
2614 }
2615
2616
2617 /****************************************************************************/
2618 /* Read an arbitrary range of data from NVRAM.                              */
2619 /*                                                                          */
2620 /* Prepares the NVRAM interface for access and reads the requested data     */
2621 /* into the supplied buffer.                                                */
2622 /*                                                                          */
2623 /* Returns:                                                                 */
2624 /*   0 on success and the data read, positive value on failure.             */
2625 /****************************************************************************/
2626 static int
2627 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2628         int buf_size)
2629 {
2630         int rc = 0;
2631         u32 cmd_flags, offset32, len32, extra;
2632
2633         DBENTER(BCE_VERBOSE_NVRAM);
2634
2635         if (buf_size == 0)
2636                 goto bce_nvram_read_exit;
2637
2638         /* Request access to the flash interface. */
2639         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2640                 goto bce_nvram_read_exit;
2641
2642         /* Enable access to flash interface */
2643         bce_enable_nvram_access(sc);
2644
2645         len32 = buf_size;
2646         offset32 = offset;
2647         extra = 0;
2648
2649         cmd_flags = 0;
2650
2651         if (offset32 & 3) {
2652                 u8 buf[4];
2653                 u32 pre_len;
2654
2655                 offset32 &= ~3;
2656                 pre_len = 4 - (offset & 3);
2657
2658                 if (pre_len >= len32) {
2659                         pre_len = len32;
2660                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2661                 }
2662                 else {
2663                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2664                 }
2665
2666                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2667
2668                 if (rc)
2669                         return rc;
2670
2671                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2672
2673                 offset32 += 4;
2674                 ret_buf += pre_len;
2675                 len32 -= pre_len;
2676         }
2677
2678         if (len32 & 3) {
2679                 extra = 4 - (len32 & 3);
2680                 len32 = (len32 + 4) & ~3;
2681         }
2682
2683         if (len32 == 4) {
2684                 u8 buf[4];
2685
2686                 if (cmd_flags)
2687                         cmd_flags = BCE_NVM_COMMAND_LAST;
2688                 else
2689                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2690                                     BCE_NVM_COMMAND_LAST;
2691
2692                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2693
2694                 memcpy(ret_buf, buf, 4 - extra);
2695         }
2696         else if (len32 > 0) {
2697                 u8 buf[4];
2698
2699                 /* Read the first word. */
2700                 if (cmd_flags)
2701                         cmd_flags = 0;
2702                 else
2703                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2704
2705                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2706
2707                 /* Advance to the next dword. */
2708                 offset32 += 4;
2709                 ret_buf += 4;
2710                 len32 -= 4;
2711
2712                 while (len32 > 4 && rc == 0) {
2713                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2714
2715                         /* Advance to the next dword. */
2716                         offset32 += 4;
2717                         ret_buf += 4;
2718                         len32 -= 4;
2719                 }
2720
2721                 if (rc)
2722                         goto bce_nvram_read_locked_exit;
2723
2724                 cmd_flags = BCE_NVM_COMMAND_LAST;
2725                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2726
2727                 memcpy(ret_buf, buf, 4 - extra);
2728         }
2729
2730 bce_nvram_read_locked_exit:
2731         /* Disable access to flash interface and release the lock. */
2732         bce_disable_nvram_access(sc);
2733         bce_release_nvram_lock(sc);
2734
2735 bce_nvram_read_exit:
2736         DBEXIT(BCE_VERBOSE_NVRAM);
2737         return rc;
2738 }
2739
2740
2741 #ifdef BCE_NVRAM_WRITE_SUPPORT
2742 /****************************************************************************/
2743 /* Write an arbitrary range of data from NVRAM.                             */
2744 /*                                                                          */
2745 /* Prepares the NVRAM interface for write access and writes the requested   */
2746 /* data from the supplied buffer.  The caller is responsible for            */
2747 /* calculating any appropriate CRCs.                                        */
2748 /*                                                                          */
2749 /* Returns:                                                                 */
2750 /*   0 on success, positive value on failure.                               */
2751 /****************************************************************************/
2752 static int
2753 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2754         int buf_size)
2755 {
2756         u32 written, offset32, len32;
2757         u8 *buf, start[4], end[4];
2758         int rc = 0;
2759         int align_start, align_end;
2760
2761         DBENTER(BCE_VERBOSE_NVRAM);
2762
2763         buf = data_buf;
2764         offset32 = offset;
2765         len32 = buf_size;
2766         align_start = align_end = 0;
2767
2768         if ((align_start = (offset32 & 3))) {
2769                 offset32 &= ~3;
2770                 len32 += align_start;
2771                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2772                         goto bce_nvram_write_exit;
2773         }
2774
2775         if (len32 & 3) {
2776                 if ((len32 > 4) || !align_start) {
2777                         align_end = 4 - (len32 & 3);
2778                         len32 += align_end;
2779                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2780                                 end, 4))) {
2781                                 goto bce_nvram_write_exit;
2782                         }
2783                 }
2784         }
2785
2786         if (align_start || align_end) {
2787                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2788                 if (buf == 0) {
2789                         rc = ENOMEM;
2790                         goto bce_nvram_write_exit;
2791                 }
2792
2793                 if (align_start) {
2794                         memcpy(buf, start, 4);
2795                 }
2796
2797                 if (align_end) {
2798                         memcpy(buf + len32 - 4, end, 4);
2799                 }
2800                 memcpy(buf + align_start, data_buf, buf_size);
2801         }
2802
2803         written = 0;
2804         while ((written < len32) && (rc == 0)) {
2805                 u32 page_start, page_end, data_start, data_end;
2806                 u32 addr, cmd_flags;
2807                 int i;
2808                 u8 flash_buffer[264];
2809
2810             /* Find the page_start addr */
2811                 page_start = offset32 + written;
2812                 page_start -= (page_start % sc->bce_flash_info->page_size);
2813                 /* Find the page_end addr */
2814                 page_end = page_start + sc->bce_flash_info->page_size;
2815                 /* Find the data_start addr */
2816                 data_start = (written == 0) ? offset32 : page_start;
2817                 /* Find the data_end addr */
2818                 data_end = (page_end > offset32 + len32) ?
2819                         (offset32 + len32) : page_end;
2820
2821                 /* Request access to the flash interface. */
2822                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2823                         goto bce_nvram_write_exit;
2824
2825                 /* Enable access to flash interface */
2826                 bce_enable_nvram_access(sc);
2827
2828                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2829                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2830                         int j;
2831
2832                         /* Read the whole page into the buffer
2833                          * (non-buffer flash only) */
2834                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2835                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2836                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2837                                 }
2838                                 rc = bce_nvram_read_dword(sc,
2839                                         page_start + j,
2840                                         &flash_buffer[j],
2841                                         cmd_flags);
2842
2843                                 if (rc)
2844                                         goto bce_nvram_write_locked_exit;
2845
2846                                 cmd_flags = 0;
2847                         }
2848                 }
2849
2850                 /* Enable writes to flash interface (unlock write-protect) */
2851                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2852                         goto bce_nvram_write_locked_exit;
2853
2854                 /* Erase the page */
2855                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2856                         goto bce_nvram_write_locked_exit;
2857
2858                 /* Re-enable the write again for the actual write */
2859                 bce_enable_nvram_write(sc);
2860
2861                 /* Loop to write back the buffer data from page_start to
2862                  * data_start */
2863                 i = 0;
2864                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2865                         for (addr = page_start; addr < data_start;
2866                                 addr += 4, i += 4) {
2867
2868                                 rc = bce_nvram_write_dword(sc, addr,
2869                                         &flash_buffer[i], cmd_flags);
2870
2871                                 if (rc != 0)
2872                                         goto bce_nvram_write_locked_exit;
2873
2874                                 cmd_flags = 0;
2875                         }
2876                 }
2877
2878                 /* Loop to write the new data from data_start to data_end */
2879                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2880                         if ((addr == page_end - 4) ||
2881                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2882                                 (addr == data_end - 4))) {
2883
2884                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2885                         }
2886                         rc = bce_nvram_write_dword(sc, addr, buf,
2887                                 cmd_flags);
2888
2889                         if (rc != 0)
2890                                 goto bce_nvram_write_locked_exit;
2891
2892                         cmd_flags = 0;
2893                         buf += 4;
2894                 }
2895
2896                 /* Loop to write back the buffer data from data_end
2897                  * to page_end */
2898                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2899                         for (addr = data_end; addr < page_end;
2900                                 addr += 4, i += 4) {
2901
2902                                 if (addr == page_end-4) {
2903                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2904                                 }
2905                                 rc = bce_nvram_write_dword(sc, addr,
2906                                         &flash_buffer[i], cmd_flags);
2907
2908                                 if (rc != 0)
2909                                         goto bce_nvram_write_locked_exit;
2910
2911                                 cmd_flags = 0;
2912                         }
2913                 }
2914
2915                 /* Disable writes to flash interface (lock write-protect) */
2916                 bce_disable_nvram_write(sc);
2917
2918                 /* Disable access to flash interface */
2919                 bce_disable_nvram_access(sc);
2920                 bce_release_nvram_lock(sc);
2921
2922                 /* Increment written */
2923                 written += data_end - data_start;
2924         }
2925
2926         goto bce_nvram_write_exit;
2927
2928 bce_nvram_write_locked_exit:
2929         bce_disable_nvram_write(sc);
2930         bce_disable_nvram_access(sc);
2931         bce_release_nvram_lock(sc);
2932
2933 bce_nvram_write_exit:
2934         if (align_start || align_end)
2935                 free(buf, M_DEVBUF);
2936
2937         DBEXIT(BCE_VERBOSE_NVRAM);
2938         return (rc);
2939 }
2940 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2941
2942
2943 /****************************************************************************/
2944 /* Verifies that NVRAM is accessible and contains valid data.               */
2945 /*                                                                          */
2946 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2947 /* correct.                                                                 */
2948 /*                                                                          */
2949 /* Returns:                                                                 */
2950 /*   0 on success, positive value on failure.                               */
2951 /****************************************************************************/
2952 static int
2953 bce_nvram_test(struct bce_softc *sc)
2954 {
2955         u32 buf[BCE_NVRAM_SIZE / 4];
2956         u8 *data = (u8 *) buf;
2957         int rc = 0;
2958         u32 magic, csum;
2959
2960         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2961
2962         /*
2963          * Check that the device NVRAM is valid by reading
2964          * the magic value at offset 0.
2965          */
2966         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2967                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2968                     __FILE__, __LINE__);
2969                 goto bce_nvram_test_exit;
2970         }
2971
2972         /*
2973          * Verify that offset 0 of the NVRAM contains
2974          * a valid magic number.
2975          */
2976         magic = bce_be32toh(buf[0]);
2977         if (magic != BCE_NVRAM_MAGIC) {
2978                 rc = ENODEV;
2979                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2980                     "Expected: 0x%08X, Found: 0x%08X\n",
2981                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2982                 goto bce_nvram_test_exit;
2983         }
2984
2985         /*
2986          * Verify that the device NVRAM includes valid
2987          * configuration data.
2988          */
2989         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2990                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2991                     "Information from  NVRAM!\n", __FILE__, __LINE__);
2992                 goto bce_nvram_test_exit;
2993         }
2994
2995         csum = ether_crc32_le(data, 0x100);
2996         if (csum != BCE_CRC32_RESIDUAL) {
2997                 rc = ENODEV;
2998                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2999                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3000                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3001                 goto bce_nvram_test_exit;
3002         }
3003
3004         csum = ether_crc32_le(data + 0x100, 0x100);
3005         if (csum != BCE_CRC32_RESIDUAL) {
3006                 rc = ENODEV;
3007                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3008                     "information NVRAM CRC! Expected: 0x%08X, "
3009                     "Found: 08%08X\n", __FILE__, __LINE__,
3010                     BCE_CRC32_RESIDUAL, csum);
3011         }
3012
3013 bce_nvram_test_exit:
3014         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3015         return rc;
3016 }
3017
3018
3019 /****************************************************************************/
3020 /* Calculates the size of the buffers to allocate based on the MTU.         */
3021 /*                                                                          */
3022 /* Returns:                                                                 */
3023 /*   Nothing.                                                               */
3024 /****************************************************************************/
3025 static void
3026 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3027 {
3028         DBENTER(BCE_VERBOSE_LOAD);
3029
3030         /* Use a single allocation type when header splitting enabled. */
3031         if (bce_hdr_split == TRUE) {
3032                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3033                 /* Make sure offset is 16 byte aligned for hardware. */
3034                 sc->rx_bd_mbuf_align_pad =
3035                         roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3036                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3037                         sc->rx_bd_mbuf_align_pad;
3038                 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
3039         } else {
3040                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3041                     ETHER_CRC_LEN) > MCLBYTES) {
3042                         /* Setup for jumbo RX buffer allocations. */
3043                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3044                         sc->rx_bd_mbuf_align_pad  =
3045                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3046                         sc->rx_bd_mbuf_data_len =
3047                             sc->rx_bd_mbuf_alloc_size -
3048                             sc->rx_bd_mbuf_align_pad;
3049                 } else {
3050                         /* Setup for standard RX buffer allocations. */
3051                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3052                         sc->rx_bd_mbuf_align_pad  =
3053                             roundup2(MCLBYTES, 16) - MCLBYTES;
3054                         sc->rx_bd_mbuf_data_len =
3055                             sc->rx_bd_mbuf_alloc_size -
3056                             sc->rx_bd_mbuf_align_pad;
3057                 }
3058         }
3059
3060 //      DBPRINT(sc, BCE_INFO_LOAD,
3061         DBPRINT(sc, BCE_WARN,
3062            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3063            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3064            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3065            sc->rx_bd_mbuf_align_pad);
3066
3067         DBEXIT(BCE_VERBOSE_LOAD);
3068
3069 }
3070
3071 /****************************************************************************/
3072 /* Identifies the current media type of the controller and sets the PHY     */
3073 /* address.                                                                 */
3074 /*                                                                          */
3075 /* Returns:                                                                 */
3076 /*   Nothing.                                                               */
3077 /****************************************************************************/
3078 static void
3079 bce_get_media(struct bce_softc *sc)
3080 {
3081         u32 val;
3082
3083         DBENTER(BCE_VERBOSE_PHY);
3084
3085         /* Assume PHY address for copper controllers. */
3086         sc->bce_phy_addr = 1;
3087
3088         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3089                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3090                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3091                 u32 strap;
3092
3093                 /*
3094                  * The BCM5709S is software configurable
3095                  * for Copper or SerDes operation.
3096                  */
3097                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3098                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3099                             "for copper.\n");
3100                         goto bce_get_media_exit;
3101                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3102                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3103                             "for dual media.\n");
3104                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3105                         goto bce_get_media_exit;
3106                 }
3107
3108                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3109                         strap = (val &
3110                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3111                 else
3112                         strap = (val &
3113                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3114
3115                 if (pci_get_function(sc->bce_dev) == 0) {
3116                         switch (strap) {
3117                         case 0x4:
3118                         case 0x5:
3119                         case 0x6:
3120                                 DBPRINT(sc, BCE_INFO_LOAD,
3121                                     "BCM5709 s/w configured for SerDes.\n");
3122                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3123                                 break;
3124                         default:
3125                                 DBPRINT(sc, BCE_INFO_LOAD,
3126                                     "BCM5709 s/w configured for Copper.\n");
3127                                 break;
3128                         }
3129                 } else {
3130                         switch (strap) {
3131                         case 0x1:
3132                         case 0x2:
3133                         case 0x4:
3134                                 DBPRINT(sc, BCE_INFO_LOAD,
3135                                     "BCM5709 s/w configured for SerDes.\n");
3136                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3137                                 break;
3138                         default:
3139                                 DBPRINT(sc, BCE_INFO_LOAD,
3140                                     "BCM5709 s/w configured for Copper.\n");
3141                                 break;
3142                         }
3143                 }
3144
3145         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3146                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3147
3148         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3149
3150                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3151
3152                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3153                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3154
3155                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3156                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3157                         sc->bce_phy_addr = 2;
3158
3159                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3160                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3161                                 sc->bce_phy_flags |=
3162                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3163                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3164                                     "capable adapter\n");
3165                         }
3166                 }
3167         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3168             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3169                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3170
3171 bce_get_media_exit:
3172         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3173                 "Using PHY address %d.\n", sc->bce_phy_addr);
3174
3175         DBEXIT(BCE_VERBOSE_PHY);
3176 }
3177
3178
3179 /****************************************************************************/
3180 /* Performs PHY initialization required before MII drivers access the       */
3181 /* device.                                                                  */
3182 /*                                                                          */
3183 /* Returns:                                                                 */
3184 /*   Nothing.                                                               */
3185 /****************************************************************************/
3186 static void
3187 bce_init_media(struct bce_softc *sc)
3188 {
3189         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3190             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3191                 /*
3192                  * Configure 5709S/5716S PHYs to use traditional IEEE
3193                  * Clause 22 method. Otherwise we have no way to attach
3194                  * the PHY in mii(4) layer. PHY specific configuration
3195                  * is done in mii layer.
3196                  */
3197
3198                 /* Select auto-negotiation MMD of the PHY. */
3199                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3200                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3201                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3202                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3203
3204                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3205                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3206                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3207         }
3208 }
3209
3210
3211 /****************************************************************************/
3212 /* Free any DMA memory owned by the driver.                                 */
3213 /*                                                                          */
3214 /* Scans through each data structre that requires DMA memory and frees      */
3215 /* the memory if allocated.                                                 */
3216 /*                                                                          */
3217 /* Returns:                                                                 */
3218 /*   Nothing.                                                               */
3219 /****************************************************************************/
3220 static void
3221 bce_dma_free(struct bce_softc *sc)
3222 {
3223         int i;
3224
3225         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3226
3227         /* Free, unmap, and destroy the status block. */
3228         if (sc->status_block != NULL) {
3229                 bus_dmamem_free(
3230                    sc->status_tag,
3231                     sc->status_block,
3232                     sc->status_map);
3233                 sc->status_block = NULL;
3234         }
3235
3236         if (sc->status_map != NULL) {
3237                 bus_dmamap_unload(
3238                     sc->status_tag,
3239                     sc->status_map);
3240                 bus_dmamap_destroy(sc->status_tag,
3241                     sc->status_map);
3242                 sc->status_map = NULL;
3243         }
3244
3245         if (sc->status_tag != NULL) {
3246                 bus_dma_tag_destroy(sc->status_tag);
3247                 sc->status_tag = NULL;
3248         }
3249
3250
3251         /* Free, unmap, and destroy the statistics block. */
3252         if (sc->stats_block != NULL) {
3253                 bus_dmamem_free(
3254                     sc->stats_tag,
3255                     sc->stats_block,
3256                     sc->stats_map);
3257                 sc->stats_block = NULL;
3258         }
3259
3260         if (sc->stats_map != NULL) {
3261                 bus_dmamap_unload(
3262                     sc->stats_tag,
3263                     sc->stats_map);
3264                 bus_dmamap_destroy(sc->stats_tag,
3265                     sc->stats_map);
3266                 sc->stats_map = NULL;
3267         }
3268
3269         if (sc->stats_tag != NULL) {
3270                 bus_dma_tag_destroy(sc->stats_tag);
3271                 sc->stats_tag = NULL;
3272         }
3273
3274
3275         /* Free, unmap and destroy all context memory pages. */
3276         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3277                 for (i = 0; i < sc->ctx_pages; i++ ) {
3278                         if (sc->ctx_block[i] != NULL) {
3279                                 bus_dmamem_free(
3280                                     sc->ctx_tag,
3281                                     sc->ctx_block[i],
3282                                     sc->ctx_map[i]);
3283                                 sc->ctx_block[i] = NULL;
3284                         }
3285
3286                         if (sc->ctx_map[i] != NULL) {
3287                                 bus_dmamap_unload(
3288                                     sc->ctx_tag,
3289                                     sc->ctx_map[i]);
3290                                 bus_dmamap_destroy(
3291                                     sc->ctx_tag,
3292                                     sc->ctx_map[i]);
3293                                 sc->ctx_map[i] = NULL;
3294                         }
3295                 }
3296
3297                 /* Destroy the context memory tag. */
3298                 if (sc->ctx_tag != NULL) {
3299                         bus_dma_tag_destroy(sc->ctx_tag);
3300                         sc->ctx_tag = NULL;
3301                 }
3302         }
3303
3304
3305         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3306         for (i = 0; i < sc->tx_pages; i++ ) {
3307                 if (sc->tx_bd_chain[i] != NULL) {
3308                         bus_dmamem_free(
3309                             sc->tx_bd_chain_tag,
3310                             sc->tx_bd_chain[i],
3311                             sc->tx_bd_chain_map[i]);
3312                         sc->tx_bd_chain[i] = NULL;
3313                 }
3314
3315                 if (sc->tx_bd_chain_map[i] != NULL) {
3316                         bus_dmamap_unload(
3317                             sc->tx_bd_chain_tag,
3318                             sc->tx_bd_chain_map[i]);
3319                         bus_dmamap_destroy(
3320                             sc->tx_bd_chain_tag,
3321                             sc->tx_bd_chain_map[i]);
3322                         sc->tx_bd_chain_map[i] = NULL;
3323                 }
3324         }
3325
3326         /* Destroy the TX buffer descriptor tag. */
3327         if (sc->tx_bd_chain_tag != NULL) {
3328                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3329                 sc->tx_bd_chain_tag = NULL;
3330         }
3331
3332
3333         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3334         for (i = 0; i < sc->rx_pages; i++ ) {
3335                 if (sc->rx_bd_chain[i] != NULL) {
3336                         bus_dmamem_free(
3337                             sc->rx_bd_chain_tag,
3338                             sc->rx_bd_chain[i],
3339                             sc->rx_bd_chain_map[i]);
3340                         sc->rx_bd_chain[i] = NULL;
3341                 }
3342
3343                 if (sc->rx_bd_chain_map[i] != NULL) {
3344                         bus_dmamap_unload(
3345                             sc->rx_bd_chain_tag,
3346                             sc->rx_bd_chain_map[i]);
3347                         bus_dmamap_destroy(
3348                             sc->rx_bd_chain_tag,
3349                             sc->rx_bd_chain_map[i]);
3350                         sc->rx_bd_chain_map[i] = NULL;
3351                 }
3352         }
3353
3354         /* Destroy the RX buffer descriptor tag. */
3355         if (sc->rx_bd_chain_tag != NULL) {
3356                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3357                 sc->rx_bd_chain_tag = NULL;
3358         }
3359
3360
3361         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3362         if (bce_hdr_split == TRUE) {
3363                 for (i = 0; i < sc->pg_pages; i++ ) {
3364                         if (sc->pg_bd_chain[i] != NULL) {
3365                                 bus_dmamem_free(
3366                                     sc->pg_bd_chain_tag,
3367                                     sc->pg_bd_chain[i],
3368                                     sc->pg_bd_chain_map[i]);
3369                                 sc->pg_bd_chain[i] = NULL;
3370                         }
3371
3372                         if (sc->pg_bd_chain_map[i] != NULL) {
3373                                 bus_dmamap_unload(
3374                                     sc->pg_bd_chain_tag,
3375                                     sc->pg_bd_chain_map[i]);
3376                                 bus_dmamap_destroy(
3377                                     sc->pg_bd_chain_tag,
3378                                     sc->pg_bd_chain_map[i]);
3379                                 sc->pg_bd_chain_map[i] = NULL;
3380                         }
3381                 }
3382
3383                 /* Destroy the page buffer descriptor tag. */
3384                 if (sc->pg_bd_chain_tag != NULL) {
3385                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3386                         sc->pg_bd_chain_tag = NULL;
3387                 }
3388         }
3389
3390
3391         /* Unload and destroy the TX mbuf maps. */
3392         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3393                 if (sc->tx_mbuf_map[i] != NULL) {
3394                         bus_dmamap_unload(sc->tx_mbuf_tag,
3395                             sc->tx_mbuf_map[i]);
3396                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3397                             sc->tx_mbuf_map[i]);
3398                         sc->tx_mbuf_map[i] = NULL;
3399                 }
3400         }
3401
3402         /* Destroy the TX mbuf tag. */
3403         if (sc->tx_mbuf_tag != NULL) {
3404                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3405                 sc->tx_mbuf_tag = NULL;
3406         }
3407
3408         /* Unload and destroy the RX mbuf maps. */
3409         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3410                 if (sc->rx_mbuf_map[i] != NULL) {
3411                         bus_dmamap_unload(sc->rx_mbuf_tag,
3412                             sc->rx_mbuf_map[i]);
3413                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3414                             sc->rx_mbuf_map[i]);
3415                         sc->rx_mbuf_map[i] = NULL;
3416                 }
3417         }
3418
3419         /* Destroy the RX mbuf tag. */
3420         if (sc->rx_mbuf_tag != NULL) {
3421                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3422                 sc->rx_mbuf_tag = NULL;
3423         }
3424
3425         /* Unload and destroy the page mbuf maps. */
3426         if (bce_hdr_split == TRUE) {
3427                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3428                         if (sc->pg_mbuf_map[i] != NULL) {
3429                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3430                                     sc->pg_mbuf_map[i]);
3431                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3432                                     sc->pg_mbuf_map[i]);
3433                                 sc->pg_mbuf_map[i] = NULL;
3434                         }
3435                 }
3436
3437                 /* Destroy the page mbuf tag. */
3438                 if (sc->pg_mbuf_tag != NULL) {
3439                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3440                         sc->pg_mbuf_tag = NULL;
3441                 }
3442         }
3443
3444         /* Destroy the parent tag */
3445         if (sc->parent_tag != NULL) {
3446                 bus_dma_tag_destroy(sc->parent_tag);
3447                 sc->parent_tag = NULL;
3448         }
3449
3450         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3451 }
3452
3453
3454 /****************************************************************************/
3455 /* Get DMA memory from the OS.                                              */
3456 /*                                                                          */
3457 /* Validates that the OS has provided DMA buffers in response to a          */
3458 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3459 /* When the callback is used the OS will return 0 for the mapping function  */
3460 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3461 /* failures back to the caller.                                             */
3462 /*                                                                          */
3463 /* Returns:                                                                 */
3464 /*   Nothing.                                                               */
3465 /****************************************************************************/
3466 static void
3467 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3468 {
3469         bus_addr_t *busaddr = arg;
3470
3471         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3472             __FUNCTION__, nseg));
3473         /* Simulate a mapping failure. */
3474         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3475             error = ENOMEM);
3476
3477         /* ToDo: How to increment debug sim_count variable here? */
3478
3479         /* Check for an error and signal the caller that an error occurred. */
3480         if (error) {
3481                 *busaddr = 0;
3482         } else {
3483                 *busaddr = segs->ds_addr;
3484         }
3485
3486         return;
3487 }
3488
3489
3490 /****************************************************************************/
3491 /* Allocate any DMA memory needed by the driver.                            */
3492 /*                                                                          */
3493 /* Allocates DMA memory needed for the various global structures needed by  */
3494 /* hardware.                                                                */
3495 /*                                                                          */
3496 /* Memory alignment requirements:                                           */
3497 /* +-----------------+----------+----------+----------+----------+          */
3498 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3499 /* +-----------------+----------+----------+----------+----------+          */
3500 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3501 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3502 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3503 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3504 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3505 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3506 /* |Context Memory   |          |          |          |          |          */
3507 /* +-----------------+----------+----------+----------+----------+          */
3508 /*                                                                          */
3509 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3510 /*                                                                          */
3511 /* Returns:                                                                 */
3512 /*   0 for success, positive value for failure.                             */
3513 /****************************************************************************/
3514 static int
3515 bce_dma_alloc(device_t dev)
3516 {
3517         struct bce_softc *sc;
3518         int i, error, rc = 0;
3519         bus_size_t max_size, max_seg_size;
3520         int max_segments;
3521
3522         sc = device_get_softc(dev);
3523
3524         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3525
3526         /*
3527          * Allocate the parent bus DMA tag appropriate for PCI.
3528          */
3529         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3530             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3531             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3532             &sc->parent_tag)) {
3533                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3534                     __FILE__, __LINE__);
3535                 rc = ENOMEM;
3536                 goto bce_dma_alloc_exit;
3537         }
3538
3539         /*
3540          * Create a DMA tag for the status block, allocate and clear the
3541          * memory, map the memory into DMA space, and fetch the physical
3542          * address of the block.
3543          */
3544         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3545             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3546             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3547             0, NULL, NULL, &sc->status_tag)) {
3548                 BCE_PRINTF("%s(%d): Could not allocate status block "
3549                     "DMA tag!\n", __FILE__, __LINE__);
3550                 rc = ENOMEM;
3551                 goto bce_dma_alloc_exit;
3552         }
3553
3554         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3555             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3556             &sc->status_map)) {
3557                 BCE_PRINTF("%s(%d): Could not allocate status block "
3558                     "DMA memory!\n", __FILE__, __LINE__);
3559                 rc = ENOMEM;
3560                 goto bce_dma_alloc_exit;
3561         }
3562
3563         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3564             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3565             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3566
3567         if (error) {
3568                 BCE_PRINTF("%s(%d): Could not map status block "
3569                     "DMA memory!\n", __FILE__, __LINE__);
3570                 rc = ENOMEM;
3571                 goto bce_dma_alloc_exit;
3572         }
3573
3574         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3575             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3576
3577         /*
3578          * Create a DMA tag for the statistics block, allocate and clear the
3579          * memory, map the memory into DMA space, and fetch the physical
3580          * address of the block.
3581          */
3582         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3583             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3584             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3585             0, NULL, NULL, &sc->stats_tag)) {
3586                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3587                     "DMA tag!\n", __FILE__, __LINE__);
3588                 rc = ENOMEM;
3589                 goto bce_dma_alloc_exit;
3590         }
3591
3592         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3593             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3594                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3595                     "DMA memory!\n", __FILE__, __LINE__);
3596                 rc = ENOMEM;
3597                 goto bce_dma_alloc_exit;
3598         }
3599
3600         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3601             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3602             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3603
3604         if(error) {
3605                 BCE_PRINTF("%s(%d): Could not map statistics block "
3606                     "DMA memory!\n", __FILE__, __LINE__);
3607                 rc = ENOMEM;
3608                 goto bce_dma_alloc_exit;
3609         }
3610
3611         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3612             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3613
3614         /* BCM5709 uses host memory as cache for context memory. */
3615         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3616                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3617                 if (sc->ctx_pages == 0)
3618                         sc->ctx_pages = 1;
3619
3620                 DBRUNIF((sc->ctx_pages > 512),
3621                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3622                     __FILE__, __LINE__, sc->ctx_pages));
3623
3624                 /*
3625                  * Create a DMA tag for the context pages,
3626                  * allocate and clear the memory, map the
3627                  * memory into DMA space, and fetch the
3628                  * physical address of the block.
3629                  */
3630                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3631                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3632                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3633                     0, NULL, NULL, &sc->ctx_tag)) {
3634                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3635                             "DMA tag!\n", __FILE__, __LINE__);
3636                         rc = ENOMEM;
3637                         goto bce_dma_alloc_exit;
3638                 }
3639
3640                 for (i = 0; i < sc->ctx_pages; i++) {
3641
3642                         if(bus_dmamem_alloc(sc->ctx_tag,
3643                             (void **)&sc->ctx_block[i],
3644                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3645                             &sc->ctx_map[i])) {
3646                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3647                                     "DMA memory!\n", __FILE__, __LINE__);
3648                                 rc = ENOMEM;
3649                                 goto bce_dma_alloc_exit;
3650                         }
3651
3652                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3653                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3654                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3655
3656                         if (error) {
3657                                 BCE_PRINTF("%s(%d): Could not map CTX "
3658                                     "DMA memory!\n", __FILE__, __LINE__);
3659                                 rc = ENOMEM;
3660                                 goto bce_dma_alloc_exit;
3661                         }
3662
3663                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3664                             "= 0x%jX\n", __FUNCTION__, i,
3665                             (uintmax_t) sc->ctx_paddr[i]);
3666                 }
3667         }
3668
3669         /*
3670          * Create a DMA tag for the TX buffer descriptor chain,
3671          * allocate and clear the  memory, and fetch the
3672          * physical address of the block.
3673          */
3674         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3675             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3676             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3677             NULL, NULL, &sc->tx_bd_chain_tag)) {
3678                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3679                     "chain DMA tag!\n", __FILE__, __LINE__);
3680                 rc = ENOMEM;
3681                 goto bce_dma_alloc_exit;
3682         }
3683
3684         for (i = 0; i < sc->tx_pages; i++) {
3685
3686                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3687                     (void **)&sc->tx_bd_chain[i],
3688                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3689                     &sc->tx_bd_chain_map[i])) {
3690                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3691                             "chain DMA memory!\n", __FILE__, __LINE__);
3692                         rc = ENOMEM;
3693                         goto bce_dma_alloc_exit;
3694                 }
3695
3696                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3697                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3698                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3699                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3700
3701                 if (error) {
3702                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3703                             "chain DMA memory!\n", __FILE__, __LINE__);
3704                         rc = ENOMEM;
3705                         goto bce_dma_alloc_exit;
3706                 }
3707
3708                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3709                     "0x%jX\n", __FUNCTION__, i,
3710                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3711         }
3712
3713         /* Check the required size before mapping to conserve resources. */
3714         if (bce_tso_enable) {
3715                 max_size     = BCE_TSO_MAX_SIZE;
3716                 max_segments = BCE_MAX_SEGMENTS;
3717                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3718         } else {
3719                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3720                 max_segments = BCE_MAX_SEGMENTS;
3721                 max_seg_size = MCLBYTES;
3722         }
3723
3724         /* Create a DMA tag for TX mbufs. */
3725         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3726             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3727             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3728                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3729                     __FILE__, __LINE__);
3730                 rc = ENOMEM;
3731                 goto bce_dma_alloc_exit;
3732         }
3733
3734         /* Create DMA maps for the TX mbufs clusters. */
3735         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3736                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3737                         &sc->tx_mbuf_map[i])) {
3738                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3739                             "map!\n", __FILE__, __LINE__);
3740                         rc = ENOMEM;
3741                         goto bce_dma_alloc_exit;
3742                 }
3743         }
3744
3745         /*
3746          * Create a DMA tag for the RX buffer descriptor chain,
3747          * allocate and clear the memory, and fetch the physical
3748          * address of the blocks.
3749          */
3750         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3751                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3752                         sc->max_bus_addr, NULL, NULL,
3753                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3754                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3755                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3756                     "DMA tag!\n", __FILE__, __LINE__);
3757                 rc = ENOMEM;
3758                 goto bce_dma_alloc_exit;
3759         }
3760
3761         for (i = 0; i < sc->rx_pages; i++) {
3762
3763                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3764                     (void **)&sc->rx_bd_chain[i],
3765                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3766                     &sc->rx_bd_chain_map[i])) {
3767                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3768                             "chain DMA memory!\n", __FILE__, __LINE__);
3769                         rc = ENOMEM;
3770                         goto bce_dma_alloc_exit;
3771                 }
3772
3773                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3774                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3775                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3776                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3777
3778                 if (error) {
3779                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3780                             "chain DMA memory!\n", __FILE__, __LINE__);
3781                         rc = ENOMEM;
3782                         goto bce_dma_alloc_exit;
3783                 }
3784
3785                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3786                     "0x%jX\n", __FUNCTION__, i,
3787                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3788         }
3789
3790         /*
3791          * Create a DMA tag for RX mbufs.
3792          */
3793         if (bce_hdr_split == TRUE)
3794                 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3795                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3796         else
3797                 max_size = max_seg_size = MJUM9BYTES;
3798         max_segments = 1;
3799
3800         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3801             "(max size = 0x%jX max segments = %d, max segment "
3802             "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3803              max_segments, (uintmax_t) max_seg_size);
3804
3805         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3806             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3807             max_size, max_segments, max_seg_size, 0, NULL, NULL,
3808             &sc->rx_mbuf_tag)) {
3809                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3810                     __FILE__, __LINE__);
3811                 rc = ENOMEM;
3812                 goto bce_dma_alloc_exit;
3813         }
3814
3815         /* Create DMA maps for the RX mbuf clusters. */
3816         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3817                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3818                     &sc->rx_mbuf_map[i])) {
3819                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3820                             "DMA map!\n", __FILE__, __LINE__);
3821                         rc = ENOMEM;
3822                         goto bce_dma_alloc_exit;
3823                 }
3824         }
3825
3826         if (bce_hdr_split == TRUE) {
3827                 /*
3828                  * Create a DMA tag for the page buffer descriptor chain,
3829                  * allocate and clear the memory, and fetch the physical
3830                  * address of the blocks.
3831                  */
3832                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3833                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3834                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3835                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3836                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3837                             "chain DMA tag!\n", __FILE__, __LINE__);
3838                         rc = ENOMEM;
3839                         goto bce_dma_alloc_exit;
3840                 }
3841
3842                 for (i = 0; i < sc->pg_pages; i++) {
3843                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3844                             (void **)&sc->pg_bd_chain[i],
3845                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3846                             &sc->pg_bd_chain_map[i])) {
3847                                 BCE_PRINTF("%s(%d): Could not allocate page "
3848                                     "descriptor chain DMA memory!\n",
3849                                     __FILE__, __LINE__);
3850                                 rc = ENOMEM;
3851                                 goto bce_dma_alloc_exit;
3852                         }
3853
3854                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3855                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3856                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3857                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3858
3859                         if (error) {
3860                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3861                                         "chain DMA memory!\n", __FILE__, __LINE__);
3862                                 rc = ENOMEM;
3863                                 goto bce_dma_alloc_exit;
3864                         }
3865
3866                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3867                                 "0x%jX\n", __FUNCTION__, i,
3868                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3869                 }
3870
3871                 /*
3872                  * Create a DMA tag for page mbufs.
3873                  */
3874                 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3875                         MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3876
3877                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3878                         sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3879                         max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3880                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3881                                 "DMA tag!\n", __FILE__, __LINE__);
3882                         rc = ENOMEM;
3883                         goto bce_dma_alloc_exit;
3884                 }
3885
3886                 /* Create DMA maps for the page mbuf clusters. */
3887                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3888                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3889                                 &sc->pg_mbuf_map[i])) {
3890                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3891                                         "DMA map!\n", __FILE__, __LINE__);
3892                                 rc = ENOMEM;
3893                                 goto bce_dma_alloc_exit;
3894                         }
3895                 }
3896         }
3897
3898 bce_dma_alloc_exit:
3899         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3900         return(rc);
3901 }
3902
3903
3904 /****************************************************************************/
3905 /* Release all resources used by the driver.                                */
3906 /*                                                                          */
3907 /* Releases all resources acquired by the driver including interrupts,      */
3908 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3909 /*                                                                          */
3910 /* Returns:                                                                 */
3911 /*   Nothing.                                                               */
3912 /****************************************************************************/
3913 static void
3914 bce_release_resources(struct bce_softc *sc)
3915 {
3916         device_t dev;
3917
3918         DBENTER(BCE_VERBOSE_RESET);
3919
3920         dev = sc->bce_dev;
3921
3922         bce_dma_free(sc);
3923
3924         if (sc->bce_intrhand != NULL) {
3925                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3926                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3927         }
3928
3929         if (sc->bce_res_irq != NULL) {
3930                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3931                 bus_release_resource(dev, SYS_RES_IRQ,
3932                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3933         }
3934
3935         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3936                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3937                 pci_release_msi(dev);
3938         }
3939
3940         if (sc->bce_res_mem != NULL) {
3941                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3942                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3943                     sc->bce_res_mem);
3944         }
3945
3946         if (sc->bce_ifp != NULL) {
3947                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3948                 if_free(sc->bce_ifp);
3949         }
3950
3951         if (mtx_initialized(&sc->bce_mtx))
3952                 BCE_LOCK_DESTROY(sc);
3953
3954         DBEXIT(BCE_VERBOSE_RESET);
3955 }
3956
3957
3958 /****************************************************************************/
3959 /* Firmware synchronization.                                                */
3960 /*                                                                          */
3961 /* Before performing certain events such as a chip reset, synchronize with  */
3962 /* the firmware first.                                                      */
3963 /*                                                                          */
3964 /* Returns:                                                                 */
3965 /*   0 for success, positive value for failure.                             */
3966 /****************************************************************************/
3967 static int
3968 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3969 {
3970         int i, rc = 0;
3971         u32 val;
3972
3973         DBENTER(BCE_VERBOSE_RESET);
3974
3975         /* Don't waste any time if we've timed out before. */
3976         if (sc->bce_fw_timed_out == TRUE) {
3977                 rc = EBUSY;
3978                 goto bce_fw_sync_exit;
3979         }
3980
3981         /* Increment the message sequence number. */
3982         sc->bce_fw_wr_seq++;
3983         msg_data |= sc->bce_fw_wr_seq;
3984
3985         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3986             "0x%08X\n", msg_data);
3987
3988         /* Send the message to the bootcode driver mailbox. */
3989         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3990
3991         /* Wait for the bootcode to acknowledge the message. */
3992         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3993                 /* Check for a response in the bootcode firmware mailbox. */
3994                 val = bce_shmem_rd(sc, BCE_FW_MB);
3995                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3996                         break;
3997                 DELAY(1000);
3998         }
3999
4000         /* If we've timed out, tell bootcode that we've stopped waiting. */
4001         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
4002             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
4003
4004                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
4005                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
4006
4007                 msg_data &= ~BCE_DRV_MSG_CODE;
4008                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4009
4010                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4011
4012                 sc->bce_fw_timed_out = TRUE;
4013                 rc = EBUSY;
4014         }
4015
4016 bce_fw_sync_exit:
4017         DBEXIT(BCE_VERBOSE_RESET);
4018         return (rc);
4019 }
4020
4021
4022 /****************************************************************************/
4023 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4024 /*                                                                          */
4025 /* Returns:                                                                 */
4026 /*   Nothing.                                                               */
4027 /****************************************************************************/
4028 static void
4029 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
4030         u32 rv2p_code_len, u32 rv2p_proc)
4031 {
4032         int i;
4033         u32 val;
4034
4035         DBENTER(BCE_VERBOSE_RESET);
4036
4037         /* Set the page size used by RV2P. */
4038         if (rv2p_proc == RV2P_PROC2) {
4039                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4040         }
4041
4042         for (i = 0; i < rv2p_code_len; i += 8) {
4043                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4044                 rv2p_code++;
4045                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4046                 rv2p_code++;
4047
4048                 if (rv2p_proc == RV2P_PROC1) {
4049                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4050                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4051                 }
4052                 else {
4053                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4054                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4055                 }
4056         }
4057
4058         /* Reset the processor, un-stall is done later. */
4059         if (rv2p_proc == RV2P_PROC1) {
4060                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4061         }
4062         else {
4063                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4064         }
4065
4066         DBEXIT(BCE_VERBOSE_RESET);
4067 }
4068
4069
4070 /****************************************************************************/
4071 /* Load RISC processor firmware.                                            */
4072 /*                                                                          */
4073 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4074 /* associated with a particular processor.                                  */
4075 /*                                                                          */
4076 /* Returns:                                                                 */
4077 /*   Nothing.                                                               */
4078 /****************************************************************************/
4079 static void
4080 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4081         struct fw_info *fw)
4082 {
4083         u32 offset;
4084
4085         DBENTER(BCE_VERBOSE_RESET);
4086
4087     bce_halt_cpu(sc, cpu_reg);
4088
4089         /* Load the Text area. */
4090         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4091         if (fw->text) {
4092                 int j;
4093
4094                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4095                         REG_WR_IND(sc, offset, fw->text[j]);
4096                 }
4097         }
4098
4099         /* Load the Data area. */
4100         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4101         if (fw->data) {
4102                 int j;
4103
4104                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4105                         REG_WR_IND(sc, offset, fw->data[j]);
4106                 }
4107         }
4108
4109         /* Load the SBSS area. */
4110         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4111         if (fw->sbss) {
4112                 int j;
4113
4114                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4115                         REG_WR_IND(sc, offset, fw->sbss[j]);
4116                 }
4117         }
4118
4119         /* Load the BSS area. */
4120         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4121         if (fw->bss) {
4122                 int j;
4123
4124                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4125                         REG_WR_IND(sc, offset, fw->bss[j]);
4126                 }
4127         }
4128
4129         /* Load the Read-Only area. */
4130         offset = cpu_reg->spad_base +
4131                 (fw->rodata_addr - cpu_reg->mips_view_base);
4132         if (fw->rodata) {
4133                 int j;
4134
4135                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4136                         REG_WR_IND(sc, offset, fw->rodata[j]);
4137                 }
4138         }
4139
4140         /* Clear the pre-fetch instruction and set the FW start address. */
4141         REG_WR_IND(sc, cpu_reg->inst, 0);
4142         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4143
4144         DBEXIT(BCE_VERBOSE_RESET);
4145 }
4146
4147
4148 /****************************************************************************/
4149 /* Starts the RISC processor.                                               */
4150 /*                                                                          */
4151 /* Assumes the CPU starting address has already been set.                   */
4152 /*                                                                          */
4153 /* Returns:                                                                 */
4154 /*   Nothing.                                                               */
4155 /****************************************************************************/
4156 static void
4157 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4158 {
4159         u32 val;
4160
4161         DBENTER(BCE_VERBOSE_RESET);
4162
4163         /* Start the CPU. */
4164         val = REG_RD_IND(sc, cpu_reg->mode);
4165         val &= ~cpu_reg->mode_value_halt;
4166         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4167         REG_WR_IND(sc, cpu_reg->mode, val);
4168
4169         DBEXIT(BCE_VERBOSE_RESET);
4170 }
4171
4172
4173 /****************************************************************************/
4174 /* Halts the RISC processor.                                                */
4175 /*                                                                          */
4176 /* Returns:                                                                 */
4177 /*   Nothing.                                                               */
4178 /****************************************************************************/
4179 static void
4180 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4181 {
4182         u32 val;
4183
4184         DBENTER(BCE_VERBOSE_RESET);
4185
4186         /* Halt the CPU. */
4187         val = REG_RD_IND(sc, cpu_reg->mode);
4188         val |= cpu_reg->mode_value_halt;
4189         REG_WR_IND(sc, cpu_reg->mode, val);
4190         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4191
4192         DBEXIT(BCE_VERBOSE_RESET);
4193 }
4194
4195
4196 /****************************************************************************/
4197 /* Initialize the RX CPU.                                                   */
4198 /*                                                                          */
4199 /* Returns:                                                                 */
4200 /*   Nothing.                                                               */
4201 /****************************************************************************/
4202 static void
4203 bce_start_rxp_cpu(struct bce_softc *sc)
4204 {
4205         struct cpu_reg cpu_reg;
4206
4207         DBENTER(BCE_VERBOSE_RESET);
4208
4209         cpu_reg.mode = BCE_RXP_CPU_MODE;
4210         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4211         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4212         cpu_reg.state = BCE_RXP_CPU_STATE;
4213         cpu_reg.state_value_clear = 0xffffff;
4214         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4215         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4216         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4217         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4218         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4219         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4220         cpu_reg.mips_view_base = 0x8000000;
4221
4222         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4223         bce_start_cpu(sc, &cpu_reg);
4224
4225         DBEXIT(BCE_VERBOSE_RESET);
4226 }
4227
4228
4229 /****************************************************************************/
4230 /* Initialize the RX CPU.                                                   */
4231 /*                                                                          */
4232 /* Returns:                                                                 */
4233 /*   Nothing.                                                               */
4234 /****************************************************************************/
4235 static void
4236 bce_init_rxp_cpu(struct bce_softc *sc)
4237 {
4238         struct cpu_reg cpu_reg;
4239         struct fw_info fw;
4240
4241         DBENTER(BCE_VERBOSE_RESET);
4242
4243         cpu_reg.mode = BCE_RXP_CPU_MODE;
4244         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4245         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4246         cpu_reg.state = BCE_RXP_CPU_STATE;
4247         cpu_reg.state_value_clear = 0xffffff;
4248         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4249         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4250         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4251         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4252         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4253         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4254         cpu_reg.mips_view_base = 0x8000000;
4255
4256         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4257                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4258                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4259                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4260                 fw.start_addr = bce_RXP_b09FwStartAddr;
4261
4262                 fw.text_addr = bce_RXP_b09FwTextAddr;
4263                 fw.text_len = bce_RXP_b09FwTextLen;
4264                 fw.text_index = 0;
4265                 fw.text = bce_RXP_b09FwText;
4266
4267                 fw.data_addr = bce_RXP_b09FwDataAddr;
4268                 fw.data_len = bce_RXP_b09FwDataLen;
4269                 fw.data_index = 0;
4270                 fw.data = bce_RXP_b09FwData;
4271
4272                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4273                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4274                 fw.sbss_index = 0;
4275                 fw.sbss = bce_RXP_b09FwSbss;
4276
4277                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4278                 fw.bss_len = bce_RXP_b09FwBssLen;
4279                 fw.bss_index = 0;
4280                 fw.bss = bce_RXP_b09FwBss;
4281
4282                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4283                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4284                 fw.rodata_index = 0;
4285                 fw.rodata = bce_RXP_b09FwRodata;
4286         } else {
4287                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4288                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4289                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4290                 fw.start_addr = bce_RXP_b06FwStartAddr;
4291
4292                 fw.text_addr = bce_RXP_b06FwTextAddr;
4293                 fw.text_len = bce_RXP_b06FwTextLen;
4294                 fw.text_index = 0;
4295                 fw.text = bce_RXP_b06FwText;
4296
4297                 fw.data_addr = bce_RXP_b06FwDataAddr;
4298                 fw.data_len = bce_RXP_b06FwDataLen;
4299                 fw.data_index = 0;
4300                 fw.data = bce_RXP_b06FwData;
4301
4302                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4303                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4304                 fw.sbss_index = 0;
4305                 fw.sbss = bce_RXP_b06FwSbss;
4306
4307                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4308                 fw.bss_len = bce_RXP_b06FwBssLen;
4309                 fw.bss_index = 0;
4310                 fw.bss = bce_RXP_b06FwBss;
4311
4312                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4313                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4314                 fw.rodata_index = 0;
4315                 fw.rodata = bce_RXP_b06FwRodata;
4316         }
4317
4318         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4319         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4320
4321     /* Delay RXP start until initialization is complete. */
4322
4323         DBEXIT(BCE_VERBOSE_RESET);
4324 }
4325
4326
4327 /****************************************************************************/
4328 /* Initialize the TX CPU.                                                   */
4329 /*                                                                          */
4330 /* Returns:                                                                 */
4331 /*   Nothing.                                                               */
4332 /****************************************************************************/
4333 static void
4334 bce_init_txp_cpu(struct bce_softc *sc)
4335 {
4336         struct cpu_reg cpu_reg;
4337         struct fw_info fw;
4338
4339         DBENTER(BCE_VERBOSE_RESET);
4340
4341         cpu_reg.mode = BCE_TXP_CPU_MODE;
4342         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4343         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4344         cpu_reg.state = BCE_TXP_CPU_STATE;
4345         cpu_reg.state_value_clear = 0xffffff;
4346         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4347         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4348         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4349         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4350         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4351         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4352         cpu_reg.mips_view_base = 0x8000000;
4353
4354         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4355                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4356                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4357                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4358                 fw.start_addr = bce_TXP_b09FwStartAddr;
4359
4360                 fw.text_addr = bce_TXP_b09FwTextAddr;
4361                 fw.text_len = bce_TXP_b09FwTextLen;
4362                 fw.text_index = 0;
4363                 fw.text = bce_TXP_b09FwText;
4364
4365                 fw.data_addr = bce_TXP_b09FwDataAddr;
4366                 fw.data_len = bce_TXP_b09FwDataLen;
4367                 fw.data_index = 0;
4368                 fw.data = bce_TXP_b09FwData;
4369
4370                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4371                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4372                 fw.sbss_index = 0;
4373                 fw.sbss = bce_TXP_b09FwSbss;
4374
4375                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4376                 fw.bss_len = bce_TXP_b09FwBssLen;
4377                 fw.bss_index = 0;
4378                 fw.bss = bce_TXP_b09FwBss;
4379
4380                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4381                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4382                 fw.rodata_index = 0;
4383                 fw.rodata = bce_TXP_b09FwRodata;
4384         } else {
4385                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4386                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4387                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4388                 fw.start_addr = bce_TXP_b06FwStartAddr;
4389
4390                 fw.text_addr = bce_TXP_b06FwTextAddr;
4391                 fw.text_len = bce_TXP_b06FwTextLen;
4392                 fw.text_index = 0;
4393                 fw.text = bce_TXP_b06FwText;
4394
4395                 fw.data_addr = bce_TXP_b06FwDataAddr;
4396                 fw.data_len = bce_TXP_b06FwDataLen;
4397                 fw.data_index = 0;
4398                 fw.data = bce_TXP_b06FwData;
4399
4400                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4401                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4402                 fw.sbss_index = 0;
4403                 fw.sbss = bce_TXP_b06FwSbss;
4404
4405                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4406                 fw.bss_len = bce_TXP_b06FwBssLen;
4407                 fw.bss_index = 0;
4408                 fw.bss = bce_TXP_b06FwBss;
4409
4410                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4411                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4412                 fw.rodata_index = 0;
4413                 fw.rodata = bce_TXP_b06FwRodata;
4414         }
4415
4416         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4417         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4418     bce_start_cpu(sc, &cpu_reg);
4419
4420         DBEXIT(BCE_VERBOSE_RESET);
4421 }
4422
4423
4424 /****************************************************************************/
4425 /* Initialize the TPAT CPU.                                                 */
4426 /*                                                                          */
4427 /* Returns:                                                                 */
4428 /*   Nothing.                                                               */
4429 /****************************************************************************/
4430 static void
4431 bce_init_tpat_cpu(struct bce_softc *sc)
4432 {
4433         struct cpu_reg cpu_reg;
4434         struct fw_info fw;
4435
4436         DBENTER(BCE_VERBOSE_RESET);
4437
4438         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4439         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4440         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4441         cpu_reg.state = BCE_TPAT_CPU_STATE;
4442         cpu_reg.state_value_clear = 0xffffff;
4443         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4444         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4445         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4446         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4447         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4448         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4449         cpu_reg.mips_view_base = 0x8000000;
4450
4451         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4452                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4453                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4454                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4455                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4456
4457                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4458                 fw.text_len = bce_TPAT_b09FwTextLen;
4459                 fw.text_index = 0;
4460                 fw.text = bce_TPAT_b09FwText;
4461
4462                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4463                 fw.data_len = bce_TPAT_b09FwDataLen;
4464                 fw.data_index = 0;
4465                 fw.data = bce_TPAT_b09FwData;
4466
4467                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4468                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4469                 fw.sbss_index = 0;
4470                 fw.sbss = bce_TPAT_b09FwSbss;
4471
4472                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4473                 fw.bss_len = bce_TPAT_b09FwBssLen;
4474                 fw.bss_index = 0;
4475                 fw.bss = bce_TPAT_b09FwBss;
4476
4477                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4478                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4479                 fw.rodata_index = 0;
4480                 fw.rodata = bce_TPAT_b09FwRodata;
4481         } else {
4482                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4483                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4484                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4485                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4486
4487                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4488                 fw.text_len = bce_TPAT_b06FwTextLen;
4489                 fw.text_index = 0;
4490                 fw.text = bce_TPAT_b06FwText;
4491
4492                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4493                 fw.data_len = bce_TPAT_b06FwDataLen;
4494                 fw.data_index = 0;
4495                 fw.data = bce_TPAT_b06FwData;
4496
4497                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4498                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4499                 fw.sbss_index = 0;
4500                 fw.sbss = bce_TPAT_b06FwSbss;
4501
4502                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4503                 fw.bss_len = bce_TPAT_b06FwBssLen;
4504                 fw.bss_index = 0;
4505                 fw.bss = bce_TPAT_b06FwBss;
4506
4507                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4508                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4509                 fw.rodata_index = 0;
4510                 fw.rodata = bce_TPAT_b06FwRodata;
4511         }
4512
4513         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4514         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4515         bce_start_cpu(sc, &cpu_reg);
4516
4517         DBEXIT(BCE_VERBOSE_RESET);
4518 }
4519
4520
4521 /****************************************************************************/
4522 /* Initialize the CP CPU.                                                   */
4523 /*                                                                          */
4524 /* Returns:                                                                 */
4525 /*   Nothing.                                                               */
4526 /****************************************************************************/
4527 static void
4528 bce_init_cp_cpu(struct bce_softc *sc)
4529 {
4530         struct cpu_reg cpu_reg;
4531         struct fw_info fw;
4532
4533         DBENTER(BCE_VERBOSE_RESET);
4534
4535         cpu_reg.mode = BCE_CP_CPU_MODE;
4536         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4537         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4538         cpu_reg.state = BCE_CP_CPU_STATE;
4539         cpu_reg.state_value_clear = 0xffffff;
4540         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4541         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4542         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4543         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4544         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4545         cpu_reg.spad_base = BCE_CP_SCRATCH;
4546         cpu_reg.mips_view_base = 0x8000000;
4547
4548         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4549                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4550                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4551                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4552                 fw.start_addr = bce_CP_b09FwStartAddr;
4553
4554                 fw.text_addr = bce_CP_b09FwTextAddr;
4555                 fw.text_len = bce_CP_b09FwTextLen;
4556                 fw.text_index = 0;
4557                 fw.text = bce_CP_b09FwText;
4558
4559                 fw.data_addr = bce_CP_b09FwDataAddr;
4560                 fw.data_len = bce_CP_b09FwDataLen;
4561                 fw.data_index = 0;
4562                 fw.data = bce_CP_b09FwData;
4563
4564                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4565                 fw.sbss_len = bce_CP_b09FwSbssLen;
4566                 fw.sbss_index = 0;
4567                 fw.sbss = bce_CP_b09FwSbss;
4568
4569                 fw.bss_addr = bce_CP_b09FwBssAddr;
4570                 fw.bss_len = bce_CP_b09FwBssLen;
4571                 fw.bss_index = 0;
4572                 fw.bss = bce_CP_b09FwBss;
4573
4574                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4575                 fw.rodata_len = bce_CP_b09FwRodataLen;
4576                 fw.rodata_index = 0;
4577                 fw.rodata = bce_CP_b09FwRodata;
4578         } else {
4579                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4580                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4581                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4582                 fw.start_addr = bce_CP_b06FwStartAddr;
4583
4584                 fw.text_addr = bce_CP_b06FwTextAddr;
4585                 fw.text_len = bce_CP_b06FwTextLen;
4586                 fw.text_index = 0;
4587                 fw.text = bce_CP_b06FwText;
4588
4589                 fw.data_addr = bce_CP_b06FwDataAddr;
4590                 fw.data_len = bce_CP_b06FwDataLen;
4591                 fw.data_index = 0;
4592                 fw.data = bce_CP_b06FwData;
4593
4594                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4595                 fw.sbss_len = bce_CP_b06FwSbssLen;
4596                 fw.sbss_index = 0;
4597                 fw.sbss = bce_CP_b06FwSbss;
4598
4599                 fw.bss_addr = bce_CP_b06FwBssAddr;
4600                 fw.bss_len = bce_CP_b06FwBssLen;
4601                 fw.bss_index = 0;
4602                 fw.bss = bce_CP_b06FwBss;
4603
4604                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4605                 fw.rodata_len = bce_CP_b06FwRodataLen;
4606                 fw.rodata_index = 0;
4607                 fw.rodata = bce_CP_b06FwRodata;
4608         }
4609
4610         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4611         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4612         bce_start_cpu(sc, &cpu_reg);
4613
4614         DBEXIT(BCE_VERBOSE_RESET);
4615 }
4616
4617
4618 /****************************************************************************/
4619 /* Initialize the COM CPU.                                                 */
4620 /*                                                                          */
4621 /* Returns:                                                                 */
4622 /*   Nothing.                                                               */
4623 /****************************************************************************/
4624 static void
4625 bce_init_com_cpu(struct bce_softc *sc)
4626 {
4627         struct cpu_reg cpu_reg;
4628         struct fw_info fw;
4629
4630         DBENTER(BCE_VERBOSE_RESET);
4631
4632         cpu_reg.mode = BCE_COM_CPU_MODE;
4633         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4634         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4635         cpu_reg.state = BCE_COM_CPU_STATE;
4636         cpu_reg.state_value_clear = 0xffffff;
4637         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4638         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4639         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4640         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4641         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4642         cpu_reg.spad_base = BCE_COM_SCRATCH;
4643         cpu_reg.mips_view_base = 0x8000000;
4644
4645         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4646                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4647                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4648                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4649                 fw.start_addr = bce_COM_b09FwStartAddr;
4650
4651                 fw.text_addr = bce_COM_b09FwTextAddr;
4652                 fw.text_len = bce_COM_b09FwTextLen;
4653                 fw.text_index = 0;
4654                 fw.text = bce_COM_b09FwText;
4655
4656                 fw.data_addr = bce_COM_b09FwDataAddr;
4657                 fw.data_len = bce_COM_b09FwDataLen;
4658                 fw.data_index = 0;
4659                 fw.data = bce_COM_b09FwData;
4660
4661                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4662                 fw.sbss_len = bce_COM_b09FwSbssLen;
4663                 fw.sbss_index = 0;
4664                 fw.sbss = bce_COM_b09FwSbss;
4665
4666                 fw.bss_addr = bce_COM_b09FwBssAddr;
4667                 fw.bss_len = bce_COM_b09FwBssLen;
4668                 fw.bss_index = 0;
4669                 fw.bss = bce_COM_b09FwBss;
4670
4671                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4672                 fw.rodata_len = bce_COM_b09FwRodataLen;
4673                 fw.rodata_index = 0;
4674                 fw.rodata = bce_COM_b09FwRodata;
4675         } else {
4676                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4677                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4678                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4679                 fw.start_addr = bce_COM_b06FwStartAddr;
4680
4681                 fw.text_addr = bce_COM_b06FwTextAddr;
4682                 fw.text_len = bce_COM_b06FwTextLen;
4683                 fw.text_index = 0;
4684                 fw.text = bce_COM_b06FwText;
4685
4686                 fw.data_addr = bce_COM_b06FwDataAddr;
4687                 fw.data_len = bce_COM_b06FwDataLen;
4688                 fw.data_index = 0;
4689                 fw.data = bce_COM_b06FwData;
4690
4691                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4692                 fw.sbss_len = bce_COM_b06FwSbssLen;
4693                 fw.sbss_index = 0;
4694                 fw.sbss = bce_COM_b06FwSbss;
4695
4696                 fw.bss_addr = bce_COM_b06FwBssAddr;
4697                 fw.bss_len = bce_COM_b06FwBssLen;
4698                 fw.bss_index = 0;
4699                 fw.bss = bce_COM_b06FwBss;
4700
4701                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4702                 fw.rodata_len = bce_COM_b06FwRodataLen;
4703                 fw.rodata_index = 0;
4704                 fw.rodata = bce_COM_b06FwRodata;
4705         }
4706
4707         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4708         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4709         bce_start_cpu(sc, &cpu_reg);
4710
4711         DBEXIT(BCE_VERBOSE_RESET);
4712 }
4713
4714
4715 /****************************************************************************/
4716 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4717 /*                                                                          */
4718 /* Loads the firmware for each CPU and starts the CPU.                      */
4719 /*                                                                          */
4720 /* Returns:                                                                 */
4721 /*   Nothing.                                                               */
4722 /****************************************************************************/
4723 static void
4724 bce_init_cpus(struct bce_softc *sc)
4725 {
4726         DBENTER(BCE_VERBOSE_RESET);
4727
4728         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4729
4730                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4731                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4732                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4733                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4734                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4735                 } else {
4736                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4737                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4738                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4739                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4740                 }
4741
4742         } else {
4743                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4744                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4745                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4746                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4747         }
4748
4749         bce_init_rxp_cpu(sc);
4750         bce_init_txp_cpu(sc);
4751         bce_init_tpat_cpu(sc);
4752         bce_init_com_cpu(sc);
4753         bce_init_cp_cpu(sc);
4754
4755         DBEXIT(BCE_VERBOSE_RESET);
4756 }
4757
4758
4759 /****************************************************************************/
4760 /* Initialize context memory.                                               */
4761 /*                                                                          */
4762 /* Clears the memory associated with each Context ID (CID).                 */
4763 /*                                                                          */
4764 /* Returns:                                                                 */
4765 /*   Nothing.                                                               */
4766 /****************************************************************************/
4767 static int
4768 bce_init_ctx(struct bce_softc *sc)
4769 {
4770         u32 offset, val, vcid_addr;
4771         int i, j, rc, retry_cnt;
4772
4773         rc = 0;
4774         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4775
4776         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4777                 retry_cnt = CTX_INIT_RETRY_COUNT;
4778
4779                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4780
4781                 /*
4782                  * BCM5709 context memory may be cached
4783                  * in host memory so prepare the host memory
4784                  * for access.
4785                  */
4786                 val = BCE_CTX_COMMAND_ENABLED |
4787                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4788                 val |= (BCM_PAGE_BITS - 8) << 16;
4789                 REG_WR(sc, BCE_CTX_COMMAND, val);
4790
4791                 /* Wait for mem init command to complete. */
4792                 for (i = 0; i < retry_cnt; i++) {
4793                         val = REG_RD(sc, BCE_CTX_COMMAND);
4794                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4795                                 break;
4796                         DELAY(2);
4797                 }
4798                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4799                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4800                             __FUNCTION__);
4801                         rc = EBUSY;
4802                         goto init_ctx_fail;
4803                 }
4804
4805                 for (i = 0; i < sc->ctx_pages; i++) {
4806                         /* Set the physical address of the context memory. */
4807                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4808                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4809                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4810                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4811                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4812                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4813                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4814
4815                         /* Verify the context memory write was successful. */
4816                         for (j = 0; j < retry_cnt; j++) {
4817                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4818                                 if ((val &
4819                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4820                                         break;
4821                                 DELAY(5);
4822                         }
4823                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4824                                 BCE_PRINTF("%s(): Failed to initialize "
4825                                     "context page %d!\n", __FUNCTION__, i);
4826                                 rc = EBUSY;
4827                                 goto init_ctx_fail;
4828                         }
4829                 }
4830         } else {
4831
4832                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4833
4834                 /*
4835                  * For the 5706/5708, context memory is local to
4836                  * the controller, so initialize the controller
4837                  * context memory.
4838                  */
4839
4840                 vcid_addr = GET_CID_ADDR(96);
4841                 while (vcid_addr) {
4842
4843                         vcid_addr -= PHY_CTX_SIZE;
4844
4845                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4846                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4847
4848                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4849                                 CTX_WR(sc, 0x00, offset, 0);
4850                         }
4851
4852                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4853                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4854                 }
4855
4856         }
4857 init_ctx_fail:
4858         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4859         return (rc);
4860 }
4861
4862
4863 /****************************************************************************/
4864 /* Fetch the permanent MAC address of the controller.                       */
4865 /*                                                                          */
4866 /* Returns:                                                                 */
4867 /*   Nothing.                                                               */
4868 /****************************************************************************/
4869 static void
4870 bce_get_mac_addr(struct bce_softc *sc)
4871 {
4872         u32 mac_lo = 0, mac_hi = 0;
4873
4874         DBENTER(BCE_VERBOSE_RESET);
4875
4876         /*
4877          * The NetXtreme II bootcode populates various NIC
4878          * power-on and runtime configuration items in a
4879          * shared memory area.  The factory configured MAC
4880          * address is available from both NVRAM and the
4881          * shared memory area so we'll read the value from
4882          * shared memory for speed.
4883          */
4884
4885         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4886         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4887
4888         if ((mac_lo == 0) && (mac_hi == 0)) {
4889                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4890                     __FILE__, __LINE__);
4891         } else {
4892                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4893                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4894                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4895                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4896                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4897                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4898         }
4899
4900         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4901             "address = %6D\n", sc->eaddr, ":");
4902         DBEXIT(BCE_VERBOSE_RESET);
4903 }
4904
4905
4906 /****************************************************************************/
4907 /* Program the MAC address.                                                 */
4908 /*                                                                          */
4909 /* Returns:                                                                 */
4910 /*   Nothing.                                                               */
4911 /****************************************************************************/
4912 static void
4913 bce_set_mac_addr(struct bce_softc *sc)
4914 {
4915         u32 val;
4916         u8 *mac_addr = sc->eaddr;
4917
4918         /* ToDo: Add support for setting multiple MAC addresses. */
4919
4920         DBENTER(BCE_VERBOSE_RESET);
4921         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4922             "%6D\n", sc->eaddr, ":");
4923
4924         val = (mac_addr[0] << 8) | mac_addr[1];
4925
4926         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4927
4928         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4929             (mac_addr[4] << 8) | mac_addr[5];
4930
4931         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4932
4933         DBEXIT(BCE_VERBOSE_RESET);
4934 }
4935
4936
4937 /****************************************************************************/
4938 /* Stop the controller.                                                     */
4939 /*                                                                          */
4940 /* Returns:                                                                 */
4941 /*   Nothing.                                                               */
4942 /****************************************************************************/
4943 static void
4944 bce_stop(struct bce_softc *sc)
4945 {
4946         struct ifnet *ifp;
4947
4948         DBENTER(BCE_VERBOSE_RESET);
4949
4950         BCE_LOCK_ASSERT(sc);
4951
4952         ifp = sc->bce_ifp;
4953
4954         callout_stop(&sc->bce_tick_callout);
4955
4956         /* Disable the transmit/receive blocks. */
4957         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4958         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4959         DELAY(20);
4960
4961         bce_disable_intr(sc);
4962
4963         /* Free RX buffers. */
4964         if (bce_hdr_split == TRUE) {
4965                 bce_free_pg_chain(sc);
4966         }
4967         bce_free_rx_chain(sc);
4968
4969         /* Free TX buffers. */
4970         bce_free_tx_chain(sc);
4971
4972         sc->watchdog_timer = 0;
4973
4974         sc->bce_link_up = FALSE;
4975
4976         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4977
4978         DBEXIT(BCE_VERBOSE_RESET);
4979 }
4980
4981
4982 static int
4983 bce_reset(struct bce_softc *sc, u32 reset_code)
4984 {
4985         u32 emac_mode_save, val;
4986         int i, rc = 0;
4987         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4988             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4989
4990         DBENTER(BCE_VERBOSE_RESET);
4991
4992         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4993             __FUNCTION__, reset_code);
4994
4995         /*
4996          * If ASF/IPMI is operational, then the EMAC Mode register already
4997          * contains appropriate values for the link settings that have
4998          * been auto-negotiated.  Resetting the chip will clobber those
4999          * values.  Save the important bits so we can restore them after
5000          * the reset.
5001          */
5002         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
5003
5004         /* Wait for pending PCI transactions to complete. */
5005         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
5006             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
5007             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
5008             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5009             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5010         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5011         DELAY(5);
5012
5013         /* Disable DMA */
5014         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5015                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5016                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5017                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5018         }
5019
5020         /* Assume bootcode is running. */
5021         sc->bce_fw_timed_out = FALSE;
5022         sc->bce_drv_cardiac_arrest = FALSE;
5023
5024         /* Give the firmware a chance to prepare for the reset. */
5025         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5026         if (rc)
5027                 goto bce_reset_exit;
5028
5029         /* Set a firmware reminder that this is a soft reset. */
5030         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5031
5032         /* Dummy read to force the chip to complete all current transactions. */
5033         val = REG_RD(sc, BCE_MISC_ID);
5034
5035         /* Chip reset. */
5036         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5037                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5038                 REG_RD(sc, BCE_MISC_COMMAND);
5039                 DELAY(5);
5040
5041                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5042                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5043
5044                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5045         } else {
5046                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5047                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5048                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5049                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5050
5051                 /* Allow up to 30us for reset to complete. */
5052                 for (i = 0; i < 10; i++) {
5053                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5054                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5055                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5056                                 break;
5057                         }
5058                         DELAY(10);
5059                 }
5060
5061                 /* Check that reset completed successfully. */
5062                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5063                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5064                         BCE_PRINTF("%s(%d): Reset failed!\n",
5065                             __FILE__, __LINE__);
5066                         rc = EBUSY;
5067                         goto bce_reset_exit;
5068                 }
5069         }
5070
5071         /* Make sure byte swapping is properly configured. */
5072         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5073         if (val != 0x01020304) {
5074                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5075                     __FILE__, __LINE__);
5076                 rc = ENODEV;
5077                 goto bce_reset_exit;
5078         }
5079
5080         /* Just completed a reset, assume that firmware is running again. */
5081         sc->bce_fw_timed_out = FALSE;
5082         sc->bce_drv_cardiac_arrest = FALSE;
5083
5084         /* Wait for the firmware to finish its initialization. */
5085         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5086         if (rc)
5087                 BCE_PRINTF("%s(%d): Firmware did not complete "
5088                     "initialization!\n", __FILE__, __LINE__);
5089         /* Get firmware capabilities. */
5090         bce_fw_cap_init(sc);
5091
5092 bce_reset_exit:
5093         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5094         if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5095                 val = REG_RD(sc, BCE_EMAC_MODE);
5096                 val = (val & ~emac_mode_mask) | emac_mode_save;
5097                 REG_WR(sc, BCE_EMAC_MODE, val);
5098         }
5099
5100         DBEXIT(BCE_VERBOSE_RESET);
5101         return (rc);
5102 }
5103
5104
5105 static int
5106 bce_chipinit(struct bce_softc *sc)
5107 {
5108         u32 val;
5109         int rc = 0;
5110
5111         DBENTER(BCE_VERBOSE_RESET);
5112
5113         bce_disable_intr(sc);
5114
5115         /*
5116          * Initialize DMA byte/word swapping, configure the number of DMA
5117          * channels and PCI clock compensation delay.
5118          */
5119         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5120             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5121 #if BYTE_ORDER == BIG_ENDIAN
5122             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5123 #endif
5124             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5125             DMA_READ_CHANS << 12 |
5126             DMA_WRITE_CHANS << 16;
5127
5128         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5129
5130         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5131                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5132
5133         /*
5134          * This setting resolves a problem observed on certain Intel PCI
5135          * chipsets that cannot handle multiple outstanding DMA operations.
5136          * See errata E9_5706A1_65.
5137          */
5138         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5139             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5140             !(sc->bce_flags & BCE_PCIX_FLAG))
5141                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5142
5143         REG_WR(sc, BCE_DMA_CONFIG, val);
5144
5145         /* Enable the RX_V2P and Context state machines before access. */
5146         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5147             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5148             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5149             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5150
5151         /* Initialize context mapping and zero out the quick contexts. */
5152         if ((rc = bce_init_ctx(sc)) != 0)
5153                 goto bce_chipinit_exit;
5154
5155         /* Initialize the on-boards CPUs */
5156         bce_init_cpus(sc);
5157
5158         /* Enable management frames (NC-SI) to flow to the MCP. */
5159         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5160                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5161                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5162         }
5163
5164         /* Prepare NVRAM for access. */
5165         if ((rc = bce_init_nvram(sc)) != 0)
5166                 goto bce_chipinit_exit;
5167
5168         /* Set the kernel bypass block size */
5169         val = REG_RD(sc, BCE_MQ_CONFIG);
5170         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5171         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5172
5173         /* Enable bins used on the 5709. */
5174         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5175                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5176                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5177                         val |= BCE_MQ_CONFIG_HALT_DIS;
5178         }
5179
5180         REG_WR(sc, BCE_MQ_CONFIG, val);
5181
5182         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5183         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5184         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5185
5186         /* Set the page size and clear the RV2P processor stall bits. */
5187         val = (BCM_PAGE_BITS - 8) << 24;
5188         REG_WR(sc, BCE_RV2P_CONFIG, val);
5189
5190         /* Configure page size. */
5191         val = REG_RD(sc, BCE_TBDR_CONFIG);
5192         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5193         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5194         REG_WR(sc, BCE_TBDR_CONFIG, val);
5195
5196         /* Set the perfect match control register to default. */
5197         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5198
5199 bce_chipinit_exit:
5200         DBEXIT(BCE_VERBOSE_RESET);
5201
5202         return(rc);
5203 }
5204
5205
5206 /****************************************************************************/
5207 /* Initialize the controller in preparation to send/receive traffic.        */
5208 /*                                                                          */
5209 /* Returns:                                                                 */
5210 /*   0 for success, positive value for failure.                             */
5211 /****************************************************************************/
5212 static int
5213 bce_blockinit(struct bce_softc *sc)
5214 {
5215         u32 reg, val;
5216         int rc = 0;
5217
5218         DBENTER(BCE_VERBOSE_RESET);
5219
5220         /* Load the hardware default MAC address. */
5221         bce_set_mac_addr(sc);
5222
5223         /* Set the Ethernet backoff seed value */
5224         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5225               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5226               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5227         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5228
5229         sc->last_status_idx = 0;
5230         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5231
5232         /* Set up link change interrupt generation. */
5233         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5234
5235         /* Program the physical address of the status block. */
5236         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5237             BCE_ADDR_LO(sc->status_block_paddr));
5238         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5239             BCE_ADDR_HI(sc->status_block_paddr));
5240
5241         /* Program the physical address of the statistics block. */
5242         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5243             BCE_ADDR_LO(sc->stats_block_paddr));
5244         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5245             BCE_ADDR_HI(sc->stats_block_paddr));
5246
5247         /* Program various host coalescing parameters. */
5248         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5249             (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
5250         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5251             (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
5252         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
5253             (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
5254         REG_WR(sc, BCE_HC_TX_TICKS,
5255             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5256         REG_WR(sc, BCE_HC_RX_TICKS,
5257             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5258         REG_WR(sc, BCE_HC_COM_TICKS,
5259             (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
5260         REG_WR(sc, BCE_HC_CMD_TICKS,
5261             (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
5262         REG_WR(sc, BCE_HC_STATS_TICKS,
5263             (sc->bce_stats_ticks & 0xffff00));
5264         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5265
5266         /* Configure the Host Coalescing block. */
5267         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5268             BCE_HC_CONFIG_COLLECT_STATS;
5269
5270 #if 0
5271         /* ToDo: Add MSI-X support. */
5272         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5273                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5274                     BCE_HC_SB_CONFIG_1;
5275
5276                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5277
5278                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5279                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5280
5281                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5282                     (sc->tx_quick_cons_trip_int << 16) |
5283                      sc->tx_quick_cons_trip);
5284
5285                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5286                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5287
5288                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5289         }
5290
5291         /*
5292          * Tell the HC block to automatically set the
5293          * INT_MASK bit after an MSI/MSI-X interrupt
5294          * is generated so the driver doesn't have to.
5295          */
5296         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5297                 val |= BCE_HC_CONFIG_ONE_SHOT;
5298
5299         /* Set the MSI-X status blocks to 128 byte boundaries. */
5300         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5301                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5302 #endif
5303
5304         REG_WR(sc, BCE_HC_CONFIG, val);
5305
5306         /* Clear the internal statistics counters. */
5307         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5308
5309         /* Verify that bootcode is running. */
5310         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5311
5312         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5313             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5314             __FILE__, __LINE__);
5315             reg = 0);
5316
5317         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5318             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5319                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5320                     "Expected: 08%08X\n", __FILE__, __LINE__,
5321                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5322                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5323                 rc = ENODEV;
5324                 goto bce_blockinit_exit;
5325         }
5326
5327         /* Enable DMA */
5328         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5329                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5330                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5331                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5332         }
5333
5334         /* Allow bootcode to apply additional fixes before enabling MAC. */
5335         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5336             BCE_DRV_MSG_CODE_RESET);
5337
5338         /* Enable link state change interrupt generation. */
5339         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5340
5341         /* Enable the RXP. */
5342         bce_start_rxp_cpu(sc);
5343
5344         /* Disable management frames (NC-SI) from flowing to the MCP. */
5345         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5346                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5347                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5348                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5349         }
5350
5351         /* Enable all remaining blocks in the MAC. */
5352         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5353                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5354                     BCE_MISC_ENABLE_DEFAULT_XI);
5355         else
5356                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5357                     BCE_MISC_ENABLE_DEFAULT);
5358
5359         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5360         DELAY(20);
5361
5362         /* Save the current host coalescing block settings. */
5363         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5364
5365 bce_blockinit_exit:
5366         DBEXIT(BCE_VERBOSE_RESET);
5367
5368         return (rc);
5369 }
5370
5371
5372 /****************************************************************************/
5373 /* Encapsulate an mbuf into the rx_bd chain.                                */
5374 /*                                                                          */
5375 /* Returns:                                                                 */
5376 /*   0 for success, positive value for failure.                             */
5377 /****************************************************************************/
5378 static int
5379 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5380     u16 *chain_prod, u32 *prod_bseq)
5381 {
5382         bus_dmamap_t map;
5383         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
5384         struct mbuf *m_new = NULL;
5385         struct rx_bd *rxbd;
5386         int nsegs, error, rc = 0;
5387 #ifdef BCE_DEBUG
5388         u16 debug_chain_prod = *chain_prod;
5389 #endif
5390
5391         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5392
5393         /* Make sure the inputs are valid. */
5394         DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC),
5395             BCE_PRINTF("%s(%d): RX producer out of range: "
5396             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5397             *chain_prod, (u16) MAX_RX_BD_ALLOC));
5398
5399         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5400             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5401             *prod, *chain_prod, *prod_bseq);
5402
5403         /* Update some debug statistic counters */
5404         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5405             sc->rx_low_watermark = sc->free_rx_bd);
5406         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5407             sc->rx_empty_count++);
5408
5409         /* Check whether this is a new mbuf allocation. */
5410         if (m == NULL) {
5411
5412                 /* Simulate an mbuf allocation failure. */
5413                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5414                     sc->mbuf_alloc_failed_count++;
5415                     sc->mbuf_alloc_failed_sim_count++;
5416                     rc = ENOBUFS;
5417                     goto bce_get_rx_buf_exit);
5418
5419                 /* This is a new mbuf allocation. */
5420                 if (bce_hdr_split == TRUE)
5421                         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
5422                 else
5423                         m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
5424                             sc->rx_bd_mbuf_alloc_size);
5425
5426                 if (m_new == NULL) {
5427                         sc->mbuf_alloc_failed_count++;
5428                         rc = ENOBUFS;
5429                         goto bce_get_rx_buf_exit;
5430                 }
5431
5432                 DBRUN(sc->debug_rx_mbuf_alloc++);
5433         } else {
5434                 /* Reuse an existing mbuf. */
5435                 m_new = m;
5436         }
5437
5438         /* Make sure we have a valid packet header. */
5439         M_ASSERTPKTHDR(m_new);
5440
5441         /* Initialize the mbuf size and pad if necessary for alignment. */
5442         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5443         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5444
5445         /* ToDo: Consider calling m_fragment() to test error handling. */
5446
5447         /* Map the mbuf cluster into device memory. */
5448         map = sc->rx_mbuf_map[*chain_prod];
5449         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
5450             segs, &nsegs, BUS_DMA_NOWAIT);
5451
5452         /* Handle any mapping errors. */
5453         if (error) {
5454                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5455                     "chain (%d)!\n", __FILE__, __LINE__, error);
5456
5457                 sc->dma_map_addr_rx_failed_count++;
5458                 m_freem(m_new);
5459
5460                 DBRUN(sc->debug_rx_mbuf_alloc--);
5461
5462                 rc = ENOBUFS;
5463                 goto bce_get_rx_buf_exit;
5464         }
5465
5466         /* All mbufs must map to a single segment. */
5467         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5468             __FUNCTION__, nsegs));
5469
5470         /* Setup the rx_bd for the segment. */
5471         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
5472
5473         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5474         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5475         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5476         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5477         *prod_bseq += segs[0].ds_len;
5478
5479         /* Save the mbuf and update our counter. */
5480         sc->rx_mbuf_ptr[*chain_prod] = m_new;
5481         sc->free_rx_bd -= nsegs;
5482
5483         DBRUNMSG(BCE_INSANE_RECV,
5484             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5485
5486         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5487             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n",
5488             __FUNCTION__, *prod, *chain_prod, *prod_bseq);
5489
5490 bce_get_rx_buf_exit:
5491         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5492
5493         return(rc);
5494 }
5495
5496
5497 /****************************************************************************/
5498 /* Encapsulate an mbuf cluster into the page chain.                         */
5499 /*                                                                          */
5500 /* Returns:                                                                 */
5501 /*   0 for success, positive value for failure.                             */
5502 /****************************************************************************/
5503 static int
5504 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5505         u16 *prod_idx)
5506 {
5507         bus_dmamap_t map;
5508         bus_addr_t busaddr;
5509         struct mbuf *m_new = NULL;
5510         struct rx_bd *pgbd;
5511         int error, rc = 0;
5512 #ifdef BCE_DEBUG
5513         u16 debug_prod_idx = *prod_idx;
5514 #endif
5515
5516         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5517
5518         /* Make sure the inputs are valid. */
5519         DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC),
5520             BCE_PRINTF("%s(%d): page producer out of range: "
5521             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5522             *prod_idx, (u16) MAX_PG_BD_ALLOC));
5523
5524         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5525             "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5526
5527         /* Update counters if we've hit a new low or run out of pages. */
5528         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5529             sc->pg_low_watermark = sc->free_pg_bd);
5530         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5531
5532         /* Check whether this is a new mbuf allocation. */
5533         if (m == NULL) {
5534
5535                 /* Simulate an mbuf allocation failure. */
5536                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5537                     sc->mbuf_alloc_failed_count++;
5538                     sc->mbuf_alloc_failed_sim_count++;
5539                     rc = ENOBUFS;
5540                     goto bce_get_pg_buf_exit);
5541
5542                 /* This is a new mbuf allocation. */
5543                 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
5544                 if (m_new == NULL) {
5545                         sc->mbuf_alloc_failed_count++;
5546                         rc = ENOBUFS;
5547                         goto bce_get_pg_buf_exit;
5548                 }
5549
5550                 DBRUN(sc->debug_pg_mbuf_alloc++);
5551         } else {
5552                 /* Reuse an existing mbuf. */
5553                 m_new = m;
5554                 m_new->m_data = m_new->m_ext.ext_buf;
5555         }
5556
5557         m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5558
5559         /* ToDo: Consider calling m_fragment() to test error handling. */
5560
5561         /* Map the mbuf cluster into device memory. */
5562         map = sc->pg_mbuf_map[*prod_idx];
5563         error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5564             sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5565             &busaddr, BUS_DMA_NOWAIT);
5566
5567         /* Handle any mapping errors. */
5568         if (error) {
5569                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5570                     __FILE__, __LINE__);
5571
5572                 m_freem(m_new);
5573                 DBRUN(sc->debug_pg_mbuf_alloc--);
5574
5575                 rc = ENOBUFS;
5576                 goto bce_get_pg_buf_exit;
5577         }
5578
5579         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5580
5581         /*
5582          * The page chain uses the same rx_bd data structure
5583          * as the receive chain but doesn't require a byte sequence (bseq).
5584          */
5585         pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5586
5587         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5588         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5589         pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
5590         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5591
5592         /* Save the mbuf and update our counter. */
5593         sc->pg_mbuf_ptr[*prod_idx] = m_new;
5594         sc->free_pg_bd--;
5595
5596         DBRUNMSG(BCE_INSANE_RECV,
5597             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5598
5599         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5600             "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5601
5602 bce_get_pg_buf_exit:
5603         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5604
5605         return(rc);
5606 }
5607
5608
5609 /****************************************************************************/
5610 /* Initialize the TX context memory.                                        */
5611 /*                                                                          */
5612 /* Returns:                                                                 */
5613 /*   Nothing                                                                */
5614 /****************************************************************************/
5615 static void
5616 bce_init_tx_context(struct bce_softc *sc)
5617 {
5618         u32 val;
5619
5620         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5621
5622         /* Initialize the context ID for an L2 TX chain. */
5623         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5624                 /* Set the CID type to support an L2 connection. */
5625                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5626                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5627                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5628                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5629                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5630                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5631
5632                 /* Point the hardware to the first page in the chain. */
5633                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5634                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5635                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5636                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5637                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5638                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5639         } else {
5640                 /* Set the CID type to support an L2 connection. */
5641                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5642                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5643                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5644                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5645
5646                 /* Point the hardware to the first page in the chain. */
5647                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5648                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5649                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5650                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5651                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5652                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5653         }
5654
5655         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5656 }
5657
5658
5659 /****************************************************************************/
5660 /* Allocate memory and initialize the TX data structures.                   */
5661 /*                                                                          */
5662 /* Returns:                                                                 */
5663 /*   0 for success, positive value for failure.                             */
5664 /****************************************************************************/
5665 static int
5666 bce_init_tx_chain(struct bce_softc *sc)
5667 {
5668         struct tx_bd *txbd;
5669         int i, rc = 0;
5670
5671         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5672
5673         /* Set the initial TX producer/consumer indices. */
5674         sc->tx_prod        = 0;
5675         sc->tx_cons        = 0;
5676         sc->tx_prod_bseq   = 0;
5677         sc->used_tx_bd     = 0;
5678         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5679         DBRUN(sc->tx_hi_watermark = 0);
5680         DBRUN(sc->tx_full_count = 0);
5681
5682         /*
5683          * The NetXtreme II supports a linked-list structre called
5684          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5685          * consists of a series of 1 or more chain pages, each of which
5686          * consists of a fixed number of BD entries.
5687          * The last BD entry on each page is a pointer to the next page
5688          * in the chain, and the last pointer in the BD chain
5689          * points back to the beginning of the chain.
5690          */
5691
5692         /* Set the TX next pointer chain entries. */
5693         for (i = 0; i < sc->tx_pages; i++) {
5694                 int j;
5695
5696                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5697
5698                 /* Check if we've reached the last page. */
5699                 if (i == (sc->tx_pages - 1))
5700                         j = 0;
5701                 else
5702                         j = i + 1;
5703
5704                 txbd->tx_bd_haddr_hi =
5705                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5706                 txbd->tx_bd_haddr_lo =
5707                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5708         }
5709
5710         bce_init_tx_context(sc);
5711
5712         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5713         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5714
5715         return(rc);
5716 }
5717
5718
5719 /****************************************************************************/
5720 /* Free memory and clear the TX data structures.                            */
5721 /*                                                                          */
5722 /* Returns:                                                                 */
5723 /*   Nothing.                                                               */
5724 /****************************************************************************/
5725 static void
5726 bce_free_tx_chain(struct bce_softc *sc)
5727 {
5728         int i;
5729
5730         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5731
5732         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5733         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5734                 if (sc->tx_mbuf_ptr[i] != NULL) {
5735                         if (sc->tx_mbuf_map[i] != NULL)
5736                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5737                                     sc->tx_mbuf_map[i],
5738                                     BUS_DMASYNC_POSTWRITE);
5739                         m_freem(sc->tx_mbuf_ptr[i]);
5740                         sc->tx_mbuf_ptr[i] = NULL;
5741                         DBRUN(sc->debug_tx_mbuf_alloc--);
5742                 }
5743         }
5744
5745         /* Clear each TX chain page. */
5746         for (i = 0; i < sc->tx_pages; i++)
5747                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5748
5749         sc->used_tx_bd = 0;
5750
5751         /* Check if we lost any mbufs in the process. */
5752         DBRUNIF((sc->debug_tx_mbuf_alloc),
5753             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5754             "from tx chain!\n", __FILE__, __LINE__,
5755             sc->debug_tx_mbuf_alloc));
5756
5757         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5758 }
5759
5760
5761 /****************************************************************************/
5762 /* Initialize the RX context memory.                                        */
5763 /*                                                                          */
5764 /* Returns:                                                                 */
5765 /*   Nothing                                                                */
5766 /****************************************************************************/
5767 static void
5768 bce_init_rx_context(struct bce_softc *sc)
5769 {
5770         u32 val;
5771
5772         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5773
5774         /* Init the type, size, and BD cache levels for the RX context. */
5775         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5776             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5777             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5778
5779         /*
5780          * Set the level for generating pause frames
5781          * when the number of available rx_bd's gets
5782          * too low (the low watermark) and the level
5783          * when pause frames can be stopped (the high
5784          * watermark).
5785          */
5786         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5787                 u32 lo_water, hi_water;
5788
5789                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5790                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5791                 } else {
5792                         lo_water = 0;
5793                 }
5794
5795                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5796                         lo_water = 0;
5797                 }
5798
5799                 hi_water = USABLE_RX_BD_ALLOC / 4;
5800
5801                 if (hi_water <= lo_water) {
5802                         lo_water = 0;
5803                 }
5804
5805                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5806                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5807
5808                 if (hi_water > 0xf)
5809                         hi_water = 0xf;
5810                 else if (hi_water == 0)
5811                         lo_water = 0;
5812
5813                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5814                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5815         }
5816
5817         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5818
5819         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5820         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5821                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5822                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5823         }
5824
5825         /* Point the hardware to the first page in the chain. */
5826         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5827         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5828         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5829         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5830
5831         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5832 }
5833
5834
5835 /****************************************************************************/
5836 /* Allocate memory and initialize the RX data structures.                   */
5837 /*                                                                          */
5838 /* Returns:                                                                 */
5839 /*   0 for success, positive value for failure.                             */
5840 /****************************************************************************/
5841 static int
5842 bce_init_rx_chain(struct bce_softc *sc)
5843 {
5844         struct rx_bd *rxbd;
5845         int i, rc = 0;
5846
5847         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5848             BCE_VERBOSE_CTX);
5849
5850         /* Initialize the RX producer and consumer indices. */
5851         sc->rx_prod        = 0;
5852         sc->rx_cons        = 0;
5853         sc->rx_prod_bseq   = 0;
5854         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5855         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5856
5857         /* Initialize the RX next pointer chain entries. */
5858         for (i = 0; i < sc->rx_pages; i++) {
5859                 int j;
5860
5861                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5862
5863                 /* Check if we've reached the last page. */
5864                 if (i == (sc->rx_pages - 1))
5865                         j = 0;
5866                 else
5867                         j = i + 1;
5868
5869                 /* Setup the chain page pointers. */
5870                 rxbd->rx_bd_haddr_hi =
5871                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5872                 rxbd->rx_bd_haddr_lo =
5873                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5874         }
5875
5876         /* Fill up the RX chain. */
5877         bce_fill_rx_chain(sc);
5878
5879         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5880         DBRUN(sc->rx_empty_count = 0);
5881         for (i = 0; i < sc->rx_pages; i++) {
5882                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5883                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5884         }
5885
5886         bce_init_rx_context(sc);
5887
5888         DBRUNMSG(BCE_EXTREME_RECV,
5889             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5890         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5891             BCE_VERBOSE_CTX);
5892
5893         /* ToDo: Are there possible failure modes here? */
5894
5895         return(rc);
5896 }
5897
5898
5899 /****************************************************************************/
5900 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5901 /* occurs.                                                                  */
5902 /*                                                                          */
5903 /* Returns:                                                                 */
5904 /*   Nothing                                                                */
5905 /****************************************************************************/
5906 static void
5907 bce_fill_rx_chain(struct bce_softc *sc)
5908 {
5909         u16 prod, prod_idx;
5910         u32 prod_bseq;
5911
5912         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5913             BCE_VERBOSE_CTX);
5914
5915         /* Get the RX chain producer indices. */
5916         prod      = sc->rx_prod;
5917         prod_bseq = sc->rx_prod_bseq;
5918
5919         /* Keep filling the RX chain until it's full. */
5920         while (sc->free_rx_bd > 0) {
5921                 prod_idx = RX_CHAIN_IDX(prod);
5922                 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5923                         /* Bail out if we can't add an mbuf to the chain. */
5924                         break;
5925                 }
5926                 prod = NEXT_RX_BD(prod);
5927         }
5928
5929         /* Save the RX chain producer indices. */
5930         sc->rx_prod      = prod;
5931         sc->rx_prod_bseq = prod_bseq;
5932
5933         /* We should never end up pointing to a next page pointer. */
5934         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5935             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5936             __FUNCTION__, sc->rx_prod));
5937
5938         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5939         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5940             BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod);
5941         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) +
5942             BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq);
5943
5944         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5945             BCE_VERBOSE_CTX);
5946 }
5947
5948
5949 /****************************************************************************/
5950 /* Free memory and clear the RX data structures.                            */
5951 /*                                                                          */
5952 /* Returns:                                                                 */
5953 /*   Nothing.                                                               */
5954 /****************************************************************************/
5955 static void
5956 bce_free_rx_chain(struct bce_softc *sc)
5957 {
5958         int i;
5959
5960         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5961
5962         /* Free any mbufs still in the RX mbuf chain. */
5963         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5964                 if (sc->rx_mbuf_ptr[i] != NULL) {
5965                         if (sc->rx_mbuf_map[i] != NULL)
5966                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5967                                     sc->rx_mbuf_map[i],
5968                                     BUS_DMASYNC_POSTREAD);
5969                         m_freem(sc->rx_mbuf_ptr[i]);
5970                         sc->rx_mbuf_ptr[i] = NULL;
5971                         DBRUN(sc->debug_rx_mbuf_alloc--);
5972                 }
5973         }
5974
5975         /* Clear each RX chain page. */
5976         for (i = 0; i < sc->rx_pages; i++)
5977                 if (sc->rx_bd_chain[i] != NULL) {
5978                         bzero((char *)sc->rx_bd_chain[i],
5979                             BCE_RX_CHAIN_PAGE_SZ);
5980                 }
5981
5982         sc->free_rx_bd = sc->max_rx_bd;
5983
5984         /* Check if we lost any mbufs in the process. */
5985         DBRUNIF((sc->debug_rx_mbuf_alloc),
5986             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5987             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5988
5989         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5990 }
5991
5992
5993 /****************************************************************************/
5994 /* Allocate memory and initialize the page data structures.                 */
5995 /* Assumes that bce_init_rx_chain() has not already been called.            */
5996 /*                                                                          */
5997 /* Returns:                                                                 */
5998 /*   0 for success, positive value for failure.                             */
5999 /****************************************************************************/
6000 static int
6001 bce_init_pg_chain(struct bce_softc *sc)
6002 {
6003         struct rx_bd *pgbd;
6004         int i, rc = 0;
6005         u32 val;
6006
6007         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6008                 BCE_VERBOSE_CTX);
6009
6010         /* Initialize the page producer and consumer indices. */
6011         sc->pg_prod        = 0;
6012         sc->pg_cons        = 0;
6013         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
6014         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
6015         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
6016         DBRUN(sc->pg_empty_count = 0);
6017
6018         /* Initialize the page next pointer chain entries. */
6019         for (i = 0; i < sc->pg_pages; i++) {
6020                 int j;
6021
6022                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
6023
6024                 /* Check if we've reached the last page. */
6025                 if (i == (sc->pg_pages - 1))
6026                         j = 0;
6027                 else
6028                         j = i + 1;
6029
6030                 /* Setup the chain page pointers. */
6031                 pgbd->rx_bd_haddr_hi =
6032                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6033                 pgbd->rx_bd_haddr_lo =
6034                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6035         }
6036
6037         /* Setup the MQ BIN mapping for host_pg_bidx. */
6038         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6039                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6040
6041         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6042
6043         /* Configure the rx_bd and page chain mbuf cluster size. */
6044         val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
6045         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6046
6047         /* Configure the context reserved for jumbo support. */
6048         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6049                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6050
6051         /* Point the hardware to the first page in the page chain. */
6052         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6053         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6054         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6055         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6056
6057         /* Fill up the page chain. */
6058         bce_fill_pg_chain(sc);
6059
6060         for (i = 0; i < sc->pg_pages; i++) {
6061                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6062                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6063         }
6064
6065         DBRUNMSG(BCE_EXTREME_RECV,
6066             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6067         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6068                 BCE_VERBOSE_CTX);
6069         return(rc);
6070 }
6071
6072
6073 /****************************************************************************/
6074 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6075 /* occurs.                                                                  */
6076 /*                                                                          */
6077 /* Returns:                                                                 */
6078 /*   Nothing                                                                */
6079 /****************************************************************************/
6080 static void
6081 bce_fill_pg_chain(struct bce_softc *sc)
6082 {
6083         u16 prod, prod_idx;
6084
6085         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6086             BCE_VERBOSE_CTX);
6087
6088         /* Get the page chain prodcuer index. */
6089         prod = sc->pg_prod;
6090
6091         /* Keep filling the page chain until it's full. */
6092         while (sc->free_pg_bd > 0) {
6093                 prod_idx = PG_CHAIN_IDX(prod);
6094                 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
6095                         /* Bail out if we can't add an mbuf to the chain. */
6096                         break;
6097                 }
6098                 prod = NEXT_PG_BD(prod);
6099         }
6100
6101         /* Save the page chain producer index. */
6102         sc->pg_prod = prod;
6103
6104         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6105             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6106             __FUNCTION__, sc->pg_prod));
6107
6108         /*
6109          * Write the mailbox and tell the chip about
6110          * the new rx_bd's in the page chain.
6111          */
6112         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
6113             BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod);
6114
6115         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6116             BCE_VERBOSE_CTX);
6117 }
6118
6119
6120 /****************************************************************************/
6121 /* Free memory and clear the RX data structures.                            */
6122 /*                                                                          */
6123 /* Returns:                                                                 */
6124 /*   Nothing.                                                               */
6125 /****************************************************************************/
6126 static void
6127 bce_free_pg_chain(struct bce_softc *sc)
6128 {
6129         int i;
6130
6131         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6132
6133         /* Free any mbufs still in the mbuf page chain. */
6134         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6135                 if (sc->pg_mbuf_ptr[i] != NULL) {
6136                         if (sc->pg_mbuf_map[i] != NULL)
6137                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6138                                     sc->pg_mbuf_map[i],
6139                                     BUS_DMASYNC_POSTREAD);
6140                         m_freem(sc->pg_mbuf_ptr[i]);
6141                         sc->pg_mbuf_ptr[i] = NULL;
6142                         DBRUN(sc->debug_pg_mbuf_alloc--);
6143                 }
6144         }
6145
6146         /* Clear each page chain pages. */
6147         for (i = 0; i < sc->pg_pages; i++)
6148                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6149
6150         sc->free_pg_bd = sc->max_pg_bd;
6151
6152         /* Check if we lost any mbufs in the process. */
6153         DBRUNIF((sc->debug_pg_mbuf_alloc),
6154             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6155             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6156
6157         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6158 }
6159
6160
6161 static u32
6162 bce_get_rphy_link(struct bce_softc *sc)
6163 {
6164         u32 advertise, link;
6165         int fdpx;
6166
6167         advertise = 0;
6168         fdpx = 0;
6169         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6170                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6171         else
6172                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6173         if (link & BCE_NETLINK_ANEG_ENB)
6174                 advertise |= BCE_NETLINK_ANEG_ENB;
6175         if (link & BCE_NETLINK_SPEED_10HALF)
6176                 advertise |= BCE_NETLINK_SPEED_10HALF;
6177         if (link & BCE_NETLINK_SPEED_10FULL) {
6178                 advertise |= BCE_NETLINK_SPEED_10FULL;
6179                 fdpx++;
6180         }
6181         if (link & BCE_NETLINK_SPEED_100HALF)
6182                 advertise |= BCE_NETLINK_SPEED_100HALF;
6183         if (link & BCE_NETLINK_SPEED_100FULL) {
6184                 advertise |= BCE_NETLINK_SPEED_100FULL;
6185                 fdpx++;
6186         }
6187         if (link & BCE_NETLINK_SPEED_1000HALF)
6188                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6189         if (link & BCE_NETLINK_SPEED_1000FULL) {
6190                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6191                 fdpx++;
6192         }
6193         if (link & BCE_NETLINK_SPEED_2500HALF)
6194                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6195         if (link & BCE_NETLINK_SPEED_2500FULL) {
6196                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6197                 fdpx++;
6198         }
6199         if (fdpx)
6200                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6201                     BCE_NETLINK_FC_PAUSE_ASYM;
6202         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6203                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6204                     BCE_NETLINK_ETH_AT_WIRESPEED;
6205
6206         return (advertise);
6207 }
6208
6209
6210 /****************************************************************************/
6211 /* Set media options.                                                       */
6212 /*                                                                          */
6213 /* Returns:                                                                 */
6214 /*   0 for success, positive value for failure.                             */
6215 /****************************************************************************/
6216 static int
6217 bce_ifmedia_upd(struct ifnet *ifp)
6218 {
6219         struct bce_softc *sc = ifp->if_softc;
6220         int error;
6221
6222         DBENTER(BCE_VERBOSE);
6223
6224         BCE_LOCK(sc);
6225         error = bce_ifmedia_upd_locked(ifp);
6226         BCE_UNLOCK(sc);
6227
6228         DBEXIT(BCE_VERBOSE);
6229         return (error);
6230 }
6231
6232
6233 /****************************************************************************/
6234 /* Set media options.                                                       */
6235 /*                                                                          */
6236 /* Returns:                                                                 */
6237 /*   Nothing.                                                               */
6238 /****************************************************************************/
6239 static int
6240 bce_ifmedia_upd_locked(struct ifnet *ifp)
6241 {
6242         struct bce_softc *sc = ifp->if_softc;
6243         struct mii_data *mii;
6244         struct mii_softc *miisc;
6245         struct ifmedia *ifm;
6246         u32 link;
6247         int error, fdx;
6248
6249         DBENTER(BCE_VERBOSE_PHY);
6250
6251         error = 0;
6252         BCE_LOCK_ASSERT(sc);
6253
6254         sc->bce_link_up = FALSE;
6255         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6256                 ifm = &sc->bce_ifmedia;
6257                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6258                         return (EINVAL);
6259                 link = 0;
6260                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6261                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6262                 case IFM_AUTO:
6263                         /*
6264                          * Check advertised link of remote PHY by reading
6265                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6266                          * Always use the same link type of remote PHY.
6267                          */
6268                         link = bce_get_rphy_link(sc);
6269                         break;
6270                 case IFM_2500_SX:
6271                         if ((sc->bce_phy_flags &
6272                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6273                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6274                                 return (EINVAL);
6275                         /*
6276                          * XXX
6277                          * Have to enable forced 2.5Gbps configuration.
6278                          */
6279                         if (fdx != 0)
6280                                 link |= BCE_NETLINK_SPEED_2500FULL;
6281                         else
6282                                 link |= BCE_NETLINK_SPEED_2500HALF;
6283                         break;
6284                 case IFM_1000_SX:
6285                         if ((sc->bce_phy_flags &
6286                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6287                                 return (EINVAL);
6288                         /*
6289                          * XXX
6290                          * Have to disable 2.5Gbps configuration.
6291                          */
6292                         if (fdx != 0)
6293                                 link = BCE_NETLINK_SPEED_1000FULL;
6294                         else
6295                                 link = BCE_NETLINK_SPEED_1000HALF;
6296                         break;
6297                 case IFM_1000_T:
6298                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6299                                 return (EINVAL);
6300                         if (fdx != 0)
6301                                 link = BCE_NETLINK_SPEED_1000FULL;
6302                         else
6303                                 link = BCE_NETLINK_SPEED_1000HALF;
6304                         break;
6305                 case IFM_100_TX:
6306                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6307                                 return (EINVAL);
6308                         if (fdx != 0)
6309                                 link = BCE_NETLINK_SPEED_100FULL;
6310                         else
6311                                 link = BCE_NETLINK_SPEED_100HALF;
6312                         break;
6313                 case IFM_10_T:
6314                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6315                                 return (EINVAL);
6316                         if (fdx != 0)
6317                                 link = BCE_NETLINK_SPEED_10FULL;
6318                         else
6319                                 link = BCE_NETLINK_SPEED_10HALF;
6320                         break;
6321                 default:
6322                         return (EINVAL);
6323                 }
6324                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6325                         /*
6326                          * XXX
6327                          * Advertise pause capability for full-duplex media.
6328                          */
6329                         if (fdx != 0)
6330                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6331                                     BCE_NETLINK_FC_PAUSE_ASYM;
6332                         if ((sc->bce_phy_flags &
6333                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6334                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6335                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6336                 }
6337
6338                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6339                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6340         } else {
6341                 mii = device_get_softc(sc->bce_miibus);
6342
6343                 /* Make sure the MII bus has been enumerated. */
6344                 if (mii) {
6345                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6346                                 mii_phy_reset(miisc);
6347                         error = mii_mediachg(mii);
6348                 }
6349         }
6350
6351         DBEXIT(BCE_VERBOSE_PHY);
6352         return (error);
6353 }
6354
6355
6356 static void
6357 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6358 {
6359         struct ifnet *ifp;
6360         u32 link;
6361
6362         ifp = sc->bce_ifp;
6363         BCE_LOCK_ASSERT(sc);
6364
6365         ifmr->ifm_status = IFM_AVALID;
6366         ifmr->ifm_active = IFM_ETHER;
6367         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6368         /* XXX Handle heart beat status? */
6369         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6370                 ifmr->ifm_status |= IFM_ACTIVE;
6371         else {
6372                 ifmr->ifm_active |= IFM_NONE;
6373                 ifp->if_baudrate = 0;
6374                 return;
6375         }
6376         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6377         case BCE_LINK_STATUS_10HALF:
6378                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6379                 ifp->if_baudrate = IF_Mbps(10UL);
6380                 break;
6381         case BCE_LINK_STATUS_10FULL:
6382                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6383                 ifp->if_baudrate = IF_Mbps(10UL);
6384                 break;
6385         case BCE_LINK_STATUS_100HALF:
6386                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6387                 ifp->if_baudrate = IF_Mbps(100UL);
6388                 break;
6389         case BCE_LINK_STATUS_100FULL:
6390                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6391                 ifp->if_baudrate = IF_Mbps(100UL);
6392                 break;
6393         case BCE_LINK_STATUS_1000HALF:
6394                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6395                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6396                 else
6397                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6398                 ifp->if_baudrate = IF_Mbps(1000UL);
6399                 break;
6400         case BCE_LINK_STATUS_1000FULL:
6401                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6402                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6403                 else
6404                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6405                 ifp->if_baudrate = IF_Mbps(1000UL);
6406                 break;
6407         case BCE_LINK_STATUS_2500HALF:
6408                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6409                         ifmr->ifm_active |= IFM_NONE;
6410                         return;
6411                 } else
6412                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6413                 ifp->if_baudrate = IF_Mbps(2500UL);
6414                 break;
6415         case BCE_LINK_STATUS_2500FULL:
6416                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6417                         ifmr->ifm_active |= IFM_NONE;
6418                         return;
6419                 } else
6420                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6421                 ifp->if_baudrate = IF_Mbps(2500UL);
6422                 break;
6423         default:
6424                 ifmr->ifm_active |= IFM_NONE;
6425                 return;
6426         }
6427
6428         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6429                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6430         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6431                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6432 }
6433
6434
6435 /****************************************************************************/
6436 /* Reports current media status.                                            */
6437 /*                                                                          */
6438 /* Returns:                                                                 */
6439 /*   Nothing.                                                               */
6440 /****************************************************************************/
6441 static void
6442 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6443 {
6444         struct bce_softc *sc = ifp->if_softc;
6445         struct mii_data *mii;
6446
6447         DBENTER(BCE_VERBOSE_PHY);
6448
6449         BCE_LOCK(sc);
6450
6451         if ((ifp->if_flags & IFF_UP) == 0) {
6452                 BCE_UNLOCK(sc);
6453                 return;
6454         }
6455
6456         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6457                 bce_ifmedia_sts_rphy(sc, ifmr);
6458         else {
6459                 mii = device_get_softc(sc->bce_miibus);
6460                 mii_pollstat(mii);
6461                 ifmr->ifm_active = mii->mii_media_active;
6462                 ifmr->ifm_status = mii->mii_media_status;
6463         }
6464
6465         BCE_UNLOCK(sc);
6466
6467         DBEXIT(BCE_VERBOSE_PHY);
6468 }
6469
6470
6471 /****************************************************************************/
6472 /* Handles PHY generated interrupt events.                                  */
6473 /*                                                                          */
6474 /* Returns:                                                                 */
6475 /*   Nothing.                                                               */
6476 /****************************************************************************/
6477 static void
6478 bce_phy_intr(struct bce_softc *sc)
6479 {
6480         u32 new_link_state, old_link_state;
6481
6482         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6483
6484         DBRUN(sc->phy_interrupts++);
6485
6486         new_link_state = sc->status_block->status_attn_bits &
6487             STATUS_ATTN_BITS_LINK_STATE;
6488         old_link_state = sc->status_block->status_attn_bits_ack &
6489             STATUS_ATTN_BITS_LINK_STATE;
6490
6491         /* Handle any changes if the link state has changed. */
6492         if (new_link_state != old_link_state) {
6493
6494                 /* Update the status_attn_bits_ack field. */
6495                 if (new_link_state) {
6496                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6497                             STATUS_ATTN_BITS_LINK_STATE);
6498                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6499                             __FUNCTION__);
6500                 } else {
6501                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6502                             STATUS_ATTN_BITS_LINK_STATE);
6503                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6504                             __FUNCTION__);
6505                 }
6506
6507                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6508                         if (new_link_state) {
6509                                 if (bootverbose)
6510                                         if_printf(sc->bce_ifp, "link UP\n");
6511                                 if_link_state_change(sc->bce_ifp,
6512                                     LINK_STATE_UP);
6513                         } else {
6514                                 if (bootverbose)
6515                                         if_printf(sc->bce_ifp, "link DOWN\n");
6516                                 if_link_state_change(sc->bce_ifp,
6517                                     LINK_STATE_DOWN);
6518                         }
6519                 }
6520                 /*
6521                  * Assume link is down and allow
6522                  * tick routine to update the state
6523                  * based on the actual media state.
6524                  */
6525                 sc->bce_link_up = FALSE;
6526                 callout_stop(&sc->bce_tick_callout);
6527                 bce_tick(sc);
6528         }
6529
6530         /* Acknowledge the link change interrupt. */
6531         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6532
6533         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6534 }
6535
6536
6537 /****************************************************************************/
6538 /* Reads the receive consumer value from the status block (skipping over    */
6539 /* chain page pointer if necessary).                                        */
6540 /*                                                                          */
6541 /* Returns:                                                                 */
6542 /*   hw_cons                                                                */
6543 /****************************************************************************/
6544 static inline u16
6545 bce_get_hw_rx_cons(struct bce_softc *sc)
6546 {
6547         u16 hw_cons;
6548
6549         rmb();
6550         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6551         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6552                 hw_cons++;
6553
6554         return hw_cons;
6555 }
6556
6557 /****************************************************************************/
6558 /* Handles received frame interrupt events.                                 */
6559 /*                                                                          */
6560 /* Returns:                                                                 */
6561 /*   Nothing.                                                               */
6562 /****************************************************************************/
6563 static void
6564 bce_rx_intr(struct bce_softc *sc)
6565 {
6566         struct ifnet *ifp = sc->bce_ifp;
6567         struct l2_fhdr *l2fhdr;
6568         struct ether_vlan_header *vh;
6569         unsigned int pkt_len;
6570         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6571         u32 status;
6572         unsigned int rem_len;
6573         u16 sw_pg_cons, sw_pg_cons_idx;
6574
6575         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6576         DBRUN(sc->interrupts_rx++);
6577         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6578             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6579             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6580
6581         /* Prepare the RX chain pages to be accessed by the host CPU. */
6582         for (int i = 0; i < sc->rx_pages; i++)
6583                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6584                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6585
6586         /* Prepare the page chain pages to be accessed by the host CPU. */
6587         if (bce_hdr_split == TRUE) {
6588                 for (int i = 0; i < sc->pg_pages; i++)
6589                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6590                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6591         }
6592
6593         /* Get the hardware's view of the RX consumer index. */
6594         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6595
6596         /* Get working copies of the driver's view of the consumer indices. */
6597         sw_rx_cons = sc->rx_cons;
6598         sw_pg_cons = sc->pg_cons;
6599
6600         /* Update some debug statistics counters */
6601         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6602             sc->rx_low_watermark = sc->free_rx_bd);
6603         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6604             sc->rx_empty_count++);
6605
6606         /* Scan through the receive chain as long as there is work to do */
6607         /* ToDo: Consider setting a limit on the number of packets processed. */
6608         rmb();
6609         while (sw_rx_cons != hw_rx_cons) {
6610                 struct mbuf *m0;
6611
6612                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6613                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6614
6615                 /* Unmap the mbuf from DMA space. */
6616                 bus_dmamap_sync(sc->rx_mbuf_tag,
6617                     sc->rx_mbuf_map[sw_rx_cons_idx],
6618                     BUS_DMASYNC_POSTREAD);
6619                 bus_dmamap_unload(sc->rx_mbuf_tag,
6620                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6621
6622                 /* Remove the mbuf from the RX chain. */
6623                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6624                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6625                 DBRUN(sc->debug_rx_mbuf_alloc--);
6626                 sc->free_rx_bd++;
6627
6628                 if(m0 == NULL) {
6629                         DBPRINT(sc, BCE_EXTREME_RECV,
6630                             "%s(): Oops! Empty mbuf pointer "
6631                             "found in sc->rx_mbuf_ptr[0x%04X]!\n",
6632                             __FUNCTION__, sw_rx_cons_idx);
6633                         goto bce_rx_int_next_rx;
6634                 }
6635
6636                 /*
6637                  * Frames received on the NetXteme II are prepended
6638                  * with an l2_fhdr structure which provides status
6639                  * information about the received frame (including
6640                  * VLAN tags and checksum info).  The frames are
6641                  * also automatically adjusted to word align the IP
6642                  * header (i.e. two null bytes are inserted before
6643                  * the Ethernet header).  As a result the data
6644                  * DMA'd by the controller into the mbuf looks
6645                  * like this:
6646                  *
6647                  * +---------+-----+---------------------+-----+
6648                  * | l2_fhdr | pad | packet data         | FCS |
6649                  * +---------+-----+---------------------+-----+
6650                  *
6651                  * The l2_fhdr needs to be checked and skipped and
6652                  * the FCS needs to be stripped before sending the
6653                  * packet up the stack.
6654                  */
6655                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6656
6657                 /* Get the packet data + FCS length and the status. */
6658                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6659                 status  = l2fhdr->l2_fhdr_status;
6660
6661                 /*
6662                  * Skip over the l2_fhdr and pad, resulting in the
6663                  * following data in the mbuf:
6664                  * +---------------------+-----+
6665                  * | packet data         | FCS |
6666                  * +---------------------+-----+
6667                  */
6668                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6669
6670                 /*
6671                  * When split header mode is used, an ethernet frame
6672                  * may be split across the receive chain and the
6673                  * page chain. If that occurs an mbuf cluster must be
6674                  * reassembled from the individual mbuf pieces.
6675                  */
6676                 if (bce_hdr_split == TRUE) {
6677                         /*
6678                          * Check whether the received frame fits in a single
6679                          * mbuf or not (i.e. packet data + FCS <=
6680                          * sc->rx_bd_mbuf_data_len bytes).
6681                          */
6682                         if (pkt_len > m0->m_len) {
6683                                 /*
6684                                  * The received frame is larger than a single mbuf.
6685                                  * If the frame was a TCP frame then only the TCP
6686                                  * header is placed in the mbuf, the remaining
6687                                  * payload (including FCS) is placed in the page
6688                                  * chain, the SPLIT flag is set, and the header
6689                                  * length is placed in the IP checksum field.
6690                                  * If the frame is not a TCP frame then the mbuf
6691                                  * is filled and the remaining bytes are placed
6692                                  * in the page chain.
6693                                  */
6694
6695                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6696                                         "packet.\n", __FUNCTION__);
6697                                 DBRUN(sc->split_header_frames_rcvd++);
6698
6699                                 /*
6700                                  * When the page chain is enabled and the TCP
6701                                  * header has been split from the TCP payload,
6702                                  * the ip_xsum structure will reflect the length
6703                                  * of the TCP header, not the IP checksum.  Set
6704                                  * the packet length of the mbuf accordingly.
6705                                  */
6706                                 if (status & L2_FHDR_STATUS_SPLIT) {
6707                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6708                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6709                                 }
6710
6711                                 rem_len = pkt_len - m0->m_len;
6712
6713                                 /* Pull mbufs off the page chain for any remaining data. */
6714                                 while (rem_len > 0) {
6715                                         struct mbuf *m_pg;
6716
6717                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6718
6719                                         /* Remove the mbuf from the page chain. */
6720                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6721                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6722                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6723                                         sc->free_pg_bd++;
6724
6725                                         /* Unmap the page chain mbuf from DMA space. */
6726                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6727                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6728                                                 BUS_DMASYNC_POSTREAD);
6729                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6730                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6731
6732                                         /* Adjust the mbuf length. */
6733                                         if (rem_len < m_pg->m_len) {
6734                                                 /* The mbuf chain is complete. */
6735                                                 m_pg->m_len = rem_len;
6736                                                 rem_len = 0;
6737                                         } else {
6738                                                 /* More packet data is waiting. */
6739                                                 rem_len -= m_pg->m_len;
6740                                         }
6741
6742                                         /* Concatenate the mbuf cluster to the mbuf. */
6743                                         m_cat(m0, m_pg);
6744
6745                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6746                                 }
6747
6748                                 /* Set the total packet length. */
6749                                 m0->m_pkthdr.len = pkt_len;
6750
6751                         } else {
6752                                 /*
6753                                  * The received packet is small and fits in a
6754                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6755                                  * FCS <= MHLEN).  In other words, the packet is
6756                                  * 154 bytes or less in size.
6757                                  */
6758
6759                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6760                                         "packet.\n", __FUNCTION__);
6761
6762                                 /* Set the total packet length. */
6763                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6764                         }
6765                 } else
6766                         /* Set the total packet length. */
6767                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6768
6769                 /* Remove the trailing Ethernet FCS. */
6770                 m_adj(m0, -ETHER_CRC_LEN);
6771
6772                 /* Check that the resulting mbuf chain is valid. */
6773                 DBRUN(m_sanity(m0, FALSE));
6774                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6775                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6776                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6777                     m_print(m0, 128));
6778
6779                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6780                     sc->l2fhdr_error_sim_count++;
6781                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6782
6783                 /* Check the received frame for errors. */
6784                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6785                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6786                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6787
6788                         /* Log the error and release the mbuf. */
6789                         ifp->if_ierrors++;
6790                         sc->l2fhdr_error_count++;
6791
6792                         m_freem(m0);
6793                         m0 = NULL;
6794                         goto bce_rx_int_next_rx;
6795                 }
6796
6797                 /* Send the packet to the appropriate interface. */
6798                 m0->m_pkthdr.rcvif = ifp;
6799
6800                 /* Assume no hardware checksum. */
6801                 m0->m_pkthdr.csum_flags = 0;
6802
6803                 /* Validate the checksum if offload enabled. */
6804                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6805
6806                         /* Check for an IP datagram. */
6807                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6808                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6809                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6810                                 DBRUN(sc->csum_offload_ip++);
6811                                 /* Check if the IP checksum is valid. */
6812                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6813                                         m0->m_pkthdr.csum_flags |=
6814                                             CSUM_IP_VALID;
6815                         }
6816
6817                         /* Check for a valid TCP/UDP frame. */
6818                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6819                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6820
6821                                 /* Check for a good TCP/UDP checksum. */
6822                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6823                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6824                                         DBRUN(sc->csum_offload_tcp_udp++);
6825                                         m0->m_pkthdr.csum_data =
6826                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6827                                         m0->m_pkthdr.csum_flags |=
6828                                             (CSUM_DATA_VALID
6829                                             | CSUM_PSEUDO_HDR);
6830                                 }
6831                         }
6832                 }
6833
6834                 /* Attach the VLAN tag. */
6835                 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
6836                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6837                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6838                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6839 #if __FreeBSD_version < 700000
6840                                 VLAN_INPUT_TAG(ifp, m0,
6841                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6842 #else
6843                                 m0->m_pkthdr.ether_vtag =
6844                                     l2fhdr->l2_fhdr_vlan_tag;
6845                                 m0->m_flags |= M_VLANTAG;
6846 #endif
6847                         } else {
6848                                 /*
6849                                  * bce(4) controllers can't disable VLAN
6850                                  * tag stripping if management firmware
6851                                  * (ASF/IPMI/UMP) is running. So we always
6852                                  * strip VLAN tag and manually reconstruct
6853                                  * the VLAN frame by appending stripped
6854                                  * VLAN tag in driver if VLAN tag stripping
6855                                  * was disabled.
6856                                  *
6857                                  * TODO: LLC SNAP handling.
6858                                  */
6859                                 bcopy(mtod(m0, uint8_t *),
6860                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6861                                     ETHER_ADDR_LEN * 2);
6862                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6863                                 vh = mtod(m0, struct ether_vlan_header *);
6864                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6865                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6866                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6867                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6868                         }
6869                 }
6870
6871                 /* Increment received packet statistics. */
6872                 ifp->if_ipackets++;
6873
6874 bce_rx_int_next_rx:
6875                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6876
6877                 /* If we have a packet, pass it up the stack */
6878                 if (m0) {
6879                         /* Make sure we don't lose our place when we release the lock. */
6880                         sc->rx_cons = sw_rx_cons;
6881                         sc->pg_cons = sw_pg_cons;
6882
6883                         BCE_UNLOCK(sc);
6884                         (*ifp->if_input)(ifp, m0);
6885                         BCE_LOCK(sc);
6886
6887                         /* Recover our place. */
6888                         sw_rx_cons = sc->rx_cons;
6889                         sw_pg_cons = sc->pg_cons;
6890                 }
6891
6892                 /* Refresh hw_cons to see if there's new work */
6893                 if (sw_rx_cons == hw_rx_cons)
6894                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6895         }
6896
6897         /* No new packets.  Refill the page chain. */
6898         if (bce_hdr_split == TRUE) {
6899                 sc->pg_cons = sw_pg_cons;
6900                 bce_fill_pg_chain(sc);
6901         }
6902
6903         /* No new packets.  Refill the RX chain. */
6904         sc->rx_cons = sw_rx_cons;
6905         bce_fill_rx_chain(sc);
6906
6907         /* Prepare the page chain pages to be accessed by the NIC. */
6908         for (int i = 0; i < sc->rx_pages; i++)
6909                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6910                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6911
6912         if (bce_hdr_split == TRUE) {
6913                 for (int i = 0; i < sc->pg_pages; i++)
6914                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6915                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6916         }
6917
6918         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6919             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6920             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6921         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6922 }
6923
6924
6925 /****************************************************************************/
6926 /* Reads the transmit consumer value from the status block (skipping over   */
6927 /* chain page pointer if necessary).                                        */
6928 /*                                                                          */
6929 /* Returns:                                                                 */
6930 /*   hw_cons                                                                */
6931 /****************************************************************************/
6932 static inline u16
6933 bce_get_hw_tx_cons(struct bce_softc *sc)
6934 {
6935         u16 hw_cons;
6936
6937         mb();
6938         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6939         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6940                 hw_cons++;
6941
6942         return hw_cons;
6943 }
6944
6945
6946 /****************************************************************************/
6947 /* Handles transmit completion interrupt events.                            */
6948 /*                                                                          */
6949 /* Returns:                                                                 */
6950 /*   Nothing.                                                               */
6951 /****************************************************************************/
6952 static void
6953 bce_tx_intr(struct bce_softc *sc)
6954 {
6955         struct ifnet *ifp = sc->bce_ifp;
6956         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6957
6958         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6959         DBRUN(sc->interrupts_tx++);
6960         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6961             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6962             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6963
6964         BCE_LOCK_ASSERT(sc);
6965
6966         /* Get the hardware's view of the TX consumer index. */
6967         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6968         sw_tx_cons = sc->tx_cons;
6969
6970         /* Prevent speculative reads of the status block. */
6971         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6972             BUS_SPACE_BARRIER_READ);
6973
6974         /* Cycle through any completed TX chain page entries. */
6975         while (sw_tx_cons != hw_tx_cons) {
6976 #ifdef BCE_DEBUG
6977                 struct tx_bd *txbd = NULL;
6978 #endif
6979                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6980
6981                 DBPRINT(sc, BCE_INFO_SEND,
6982                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6983                     "sw_tx_chain_cons = 0x%04X\n",
6984                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6985
6986                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6987                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6988                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6989                     (int) MAX_TX_BD_ALLOC);
6990                     bce_breakpoint(sc));
6991
6992                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6993                     [TX_IDX(sw_tx_chain_cons)]);
6994
6995                 DBRUNIF((txbd == NULL),
6996                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6997                     __FILE__, __LINE__, sw_tx_chain_cons);
6998                     bce_breakpoint(sc));
6999
7000                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
7001                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
7002
7003                 /*
7004                  * Free the associated mbuf. Remember
7005                  * that only the last tx_bd of a packet
7006                  * has an mbuf pointer and DMA map.
7007                  */
7008                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
7009
7010                         /* Validate that this is the last tx_bd. */
7011                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
7012                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
7013                             "txmbuf == NULL!\n", __FILE__, __LINE__);
7014                             bce_breakpoint(sc));
7015
7016                         DBRUNMSG(BCE_INFO_SEND,
7017                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
7018                             "from tx_bd[0x%04X]\n", __FUNCTION__,
7019                             sw_tx_chain_cons));
7020
7021                         /* Unmap the mbuf. */
7022                         bus_dmamap_unload(sc->tx_mbuf_tag,
7023                             sc->tx_mbuf_map[sw_tx_chain_cons]);
7024
7025                         /* Free the mbuf. */
7026                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
7027                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
7028                         DBRUN(sc->debug_tx_mbuf_alloc--);
7029
7030                         ifp->if_opackets++;
7031                 }
7032
7033                 sc->used_tx_bd--;
7034                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
7035
7036                 /* Refresh hw_cons to see if there's new work. */
7037                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7038
7039                 /* Prevent speculative reads of the status block. */
7040                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7041                     BUS_SPACE_BARRIER_READ);
7042         }
7043
7044         /* Clear the TX timeout timer. */
7045         sc->watchdog_timer = 0;
7046
7047         /* Clear the tx hardware queue full flag. */
7048         if (sc->used_tx_bd < sc->max_tx_bd) {
7049                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7050                     DBPRINT(sc, BCE_INFO_SEND,
7051                     "%s(): Open TX chain! %d/%d (used/total)\n",
7052                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7053                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7054         }
7055
7056         sc->tx_cons = sw_tx_cons;
7057
7058         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7059             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7060             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7061         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7062 }
7063
7064
7065 /****************************************************************************/
7066 /* Disables interrupt generation.                                           */
7067 /*                                                                          */
7068 /* Returns:                                                                 */
7069 /*   Nothing.                                                               */
7070 /****************************************************************************/
7071 static void
7072 bce_disable_intr(struct bce_softc *sc)
7073 {
7074         DBENTER(BCE_VERBOSE_INTR);
7075
7076         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7077         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7078
7079         DBEXIT(BCE_VERBOSE_INTR);
7080 }
7081
7082
7083 /****************************************************************************/
7084 /* Enables interrupt generation.                                            */
7085 /*                                                                          */
7086 /* Returns:                                                                 */
7087 /*   Nothing.                                                               */
7088 /****************************************************************************/
7089 static void
7090 bce_enable_intr(struct bce_softc *sc, int coal_now)
7091 {
7092         DBENTER(BCE_VERBOSE_INTR);
7093
7094         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7095             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7096             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7097
7098         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7099             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7100
7101         /* Force an immediate interrupt (whether there is new data or not). */
7102         if (coal_now)
7103                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7104
7105         DBEXIT(BCE_VERBOSE_INTR);
7106 }
7107
7108
7109 /****************************************************************************/
7110 /* Handles controller initialization.                                       */
7111 /*                                                                          */
7112 /* Returns:                                                                 */
7113 /*   Nothing.                                                               */
7114 /****************************************************************************/
7115 static void
7116 bce_init_locked(struct bce_softc *sc)
7117 {
7118         struct ifnet *ifp;
7119         u32 ether_mtu = 0;
7120
7121         DBENTER(BCE_VERBOSE_RESET);
7122
7123         BCE_LOCK_ASSERT(sc);
7124
7125         ifp = sc->bce_ifp;
7126
7127         /* Check if the driver is still running and bail out if it is. */
7128         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7129                 goto bce_init_locked_exit;
7130
7131         bce_stop(sc);
7132
7133         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7134                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7135                     __FILE__, __LINE__);
7136                 goto bce_init_locked_exit;
7137         }
7138
7139         if (bce_chipinit(sc)) {
7140                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7141                     __FILE__, __LINE__);
7142                 goto bce_init_locked_exit;
7143         }
7144
7145         if (bce_blockinit(sc)) {
7146                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7147                     __FILE__, __LINE__);
7148                 goto bce_init_locked_exit;
7149         }
7150
7151         /* Load our MAC address. */
7152         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7153         bce_set_mac_addr(sc);
7154
7155         if (bce_hdr_split == FALSE)
7156                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7157         /*
7158          * Calculate and program the hardware Ethernet MTU
7159          * size. Be generous on the receive if we have room
7160          * and allowed by the user.
7161          */
7162         if (bce_strict_rx_mtu == TRUE)
7163                 ether_mtu = ifp->if_mtu;
7164         else {
7165                 if (bce_hdr_split == TRUE) {
7166                         if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
7167                                    sc->pg_bd_mbuf_alloc_size))
7168                                         ether_mtu = sc->rx_bd_mbuf_data_len +
7169                                            sc->pg_bd_mbuf_alloc_size;
7170                         else
7171                                 ether_mtu = ifp->if_mtu;
7172                 } else {
7173                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7174                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7175                         else
7176                                 ether_mtu = ifp->if_mtu;
7177                 }
7178         }
7179
7180         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7181
7182         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7183             __FUNCTION__, ether_mtu);
7184
7185         /* Program the mtu, enabling jumbo frame support if necessary. */
7186         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7187                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7188                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7189                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7190         else
7191                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7192
7193         /* Program appropriate promiscuous/multicast filtering. */
7194         bce_set_rx_mode(sc);
7195
7196         if (bce_hdr_split == TRUE) {
7197                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
7198                         __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
7199
7200                 /* Init page buffer descriptor chain. */
7201                 bce_init_pg_chain(sc);
7202         }
7203
7204         /* Init RX buffer descriptor chain. */
7205         bce_init_rx_chain(sc);
7206
7207         /* Init TX buffer descriptor chain. */
7208         bce_init_tx_chain(sc);
7209
7210         /* Enable host interrupts. */
7211         bce_enable_intr(sc, 1);
7212
7213         bce_ifmedia_upd_locked(ifp);
7214
7215         /* Let the OS know the driver is up and running. */
7216         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7217         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7218
7219         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7220
7221 bce_init_locked_exit:
7222         DBEXIT(BCE_VERBOSE_RESET);
7223 }
7224
7225
7226 /****************************************************************************/
7227 /* Initialize the controller just enough so that any management firmware    */
7228 /* running on the device will continue to operate correctly.                */
7229 /*                                                                          */
7230 /* Returns:                                                                 */
7231 /*   Nothing.                                                               */
7232 /****************************************************************************/
7233 static void
7234 bce_mgmt_init_locked(struct bce_softc *sc)
7235 {
7236         struct ifnet *ifp;
7237
7238         DBENTER(BCE_VERBOSE_RESET);
7239
7240         BCE_LOCK_ASSERT(sc);
7241
7242         /* Bail out if management firmware is not running. */
7243         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7244                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7245                     "No management firmware running...\n");
7246                 goto bce_mgmt_init_locked_exit;
7247         }
7248
7249         ifp = sc->bce_ifp;
7250
7251         /* Enable all critical blocks in the MAC. */
7252         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7253         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7254         DELAY(20);
7255
7256         bce_ifmedia_upd_locked(ifp);
7257
7258 bce_mgmt_init_locked_exit:
7259         DBEXIT(BCE_VERBOSE_RESET);
7260 }
7261
7262
7263 /****************************************************************************/
7264 /* Handles controller initialization when called from an unlocked routine.  */
7265 /*                                                                          */
7266 /* Returns:                                                                 */
7267 /*   Nothing.                                                               */
7268 /****************************************************************************/
7269 static void
7270 bce_init(void *xsc)
7271 {
7272         struct bce_softc *sc = xsc;
7273
7274         DBENTER(BCE_VERBOSE_RESET);
7275
7276         BCE_LOCK(sc);
7277         bce_init_locked(sc);
7278         BCE_UNLOCK(sc);
7279
7280         DBEXIT(BCE_VERBOSE_RESET);
7281 }
7282
7283
7284 /****************************************************************************/
7285 /* Modifies an mbuf for TSO on the hardware.                                */
7286 /*                                                                          */
7287 /* Returns:                                                                 */
7288 /*   Pointer to a modified mbuf.                                            */
7289 /****************************************************************************/
7290 static struct mbuf *
7291 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7292 {
7293         struct mbuf *m;
7294         struct ether_header *eh;
7295         struct ip *ip;
7296         struct tcphdr *th;
7297         u16 etype;
7298         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7299
7300         DBRUN(sc->tso_frames_requested++);
7301
7302         /* Controller may modify mbuf chains. */
7303         if (M_WRITABLE(*m_head) == 0) {
7304                 m = m_dup(*m_head, M_DONTWAIT);
7305                 m_freem(*m_head);
7306                 if (m == NULL) {
7307                         sc->mbuf_alloc_failed_count++;
7308                         *m_head = NULL;
7309                         return (NULL);
7310                 }
7311                 *m_head = m;
7312         }
7313
7314         /*
7315          * For TSO the controller needs two pieces of info,
7316          * the MSS and the IP+TCP options length.
7317          */
7318         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7319         if (m == NULL) {
7320                 *m_head = NULL;
7321                 return (NULL);
7322         }
7323         eh = mtod(m, struct ether_header *);
7324         etype = ntohs(eh->ether_type);
7325
7326         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7327         switch (etype) {
7328         case ETHERTYPE_IP:
7329                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7330                 /* TSO only supported for TCP protocol. */
7331                 if (ip->ip_p != IPPROTO_TCP) {
7332                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7333                             __FILE__, __LINE__);
7334                         m_freem(*m_head);
7335                         *m_head = NULL;
7336                         return (NULL);
7337                 }
7338
7339                 /* Get IP header length in bytes (min 20) */
7340                 ip_hlen = ip->ip_hl << 2;
7341                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7342                     sizeof(struct tcphdr));
7343                 if (m == NULL) {
7344                         *m_head = NULL;
7345                         return (NULL);
7346                 }
7347
7348                 /* Get the TCP header length in bytes (min 20) */
7349                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7350                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7351                 tcp_hlen = (th->th_off << 2);
7352
7353                 /* Make sure all IP/TCP options live in the same buffer. */
7354                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7355                     tcp_hlen);
7356                 if (m == NULL) {
7357                         *m_head = NULL;
7358                         return (NULL);
7359                 }
7360
7361                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7362                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7363                 ip_len = ip->ip_len;
7364                 ip->ip_len = 0;
7365                 ip->ip_sum = 0;
7366                 break;
7367         case ETHERTYPE_IPV6:
7368                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7369                     __FILE__, __LINE__);
7370                 m_freem(*m_head);
7371                 *m_head = NULL;
7372                 return (NULL);
7373                 /* NOT REACHED */
7374         default:
7375                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7376                     __FILE__, __LINE__);
7377                 m_freem(*m_head);
7378                 *m_head = NULL;
7379                 return (NULL);
7380         }
7381
7382         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7383
7384         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7385             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7386             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7387             tcp_hlen, ip_len);
7388
7389         /* Set the LSO flag in the TX BD */
7390         *flags |= TX_BD_FLAGS_SW_LSO;
7391
7392         /* Set the length of IP + TCP options (in 32 bit words) */
7393         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7394             sizeof(struct tcphdr)) >> 2) << 8);
7395
7396         DBRUN(sc->tso_frames_completed++);
7397         return (*m_head);
7398 }
7399
7400
7401 /****************************************************************************/
7402 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7403 /* memory visible to the controller.                                        */
7404 /*                                                                          */
7405 /* Returns:                                                                 */
7406 /*   0 for success, positive value for failure.                             */
7407 /* Modified:                                                                */
7408 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7409 /****************************************************************************/
7410 static int
7411 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7412 {
7413         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7414         bus_dmamap_t map;
7415         struct tx_bd *txbd = NULL;
7416         struct mbuf *m0;
7417         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7418         u32 prod_bseq;
7419
7420 #ifdef BCE_DEBUG
7421         u16 debug_prod;
7422 #endif
7423
7424         int i, error, nsegs, rc = 0;
7425
7426         DBENTER(BCE_VERBOSE_SEND);
7427
7428         /* Make sure we have room in the TX chain. */
7429         if (sc->used_tx_bd >= sc->max_tx_bd)
7430                 goto bce_tx_encap_exit;
7431
7432         /* Transfer any checksum offload flags to the bd. */
7433         m0 = *m_head;
7434         if (m0->m_pkthdr.csum_flags) {
7435                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7436                         m0 = bce_tso_setup(sc, m_head, &flags);
7437                         if (m0 == NULL) {
7438                                 DBRUN(sc->tso_frames_failed++);
7439                                 goto bce_tx_encap_exit;
7440                         }
7441                         mss = htole16(m0->m_pkthdr.tso_segsz);
7442                 } else {
7443                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7444                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7445                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7446                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7447                 }
7448         }
7449
7450         /* Transfer any VLAN tags to the bd. */
7451         if (m0->m_flags & M_VLANTAG) {
7452                 flags |= TX_BD_FLAGS_VLAN_TAG;
7453                 vlan_tag = m0->m_pkthdr.ether_vtag;
7454         }
7455
7456         /* Map the mbuf into DMAable memory. */
7457         prod = sc->tx_prod;
7458         chain_prod = TX_CHAIN_IDX(prod);
7459         map = sc->tx_mbuf_map[chain_prod];
7460
7461         /* Map the mbuf into our DMA address space. */
7462         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7463             segs, &nsegs, BUS_DMA_NOWAIT);
7464
7465         /* Check if the DMA mapping was successful */
7466         if (error == EFBIG) {
7467                 sc->mbuf_frag_count++;
7468
7469                 /* Try to defrag the mbuf. */
7470                 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS);
7471                 if (m0 == NULL) {
7472                         /* Defrag was unsuccessful */
7473                         m_freem(*m_head);
7474                         *m_head = NULL;
7475                         sc->mbuf_alloc_failed_count++;
7476                         rc = ENOBUFS;
7477                         goto bce_tx_encap_exit;
7478                 }
7479
7480                 /* Defrag was successful, try mapping again */
7481                 *m_head = m0;
7482                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7483                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7484
7485                 /* Still getting an error after a defrag. */
7486                 if (error == ENOMEM) {
7487                         /* Insufficient DMA buffers available. */
7488                         sc->dma_map_addr_tx_failed_count++;
7489                         rc = error;
7490                         goto bce_tx_encap_exit;
7491                 } else if (error != 0) {
7492                         /* Release it and return an error. */
7493                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7494                             "TX chain!\n", __FILE__, __LINE__);
7495                         m_freem(m0);
7496                         *m_head = NULL;
7497                         sc->dma_map_addr_tx_failed_count++;
7498                         rc = ENOBUFS;
7499                         goto bce_tx_encap_exit;
7500                 }
7501         } else if (error == ENOMEM) {
7502                 /* Insufficient DMA buffers available. */
7503                 sc->dma_map_addr_tx_failed_count++;
7504                 rc = error;
7505                 goto bce_tx_encap_exit;
7506         } else if (error != 0) {
7507                 m_freem(m0);
7508                 *m_head = NULL;
7509                 sc->dma_map_addr_tx_failed_count++;
7510                 rc = error;
7511                 goto bce_tx_encap_exit;
7512         }
7513
7514         /* Make sure there's room in the chain */
7515         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7516                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7517                 rc = ENOBUFS;
7518                 goto bce_tx_encap_exit;
7519         }
7520
7521         /* prod points to an empty tx_bd at this point. */
7522         prod_bseq  = sc->tx_prod_bseq;
7523
7524 #ifdef BCE_DEBUG
7525         debug_prod = chain_prod;
7526 #endif
7527
7528         DBPRINT(sc, BCE_INFO_SEND,
7529             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7530             "prod_bseq = 0x%08X\n",
7531             __FUNCTION__, prod, chain_prod, prod_bseq);
7532
7533         /*
7534          * Cycle through each mbuf segment that makes up
7535          * the outgoing frame, gathering the mapping info
7536          * for that segment and creating a tx_bd for
7537          * the mbuf.
7538          */
7539         for (i = 0; i < nsegs ; i++) {
7540
7541                 chain_prod = TX_CHAIN_IDX(prod);
7542                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7543                     [TX_IDX(chain_prod)];
7544
7545                 txbd->tx_bd_haddr_lo =
7546                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7547                 txbd->tx_bd_haddr_hi =
7548                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7549                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7550                     htole16(segs[i].ds_len);
7551                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7552                 txbd->tx_bd_flags = htole16(flags);
7553                 prod_bseq += segs[i].ds_len;
7554                 if (i == 0)
7555                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7556                 prod = NEXT_TX_BD(prod);
7557         }
7558
7559         /* Set the END flag on the last TX buffer descriptor. */
7560         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7561
7562         DBRUNMSG(BCE_EXTREME_SEND,
7563             bce_dump_tx_chain(sc, debug_prod, nsegs));
7564
7565         /*
7566          * Ensure that the mbuf pointer for this transmission
7567          * is placed at the array index of the last
7568          * descriptor in this chain.  This is done
7569          * because a single map is used for all
7570          * segments of the mbuf and we don't want to
7571          * unload the map before all of the segments
7572          * have been freed.
7573          */
7574         sc->tx_mbuf_ptr[chain_prod] = m0;
7575         sc->used_tx_bd += nsegs;
7576
7577         /* Update some debug statistic counters */
7578         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7579             sc->tx_hi_watermark = sc->used_tx_bd);
7580         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7581         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7582
7583         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7584
7585         /* prod points to the next free tx_bd at this point. */
7586         sc->tx_prod = prod;
7587         sc->tx_prod_bseq = prod_bseq;
7588
7589         /* Tell the chip about the waiting TX frames. */
7590         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7591             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7592         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7593             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7594
7595 bce_tx_encap_exit:
7596         DBEXIT(BCE_VERBOSE_SEND);
7597         return(rc);
7598 }
7599
7600
7601 /****************************************************************************/
7602 /* Main transmit routine when called from another routine with a lock.      */
7603 /*                                                                          */
7604 /* Returns:                                                                 */
7605 /*   Nothing.                                                               */
7606 /****************************************************************************/
7607 static void
7608 bce_start_locked(struct ifnet *ifp)
7609 {
7610         struct bce_softc *sc = ifp->if_softc;
7611         struct mbuf *m_head = NULL;
7612         int count = 0;
7613         u16 tx_prod, tx_chain_prod;
7614
7615         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7616
7617         BCE_LOCK_ASSERT(sc);
7618
7619         /* prod points to the next free tx_bd. */
7620         tx_prod = sc->tx_prod;
7621         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7622
7623         DBPRINT(sc, BCE_INFO_SEND,
7624             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7625             "tx_prod_bseq = 0x%08X\n",
7626             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7627
7628         /* If there's no link or the transmit queue is empty then just exit. */
7629         if (sc->bce_link_up == FALSE) {
7630                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7631                     __FUNCTION__);
7632                 goto bce_start_locked_exit;
7633         }
7634
7635         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7636                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7637                     __FUNCTION__);
7638                 goto bce_start_locked_exit;
7639         }
7640
7641         /*
7642          * Keep adding entries while there is space in the ring.
7643          */
7644         while (sc->used_tx_bd < sc->max_tx_bd) {
7645
7646                 /* Check for any frames to send. */
7647                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7648
7649                 /* Stop when the transmit queue is empty. */
7650                 if (m_head == NULL)
7651                         break;
7652
7653                 /*
7654                  * Pack the data into the transmit ring. If we
7655                  * don't have room, place the mbuf back at the
7656                  * head of the queue and set the OACTIVE flag
7657                  * to wait for the NIC to drain the chain.
7658                  */
7659                 if (bce_tx_encap(sc, &m_head)) {
7660                         if (m_head != NULL)
7661                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7662                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7663                         DBPRINT(sc, BCE_INFO_SEND,
7664                             "TX chain is closed for business! Total "
7665                             "tx_bd used = %d\n", sc->used_tx_bd);
7666                         break;
7667                 }
7668
7669                 count++;
7670
7671                 /* Send a copy of the frame to any BPF listeners. */
7672                 ETHER_BPF_MTAP(ifp, m_head);
7673         }
7674
7675         /* Exit if no packets were dequeued. */
7676         if (count == 0) {
7677                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7678                     "dequeued\n", __FUNCTION__);
7679                 goto bce_start_locked_exit;
7680         }
7681
7682         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7683             "send queue.\n", __FUNCTION__, count);
7684
7685         /* Set the tx timeout. */
7686         sc->watchdog_timer = BCE_TX_TIMEOUT;
7687
7688         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7689         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7690
7691 bce_start_locked_exit:
7692         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7693         return;
7694 }
7695
7696
7697 /****************************************************************************/
7698 /* Main transmit routine when called from another routine without a lock.   */
7699 /*                                                                          */
7700 /* Returns:                                                                 */
7701 /*   Nothing.                                                               */
7702 /****************************************************************************/
7703 static void
7704 bce_start(struct ifnet *ifp)
7705 {
7706         struct bce_softc *sc = ifp->if_softc;
7707
7708         DBENTER(BCE_VERBOSE_SEND);
7709
7710         BCE_LOCK(sc);
7711         bce_start_locked(ifp);
7712         BCE_UNLOCK(sc);
7713
7714         DBEXIT(BCE_VERBOSE_SEND);
7715 }
7716
7717
7718 /****************************************************************************/
7719 /* Handles any IOCTL calls from the operating system.                       */
7720 /*                                                                          */
7721 /* Returns:                                                                 */
7722 /*   0 for success, positive value for failure.                             */
7723 /****************************************************************************/
7724 static int
7725 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7726 {
7727         struct bce_softc *sc = ifp->if_softc;
7728         struct ifreq *ifr = (struct ifreq *) data;
7729         struct mii_data *mii;
7730         int mask, error = 0;
7731
7732         DBENTER(BCE_VERBOSE_MISC);
7733
7734         switch(command) {
7735
7736         /* Set the interface MTU. */
7737         case SIOCSIFMTU:
7738                 /* Check that the MTU setting is supported. */
7739                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7740                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7741                         error = EINVAL;
7742                         break;
7743                 }
7744
7745                 DBPRINT(sc, BCE_INFO_MISC,
7746                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7747                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7748
7749                 BCE_LOCK(sc);
7750                 ifp->if_mtu = ifr->ifr_mtu;
7751                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7752                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7753                         bce_init_locked(sc);
7754                 }
7755                 BCE_UNLOCK(sc);
7756                 break;
7757
7758         /* Set interface flags. */
7759         case SIOCSIFFLAGS:
7760                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7761
7762                 BCE_LOCK(sc);
7763
7764                 /* Check if the interface is up. */
7765                 if (ifp->if_flags & IFF_UP) {
7766                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7767                                 /* Change promiscuous/multicast flags as necessary. */
7768                                 bce_set_rx_mode(sc);
7769                         } else {
7770                                 /* Start the HW */
7771                                 bce_init_locked(sc);
7772                         }
7773                 } else {
7774                         /* The interface is down, check if driver is running. */
7775                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7776                                 bce_stop(sc);
7777
7778                                 /* If MFW is running, restart the controller a bit. */
7779                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7780                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7781                                         bce_chipinit(sc);
7782                                         bce_mgmt_init_locked(sc);
7783                                 }
7784                         }
7785                 }
7786
7787                 BCE_UNLOCK(sc);
7788                 break;
7789
7790         /* Add/Delete multicast address */
7791         case SIOCADDMULTI:
7792         case SIOCDELMULTI:
7793                 DBPRINT(sc, BCE_VERBOSE_MISC,
7794                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7795
7796                 BCE_LOCK(sc);
7797                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7798                         bce_set_rx_mode(sc);
7799                 BCE_UNLOCK(sc);
7800
7801                 break;
7802
7803         /* Set/Get Interface media */
7804         case SIOCSIFMEDIA:
7805         case SIOCGIFMEDIA:
7806                 DBPRINT(sc, BCE_VERBOSE_MISC,
7807                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7808                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7809                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7810                             command);
7811                 else {
7812                         mii = device_get_softc(sc->bce_miibus);
7813                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7814                             command);
7815                 }
7816                 break;
7817
7818         /* Set interface capability */
7819         case SIOCSIFCAP:
7820                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7821                 DBPRINT(sc, BCE_INFO_MISC,
7822                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7823
7824                 /* Toggle the TX checksum capabilities enable flag. */
7825                 if (mask & IFCAP_TXCSUM &&
7826                     ifp->if_capabilities & IFCAP_TXCSUM) {
7827                         ifp->if_capenable ^= IFCAP_TXCSUM;
7828                         if (IFCAP_TXCSUM & ifp->if_capenable)
7829                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7830                         else
7831                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7832                 }
7833
7834                 /* Toggle the RX checksum capabilities enable flag. */
7835                 if (mask & IFCAP_RXCSUM &&
7836                     ifp->if_capabilities & IFCAP_RXCSUM)
7837                         ifp->if_capenable ^= IFCAP_RXCSUM;
7838
7839                 /* Toggle the TSO capabilities enable flag. */
7840                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7841                     ifp->if_capabilities & IFCAP_TSO4) {
7842                         ifp->if_capenable ^= IFCAP_TSO4;
7843                         if (IFCAP_TSO4 & ifp->if_capenable)
7844                                 ifp->if_hwassist |= CSUM_TSO;
7845                         else
7846                                 ifp->if_hwassist &= ~CSUM_TSO;
7847                 }
7848
7849                 if (mask & IFCAP_VLAN_HWCSUM &&
7850                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7851                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7852
7853                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7854                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7855                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7856                 /*
7857                  * Don't actually disable VLAN tag stripping as
7858                  * management firmware (ASF/IPMI/UMP) requires the
7859                  * feature. If VLAN tag stripping is disabled driver
7860                  * will manually reconstruct the VLAN frame by
7861                  * appending stripped VLAN tag.
7862                  */
7863                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7864                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7865                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7866                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7867                             == 0)
7868                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7869                 }
7870                 VLAN_CAPABILITIES(ifp);
7871                 break;
7872         default:
7873                 /* We don't know how to handle the IOCTL, pass it on. */
7874                 error = ether_ioctl(ifp, command, data);
7875                 break;
7876         }
7877
7878         DBEXIT(BCE_VERBOSE_MISC);
7879         return(error);
7880 }
7881
7882
7883 /****************************************************************************/
7884 /* Transmit timeout handler.                                                */
7885 /*                                                                          */
7886 /* Returns:                                                                 */
7887 /*   Nothing.                                                               */
7888 /****************************************************************************/
7889 static void
7890 bce_watchdog(struct bce_softc *sc)
7891 {
7892         uint32_t status;
7893
7894         DBENTER(BCE_EXTREME_SEND);
7895
7896         BCE_LOCK_ASSERT(sc);
7897
7898         status = 0;
7899         /* If the watchdog timer hasn't expired then just exit. */
7900         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7901                 goto bce_watchdog_exit;
7902
7903         status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7904         /* If pause frames are active then don't reset the hardware. */
7905         if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7906                 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7907                         /*
7908                          * If link partner has us in XOFF state then wait for
7909                          * the condition to clear.
7910                          */
7911                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7912                         goto bce_watchdog_exit;
7913                 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7914                         (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7915                         /*
7916                          * If we're not currently XOFF'ed but have recently
7917                          * been XOFF'd/XON'd then assume that's delaying TX
7918                          * this time around.
7919                          */
7920                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7921                         goto bce_watchdog_exit;
7922                 }
7923                 /*
7924                  * Any other condition is unexpected and the controller
7925                  * should be reset.
7926                  */
7927         }
7928
7929         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7930             __FILE__, __LINE__);
7931
7932         DBRUNMSG(BCE_INFO,
7933             bce_dump_driver_state(sc);
7934             bce_dump_status_block(sc);
7935             bce_dump_stats_block(sc);
7936             bce_dump_ftqs(sc);
7937             bce_dump_txp_state(sc, 0);
7938             bce_dump_rxp_state(sc, 0);
7939             bce_dump_tpat_state(sc, 0);
7940             bce_dump_cp_state(sc, 0);
7941             bce_dump_com_state(sc, 0));
7942
7943         DBRUN(bce_breakpoint(sc));
7944
7945         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7946
7947         bce_init_locked(sc);
7948         sc->bce_ifp->if_oerrors++;
7949
7950 bce_watchdog_exit:
7951         REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7952         DBEXIT(BCE_EXTREME_SEND);
7953 }
7954
7955
7956 /*
7957  * Interrupt handler.
7958  */
7959 /****************************************************************************/
7960 /* Main interrupt entry point.  Verifies that the controller generated the  */
7961 /* interrupt and then calls a separate routine for handle the various       */
7962 /* interrupt causes (PHY, TX, RX).                                          */
7963 /*                                                                          */
7964 /* Returns:                                                                 */
7965 /*   0 for success, positive value for failure.                             */
7966 /****************************************************************************/
7967 static void
7968 bce_intr(void *xsc)
7969 {
7970         struct bce_softc *sc;
7971         struct ifnet *ifp;
7972         u32 status_attn_bits;
7973         u16 hw_rx_cons, hw_tx_cons;
7974
7975         sc = xsc;
7976         ifp = sc->bce_ifp;
7977
7978         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7979         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7980         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7981
7982         BCE_LOCK(sc);
7983
7984         DBRUN(sc->interrupts_generated++);
7985
7986         /* Synchnorize before we read from interface's status block */
7987         bus_dmamap_sync(sc->status_tag, sc->status_map,
7988             BUS_DMASYNC_POSTREAD);
7989
7990         /*
7991          * If the hardware status block index
7992          * matches the last value read by the
7993          * driver and we haven't asserted our
7994          * interrupt then there's nothing to do.
7995          */
7996         if ((sc->status_block->status_idx == sc->last_status_idx) &&
7997             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7998              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7999                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
8000                     __FUNCTION__);
8001                 goto bce_intr_exit;
8002         }
8003
8004         /* Ack the interrupt and stop others from occuring. */
8005         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
8006             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
8007             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
8008
8009         /* Check if the hardware has finished any work. */
8010         hw_rx_cons = bce_get_hw_rx_cons(sc);
8011         hw_tx_cons = bce_get_hw_tx_cons(sc);
8012
8013         /* Keep processing data as long as there is work to do. */
8014         for (;;) {
8015
8016                 status_attn_bits = sc->status_block->status_attn_bits;
8017
8018                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
8019                     BCE_PRINTF("Simulating unexpected status attention "
8020                     "bit set.");
8021                     sc->unexpected_attention_sim_count++;
8022                     status_attn_bits = status_attn_bits |
8023                     STATUS_ATTN_BITS_PARITY_ERROR);
8024
8025                 /* Was it a link change interrupt? */
8026                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
8027                     (sc->status_block->status_attn_bits_ack &
8028                      STATUS_ATTN_BITS_LINK_STATE)) {
8029                         bce_phy_intr(sc);
8030
8031                         /* Clear transient updates during link state change. */
8032                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
8033                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
8034                         REG_RD(sc, BCE_HC_COMMAND);
8035                 }
8036
8037                 /* If any other attention is asserted, the chip is toast. */
8038                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
8039                     (sc->status_block->status_attn_bits_ack &
8040                     ~STATUS_ATTN_BITS_LINK_STATE))) {
8041
8042                         sc->unexpected_attention_count++;
8043
8044                         BCE_PRINTF("%s(%d): Fatal attention detected: "
8045                             "0x%08X\n", __FILE__, __LINE__,
8046                             sc->status_block->status_attn_bits);
8047
8048                         DBRUNMSG(BCE_FATAL,
8049                             if (unexpected_attention_sim_control == 0)
8050                                 bce_breakpoint(sc));
8051
8052                         bce_init_locked(sc);
8053                         goto bce_intr_exit;
8054                 }
8055
8056                 /* Check for any completed RX frames. */
8057                 if (hw_rx_cons != sc->hw_rx_cons)
8058                         bce_rx_intr(sc);
8059
8060                 /* Check for any completed TX frames. */
8061                 if (hw_tx_cons != sc->hw_tx_cons)
8062                         bce_tx_intr(sc);
8063
8064                 /* Save status block index value for the next interrupt. */
8065                 sc->last_status_idx = sc->status_block->status_idx;
8066
8067                 /*
8068                  * Prevent speculative reads from getting
8069                  * ahead of the status block.
8070                  */
8071                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8072                     BUS_SPACE_BARRIER_READ);
8073
8074                 /*
8075                  * If there's no work left then exit the
8076                  * interrupt service routine.
8077                  */
8078                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8079                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8080
8081                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8082                     (hw_tx_cons == sc->hw_tx_cons))
8083                         break;
8084
8085         }
8086
8087         bus_dmamap_sync(sc->status_tag, sc->status_map,
8088             BUS_DMASYNC_PREREAD);
8089
8090         /* Re-enable interrupts. */
8091         bce_enable_intr(sc, 0);
8092
8093         /* Handle any frames that arrived while handling the interrupt. */
8094         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8095             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8096                 bce_start_locked(ifp);
8097
8098 bce_intr_exit:
8099         BCE_UNLOCK(sc);
8100
8101         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8102 }
8103
8104
8105 /****************************************************************************/
8106 /* Programs the various packet receive modes (broadcast and multicast).     */
8107 /*                                                                          */
8108 /* Returns:                                                                 */
8109 /*   Nothing.                                                               */
8110 /****************************************************************************/
8111 static void
8112 bce_set_rx_mode(struct bce_softc *sc)
8113 {
8114         struct ifnet *ifp;
8115         struct ifmultiaddr *ifma;
8116         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8117         u32 rx_mode, sort_mode;
8118         int h, i;
8119
8120         DBENTER(BCE_VERBOSE_MISC);
8121
8122         BCE_LOCK_ASSERT(sc);
8123
8124         ifp = sc->bce_ifp;
8125
8126         /* Initialize receive mode default settings. */
8127         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8128             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8129         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8130
8131         /*
8132          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8133          * be enbled.
8134          */
8135         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8136             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8137                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8138
8139         /*
8140          * Check for promiscuous, all multicast, or selected
8141          * multicast address filtering.
8142          */
8143         if (ifp->if_flags & IFF_PROMISC) {
8144                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8145
8146                 /* Enable promiscuous mode. */
8147                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8148                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8149         } else if (ifp->if_flags & IFF_ALLMULTI) {
8150                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8151
8152                 /* Enable all multicast addresses. */
8153                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8154                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
8155         }
8156                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8157         } else {
8158                 /* Accept one or more multicast(s). */
8159                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8160
8161                 if_maddr_rlock(ifp);
8162                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8163                         if (ifma->ifma_addr->sa_family != AF_LINK)
8164                                 continue;
8165                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8166                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8167                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8168                 }
8169                 if_maddr_runlock(ifp);
8170
8171                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8172                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8173
8174                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8175         }
8176
8177         /* Only make changes if the recive mode has actually changed. */
8178         if (rx_mode != sc->rx_mode) {
8179                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8180                     "0x%08X\n", rx_mode);
8181
8182                 sc->rx_mode = rx_mode;
8183                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8184         }
8185
8186         /* Disable and clear the exisitng sort before enabling a new sort. */
8187         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8188         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8189         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8190
8191         DBEXIT(BCE_VERBOSE_MISC);
8192 }
8193
8194
8195 /****************************************************************************/
8196 /* Called periodically to updates statistics from the controllers           */
8197 /* statistics block.                                                        */
8198 /*                                                                          */
8199 /* Returns:                                                                 */
8200 /*   Nothing.                                                               */
8201 /****************************************************************************/
8202 static void
8203 bce_stats_update(struct bce_softc *sc)
8204 {
8205         struct ifnet *ifp;
8206         struct statistics_block *stats;
8207
8208         DBENTER(BCE_EXTREME_MISC);
8209
8210         ifp = sc->bce_ifp;
8211
8212         stats = (struct statistics_block *) sc->stats_block;
8213
8214         /*
8215          * Certain controllers don't report
8216          * carrier sense errors correctly.
8217          * See errata E11_5708CA0_1165.
8218          */
8219         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8220             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8221                 ifp->if_oerrors +=
8222                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8223
8224         /*
8225          * Update the sysctl statistics from the
8226          * hardware statistics.
8227          */
8228         sc->stat_IfHCInOctets =
8229             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8230              (u64) stats->stat_IfHCInOctets_lo;
8231
8232         sc->stat_IfHCInBadOctets =
8233             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8234              (u64) stats->stat_IfHCInBadOctets_lo;
8235
8236         sc->stat_IfHCOutOctets =
8237             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8238              (u64) stats->stat_IfHCOutOctets_lo;
8239
8240         sc->stat_IfHCOutBadOctets =
8241             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8242              (u64) stats->stat_IfHCOutBadOctets_lo;
8243
8244         sc->stat_IfHCInUcastPkts =
8245             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8246              (u64) stats->stat_IfHCInUcastPkts_lo;
8247
8248         sc->stat_IfHCInMulticastPkts =
8249             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8250              (u64) stats->stat_IfHCInMulticastPkts_lo;
8251
8252         sc->stat_IfHCInBroadcastPkts =
8253             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8254              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8255
8256         sc->stat_IfHCOutUcastPkts =
8257             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8258              (u64) stats->stat_IfHCOutUcastPkts_lo;
8259
8260         sc->stat_IfHCOutMulticastPkts =
8261             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8262              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8263
8264         sc->stat_IfHCOutBroadcastPkts =
8265             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8266              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8267
8268         /* ToDo: Preserve counters beyond 32 bits? */
8269         /* ToDo: Read the statistics from auto-clear regs? */
8270
8271         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8272             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8273
8274         sc->stat_Dot3StatsCarrierSenseErrors =
8275             stats->stat_Dot3StatsCarrierSenseErrors;
8276
8277         sc->stat_Dot3StatsFCSErrors =
8278             stats->stat_Dot3StatsFCSErrors;
8279
8280         sc->stat_Dot3StatsAlignmentErrors =
8281             stats->stat_Dot3StatsAlignmentErrors;
8282
8283         sc->stat_Dot3StatsSingleCollisionFrames =
8284             stats->stat_Dot3StatsSingleCollisionFrames;
8285
8286         sc->stat_Dot3StatsMultipleCollisionFrames =
8287             stats->stat_Dot3StatsMultipleCollisionFrames;
8288
8289         sc->stat_Dot3StatsDeferredTransmissions =
8290             stats->stat_Dot3StatsDeferredTransmissions;
8291
8292         sc->stat_Dot3StatsExcessiveCollisions =
8293             stats->stat_Dot3StatsExcessiveCollisions;
8294
8295         sc->stat_Dot3StatsLateCollisions =
8296             stats->stat_Dot3StatsLateCollisions;
8297
8298         sc->stat_EtherStatsCollisions =
8299             stats->stat_EtherStatsCollisions;
8300
8301         sc->stat_EtherStatsFragments =
8302             stats->stat_EtherStatsFragments;
8303
8304         sc->stat_EtherStatsJabbers =
8305             stats->stat_EtherStatsJabbers;
8306
8307         sc->stat_EtherStatsUndersizePkts =
8308             stats->stat_EtherStatsUndersizePkts;
8309
8310         sc->stat_EtherStatsOversizePkts =
8311              stats->stat_EtherStatsOversizePkts;
8312
8313         sc->stat_EtherStatsPktsRx64Octets =
8314             stats->stat_EtherStatsPktsRx64Octets;
8315
8316         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8317             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8318
8319         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8320             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8321
8322         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8323             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8324
8325         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8326             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8327
8328         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8329             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8330
8331         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8332             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8333
8334         sc->stat_EtherStatsPktsTx64Octets =
8335             stats->stat_EtherStatsPktsTx64Octets;
8336
8337         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8338             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8339
8340         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8341             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8342
8343         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8344             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8345
8346         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8347             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8348
8349         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8350             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8351
8352         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8353             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8354
8355         sc->stat_XonPauseFramesReceived =
8356             stats->stat_XonPauseFramesReceived;
8357
8358         sc->stat_XoffPauseFramesReceived =
8359             stats->stat_XoffPauseFramesReceived;
8360
8361         sc->stat_OutXonSent =
8362             stats->stat_OutXonSent;
8363
8364         sc->stat_OutXoffSent =
8365             stats->stat_OutXoffSent;
8366
8367         sc->stat_FlowControlDone =
8368             stats->stat_FlowControlDone;
8369
8370         sc->stat_MacControlFramesReceived =
8371             stats->stat_MacControlFramesReceived;
8372
8373         sc->stat_XoffStateEntered =
8374             stats->stat_XoffStateEntered;
8375
8376         sc->stat_IfInFramesL2FilterDiscards =
8377             stats->stat_IfInFramesL2FilterDiscards;
8378
8379         sc->stat_IfInRuleCheckerDiscards =
8380             stats->stat_IfInRuleCheckerDiscards;
8381
8382         sc->stat_IfInFTQDiscards =
8383             stats->stat_IfInFTQDiscards;
8384
8385         sc->stat_IfInMBUFDiscards =
8386             stats->stat_IfInMBUFDiscards;
8387
8388         sc->stat_IfInRuleCheckerP4Hit =
8389             stats->stat_IfInRuleCheckerP4Hit;
8390
8391         sc->stat_CatchupInRuleCheckerDiscards =
8392             stats->stat_CatchupInRuleCheckerDiscards;
8393
8394         sc->stat_CatchupInFTQDiscards =
8395             stats->stat_CatchupInFTQDiscards;
8396
8397         sc->stat_CatchupInMBUFDiscards =
8398             stats->stat_CatchupInMBUFDiscards;
8399
8400         sc->stat_CatchupInRuleCheckerP4Hit =
8401             stats->stat_CatchupInRuleCheckerP4Hit;
8402
8403         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8404
8405         /*
8406          * Update the interface statistics from the
8407          * hardware statistics.
8408          */
8409         ifp->if_collisions =
8410             (u_long) sc->stat_EtherStatsCollisions;
8411
8412         /* ToDo: This method loses soft errors. */
8413         ifp->if_ierrors =
8414             (u_long) sc->stat_EtherStatsUndersizePkts +
8415             (u_long) sc->stat_EtherStatsOversizePkts +
8416             (u_long) sc->stat_IfInMBUFDiscards +
8417             (u_long) sc->stat_Dot3StatsAlignmentErrors +
8418             (u_long) sc->stat_Dot3StatsFCSErrors +
8419             (u_long) sc->stat_IfInRuleCheckerDiscards +
8420             (u_long) sc->stat_IfInFTQDiscards +
8421             (u_long) sc->com_no_buffers;
8422
8423         /* ToDo: This method loses soft errors. */
8424         ifp->if_oerrors =
8425             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8426             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8427             (u_long) sc->stat_Dot3StatsLateCollisions;
8428
8429         /* ToDo: Add additional statistics? */
8430
8431         DBEXIT(BCE_EXTREME_MISC);
8432 }
8433
8434
8435 /****************************************************************************/
8436 /* Periodic function to notify the bootcode that the driver is still        */
8437 /* present.                                                                 */
8438 /*                                                                          */
8439 /* Returns:                                                                 */
8440 /*   Nothing.                                                               */
8441 /****************************************************************************/
8442 static void
8443 bce_pulse(void *xsc)
8444 {
8445         struct bce_softc *sc = xsc;
8446         u32 msg;
8447
8448         DBENTER(BCE_EXTREME_MISC);
8449
8450         BCE_LOCK_ASSERT(sc);
8451
8452         /* Tell the firmware that the driver is still running. */
8453         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8454         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8455
8456         /* Update the bootcode condition. */
8457         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8458
8459         /* Report whether the bootcode still knows the driver is running. */
8460         if (bce_verbose || bootverbose) {
8461                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8462                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8463                                 sc->bce_drv_cardiac_arrest = TRUE;
8464                                 BCE_PRINTF("%s(): Warning: bootcode "
8465                                     "thinks driver is absent! "
8466                                     "(bc_state = 0x%08X)\n",
8467                                     __FUNCTION__, sc->bc_state);
8468                         }
8469                 } else {
8470                         /*
8471                          * Not supported by all bootcode versions.
8472                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8473                          * will require the driver to reset the
8474                          * controller to clear this condition.
8475                          */
8476                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8477                                 sc->bce_drv_cardiac_arrest = FALSE;
8478                                 BCE_PRINTF("%s(): Bootcode found the "
8479                                     "driver pulse! (bc_state = 0x%08X)\n",
8480                                     __FUNCTION__, sc->bc_state);
8481                         }
8482                 }
8483         }
8484
8485
8486         /* Schedule the next pulse. */
8487         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8488
8489         DBEXIT(BCE_EXTREME_MISC);
8490 }
8491
8492
8493 /****************************************************************************/
8494 /* Periodic function to perform maintenance tasks.                          */
8495 /*                                                                          */
8496 /* Returns:                                                                 */
8497 /*   Nothing.                                                               */
8498 /****************************************************************************/
8499 static void
8500 bce_tick(void *xsc)
8501 {
8502         struct bce_softc *sc = xsc;
8503         struct mii_data *mii;
8504         struct ifnet *ifp;
8505         struct ifmediareq ifmr;
8506
8507         ifp = sc->bce_ifp;
8508
8509         DBENTER(BCE_EXTREME_MISC);
8510
8511         BCE_LOCK_ASSERT(sc);
8512
8513         /* Schedule the next tick. */
8514         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8515
8516         /* Update the statistics from the hardware statistics block. */
8517         bce_stats_update(sc);
8518
8519         /*
8520          * ToDo: This is a safety measure.  Need to re-evaluate
8521          * high level processing logic and eliminate this code.
8522          */
8523         /* Top off the receive and page chains. */
8524         if (bce_hdr_split == TRUE)
8525                 bce_fill_pg_chain(sc);
8526         bce_fill_rx_chain(sc);
8527
8528         /* Check that chip hasn't hung. */
8529         bce_watchdog(sc);
8530
8531         /* If link is up already up then we're done. */
8532         if (sc->bce_link_up == TRUE)
8533                 goto bce_tick_exit;
8534
8535         /* Link is down.  Check what the PHY's doing. */
8536         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8537                 bzero(&ifmr, sizeof(ifmr));
8538                 bce_ifmedia_sts_rphy(sc, &ifmr);
8539                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8540                     (IFM_ACTIVE | IFM_AVALID)) {
8541                         sc->bce_link_up = TRUE;
8542                         bce_miibus_statchg(sc->bce_dev);
8543                 }
8544         } else {
8545                 mii = device_get_softc(sc->bce_miibus);
8546                 mii_tick(mii);
8547                 /* Check if the link has come up. */
8548                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8549                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8550                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8551                             __FUNCTION__);
8552                         sc->bce_link_up = TRUE;
8553                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8554                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8555                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8556                             (bce_verbose || bootverbose))
8557                                 BCE_PRINTF("Gigabit link up!\n");
8558                 }
8559
8560         }
8561         if (sc->bce_link_up == TRUE) {
8562                 /* Now that link is up, handle any outstanding TX traffic. */
8563                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8564                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8565                             "pending TX traffic.\n", __FUNCTION__);
8566                         bce_start_locked(ifp);
8567                 }
8568         }
8569
8570 bce_tick_exit:
8571         DBEXIT(BCE_EXTREME_MISC);
8572         return;
8573 }
8574
8575 static void
8576 bce_fw_cap_init(struct bce_softc *sc)
8577 {
8578         u32 ack, cap, link;
8579
8580         ack = 0;
8581         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8582         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8583             BCE_FW_CAP_SIGNATURE_MAGIC)
8584                 return;
8585         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8586             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8587                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8588                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8589         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8590             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8591                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8592                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8593                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8594                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8595                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8596                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8597                     BCE_FW_CAP_REMOTE_PHY_CAP;
8598         }
8599
8600         if (ack != 0)
8601                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8602 }
8603
8604
8605 #ifdef BCE_DEBUG
8606 /****************************************************************************/
8607 /* Allows the driver state to be dumped through the sysctl interface.       */
8608 /*                                                                          */
8609 /* Returns:                                                                 */
8610 /*   0 for success, positive value for failure.                             */
8611 /****************************************************************************/
8612 static int
8613 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8614 {
8615         int error;
8616         int result;
8617         struct bce_softc *sc;
8618
8619         result = -1;
8620         error = sysctl_handle_int(oidp, &result, 0, req);
8621
8622         if (error || !req->newptr)
8623                 return (error);
8624
8625         if (result == 1) {
8626                 sc = (struct bce_softc *)arg1;
8627                 bce_dump_driver_state(sc);
8628         }
8629
8630         return error;
8631 }
8632
8633
8634 /****************************************************************************/
8635 /* Allows the hardware state to be dumped through the sysctl interface.     */
8636 /*                                                                          */
8637 /* Returns:                                                                 */
8638 /*   0 for success, positive value for failure.                             */
8639 /****************************************************************************/
8640 static int
8641 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8642 {
8643         int error;
8644         int result;
8645         struct bce_softc *sc;
8646
8647         result = -1;
8648         error = sysctl_handle_int(oidp, &result, 0, req);
8649
8650         if (error || !req->newptr)
8651                 return (error);
8652
8653         if (result == 1) {
8654                 sc = (struct bce_softc *)arg1;
8655                 bce_dump_hw_state(sc);
8656         }
8657
8658         return error;
8659 }
8660
8661
8662 /****************************************************************************/
8663 /* Allows the status block to be dumped through the sysctl interface.       */
8664 /*                                                                          */
8665 /* Returns:                                                                 */
8666 /*   0 for success, positive value for failure.                             */
8667 /****************************************************************************/
8668 static int
8669 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8670 {
8671         int error;
8672         int result;
8673         struct bce_softc *sc;
8674
8675         result = -1;
8676         error = sysctl_handle_int(oidp, &result, 0, req);
8677
8678         if (error || !req->newptr)
8679                 return (error);
8680
8681         if (result == 1) {
8682                 sc = (struct bce_softc *)arg1;
8683                 bce_dump_status_block(sc);
8684         }
8685
8686         return error;
8687 }
8688
8689
8690 /****************************************************************************/
8691 /* Allows the stats block to be dumped through the sysctl interface.        */
8692 /*                                                                          */
8693 /* Returns:                                                                 */
8694 /*   0 for success, positive value for failure.                             */
8695 /****************************************************************************/
8696 static int
8697 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8698 {
8699         int error;
8700         int result;
8701         struct bce_softc *sc;
8702
8703         result = -1;
8704         error = sysctl_handle_int(oidp, &result, 0, req);
8705
8706         if (error || !req->newptr)
8707                 return (error);
8708
8709         if (result == 1) {
8710                 sc = (struct bce_softc *)arg1;
8711                 bce_dump_stats_block(sc);
8712         }
8713
8714         return error;
8715 }
8716
8717
8718 /****************************************************************************/
8719 /* Allows the stat counters to be cleared without unloading/reloading the   */
8720 /* driver.                                                                  */
8721 /*                                                                          */
8722 /* Returns:                                                                 */
8723 /*   0 for success, positive value for failure.                             */
8724 /****************************************************************************/
8725 static int
8726 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8727 {
8728         int error;
8729         int result;
8730         struct bce_softc *sc;
8731
8732         result = -1;
8733         error = sysctl_handle_int(oidp, &result, 0, req);
8734
8735         if (error || !req->newptr)
8736                 return (error);
8737
8738         if (result == 1) {
8739                 sc = (struct bce_softc *)arg1;
8740                 struct statistics_block *stats;
8741
8742                 stats = (struct statistics_block *) sc->stats_block;
8743                 bzero(stats, sizeof(struct statistics_block));
8744
8745                 /* Clear the internal H/W statistics counters. */
8746                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8747
8748                 /* Reset the driver maintained statistics. */
8749                 sc->interrupts_rx =
8750                     sc->interrupts_tx = 0;
8751                 sc->tso_frames_requested =
8752                     sc->tso_frames_completed =
8753                     sc->tso_frames_failed = 0;
8754                 sc->rx_empty_count =
8755                     sc->tx_full_count = 0;
8756                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8757                 sc->tx_hi_watermark = 0;
8758                 sc->l2fhdr_error_count =
8759                     sc->l2fhdr_error_sim_count = 0;
8760                 sc->mbuf_alloc_failed_count =
8761                     sc->mbuf_alloc_failed_sim_count = 0;
8762                 sc->dma_map_addr_rx_failed_count =
8763                     sc->dma_map_addr_tx_failed_count = 0;
8764                 sc->mbuf_frag_count = 0;
8765                 sc->csum_offload_tcp_udp =
8766                     sc->csum_offload_ip = 0;
8767                 sc->vlan_tagged_frames_rcvd =
8768                     sc->vlan_tagged_frames_stripped = 0;
8769                 sc->split_header_frames_rcvd =
8770                     sc->split_header_tcp_frames_rcvd = 0;
8771
8772                 /* Clear firmware maintained statistics. */
8773                 REG_WR_IND(sc, 0x120084, 0);
8774         }
8775
8776         return error;
8777 }
8778
8779
8780 /****************************************************************************/
8781 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8782 /* interface.                                                               */
8783 /*                                                                          */
8784 /* Returns:                                                                 */
8785 /*   0 for success, positive value for failure.                             */
8786 /****************************************************************************/
8787 static int
8788 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8789 {
8790         int error;
8791         int result;
8792         struct bce_softc *sc;
8793
8794         result = -1;
8795         error = sysctl_handle_int(oidp, &result, 0, req);
8796
8797         if (error || !req->newptr)
8798                 return (error);
8799
8800         if (result == 1) {
8801                 sc = (struct bce_softc *)arg1;
8802                 bce_dump_shmem_state(sc);
8803         }
8804
8805         return error;
8806 }
8807
8808
8809 /****************************************************************************/
8810 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8811 /*                                                                          */
8812 /* Returns:                                                                 */
8813 /*   0 for success, positive value for failure.                             */
8814 /****************************************************************************/
8815 static int
8816 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8817 {
8818         int error;
8819         int result;
8820         struct bce_softc *sc;
8821
8822         result = -1;
8823         error = sysctl_handle_int(oidp, &result, 0, req);
8824
8825         if (error || !req->newptr)
8826                 return (error);
8827
8828         if (result == 1) {
8829                 sc = (struct bce_softc *)arg1;
8830                 bce_dump_bc_state(sc);
8831         }
8832
8833         return error;
8834 }
8835
8836
8837 /****************************************************************************/
8838 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8839 /*                                                                          */
8840 /* Returns:                                                                 */
8841 /*   0 for success, positive value for failure.                             */
8842 /****************************************************************************/
8843 static int
8844 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8845 {
8846         int error;
8847         int result;
8848         struct bce_softc *sc;
8849
8850         result = -1;
8851         error = sysctl_handle_int(oidp, &result, 0, req);
8852
8853         if (error || !req->newptr)
8854                 return (error);
8855
8856         if (result == 1) {
8857                 sc = (struct bce_softc *)arg1;
8858                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8859         }
8860
8861         return error;
8862 }
8863
8864
8865 /****************************************************************************/
8866 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8867 /*                                                                          */
8868 /* Returns:                                                                 */
8869 /*   0 for success, positive value for failure.                             */
8870 /****************************************************************************/
8871 static int
8872 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8873 {
8874         int error;
8875         int result;
8876         struct bce_softc *sc;
8877
8878         result = -1;
8879         error = sysctl_handle_int(oidp, &result, 0, req);
8880
8881         if (error || !req->newptr)
8882                 return (error);
8883
8884         if (result == 1) {
8885                 sc = (struct bce_softc *)arg1;
8886                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8887         }
8888
8889         return error;
8890 }
8891
8892
8893 /****************************************************************************/
8894 /* Provides a sysctl interface to allow dumping the TX chain.               */
8895 /*                                                                          */
8896 /* Returns:                                                                 */
8897 /*   0 for success, positive value for failure.                             */
8898 /****************************************************************************/
8899 static int
8900 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8901 {
8902         int error;
8903         int result;
8904         struct bce_softc *sc;
8905
8906         result = -1;
8907         error = sysctl_handle_int(oidp, &result, 0, req);
8908
8909         if (error || !req->newptr)
8910                 return (error);
8911
8912         if (result == 1) {
8913                 sc = (struct bce_softc *)arg1;
8914                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8915         }
8916
8917         return error;
8918 }
8919
8920
8921 /****************************************************************************/
8922 /* Provides a sysctl interface to allow dumping the page chain.             */
8923 /*                                                                          */
8924 /* Returns:                                                                 */
8925 /*   0 for success, positive value for failure.                             */
8926 /****************************************************************************/
8927 static int
8928 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8929 {
8930         int error;
8931         int result;
8932         struct bce_softc *sc;
8933
8934         result = -1;
8935         error = sysctl_handle_int(oidp, &result, 0, req);
8936
8937         if (error || !req->newptr)
8938                 return (error);
8939
8940         if (result == 1) {
8941                 sc = (struct bce_softc *)arg1;
8942                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8943         }
8944
8945         return error;
8946 }
8947
8948 /****************************************************************************/
8949 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8950 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8951 /*                                                                          */
8952 /* Returns:                                                                 */
8953 /*   0 for success, positive value for failure.                             */
8954 /****************************************************************************/
8955 static int
8956 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8957 {
8958         struct bce_softc *sc = (struct bce_softc *)arg1;
8959         int error;
8960         u32 result;
8961         u32 val[1];
8962         u8 *data = (u8 *) val;
8963
8964         result = -1;
8965         error = sysctl_handle_int(oidp, &result, 0, req);
8966         if (error || (req->newptr == NULL))
8967                 return (error);
8968
8969         error = bce_nvram_read(sc, result, data, 4);
8970
8971         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8972
8973         return (error);
8974 }
8975
8976
8977 /****************************************************************************/
8978 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8979 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8980 /*                                                                          */
8981 /* Returns:                                                                 */
8982 /*   0 for success, positive value for failure.                             */
8983 /****************************************************************************/
8984 static int
8985 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8986 {
8987         struct bce_softc *sc = (struct bce_softc *)arg1;
8988         int error;
8989         u32 val, result;
8990
8991         result = -1;
8992         error = sysctl_handle_int(oidp, &result, 0, req);
8993         if (error || (req->newptr == NULL))
8994                 return (error);
8995
8996         /* Make sure the register is accessible. */
8997         if (result < 0x8000) {
8998                 val = REG_RD(sc, result);
8999                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
9000         } else if (result < 0x0280000) {
9001                 val = REG_RD_IND(sc, result);
9002                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
9003         }
9004
9005         return (error);
9006 }
9007
9008
9009 /****************************************************************************/
9010 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
9011 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
9012 /*                                                                          */
9013 /* Returns:                                                                 */
9014 /*   0 for success, positive value for failure.                             */
9015 /****************************************************************************/
9016 static int
9017 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
9018 {
9019         struct bce_softc *sc;
9020         device_t dev;
9021         int error, result;
9022         u16 val;
9023
9024         result = -1;
9025         error = sysctl_handle_int(oidp, &result, 0, req);
9026         if (error || (req->newptr == NULL))
9027                 return (error);
9028
9029         /* Make sure the register is accessible. */
9030         if (result < 0x20) {
9031                 sc = (struct bce_softc *)arg1;
9032                 dev = sc->bce_dev;
9033                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
9034                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9035         }
9036         return (error);
9037 }
9038
9039
9040 /****************************************************************************/
9041 /* Provides a sysctl interface for dumping the nvram contents.              */
9042 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9043 /*                                                                          */
9044 /* Returns:                                                                 */
9045 /*   0 for success, positive errno for failure.                             */
9046 /****************************************************************************/
9047 static int
9048 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9049 {
9050         struct bce_softc *sc = (struct bce_softc *)arg1;
9051         int error, i;
9052
9053         if (sc->nvram_buf == NULL)
9054                 sc->nvram_buf = malloc(sc->bce_flash_size,
9055                                     M_TEMP, M_ZERO | M_WAITOK);
9056
9057         error = 0;
9058         if (req->oldlen == sc->bce_flash_size) {
9059                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9060                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9061         }
9062
9063         if (error == 0)
9064                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9065
9066         return error;
9067 }
9068
9069 #ifdef BCE_NVRAM_WRITE_SUPPORT
9070 /****************************************************************************/
9071 /* Provides a sysctl interface for writing to nvram.                        */
9072 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9073 /*                                                                          */
9074 /* Returns:                                                                 */
9075 /*   0 for success, positive errno for failure.                             */
9076 /****************************************************************************/
9077 static int
9078 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9079 {
9080         struct bce_softc *sc = (struct bce_softc *)arg1;
9081         int error;
9082
9083         if (sc->nvram_buf == NULL)
9084                 sc->nvram_buf = malloc(sc->bce_flash_size,
9085                                     M_TEMP, M_ZERO | M_WAITOK);
9086         else
9087                 bzero(sc->nvram_buf, sc->bce_flash_size);
9088
9089         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9090         if (error == 0)
9091                 return (error);
9092
9093         if (req->newlen == sc->bce_flash_size)
9094                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9095                             sc->bce_flash_size);
9096
9097
9098         return error;
9099 }
9100 #endif
9101
9102
9103 /****************************************************************************/
9104 /* Provides a sysctl interface to allow reading a CID.                      */
9105 /*                                                                          */
9106 /* Returns:                                                                 */
9107 /*   0 for success, positive value for failure.                             */
9108 /****************************************************************************/
9109 static int
9110 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9111 {
9112         struct bce_softc *sc;
9113         int error, result;
9114
9115         result = -1;
9116         error = sysctl_handle_int(oidp, &result, 0, req);
9117         if (error || (req->newptr == NULL))
9118                 return (error);
9119
9120         /* Make sure the register is accessible. */
9121         if (result <= TX_CID) {
9122                 sc = (struct bce_softc *)arg1;
9123                 bce_dump_ctx(sc, result);
9124         }
9125
9126         return (error);
9127 }
9128
9129
9130 /****************************************************************************/
9131 /* Provides a sysctl interface to forcing the driver to dump state and      */
9132 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9133 /*                                                                          */
9134 /* Returns:                                                                 */
9135 /*   0 for success, positive value for failure.                             */
9136 /****************************************************************************/
9137 static int
9138 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9139 {
9140         int error;
9141         int result;
9142         struct bce_softc *sc;
9143
9144         result = -1;
9145         error = sysctl_handle_int(oidp, &result, 0, req);
9146
9147         if (error || !req->newptr)
9148                 return (error);
9149
9150         if (result == 1) {
9151                 sc = (struct bce_softc *)arg1;
9152                 bce_breakpoint(sc);
9153         }
9154
9155         return error;
9156 }
9157 #endif
9158
9159 /****************************************************************************/
9160 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9161 /*                                                                          */
9162 /* Returns:                                                                 */
9163 /*   0 for success, positive value for failure.                             */
9164 /****************************************************************************/
9165 static void
9166 bce_add_sysctls(struct bce_softc *sc)
9167 {
9168         struct sysctl_ctx_list *ctx;
9169         struct sysctl_oid_list *children;
9170
9171         DBENTER(BCE_VERBOSE_MISC);
9172
9173         ctx = device_get_sysctl_ctx(sc->bce_dev);
9174         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9175
9176 #ifdef BCE_DEBUG
9177         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9178             "l2fhdr_error_sim_control",
9179             CTLFLAG_RW, &l2fhdr_error_sim_control,
9180             0, "Debug control to force l2fhdr errors");
9181
9182         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9183             "l2fhdr_error_sim_count",
9184             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9185             0, "Number of simulated l2_fhdr errors");
9186 #endif
9187
9188         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9189             "l2fhdr_error_count",
9190             CTLFLAG_RD, &sc->l2fhdr_error_count,
9191             0, "Number of l2_fhdr errors");
9192
9193 #ifdef BCE_DEBUG
9194         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9195             "mbuf_alloc_failed_sim_control",
9196             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9197             0, "Debug control to force mbuf allocation failures");
9198
9199         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9200             "mbuf_alloc_failed_sim_count",
9201             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9202             0, "Number of simulated mbuf cluster allocation failures");
9203 #endif
9204
9205         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9206             "mbuf_alloc_failed_count",
9207             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9208             0, "Number of mbuf allocation failures");
9209
9210         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9211             "mbuf_frag_count",
9212             CTLFLAG_RD, &sc->mbuf_frag_count,
9213             0, "Number of fragmented mbufs");
9214
9215 #ifdef BCE_DEBUG
9216         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9217             "dma_map_addr_failed_sim_control",
9218             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9219             0, "Debug control to force DMA mapping failures");
9220
9221         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9222         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9223             "dma_map_addr_failed_sim_count",
9224             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9225             0, "Number of simulated DMA mapping failures");
9226
9227 #endif
9228
9229         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9230             "dma_map_addr_rx_failed_count",
9231             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9232             0, "Number of RX DMA mapping failures");
9233
9234         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9235             "dma_map_addr_tx_failed_count",
9236             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9237             0, "Number of TX DMA mapping failures");
9238
9239 #ifdef BCE_DEBUG
9240         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9241             "unexpected_attention_sim_control",
9242             CTLFLAG_RW, &unexpected_attention_sim_control,
9243             0, "Debug control to simulate unexpected attentions");
9244
9245         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9246             "unexpected_attention_sim_count",
9247             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9248             0, "Number of simulated unexpected attentions");
9249 #endif
9250
9251         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9252             "unexpected_attention_count",
9253             CTLFLAG_RW, &sc->unexpected_attention_count,
9254             0, "Number of unexpected attentions");
9255
9256 #ifdef BCE_DEBUG
9257         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9258             "debug_bootcode_running_failure",
9259             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9260             0, "Debug control to force bootcode running failures");
9261
9262         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9263             "rx_low_watermark",
9264             CTLFLAG_RD, &sc->rx_low_watermark,
9265             0, "Lowest level of free rx_bd's");
9266
9267         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9268             "rx_empty_count",
9269             CTLFLAG_RD, &sc->rx_empty_count,
9270             "Number of times the RX chain was empty");
9271
9272         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9273             "tx_hi_watermark",
9274             CTLFLAG_RD, &sc->tx_hi_watermark,
9275             0, "Highest level of used tx_bd's");
9276
9277         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9278             "tx_full_count",
9279             CTLFLAG_RD, &sc->tx_full_count,
9280             "Number of times the TX chain was full");
9281
9282         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9283             "tso_frames_requested",
9284             CTLFLAG_RD, &sc->tso_frames_requested,
9285             "Number of TSO frames requested");
9286
9287         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9288             "tso_frames_completed",
9289             CTLFLAG_RD, &sc->tso_frames_completed,
9290             "Number of TSO frames completed");
9291
9292         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9293             "tso_frames_failed",
9294             CTLFLAG_RD, &sc->tso_frames_failed,
9295             "Number of TSO frames failed");
9296
9297         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9298             "csum_offload_ip",
9299             CTLFLAG_RD, &sc->csum_offload_ip,
9300             "Number of IP checksum offload frames");
9301
9302         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9303             "csum_offload_tcp_udp",
9304             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9305             "Number of TCP/UDP checksum offload frames");
9306
9307         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9308             "vlan_tagged_frames_rcvd",
9309             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9310             "Number of VLAN tagged frames received");
9311
9312         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9313             "vlan_tagged_frames_stripped",
9314             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9315             "Number of VLAN tagged frames stripped");
9316
9317         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9318             "interrupts_rx",
9319             CTLFLAG_RD, &sc->interrupts_rx,
9320             "Number of RX interrupts");
9321
9322         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9323             "interrupts_tx",
9324             CTLFLAG_RD, &sc->interrupts_tx,
9325             "Number of TX interrupts");
9326
9327         if (bce_hdr_split == TRUE) {
9328                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9329                     "split_header_frames_rcvd",
9330                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9331                     "Number of split header frames received");
9332
9333                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9334                     "split_header_tcp_frames_rcvd",
9335                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9336                     "Number of split header TCP frames received");
9337         }
9338
9339         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9340             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9341             (void *)sc, 0,
9342             bce_sysctl_nvram_dump, "S", "");
9343
9344 #ifdef BCE_NVRAM_WRITE_SUPPORT
9345         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9346             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9347             (void *)sc, 0,
9348             bce_sysctl_nvram_write, "S", "");
9349 #endif
9350 #endif /* BCE_DEBUG */
9351
9352         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9353             "stat_IfHcInOctets",
9354             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9355             "Bytes received");
9356
9357         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9358             "stat_IfHCInBadOctets",
9359             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9360             "Bad bytes received");
9361
9362         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9363             "stat_IfHCOutOctets",
9364             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9365             "Bytes sent");
9366
9367         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9368             "stat_IfHCOutBadOctets",
9369             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9370             "Bad bytes sent");
9371
9372         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9373             "stat_IfHCInUcastPkts",
9374             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9375             "Unicast packets received");
9376
9377         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9378             "stat_IfHCInMulticastPkts",
9379             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9380             "Multicast packets received");
9381
9382         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9383             "stat_IfHCInBroadcastPkts",
9384             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9385             "Broadcast packets received");
9386
9387         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9388             "stat_IfHCOutUcastPkts",
9389             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9390             "Unicast packets sent");
9391
9392         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9393             "stat_IfHCOutMulticastPkts",
9394             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9395             "Multicast packets sent");
9396
9397         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9398             "stat_IfHCOutBroadcastPkts",
9399             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9400             "Broadcast packets sent");
9401
9402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9403             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9404             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9405             0, "Internal MAC transmit errors");
9406
9407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9408             "stat_Dot3StatsCarrierSenseErrors",
9409             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9410             0, "Carrier sense errors");
9411
9412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9413             "stat_Dot3StatsFCSErrors",
9414             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9415             0, "Frame check sequence errors");
9416
9417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9418             "stat_Dot3StatsAlignmentErrors",
9419             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9420             0, "Alignment errors");
9421
9422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9423             "stat_Dot3StatsSingleCollisionFrames",
9424             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9425             0, "Single Collision Frames");
9426
9427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9428             "stat_Dot3StatsMultipleCollisionFrames",
9429             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9430             0, "Multiple Collision Frames");
9431
9432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9433             "stat_Dot3StatsDeferredTransmissions",
9434             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9435             0, "Deferred Transmissions");
9436
9437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9438             "stat_Dot3StatsExcessiveCollisions",
9439             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9440             0, "Excessive Collisions");
9441
9442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9443             "stat_Dot3StatsLateCollisions",
9444             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9445             0, "Late Collisions");
9446
9447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9448             "stat_EtherStatsCollisions",
9449             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9450             0, "Collisions");
9451
9452         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9453             "stat_EtherStatsFragments",
9454             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9455             0, "Fragments");
9456
9457         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9458             "stat_EtherStatsJabbers",
9459             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9460             0, "Jabbers");
9461
9462         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9463             "stat_EtherStatsUndersizePkts",
9464             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9465             0, "Undersize packets");
9466
9467         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9468             "stat_EtherStatsOversizePkts",
9469             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9470             0, "stat_EtherStatsOversizePkts");
9471
9472         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9473             "stat_EtherStatsPktsRx64Octets",
9474             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9475             0, "Bytes received in 64 byte packets");
9476
9477         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9478             "stat_EtherStatsPktsRx65Octetsto127Octets",
9479             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9480             0, "Bytes received in 65 to 127 byte packets");
9481
9482         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9483             "stat_EtherStatsPktsRx128Octetsto255Octets",
9484             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9485             0, "Bytes received in 128 to 255 byte packets");
9486
9487         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9488             "stat_EtherStatsPktsRx256Octetsto511Octets",
9489             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9490             0, "Bytes received in 256 to 511 byte packets");
9491
9492         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9493             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9494             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9495             0, "Bytes received in 512 to 1023 byte packets");
9496
9497         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9498             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9499             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9500             0, "Bytes received in 1024 t0 1522 byte packets");
9501
9502         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9503             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9504             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9505             0, "Bytes received in 1523 to 9022 byte packets");
9506
9507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9508             "stat_EtherStatsPktsTx64Octets",
9509             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9510             0, "Bytes sent in 64 byte packets");
9511
9512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9513             "stat_EtherStatsPktsTx65Octetsto127Octets",
9514             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9515             0, "Bytes sent in 65 to 127 byte packets");
9516
9517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9518             "stat_EtherStatsPktsTx128Octetsto255Octets",
9519             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9520             0, "Bytes sent in 128 to 255 byte packets");
9521
9522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9523             "stat_EtherStatsPktsTx256Octetsto511Octets",
9524             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9525             0, "Bytes sent in 256 to 511 byte packets");
9526
9527         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9528             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9529             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9530             0, "Bytes sent in 512 to 1023 byte packets");
9531
9532         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9533             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9534             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9535             0, "Bytes sent in 1024 to 1522 byte packets");
9536
9537         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9538             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9539             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9540             0, "Bytes sent in 1523 to 9022 byte packets");
9541
9542         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9543             "stat_XonPauseFramesReceived",
9544             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9545             0, "XON pause frames receved");
9546
9547         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9548             "stat_XoffPauseFramesReceived",
9549             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9550             0, "XOFF pause frames received");
9551
9552         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9553             "stat_OutXonSent",
9554             CTLFLAG_RD, &sc->stat_OutXonSent,
9555             0, "XON pause frames sent");
9556
9557         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9558             "stat_OutXoffSent",
9559             CTLFLAG_RD, &sc->stat_OutXoffSent,
9560             0, "XOFF pause frames sent");
9561
9562         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9563             "stat_FlowControlDone",
9564             CTLFLAG_RD, &sc->stat_FlowControlDone,
9565             0, "Flow control done");
9566
9567         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9568             "stat_MacControlFramesReceived",
9569             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9570             0, "MAC control frames received");
9571
9572         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9573             "stat_XoffStateEntered",
9574             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9575             0, "XOFF state entered");
9576
9577         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9578             "stat_IfInFramesL2FilterDiscards",
9579             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9580             0, "Received L2 packets discarded");
9581
9582         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9583             "stat_IfInRuleCheckerDiscards",
9584             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9585             0, "Received packets discarded by rule");
9586
9587         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9588             "stat_IfInFTQDiscards",
9589             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9590             0, "Received packet FTQ discards");
9591
9592         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9593             "stat_IfInMBUFDiscards",
9594             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9595             0, "Received packets discarded due to lack "
9596             "of controller buffer memory");
9597
9598         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9599             "stat_IfInRuleCheckerP4Hit",
9600             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9601             0, "Received packets rule checker hits");
9602
9603         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9604             "stat_CatchupInRuleCheckerDiscards",
9605             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9606             0, "Received packets discarded in Catchup path");
9607
9608         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9609             "stat_CatchupInFTQDiscards",
9610             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9611             0, "Received packets discarded in FTQ in Catchup path");
9612
9613         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9614             "stat_CatchupInMBUFDiscards",
9615             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9616             0, "Received packets discarded in controller "
9617             "buffer memory in Catchup path");
9618
9619         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9620             "stat_CatchupInRuleCheckerP4Hit",
9621             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9622             0, "Received packets rule checker hits in Catchup path");
9623
9624         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9625             "com_no_buffers",
9626             CTLFLAG_RD, &sc->com_no_buffers,
9627             0, "Valid packets received but no RX buffers available");
9628
9629 #ifdef BCE_DEBUG
9630         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9631             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9632             (void *)sc, 0,
9633             bce_sysctl_driver_state, "I", "Drive state information");
9634
9635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9636             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9637             (void *)sc, 0,
9638             bce_sysctl_hw_state, "I", "Hardware state information");
9639
9640         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9641             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9642             (void *)sc, 0,
9643             bce_sysctl_status_block, "I", "Dump status block");
9644
9645         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9646             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9647             (void *)sc, 0,
9648             bce_sysctl_stats_block, "I", "Dump statistics block");
9649
9650         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9651             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9652             (void *)sc, 0,
9653             bce_sysctl_stats_clear, "I", "Clear statistics block");
9654
9655         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9656             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9657             (void *)sc, 0,
9658             bce_sysctl_shmem_state, "I", "Shared memory state information");
9659
9660         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9661             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9662             (void *)sc, 0,
9663             bce_sysctl_bc_state, "I", "Bootcode state information");
9664
9665         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9666             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9667             (void *)sc, 0,
9668             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9669
9670         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9671             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9672             (void *)sc, 0,
9673             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9674
9675         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9676             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9677             (void *)sc, 0,
9678             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9679
9680         if (bce_hdr_split == TRUE) {
9681                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9682                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9683                     (void *)sc, 0,
9684                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9685         }
9686
9687         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9688             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9689             (void *)sc, 0,
9690             bce_sysctl_dump_ctx, "I", "Dump context memory");
9691
9692         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9693             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9694             (void *)sc, 0,
9695             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9696
9697         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9698             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9699             (void *)sc, 0,
9700             bce_sysctl_reg_read, "I", "Register read");
9701
9702         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9703             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9704             (void *)sc, 0,
9705             bce_sysctl_nvram_read, "I", "NVRAM read");
9706
9707         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9708             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9709             (void *)sc, 0,
9710             bce_sysctl_phy_read, "I", "PHY register read");
9711
9712 #endif
9713
9714         DBEXIT(BCE_VERBOSE_MISC);
9715 }
9716
9717
9718 /****************************************************************************/
9719 /* BCE Debug Routines                                                       */
9720 /****************************************************************************/
9721 #ifdef BCE_DEBUG
9722
9723 /****************************************************************************/
9724 /* Freezes the controller to allow for a cohesive state dump.               */
9725 /*                                                                          */
9726 /* Returns:                                                                 */
9727 /*   Nothing.                                                               */
9728 /****************************************************************************/
9729 static __attribute__ ((noinline)) void
9730 bce_freeze_controller(struct bce_softc *sc)
9731 {
9732         u32 val;
9733         val = REG_RD(sc, BCE_MISC_COMMAND);
9734         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9735         REG_WR(sc, BCE_MISC_COMMAND, val);
9736 }
9737
9738
9739 /****************************************************************************/
9740 /* Unfreezes the controller after a freeze operation.  This may not always  */
9741 /* work and the controller will require a reset!                            */
9742 /*                                                                          */
9743 /* Returns:                                                                 */
9744 /*   Nothing.                                                               */
9745 /****************************************************************************/
9746 static __attribute__ ((noinline)) void
9747 bce_unfreeze_controller(struct bce_softc *sc)
9748 {
9749         u32 val;
9750         val = REG_RD(sc, BCE_MISC_COMMAND);
9751         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9752         REG_WR(sc, BCE_MISC_COMMAND, val);
9753 }
9754
9755
9756 /****************************************************************************/
9757 /* Prints out Ethernet frame information from an mbuf.                      */
9758 /*                                                                          */
9759 /* Partially decode an Ethernet frame to look at some important headers.    */
9760 /*                                                                          */
9761 /* Returns:                                                                 */
9762 /*   Nothing.                                                               */
9763 /****************************************************************************/
9764 static __attribute__ ((noinline)) void
9765 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9766 {
9767         struct ether_vlan_header *eh;
9768         u16 etype;
9769         int ehlen;
9770         struct ip *ip;
9771         struct tcphdr *th;
9772         struct udphdr *uh;
9773         struct arphdr *ah;
9774
9775         BCE_PRINTF(
9776             "-----------------------------"
9777             " Frame Decode "
9778             "-----------------------------\n");
9779
9780         eh = mtod(m, struct ether_vlan_header *);
9781
9782         /* Handle VLAN encapsulation if present. */
9783         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9784                 etype = ntohs(eh->evl_proto);
9785                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9786         } else {
9787                 etype = ntohs(eh->evl_encap_proto);
9788                 ehlen = ETHER_HDR_LEN;
9789         }
9790
9791         /* ToDo: Add VLAN output. */
9792         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9793             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9794
9795         switch (etype) {
9796         case ETHERTYPE_IP:
9797                 ip = (struct ip *)(m->m_data + ehlen);
9798                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9799                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9800                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9801                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9802
9803                 switch (ip->ip_p) {
9804                 case IPPROTO_TCP:
9805                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9806                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9807                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9808                             ntohs(th->th_dport), ntohs(th->th_sport),
9809                             (th->th_off << 2), th->th_flags,
9810                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9811                             "\02SYN\01FIN", ntohs(th->th_sum));
9812                         break;
9813                 case IPPROTO_UDP:
9814                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9815                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9816                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9817                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9818                             ntohs(uh->uh_sum));
9819                         break;
9820                 case IPPROTO_ICMP:
9821                         BCE_PRINTF("icmp:\n");
9822                         break;
9823                 default:
9824                         BCE_PRINTF("----: Other IP protocol.\n");
9825                         }
9826                 break;
9827         case ETHERTYPE_IPV6:
9828                 BCE_PRINTF("ipv6: No decode supported.\n");
9829                 break;
9830         case ETHERTYPE_ARP:
9831                 BCE_PRINTF("-arp: ");
9832                 ah = (struct arphdr *) (m->m_data + ehlen);
9833                 switch (ntohs(ah->ar_op)) {
9834                 case ARPOP_REVREQUEST:
9835                         printf("reverse ARP request\n");
9836                         break;
9837                 case ARPOP_REVREPLY:
9838                         printf("reverse ARP reply\n");
9839                         break;
9840                 case ARPOP_REQUEST:
9841                         printf("ARP request\n");
9842                         break;
9843                 case ARPOP_REPLY:
9844                         printf("ARP reply\n");
9845                         break;
9846                 default:
9847                         printf("other ARP operation\n");
9848                 }
9849                 break;
9850         default:
9851                 BCE_PRINTF("----: Other protocol.\n");
9852         }
9853
9854         BCE_PRINTF(
9855                 "-----------------------------"
9856                 "--------------"
9857                 "-----------------------------\n");
9858 }
9859
9860
9861 /****************************************************************************/
9862 /* Prints out information about an mbuf.                                    */
9863 /*                                                                          */
9864 /* Returns:                                                                 */
9865 /*   Nothing.                                                               */
9866 /****************************************************************************/
9867 static __attribute__ ((noinline)) void
9868 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9869 {
9870         struct mbuf *mp = m;
9871
9872         if (m == NULL) {
9873                 BCE_PRINTF("mbuf: null pointer\n");
9874                 return;
9875         }
9876
9877         while (mp) {
9878                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9879                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9880                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9881
9882                 if (mp->m_flags & M_PKTHDR) {
9883                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9884                             "csum_flags = %b\n", mp->m_pkthdr.len,
9885                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9886                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9887                             "\22M_PROMISC\23M_NOFREE",
9888                             mp->m_pkthdr.csum_flags,
9889                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9890                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9891                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9892                             "\14CSUM_PSEUDO_HDR");
9893                 }
9894
9895                 if (mp->m_flags & M_EXT) {
9896                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9897                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9898                         switch (mp->m_ext.ext_type) {
9899                         case EXT_CLUSTER:
9900                                 printf("EXT_CLUSTER\n"); break;
9901                         case EXT_SFBUF:
9902                                 printf("EXT_SFBUF\n"); break;
9903                         case EXT_JUMBO9:
9904                                 printf("EXT_JUMBO9\n"); break;
9905                         case EXT_JUMBO16:
9906                                 printf("EXT_JUMBO16\n"); break;
9907                         case EXT_PACKET:
9908                                 printf("EXT_PACKET\n"); break;
9909                         case EXT_MBUF:
9910                                 printf("EXT_MBUF\n"); break;
9911                         case EXT_NET_DRV:
9912                                 printf("EXT_NET_DRV\n"); break;
9913                         case EXT_MOD_TYPE:
9914                                 printf("EXT_MDD_TYPE\n"); break;
9915                         case EXT_DISPOSABLE:
9916                                 printf("EXT_DISPOSABLE\n"); break;
9917                         case EXT_EXTREF:
9918                                 printf("EXT_EXTREF\n"); break;
9919                         default:
9920                                 printf("UNKNOWN\n");
9921                         }
9922                 }
9923
9924                 mp = mp->m_next;
9925         }
9926 }
9927
9928
9929 /****************************************************************************/
9930 /* Prints out the mbufs in the TX mbuf chain.                               */
9931 /*                                                                          */
9932 /* Returns:                                                                 */
9933 /*   Nothing.                                                               */
9934 /****************************************************************************/
9935 static __attribute__ ((noinline)) void
9936 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9937 {
9938         struct mbuf *m;
9939
9940         BCE_PRINTF(
9941                 "----------------------------"
9942                 "  tx mbuf data  "
9943                 "----------------------------\n");
9944
9945         for (int i = 0; i < count; i++) {
9946                 m = sc->tx_mbuf_ptr[chain_prod];
9947                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9948                 bce_dump_mbuf(sc, m);
9949                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9950         }
9951
9952         BCE_PRINTF(
9953                 "----------------------------"
9954                 "----------------"
9955                 "----------------------------\n");
9956 }
9957
9958
9959 /****************************************************************************/
9960 /* Prints out the mbufs in the RX mbuf chain.                               */
9961 /*                                                                          */
9962 /* Returns:                                                                 */
9963 /*   Nothing.                                                               */
9964 /****************************************************************************/
9965 static __attribute__ ((noinline)) void
9966 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9967 {
9968         struct mbuf *m;
9969
9970         BCE_PRINTF(
9971                 "----------------------------"
9972                 "  rx mbuf data  "
9973                 "----------------------------\n");
9974
9975         for (int i = 0; i < count; i++) {
9976                 m = sc->rx_mbuf_ptr[chain_prod];
9977                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9978                 bce_dump_mbuf(sc, m);
9979                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9980         }
9981
9982
9983         BCE_PRINTF(
9984                 "----------------------------"
9985                 "----------------"
9986                 "----------------------------\n");
9987 }
9988
9989
9990 /****************************************************************************/
9991 /* Prints out the mbufs in the mbuf page chain.                             */
9992 /*                                                                          */
9993 /* Returns:                                                                 */
9994 /*   Nothing.                                                               */
9995 /****************************************************************************/
9996 static __attribute__ ((noinline)) void
9997 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9998 {
9999         struct mbuf *m;
10000
10001         BCE_PRINTF(
10002                 "----------------------------"
10003                 "  pg mbuf data  "
10004                 "----------------------------\n");
10005
10006         for (int i = 0; i < count; i++) {
10007                 m = sc->pg_mbuf_ptr[chain_prod];
10008                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
10009                 bce_dump_mbuf(sc, m);
10010                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
10011         }
10012
10013
10014         BCE_PRINTF(
10015                 "----------------------------"
10016                 "----------------"
10017                 "----------------------------\n");
10018 }
10019
10020
10021 /****************************************************************************/
10022 /* Prints out a tx_bd structure.                                            */
10023 /*                                                                          */
10024 /* Returns:                                                                 */
10025 /*   Nothing.                                                               */
10026 /****************************************************************************/
10027 static __attribute__ ((noinline)) void
10028 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
10029 {
10030         int i = 0;
10031
10032         if (idx > MAX_TX_BD_ALLOC)
10033                 /* Index out of range. */
10034                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
10035         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
10036                 /* TX Chain page pointer. */
10037                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10038                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
10039                     txbd->tx_bd_haddr_lo);
10040         else {
10041                 /* Normal tx_bd entry. */
10042                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
10043                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
10044                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
10045                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10046                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10047
10048                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10049                         if (i>0)
10050                                 printf("|");
10051                         printf("CONN_FAULT");
10052                         i++;
10053                 }
10054
10055                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10056                         if (i>0)
10057                                 printf("|");
10058                         printf("TCP_UDP_CKSUM");
10059                         i++;
10060                 }
10061
10062                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10063                         if (i>0)
10064                                 printf("|");
10065                         printf("IP_CKSUM");
10066                         i++;
10067                 }
10068
10069                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10070                         if (i>0)
10071                                 printf("|");
10072                         printf("VLAN");
10073                         i++;
10074                 }
10075
10076                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10077                         if (i>0)
10078                                 printf("|");
10079                         printf("COAL_NOW");
10080                         i++;
10081                 }
10082
10083                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10084                         if (i>0)
10085                                 printf("|");
10086                         printf("DONT_GEN_CRC");
10087                         i++;
10088                 }
10089
10090                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10091                         if (i>0)
10092                                 printf("|");
10093                         printf("START");
10094                         i++;
10095                 }
10096
10097                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10098                         if (i>0)
10099                                 printf("|");
10100                         printf("END");
10101                         i++;
10102                 }
10103
10104                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10105                         if (i>0)
10106                                 printf("|");
10107                         printf("LSO");
10108                         i++;
10109                 }
10110
10111                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10112                         if (i>0)
10113                                 printf("|");
10114                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10115                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10116                 }
10117
10118                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10119                         if (i>0)
10120                                 printf("|");
10121                         printf("SW_FLAGS");
10122                         i++;
10123                 }
10124
10125                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10126                         if (i>0)
10127                                 printf("|");
10128                         printf("SNAP)");
10129                 } else {
10130                         printf(")\n");
10131                 }
10132         }
10133 }
10134
10135
10136 /****************************************************************************/
10137 /* Prints out a rx_bd structure.                                            */
10138 /*                                                                          */
10139 /* Returns:                                                                 */
10140 /*   Nothing.                                                               */
10141 /****************************************************************************/
10142 static __attribute__ ((noinline)) void
10143 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10144 {
10145         if (idx > MAX_RX_BD_ALLOC)
10146                 /* Index out of range. */
10147                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10148         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10149                 /* RX Chain page pointer. */
10150                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10151                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10152                     rxbd->rx_bd_haddr_lo);
10153         else
10154                 /* Normal rx_bd entry. */
10155                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10156                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10157                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10158                     rxbd->rx_bd_flags);
10159 }
10160
10161
10162 /****************************************************************************/
10163 /* Prints out a rx_bd structure in the page chain.                          */
10164 /*                                                                          */
10165 /* Returns:                                                                 */
10166 /*   Nothing.                                                               */
10167 /****************************************************************************/
10168 static __attribute__ ((noinline)) void
10169 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10170 {
10171         if (idx > MAX_PG_BD_ALLOC)
10172                 /* Index out of range. */
10173                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10174         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10175                 /* Page Chain page pointer. */
10176                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10177                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10178         else
10179                 /* Normal rx_bd entry. */
10180                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10181                         "flags = 0x%08X\n", idx,
10182                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10183                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10184 }
10185
10186
10187 /****************************************************************************/
10188 /* Prints out a l2_fhdr structure.                                          */
10189 /*                                                                          */
10190 /* Returns:                                                                 */
10191 /*   Nothing.                                                               */
10192 /****************************************************************************/
10193 static __attribute__ ((noinline)) void
10194 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10195 {
10196         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10197                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10198                 "tcp_udp_xsum = 0x%04X\n", idx,
10199                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10200                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10201                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10202 }
10203
10204
10205 /****************************************************************************/
10206 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10207 /*                                                                          */
10208 /* Returns:                                                                 */
10209 /*   Nothing.                                                               */
10210 /****************************************************************************/
10211 static __attribute__ ((noinline)) void
10212 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10213 {
10214         if (cid > TX_CID) {
10215                 BCE_PRINTF(" Unknown CID\n");
10216                 return;
10217         }
10218
10219         BCE_PRINTF(
10220             "----------------------------"
10221             "    CTX Data    "
10222             "----------------------------\n");
10223
10224         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10225
10226         if (cid == RX_CID) {
10227                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10228                    "producer index\n",
10229                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10230                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10231                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10232                     BCE_L2CTX_RX_HOST_BSEQ));
10233                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10234                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10235                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10236                     "descriptor address\n",
10237                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10238                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10239                     "descriptor address\n",
10240                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10241                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10242                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10243                     BCE_L2CTX_RX_NX_BDIDX));
10244                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10245                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10246                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10247                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10248                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10249                     BCE_L2CTX_RX_PG_BUF_SIZE));
10250                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10251                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10252                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10253                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10254                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10255                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10256                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10257                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10258                     BCE_L2CTX_RX_NX_PG_BDIDX));
10259         } else if (cid == TX_CID) {
10260                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10261                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10262                             CTX_RD(sc, GET_CID_ADDR(cid),
10263                             BCE_L2CTX_TX_TYPE_XI));
10264                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10265                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10266                             BCE_L2CTX_TX_CMD_TYPE_XI));
10267                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10268                             "h/w buffer descriptor address\n",
10269                             CTX_RD(sc, GET_CID_ADDR(cid),
10270                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10271                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10272                             "h/w buffer descriptor address\n",
10273                             CTX_RD(sc, GET_CID_ADDR(cid),
10274                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10275                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10276                             "host producer index\n",
10277                             CTX_RD(sc, GET_CID_ADDR(cid),
10278                             BCE_L2CTX_TX_HOST_BIDX_XI));
10279                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10280                             "host byte sequence\n",
10281                             CTX_RD(sc, GET_CID_ADDR(cid),
10282                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10283                 } else {
10284                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10285                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10286                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10287                             CTX_RD(sc, GET_CID_ADDR(cid),
10288                             BCE_L2CTX_TX_CMD_TYPE));
10289                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10290                             "h/w buffer descriptor address\n",
10291                             CTX_RD(sc, GET_CID_ADDR(cid),
10292                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10293                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10294                             "h/w buffer descriptor address\n",
10295                             CTX_RD(sc, GET_CID_ADDR(cid),
10296                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10297                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10298                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10299                             BCE_L2CTX_TX_HOST_BIDX));
10300                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10301                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10302                             BCE_L2CTX_TX_HOST_BSEQ));
10303                 }
10304         }
10305
10306         BCE_PRINTF(
10307            "----------------------------"
10308            "    Raw CTX     "
10309            "----------------------------\n");
10310
10311         for (int i = 0x0; i < 0x300; i += 0x10) {
10312                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10313                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10314                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10315                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10316                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10317         }
10318
10319
10320         BCE_PRINTF(
10321            "----------------------------"
10322            "----------------"
10323            "----------------------------\n");
10324 }
10325
10326
10327 /****************************************************************************/
10328 /* Prints out the FTQ data.                                                 */
10329 /*                                                                          */
10330 /* Returns:                                                                */
10331 /*   Nothing.                                                               */
10332 /****************************************************************************/
10333 static __attribute__ ((noinline)) void
10334 bce_dump_ftqs(struct bce_softc *sc)
10335 {
10336         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10337
10338         BCE_PRINTF(
10339             "----------------------------"
10340             "    FTQ Data    "
10341             "----------------------------\n");
10342
10343         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10344             "Max_Depth  Valid_Cnt \n");
10345         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10346             "---------- ----------\n");
10347
10348         /* Setup the generic statistic counters for the FTQ valid count. */
10349         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10350             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10351             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10352             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10353         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10354
10355         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10356             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10357             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10358             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10359         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10360
10361         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10362             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10363             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10364             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10365         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10366
10367         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10368             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10369             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10370             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10371         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10372
10373         /* Input queue to the Receive Lookup state machine */
10374         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10375         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10376         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10377         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10378         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10379         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10380             cmd, ctl, cur_depth, max_depth, valid_cnt);
10381
10382         /* Input queue to the Receive Processor */
10383         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10384         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10385         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10386         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10387         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10388         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10389             cmd, ctl, cur_depth, max_depth, valid_cnt);
10390
10391         /* Input queue to the Recevie Processor */
10392         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10393         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10394         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10395         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10396         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10397         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10398             cmd, ctl, cur_depth, max_depth, valid_cnt);
10399
10400         /* Input queue to the Receive Virtual to Physical state machine */
10401         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10402         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10403         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10404         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10405         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10406         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10407             cmd, ctl, cur_depth, max_depth, valid_cnt);
10408
10409         /* Input queue to the Recevie Virtual to Physical state machine */
10410         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10411         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10412         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10413         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10414         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10415         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10416             cmd, ctl, cur_depth, max_depth, valid_cnt);
10417
10418         /* Input queue to the Receive Virtual to Physical state machine */
10419         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10420         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10421         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10422         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10423         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10424         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10425             cmd, ctl, cur_depth, max_depth, valid_cnt);
10426
10427         /* Input queue to the Receive DMA state machine */
10428         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10429         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10430         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10431         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10432         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10433         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10434             cmd, ctl, cur_depth, max_depth, valid_cnt);
10435
10436         /* Input queue to the Transmit Scheduler state machine */
10437         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10438         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10439         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10440         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10441         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10442         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10443             cmd, ctl, cur_depth, max_depth, valid_cnt);
10444
10445         /* Input queue to the Transmit Buffer Descriptor state machine */
10446         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10447         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10448         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10449         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10450         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10451         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10452             cmd, ctl, cur_depth, max_depth, valid_cnt);
10453
10454         /* Input queue to the Transmit Processor */
10455         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10456         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10457         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10458         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10459         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10460         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10461             cmd, ctl, cur_depth, max_depth, valid_cnt);
10462
10463         /* Input queue to the Transmit DMA state machine */
10464         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10465         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10466         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10467         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10468         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10469         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10470             cmd, ctl, cur_depth, max_depth, valid_cnt);
10471
10472         /* Input queue to the Transmit Patch-Up Processor */
10473         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10474         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10475         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10476         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10477         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10478         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10479             cmd, ctl, cur_depth, max_depth, valid_cnt);
10480
10481         /* Input queue to the Transmit Assembler state machine */
10482         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10483         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10484         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10485         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10486         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10487         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10488             cmd, ctl, cur_depth, max_depth, valid_cnt);
10489
10490         /* Input queue to the Completion Processor */
10491         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10492         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10493         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10494         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10495         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10496         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10497             cmd, ctl, cur_depth, max_depth, valid_cnt);
10498
10499         /* Input queue to the Completion Processor */
10500         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10501         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10502         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10503         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10504         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10505         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10506             cmd, ctl, cur_depth, max_depth, valid_cnt);
10507
10508         /* Input queue to the Completion Processor */
10509         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10510         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10511         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10512         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10513         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10514         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10515             cmd, ctl, cur_depth, max_depth, valid_cnt);
10516
10517         /* Setup the generic statistic counters for the FTQ valid count. */
10518         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10519             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10520             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10521
10522         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10523                 val = val |
10524                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10525                      24);
10526         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10527
10528         /* Input queue to the Management Control Processor */
10529         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10530         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10531         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10532         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10533         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10534         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10535             cmd, ctl, cur_depth, max_depth, valid_cnt);
10536
10537         /* Input queue to the Command Processor */
10538         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10539         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10540         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10541         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10542         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10543         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10544             cmd, ctl, cur_depth, max_depth, valid_cnt);
10545
10546         /* Input queue to the Completion Scheduler state machine */
10547         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10548         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10549         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10550         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10551         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10552         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10553             cmd, ctl, cur_depth, max_depth, valid_cnt);
10554
10555         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10556                 /* Input queue to the RV2P Command Scheduler */
10557                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10558                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10559                 cur_depth = (ctl & 0xFFC00000) >> 22;
10560                 max_depth = (ctl & 0x003FF000) >> 12;
10561                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10562                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10563                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10564         }
10565
10566         BCE_PRINTF(
10567             "----------------------------"
10568             "----------------"
10569             "----------------------------\n");
10570 }
10571
10572
10573 /****************************************************************************/
10574 /* Prints out the TX chain.                                                 */
10575 /*                                                                          */
10576 /* Returns:                                                                 */
10577 /*   Nothing.                                                               */
10578 /****************************************************************************/
10579 static __attribute__ ((noinline)) void
10580 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10581 {
10582         struct tx_bd *txbd;
10583
10584         /* First some info about the tx_bd chain structure. */
10585         BCE_PRINTF(
10586             "----------------------------"
10587             "  tx_bd  chain  "
10588             "----------------------------\n");
10589
10590         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10591             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10592         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10593             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10594         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10595
10596         BCE_PRINTF(
10597             "----------------------------"
10598             "   tx_bd data   "
10599             "----------------------------\n");
10600
10601         /* Now print out a decoded list of TX buffer descriptors. */
10602         for (int i = 0; i < count; i++) {
10603                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10604                 bce_dump_txbd(sc, tx_prod, txbd);
10605                 tx_prod++;
10606         }
10607
10608         BCE_PRINTF(
10609             "----------------------------"
10610             "----------------"
10611             "----------------------------\n");
10612 }
10613
10614
10615 /****************************************************************************/
10616 /* Prints out the RX chain.                                                 */
10617 /*                                                                          */
10618 /* Returns:                                                                 */
10619 /*   Nothing.                                                               */
10620 /****************************************************************************/
10621 static __attribute__ ((noinline)) void
10622 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10623 {
10624         struct rx_bd *rxbd;
10625
10626         /* First some info about the rx_bd chain structure. */
10627         BCE_PRINTF(
10628             "----------------------------"
10629             "  rx_bd  chain  "
10630             "----------------------------\n");
10631
10632         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10633             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10634
10635         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10636             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10637
10638         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10639
10640         BCE_PRINTF(
10641             "----------------------------"
10642             "   rx_bd data   "
10643             "----------------------------\n");
10644
10645         /* Now print out the rx_bd's themselves. */
10646         for (int i = 0; i < count; i++) {
10647                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10648                 bce_dump_rxbd(sc, rx_prod, rxbd);
10649                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10650         }
10651
10652         BCE_PRINTF(
10653             "----------------------------"
10654             "----------------"
10655             "----------------------------\n");
10656 }
10657
10658
10659 /****************************************************************************/
10660 /* Prints out the page chain.                                               */
10661 /*                                                                          */
10662 /* Returns:                                                                 */
10663 /*   Nothing.                                                               */
10664 /****************************************************************************/
10665 static __attribute__ ((noinline)) void
10666 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10667 {
10668         struct rx_bd *pgbd;
10669
10670         /* First some info about the page chain structure. */
10671         BCE_PRINTF(
10672             "----------------------------"
10673             "   page chain   "
10674             "----------------------------\n");
10675
10676         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10677             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10678
10679         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10680             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10681
10682         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10683
10684         BCE_PRINTF(
10685             "----------------------------"
10686             "   page data    "
10687             "----------------------------\n");
10688
10689         /* Now print out the rx_bd's themselves. */
10690         for (int i = 0; i < count; i++) {
10691                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10692                 bce_dump_pgbd(sc, pg_prod, pgbd);
10693                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10694         }
10695
10696         BCE_PRINTF(
10697             "----------------------------"
10698             "----------------"
10699             "----------------------------\n");
10700 }
10701
10702
10703 #define BCE_PRINT_RX_CONS(arg)                                          \
10704 if (sblk->status_rx_quick_consumer_index##arg)                          \
10705         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10706             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10707             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10708             arg);
10709
10710
10711 #define BCE_PRINT_TX_CONS(arg)                                          \
10712 if (sblk->status_tx_quick_consumer_index##arg)                          \
10713         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10714             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10715             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10716             arg);
10717
10718 /****************************************************************************/
10719 /* Prints out the status block from host memory.                            */
10720 /*                                                                          */
10721 /* Returns:                                                                 */
10722 /*   Nothing.                                                               */
10723 /****************************************************************************/
10724 static __attribute__ ((noinline)) void
10725 bce_dump_status_block(struct bce_softc *sc)
10726 {
10727         struct status_block *sblk;
10728
10729         sblk = sc->status_block;
10730
10731         BCE_PRINTF(
10732             "----------------------------"
10733             "  Status Block  "
10734             "----------------------------\n");
10735
10736         /* Theses indices are used for normal L2 drivers. */
10737         BCE_PRINTF("    0x%08X - attn_bits\n",
10738             sblk->status_attn_bits);
10739
10740         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10741             sblk->status_attn_bits_ack);
10742
10743         BCE_PRINT_RX_CONS(0);
10744         BCE_PRINT_TX_CONS(0)
10745
10746         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10747
10748         /* Theses indices are not used for normal L2 drivers. */
10749         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10750         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10751         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10752         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10753         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10754
10755         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10756
10757         if (sblk->status_completion_producer_index ||
10758             sblk->status_cmd_consumer_index)
10759                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10760                     sblk->status_completion_producer_index,
10761                     sblk->status_cmd_consumer_index);
10762
10763         BCE_PRINTF(
10764             "----------------------------"
10765             "----------------"
10766             "----------------------------\n");
10767 }
10768
10769
10770 #define BCE_PRINT_64BIT_STAT(arg)                               \
10771 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10772         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10773             sblk->arg##_lo, #arg);
10774
10775 #define BCE_PRINT_32BIT_STAT(arg)                               \
10776 if (sblk->arg)                                                  \
10777         BCE_PRINTF("         0x%08X : %s\n",                    \
10778             sblk->arg, #arg);
10779
10780 /****************************************************************************/
10781 /* Prints out the statistics block from host memory.                        */
10782 /*                                                                          */
10783 /* Returns:                                                                 */
10784 /*   Nothing.                                                               */
10785 /****************************************************************************/
10786 static __attribute__ ((noinline)) void
10787 bce_dump_stats_block(struct bce_softc *sc)
10788 {
10789         struct statistics_block *sblk;
10790
10791         sblk = sc->stats_block;
10792
10793         BCE_PRINTF(
10794             "---------------"
10795             " Stats Block  (All Stats Not Shown Are 0) "
10796             "---------------\n");
10797
10798         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10799         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10800         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10801         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10802         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10803         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10804         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10805         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10806         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10807         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10808         BCE_PRINT_32BIT_STAT(
10809             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10810         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10811         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10812         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10813         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10814         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10815         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10816         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10817         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10818         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10819         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10820         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10821         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10822         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10823         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10824         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10825         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10826         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10827         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10828         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10829         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10830         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10831         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10832         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10833         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10834         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10835         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10836         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10837         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10838         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10839         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10840         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10841         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10842         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10843         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10844         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10845         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10846         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10847         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10848         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10849         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10850         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10851         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10852         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10853
10854         BCE_PRINTF(
10855             "----------------------------"
10856             "----------------"
10857             "----------------------------\n");
10858 }
10859
10860
10861 /****************************************************************************/
10862 /* Prints out a summary of the driver state.                                */
10863 /*                                                                          */
10864 /* Returns:                                                                 */
10865 /*   Nothing.                                                               */
10866 /****************************************************************************/
10867 static __attribute__ ((noinline)) void
10868 bce_dump_driver_state(struct bce_softc *sc)
10869 {
10870         u32 val_hi, val_lo;
10871
10872         BCE_PRINTF(
10873             "-----------------------------"
10874             " Driver State "
10875             "-----------------------------\n");
10876
10877         val_hi = BCE_ADDR_HI(sc);
10878         val_lo = BCE_ADDR_LO(sc);
10879         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10880             "address\n", val_hi, val_lo);
10881
10882         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10883         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10884         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10885             "address\n", val_hi, val_lo);
10886
10887         val_hi = BCE_ADDR_HI(sc->status_block);
10888         val_lo = BCE_ADDR_LO(sc->status_block);
10889         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10890             "virtual address\n",        val_hi, val_lo);
10891
10892         val_hi = BCE_ADDR_HI(sc->stats_block);
10893         val_lo = BCE_ADDR_LO(sc->stats_block);
10894         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10895             "virtual address\n", val_hi, val_lo);
10896
10897         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10898         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10899         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10900             "virtual adddress\n", val_hi, val_lo);
10901
10902         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10903         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10904         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10905             "virtual address\n", val_hi, val_lo);
10906
10907         if (bce_hdr_split == TRUE) {
10908                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10909                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10910                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10911                     "virtual address\n", val_hi, val_lo);
10912         }
10913
10914         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10915         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10916         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10917             "virtual address\n",        val_hi, val_lo);
10918
10919         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10920         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10921         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10922             "virtual address\n", val_hi, val_lo);
10923
10924         if (bce_hdr_split == TRUE) {
10925                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10926                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10927                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10928                     "virtual address\n", val_hi, val_lo);
10929         }
10930
10931         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10932             "h/w intrs\n",
10933             (long long unsigned int) sc->interrupts_generated);
10934
10935         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10936             "rx interrupts handled\n",
10937             (long long unsigned int) sc->interrupts_rx);
10938
10939         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10940             "tx interrupts handled\n",
10941             (long long unsigned int) sc->interrupts_tx);
10942
10943         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10944             "phy interrupts handled\n",
10945             (long long unsigned int) sc->phy_interrupts);
10946
10947         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10948             "status block index\n", sc->last_status_idx);
10949
10950         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10951             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10952
10953         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10954             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10955
10956         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10957             "byte seq index\n", sc->tx_prod_bseq);
10958
10959         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10960             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10961
10962         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10963             "tx_bd's\n", sc->used_tx_bd);
10964
10965         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10966             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10967
10968         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10969             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10970
10971         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10972             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10973
10974         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10975             "byte seq index\n", sc->rx_prod_bseq);
10976
10977         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10978                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10979
10980         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10981             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10982
10983         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10984             "rx_bd's\n", sc->free_rx_bd);
10985
10986         if (bce_hdr_split == TRUE) {
10987                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10988                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10989
10990                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10991                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10992
10993                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10994                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10995         }
10996
10997         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10998             "rx_bd's\n", sc->free_pg_bd);
10999
11000         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
11001             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
11002
11003         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
11004             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
11005
11006         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
11007             "bce mac flags\n", sc->bce_flags);
11008
11009         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
11010             "bce phy flags\n", sc->bce_phy_flags);
11011
11012         BCE_PRINTF(
11013             "----------------------------"
11014             "----------------"
11015             "----------------------------\n");
11016 }
11017
11018
11019 /****************************************************************************/
11020 /* Prints out the hardware state through a summary of important register,   */
11021 /* followed by a complete register dump.                                    */
11022 /*                                                                          */
11023 /* Returns:                                                                 */
11024 /*   Nothing.                                                               */
11025 /****************************************************************************/
11026 static __attribute__ ((noinline)) void
11027 bce_dump_hw_state(struct bce_softc *sc)
11028 {
11029         u32 val;
11030
11031         BCE_PRINTF(
11032             "----------------------------"
11033             " Hardware State "
11034             "----------------------------\n");
11035
11036         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11037
11038         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
11039         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
11040             val, BCE_MISC_ENABLE_STATUS_BITS);
11041
11042         val = REG_RD(sc, BCE_DMA_STATUS);
11043         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11044             val, BCE_DMA_STATUS);
11045
11046         val = REG_RD(sc, BCE_CTX_STATUS);
11047         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11048             val, BCE_CTX_STATUS);
11049
11050         val = REG_RD(sc, BCE_EMAC_STATUS);
11051         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11052             val, BCE_EMAC_STATUS);
11053
11054         val = REG_RD(sc, BCE_RPM_STATUS);
11055         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11056             val, BCE_RPM_STATUS);
11057
11058         /* ToDo: Create a #define for this constant. */
11059         val = REG_RD(sc, 0x2004);
11060         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11061             val, 0x2004);
11062
11063         val = REG_RD(sc, BCE_RV2P_STATUS);
11064         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11065             val, BCE_RV2P_STATUS);
11066
11067         /* ToDo: Create a #define for this constant. */
11068         val = REG_RD(sc, 0x2c04);
11069         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11070             val, 0x2c04);
11071
11072         val = REG_RD(sc, BCE_TBDR_STATUS);
11073         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11074             val, BCE_TBDR_STATUS);
11075
11076         val = REG_RD(sc, BCE_TDMA_STATUS);
11077         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11078             val, BCE_TDMA_STATUS);
11079
11080         val = REG_RD(sc, BCE_HC_STATUS);
11081         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11082             val, BCE_HC_STATUS);
11083
11084         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11085         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11086             val, BCE_TXP_CPU_STATE);
11087
11088         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11089         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11090             val, BCE_TPAT_CPU_STATE);
11091
11092         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11093         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11094             val, BCE_RXP_CPU_STATE);
11095
11096         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11097         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11098             val, BCE_COM_CPU_STATE);
11099
11100         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11101         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11102             val, BCE_MCP_CPU_STATE);
11103
11104         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11105         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11106             val, BCE_CP_CPU_STATE);
11107
11108         BCE_PRINTF(
11109             "----------------------------"
11110             "----------------"
11111             "----------------------------\n");
11112
11113         BCE_PRINTF(
11114             "----------------------------"
11115             " Register  Dump "
11116             "----------------------------\n");
11117
11118         for (int i = 0x400; i < 0x8000; i += 0x10) {
11119                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11120                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11121                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11122         }
11123
11124         BCE_PRINTF(
11125             "----------------------------"
11126             "----------------"
11127             "----------------------------\n");
11128 }
11129
11130
11131 /****************************************************************************/
11132 /* Prints out the contentst of shared memory which is used for host driver  */
11133 /* to bootcode firmware communication.                                      */
11134 /*                                                                          */
11135 /* Returns:                                                                 */
11136 /*   Nothing.                                                               */
11137 /****************************************************************************/
11138 static __attribute__ ((noinline)) void
11139 bce_dump_shmem_state(struct bce_softc *sc)
11140 {
11141         BCE_PRINTF(
11142             "----------------------------"
11143             " Hardware State "
11144             "----------------------------\n");
11145
11146         BCE_PRINTF("0x%08X - Shared memory base address\n",
11147             sc->bce_shmem_base);
11148         BCE_PRINTF("%s - bootcode version\n",
11149             sc->bce_bc_ver);
11150
11151         BCE_PRINTF(
11152             "----------------------------"
11153             "   Shared Mem   "
11154             "----------------------------\n");
11155
11156         for (int i = 0x0; i < 0x200; i += 0x10) {
11157                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11158                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11159                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11160         }
11161
11162         BCE_PRINTF(
11163             "----------------------------"
11164             "----------------"
11165             "----------------------------\n");
11166 }
11167
11168
11169 /****************************************************************************/
11170 /* Prints out the mailbox queue registers.                                  */
11171 /*                                                                          */
11172 /* Returns:                                                                 */
11173 /*   Nothing.                                                               */
11174 /****************************************************************************/
11175 static __attribute__ ((noinline)) void
11176 bce_dump_mq_regs(struct bce_softc *sc)
11177 {
11178         BCE_PRINTF(
11179             "----------------------------"
11180             "    MQ Regs     "
11181             "----------------------------\n");
11182
11183         BCE_PRINTF(
11184             "----------------------------"
11185             "----------------"
11186             "----------------------------\n");
11187
11188         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11189                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11190                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11191                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11192         }
11193
11194         BCE_PRINTF(
11195             "----------------------------"
11196             "----------------"
11197             "----------------------------\n");
11198 }
11199
11200
11201 /****************************************************************************/
11202 /* Prints out the bootcode state.                                           */
11203 /*                                                                          */
11204 /* Returns:                                                                 */
11205 /*   Nothing.                                                               */
11206 /****************************************************************************/
11207 static __attribute__ ((noinline)) void
11208 bce_dump_bc_state(struct bce_softc *sc)
11209 {
11210         u32 val;
11211
11212         BCE_PRINTF(
11213             "----------------------------"
11214             " Bootcode State "
11215             "----------------------------\n");
11216
11217         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11218
11219         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11220         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11221             val, BCE_BC_RESET_TYPE);
11222
11223         val = bce_shmem_rd(sc, BCE_BC_STATE);
11224         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11225             val, BCE_BC_STATE);
11226
11227         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11228         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11229             val, BCE_BC_STATE_CONDITION);
11230
11231         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11232         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11233             val, BCE_BC_STATE_DEBUG_CMD);
11234
11235         BCE_PRINTF(
11236             "----------------------------"
11237             "----------------"
11238             "----------------------------\n");
11239 }
11240
11241
11242 /****************************************************************************/
11243 /* Prints out the TXP processor state.                                      */
11244 /*                                                                          */
11245 /* Returns:                                                                 */
11246 /*   Nothing.                                                               */
11247 /****************************************************************************/
11248 static __attribute__ ((noinline)) void
11249 bce_dump_txp_state(struct bce_softc *sc, int regs)
11250 {
11251         u32 val;
11252         u32 fw_version[3];
11253
11254         BCE_PRINTF(
11255             "----------------------------"
11256             "   TXP  State   "
11257             "----------------------------\n");
11258
11259         for (int i = 0; i < 3; i++)
11260                 fw_version[i] = htonl(REG_RD_IND(sc,
11261                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11262         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11263
11264         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11265         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11266             val, BCE_TXP_CPU_MODE);
11267
11268         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11269         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11270             val, BCE_TXP_CPU_STATE);
11271
11272         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11273         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11274             val, BCE_TXP_CPU_EVENT_MASK);
11275
11276         if (regs) {
11277                 BCE_PRINTF(
11278                     "----------------------------"
11279                     " Register  Dump "
11280                     "----------------------------\n");
11281
11282                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11283                         /* Skip the big blank spaces */
11284                         if (i < 0x454000 && i > 0x5ffff)
11285                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11286                                     "0x%08X 0x%08X\n", i,
11287                                     REG_RD_IND(sc, i),
11288                                     REG_RD_IND(sc, i + 0x4),
11289                                     REG_RD_IND(sc, i + 0x8),
11290                                     REG_RD_IND(sc, i + 0xC));
11291                 }
11292         }
11293
11294         BCE_PRINTF(
11295             "----------------------------"
11296             "----------------"
11297             "----------------------------\n");
11298 }
11299
11300
11301 /****************************************************************************/
11302 /* Prints out the RXP processor state.                                      */
11303 /*                                                                          */
11304 /* Returns:                                                                 */
11305 /*   Nothing.                                                               */
11306 /****************************************************************************/
11307 static __attribute__ ((noinline)) void
11308 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11309 {
11310         u32 val;
11311         u32 fw_version[3];
11312
11313         BCE_PRINTF(
11314             "----------------------------"
11315             "   RXP  State   "
11316             "----------------------------\n");
11317
11318         for (int i = 0; i < 3; i++)
11319                 fw_version[i] = htonl(REG_RD_IND(sc,
11320                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11321
11322         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11323
11324         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11325         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11326             val, BCE_RXP_CPU_MODE);
11327
11328         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11329         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11330             val, BCE_RXP_CPU_STATE);
11331
11332         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11333         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11334             val, BCE_RXP_CPU_EVENT_MASK);
11335
11336         if (regs) {
11337                 BCE_PRINTF(
11338                     "----------------------------"
11339                     " Register  Dump "
11340                     "----------------------------\n");
11341
11342                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11343                         /* Skip the big blank sapces */
11344                         if (i < 0xc5400 && i > 0xdffff)
11345                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11346                                     "0x%08X 0x%08X\n", i,
11347                                     REG_RD_IND(sc, i),
11348                                     REG_RD_IND(sc, i + 0x4),
11349                                     REG_RD_IND(sc, i + 0x8),
11350                                     REG_RD_IND(sc, i + 0xC));
11351                 }
11352         }
11353
11354         BCE_PRINTF(
11355             "----------------------------"
11356             "----------------"
11357             "----------------------------\n");
11358 }
11359
11360
11361 /****************************************************************************/
11362 /* Prints out the TPAT processor state.                                     */
11363 /*                                                                          */
11364 /* Returns:                                                                 */
11365 /*   Nothing.                                                               */
11366 /****************************************************************************/
11367 static __attribute__ ((noinline)) void
11368 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11369 {
11370         u32 val;
11371         u32 fw_version[3];
11372
11373         BCE_PRINTF(
11374             "----------------------------"
11375             "   TPAT State   "
11376             "----------------------------\n");
11377
11378         for (int i = 0; i < 3; i++)
11379                 fw_version[i] = htonl(REG_RD_IND(sc,
11380                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11381
11382         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11383
11384         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11385         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11386             val, BCE_TPAT_CPU_MODE);
11387
11388         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11389         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11390             val, BCE_TPAT_CPU_STATE);
11391
11392         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11393         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11394             val, BCE_TPAT_CPU_EVENT_MASK);
11395
11396         if (regs) {
11397                 BCE_PRINTF(
11398                     "----------------------------"
11399                     " Register  Dump "
11400                     "----------------------------\n");
11401
11402                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11403                         /* Skip the big blank spaces */
11404                         if (i < 0x854000 && i > 0x9ffff)
11405                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11406                                     "0x%08X 0x%08X\n", i,
11407                                     REG_RD_IND(sc, i),
11408                                     REG_RD_IND(sc, i + 0x4),
11409                                     REG_RD_IND(sc, i + 0x8),
11410                                     REG_RD_IND(sc, i + 0xC));
11411                 }
11412         }
11413
11414         BCE_PRINTF(
11415                 "----------------------------"
11416                 "----------------"
11417                 "----------------------------\n");
11418 }
11419
11420
11421 /****************************************************************************/
11422 /* Prints out the Command Procesor (CP) state.                              */
11423 /*                                                                          */
11424 /* Returns:                                                                 */
11425 /*   Nothing.                                                               */
11426 /****************************************************************************/
11427 static __attribute__ ((noinline)) void
11428 bce_dump_cp_state(struct bce_softc *sc, int regs)
11429 {
11430         u32 val;
11431         u32 fw_version[3];
11432
11433         BCE_PRINTF(
11434             "----------------------------"
11435             "    CP State    "
11436             "----------------------------\n");
11437
11438         for (int i = 0; i < 3; i++)
11439                 fw_version[i] = htonl(REG_RD_IND(sc,
11440                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11441
11442         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11443
11444         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11445         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11446             val, BCE_CP_CPU_MODE);
11447
11448         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11449         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11450             val, BCE_CP_CPU_STATE);
11451
11452         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11453         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11454             BCE_CP_CPU_EVENT_MASK);
11455
11456         if (regs) {
11457                 BCE_PRINTF(
11458                     "----------------------------"
11459                     " Register  Dump "
11460                     "----------------------------\n");
11461
11462                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11463                         /* Skip the big blank spaces */
11464                         if (i < 0x185400 && i > 0x19ffff)
11465                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11466                                     "0x%08X 0x%08X\n", i,
11467                                     REG_RD_IND(sc, i),
11468                                     REG_RD_IND(sc, i + 0x4),
11469                                     REG_RD_IND(sc, i + 0x8),
11470                                     REG_RD_IND(sc, i + 0xC));
11471                 }
11472         }
11473
11474         BCE_PRINTF(
11475             "----------------------------"
11476             "----------------"
11477             "----------------------------\n");
11478 }
11479
11480
11481 /****************************************************************************/
11482 /* Prints out the Completion Procesor (COM) state.                          */
11483 /*                                                                          */
11484 /* Returns:                                                                 */
11485 /*   Nothing.                                                               */
11486 /****************************************************************************/
11487 static __attribute__ ((noinline)) void
11488 bce_dump_com_state(struct bce_softc *sc, int regs)
11489 {
11490         u32 val;
11491         u32 fw_version[4];
11492
11493         BCE_PRINTF(
11494             "----------------------------"
11495             "   COM State    "
11496             "----------------------------\n");
11497
11498         for (int i = 0; i < 3; i++)
11499                 fw_version[i] = htonl(REG_RD_IND(sc,
11500                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11501
11502         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11503
11504         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11505         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11506             val, BCE_COM_CPU_MODE);
11507
11508         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11509         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11510             val, BCE_COM_CPU_STATE);
11511
11512         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11513         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11514             BCE_COM_CPU_EVENT_MASK);
11515
11516         if (regs) {
11517                 BCE_PRINTF(
11518                     "----------------------------"
11519                     " Register  Dump "
11520                     "----------------------------\n");
11521
11522                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11523                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11524                             "0x%08X 0x%08X\n", i,
11525                             REG_RD_IND(sc, i),
11526                             REG_RD_IND(sc, i + 0x4),
11527                             REG_RD_IND(sc, i + 0x8),
11528                             REG_RD_IND(sc, i + 0xC));
11529                 }
11530         }
11531
11532         BCE_PRINTF(
11533                 "----------------------------"
11534                 "----------------"
11535                 "----------------------------\n");
11536 }
11537
11538
11539 /****************************************************************************/
11540 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11541 /*                                                                          */
11542 /* Returns:                                                                 */
11543 /*   Nothing.                                                               */
11544 /****************************************************************************/
11545 static __attribute__ ((noinline)) void
11546 bce_dump_rv2p_state(struct bce_softc *sc)
11547 {
11548         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11549
11550         BCE_PRINTF(
11551             "----------------------------"
11552             "   RV2P State   "
11553             "----------------------------\n");
11554
11555         /* Stall the RV2P processors. */
11556         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11557         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11558         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11559
11560         /* Read the firmware version. */
11561         val = 0x00000001;
11562         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11563         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11564         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11565             BCE_RV2P_INSTR_HIGH_HIGH;
11566         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11567             fw_ver_high, fw_ver_low);
11568
11569         val = 0x00000001;
11570         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11571         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11572         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11573             BCE_RV2P_INSTR_HIGH_HIGH;
11574         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11575             fw_ver_high, fw_ver_low);
11576
11577         /* Resume the RV2P processors. */
11578         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11579         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11580         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11581
11582         /* Fetch the program counter value. */
11583         val = 0x68007800;
11584         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11585         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11586         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11587         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11588         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11589         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11590
11591         /* Fetch the program counter value again to see if it is advancing. */
11592         val = 0x68007800;
11593         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11594         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11595         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11596         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11597         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11598         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11599
11600         BCE_PRINTF(
11601             "----------------------------"
11602             "----------------"
11603             "----------------------------\n");
11604 }
11605
11606
11607 /****************************************************************************/
11608 /* Prints out the driver state and then enters the debugger.                */
11609 /*                                                                          */
11610 /* Returns:                                                                 */
11611 /*   Nothing.                                                               */
11612 /****************************************************************************/
11613 static __attribute__ ((noinline)) void
11614 bce_breakpoint(struct bce_softc *sc)
11615 {
11616
11617         /*
11618          * Unreachable code to silence compiler warnings
11619          * about unused functions.
11620          */
11621         if (0) {
11622                 bce_freeze_controller(sc);
11623                 bce_unfreeze_controller(sc);
11624                 bce_dump_enet(sc, NULL);
11625                 bce_dump_txbd(sc, 0, NULL);
11626                 bce_dump_rxbd(sc, 0, NULL);
11627                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11628                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11629                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11630                 bce_dump_l2fhdr(sc, 0, NULL);
11631                 bce_dump_ctx(sc, RX_CID);
11632                 bce_dump_ftqs(sc);
11633                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11634                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11635                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11636                 bce_dump_status_block(sc);
11637                 bce_dump_stats_block(sc);
11638                 bce_dump_driver_state(sc);
11639                 bce_dump_hw_state(sc);
11640                 bce_dump_bc_state(sc);
11641                 bce_dump_txp_state(sc, 0);
11642                 bce_dump_rxp_state(sc, 0);
11643                 bce_dump_tpat_state(sc, 0);
11644                 bce_dump_cp_state(sc, 0);
11645                 bce_dump_com_state(sc, 0);
11646                 bce_dump_rv2p_state(sc);
11647                 bce_dump_pgbd(sc, 0, NULL);
11648         }
11649
11650         bce_dump_status_block(sc);
11651         bce_dump_driver_state(sc);
11652
11653         /* Call the debugger. */
11654         breakpoint();
11655
11656         return;
11657 }
11658 #endif