2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
86 #include <net/if_arp.h>
87 #include <net/ethernet.h>
88 #include <net/if_dl.h>
89 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/if_vlan_var.h>
96 #include <netinet/in_systm.h>
97 #include <netinet/in.h>
98 #include <netinet/ip.h>
99 #include <netinet/tcp.h>
101 #include <machine/bus.h>
102 #include <machine/resource.h>
104 #include <sys/rman.h>
106 #include <dev/mii/mii.h>
107 #include <dev/mii/miivar.h>
109 #include <dev/mii/brgphyreg.h>
112 #include <dev/ofw/ofw_bus.h>
113 #include <dev/ofw/openfirm.h>
114 #include <machine/ofw_machdep.h>
115 #include <machine/ver.h>
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
121 #include <dev/bge/if_bgereg.h>
123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126 MODULE_DEPEND(bge, pci, 1, 1, 1);
127 MODULE_DEPEND(bge, ether, 1, 1, 1);
128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130 /* "device miibus" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 * Various supported device vendors/types and their names. Note: the
135 * spec seems to indicate that the hardware still has Alteon's vendor
136 * ID burned into it, though it will always be overriden by the vendor
137 * ID in the EEPROM. Just to be safe, we cover all possibilities.
139 static const struct bge_type {
143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
230 { SK_VENDORID, SK_DEVICEID_ALTIMA },
232 { TC_VENDORID, TC_DEVICEID_3C996 },
234 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
235 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
236 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
241 static const struct bge_vendor {
245 { ALTEON_VENDORID, "Alteon" },
246 { ALTIMA_VENDORID, "Altima" },
247 { APPLE_VENDORID, "Apple" },
248 { BCOM_VENDORID, "Broadcom" },
249 { SK_VENDORID, "SysKonnect" },
250 { TC_VENDORID, "3Com" },
251 { FJTSU_VENDORID, "Fujitsu" },
256 static const struct bge_revision {
259 } bge_revisions[] = {
260 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
261 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
262 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
263 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
264 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
265 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
266 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
267 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
268 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
269 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
270 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
271 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
272 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
273 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
274 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
275 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
276 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
277 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
278 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
279 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
280 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
281 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
282 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
283 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
284 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
285 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
286 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
287 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
288 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
289 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
290 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
291 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
292 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
293 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
294 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
295 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
296 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
297 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
298 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
299 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
300 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
301 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
302 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
303 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
304 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
305 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
306 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
307 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
308 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
309 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
310 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
311 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
312 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
313 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
314 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
315 /* 5754 and 5787 share the same ASIC ID */
316 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
317 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
318 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
319 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
320 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
321 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
322 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
323 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
324 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
330 * Some defaults for major revisions, so that newer steppings
331 * that we don't know about have a shot at working.
333 static const struct bge_revision bge_majorrevs[] = {
334 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
335 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
336 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
337 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
338 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
339 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
340 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
341 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
342 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
343 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
344 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
345 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
346 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
347 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
348 /* 5754 and 5787 share the same ASIC ID */
349 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
350 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
351 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
352 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
353 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
354 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
355 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
356 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
361 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
362 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
363 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
364 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
365 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
366 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
367 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
368 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
370 const struct bge_revision * bge_lookup_rev(uint32_t);
371 const struct bge_vendor * bge_lookup_vendor(uint16_t);
373 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
375 static int bge_probe(device_t);
376 static int bge_attach(device_t);
377 static int bge_detach(device_t);
378 static int bge_suspend(device_t);
379 static int bge_resume(device_t);
380 static void bge_release_resources(struct bge_softc *);
381 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
382 static int bge_dma_alloc(struct bge_softc *);
383 static void bge_dma_free(struct bge_softc *);
384 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
385 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
387 static void bge_devinfo(struct bge_softc *);
388 static int bge_mbox_reorder(struct bge_softc *);
390 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
391 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
392 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
393 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
394 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
396 static void bge_txeof(struct bge_softc *, uint16_t);
397 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
398 static int bge_rxeof(struct bge_softc *, uint16_t, int);
400 static void bge_asf_driver_up (struct bge_softc *);
401 static void bge_tick(void *);
402 static void bge_stats_clear_regs(struct bge_softc *);
403 static void bge_stats_update(struct bge_softc *);
404 static void bge_stats_update_regs(struct bge_softc *);
405 static struct mbuf *bge_check_short_dma(struct mbuf *);
406 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
407 uint16_t *, uint16_t *);
408 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
410 static void bge_intr(void *);
411 static int bge_msi_intr(void *);
412 static void bge_intr_task(void *, int);
413 static void bge_start_locked(struct ifnet *);
414 static void bge_start(struct ifnet *);
415 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
416 static void bge_init_locked(struct bge_softc *);
417 static void bge_init(void *);
418 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
419 static void bge_stop(struct bge_softc *);
420 static void bge_watchdog(struct bge_softc *);
421 static int bge_shutdown(device_t);
422 static int bge_ifmedia_upd_locked(struct ifnet *);
423 static int bge_ifmedia_upd(struct ifnet *);
424 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
426 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
427 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
429 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
430 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
432 static void bge_setpromisc(struct bge_softc *);
433 static void bge_setmulti(struct bge_softc *);
434 static void bge_setvlan(struct bge_softc *);
436 static __inline void bge_rxreuse_std(struct bge_softc *, int);
437 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
438 static int bge_newbuf_std(struct bge_softc *, int);
439 static int bge_newbuf_jumbo(struct bge_softc *, int);
440 static int bge_init_rx_ring_std(struct bge_softc *);
441 static void bge_free_rx_ring_std(struct bge_softc *);
442 static int bge_init_rx_ring_jumbo(struct bge_softc *);
443 static void bge_free_rx_ring_jumbo(struct bge_softc *);
444 static void bge_free_tx_ring(struct bge_softc *);
445 static int bge_init_tx_ring(struct bge_softc *);
447 static int bge_chipinit(struct bge_softc *);
448 static int bge_blockinit(struct bge_softc *);
449 static uint32_t bge_dma_swap_options(struct bge_softc *);
451 static int bge_has_eaddr(struct bge_softc *);
452 static uint32_t bge_readmem_ind(struct bge_softc *, int);
453 static void bge_writemem_ind(struct bge_softc *, int, int);
454 static void bge_writembx(struct bge_softc *, int, int);
456 static uint32_t bge_readreg_ind(struct bge_softc *, int);
458 static void bge_writemem_direct(struct bge_softc *, int, int);
459 static void bge_writereg_ind(struct bge_softc *, int, int);
461 static int bge_miibus_readreg(device_t, int, int);
462 static int bge_miibus_writereg(device_t, int, int, int);
463 static void bge_miibus_statchg(device_t);
464 #ifdef DEVICE_POLLING
465 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
468 #define BGE_RESET_SHUTDOWN 0
469 #define BGE_RESET_START 1
470 #define BGE_RESET_SUSPEND 2
471 static void bge_sig_post_reset(struct bge_softc *, int);
472 static void bge_sig_legacy(struct bge_softc *, int);
473 static void bge_sig_pre_reset(struct bge_softc *, int);
474 static void bge_stop_fw(struct bge_softc *);
475 static int bge_reset(struct bge_softc *);
476 static void bge_link_upd(struct bge_softc *);
478 static void bge_ape_lock_init(struct bge_softc *);
479 static void bge_ape_read_fw_ver(struct bge_softc *);
480 static int bge_ape_lock(struct bge_softc *, int);
481 static void bge_ape_unlock(struct bge_softc *, int);
482 static void bge_ape_send_event(struct bge_softc *, uint32_t);
483 static void bge_ape_driver_state_change(struct bge_softc *, int);
486 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
487 * leak information to untrusted users. It is also known to cause alignment
488 * traps on certain architectures.
490 #ifdef BGE_REGISTER_DEBUG
491 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
492 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
493 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
494 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
496 static void bge_add_sysctls(struct bge_softc *);
497 static void bge_add_sysctl_stats_regs(struct bge_softc *,
498 struct sysctl_ctx_list *, struct sysctl_oid_list *);
499 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
500 struct sysctl_oid_list *);
501 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
503 static device_method_t bge_methods[] = {
504 /* Device interface */
505 DEVMETHOD(device_probe, bge_probe),
506 DEVMETHOD(device_attach, bge_attach),
507 DEVMETHOD(device_detach, bge_detach),
508 DEVMETHOD(device_shutdown, bge_shutdown),
509 DEVMETHOD(device_suspend, bge_suspend),
510 DEVMETHOD(device_resume, bge_resume),
513 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
514 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
515 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
520 static driver_t bge_driver = {
523 sizeof(struct bge_softc)
526 static devclass_t bge_devclass;
528 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
529 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
531 static int bge_allow_asf = 1;
533 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
535 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
536 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
537 "Allow ASF mode if available");
539 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
540 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
541 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
542 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
543 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
546 bge_has_eaddr(struct bge_softc *sc)
549 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
556 * The on-board BGEs found in sun4u machines aren't fitted with
557 * an EEPROM which means that we have to obtain the MAC address
558 * via OFW and that some tests will always fail. We distinguish
559 * such BGEs by the subvendor ID, which also has to be obtained
560 * from OFW instead of the PCI configuration space as the latter
561 * indicates Broadcom as the subvendor of the netboot interface.
562 * For early Blade 1500 and 2500 we even have to check the OFW
563 * device path as the subvendor ID always defaults to Broadcom
566 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
567 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
568 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
570 memset(buf, 0, sizeof(buf));
571 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
572 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
573 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
575 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
576 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
584 bge_readmem_ind(struct bge_softc *sc, int off)
589 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
590 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
595 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
596 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
597 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
602 bge_writemem_ind(struct bge_softc *sc, int off, int val)
606 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
607 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
612 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
613 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
614 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
619 bge_readreg_ind(struct bge_softc *sc, int off)
625 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
626 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
631 bge_writereg_ind(struct bge_softc *sc, int off, int val)
637 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
638 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
642 bge_writemem_direct(struct bge_softc *sc, int off, int val)
644 CSR_WRITE_4(sc, off, val);
648 bge_writembx(struct bge_softc *sc, int off, int val)
650 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
651 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
653 CSR_WRITE_4(sc, off, val);
654 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
659 * Clear all stale locks and select the lock for this driver instance.
662 bge_ape_lock_init(struct bge_softc *sc)
664 uint32_t bit, regbase;
667 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
668 regbase = BGE_APE_LOCK_GRANT;
670 regbase = BGE_APE_PER_LOCK_GRANT;
672 /* Clear any stale locks. */
673 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
675 case BGE_APE_LOCK_PHY0:
676 case BGE_APE_LOCK_PHY1:
677 case BGE_APE_LOCK_PHY2:
678 case BGE_APE_LOCK_PHY3:
679 bit = BGE_APE_LOCK_GRANT_DRIVER0;
682 if (sc->bge_func_addr != 0)
683 bit = BGE_APE_LOCK_GRANT_DRIVER0;
685 bit = (1 << sc->bge_func_addr);
687 APE_WRITE_4(sc, regbase + 4 * i, bit);
690 /* Select the PHY lock based on the device's function number. */
691 switch (sc->bge_func_addr) {
693 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
696 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
699 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
702 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
705 device_printf(sc->bge_dev,
706 "PHY lock not supported on this function\n");
711 * Check for APE firmware, set flags, and print version info.
714 bge_ape_read_fw_ver(struct bge_softc *sc)
717 uint32_t apedata, features;
719 /* Check for a valid APE signature in shared memory. */
720 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
721 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
722 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
726 /* Check if APE firmware is running. */
727 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
728 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
729 device_printf(sc->bge_dev, "APE signature found "
730 "but FW status not ready! 0x%08x\n", apedata);
734 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
736 /* Fetch the APE firwmare type and version. */
737 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
738 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
739 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
740 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
742 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
743 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
748 /* Print the APE firmware version. */
749 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
751 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
752 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
753 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
754 (apedata & BGE_APE_FW_VERSION_BLDMSK));
758 bge_ape_lock(struct bge_softc *sc, int locknum)
760 uint32_t bit, gnt, req, status;
763 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
766 /* Lock request/grant registers have different bases. */
767 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
768 req = BGE_APE_LOCK_REQ;
769 gnt = BGE_APE_LOCK_GRANT;
771 req = BGE_APE_PER_LOCK_REQ;
772 gnt = BGE_APE_PER_LOCK_GRANT;
778 case BGE_APE_LOCK_GPIO:
779 /* Lock required when using GPIO. */
780 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
782 if (sc->bge_func_addr == 0)
783 bit = BGE_APE_LOCK_REQ_DRIVER0;
785 bit = (1 << sc->bge_func_addr);
787 case BGE_APE_LOCK_GRC:
788 /* Lock required to reset the device. */
789 if (sc->bge_func_addr == 0)
790 bit = BGE_APE_LOCK_REQ_DRIVER0;
792 bit = (1 << sc->bge_func_addr);
794 case BGE_APE_LOCK_MEM:
795 /* Lock required when accessing certain APE memory. */
796 if (sc->bge_func_addr == 0)
797 bit = BGE_APE_LOCK_REQ_DRIVER0;
799 bit = (1 << sc->bge_func_addr);
801 case BGE_APE_LOCK_PHY0:
802 case BGE_APE_LOCK_PHY1:
803 case BGE_APE_LOCK_PHY2:
804 case BGE_APE_LOCK_PHY3:
805 /* Lock required when accessing PHYs. */
806 bit = BGE_APE_LOCK_REQ_DRIVER0;
812 /* Request a lock. */
813 APE_WRITE_4(sc, req + off, bit);
815 /* Wait up to 1 second to acquire lock. */
816 for (i = 0; i < 20000; i++) {
817 status = APE_READ_4(sc, gnt + off);
823 /* Handle any errors. */
825 device_printf(sc->bge_dev, "APE lock %d request failed! "
826 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
827 locknum, req + off, bit & 0xFFFF, gnt + off,
829 /* Revoke the lock request. */
830 APE_WRITE_4(sc, gnt + off, bit);
838 bge_ape_unlock(struct bge_softc *sc, int locknum)
843 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
846 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
847 gnt = BGE_APE_LOCK_GRANT;
849 gnt = BGE_APE_PER_LOCK_GRANT;
854 case BGE_APE_LOCK_GPIO:
855 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
857 if (sc->bge_func_addr == 0)
858 bit = BGE_APE_LOCK_GRANT_DRIVER0;
860 bit = (1 << sc->bge_func_addr);
862 case BGE_APE_LOCK_GRC:
863 if (sc->bge_func_addr == 0)
864 bit = BGE_APE_LOCK_GRANT_DRIVER0;
866 bit = (1 << sc->bge_func_addr);
868 case BGE_APE_LOCK_MEM:
869 if (sc->bge_func_addr == 0)
870 bit = BGE_APE_LOCK_GRANT_DRIVER0;
872 bit = (1 << sc->bge_func_addr);
874 case BGE_APE_LOCK_PHY0:
875 case BGE_APE_LOCK_PHY1:
876 case BGE_APE_LOCK_PHY2:
877 case BGE_APE_LOCK_PHY3:
878 bit = BGE_APE_LOCK_GRANT_DRIVER0;
884 APE_WRITE_4(sc, gnt + off, bit);
888 * Send an event to the APE firmware.
891 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
896 /* NCSI does not support APE events. */
897 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
900 /* Wait up to 1ms for APE to service previous event. */
901 for (i = 10; i > 0; i--) {
902 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
904 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
905 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
906 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
907 BGE_APE_EVENT_STATUS_EVENT_PENDING);
908 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
909 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
912 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
916 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
921 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
923 uint32_t apedata, event;
925 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
929 case BGE_RESET_START:
930 /* If this is the first load, clear the load counter. */
931 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
932 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
933 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
935 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
936 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
938 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
939 BGE_APE_HOST_SEG_SIG_MAGIC);
940 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
941 BGE_APE_HOST_SEG_LEN_MAGIC);
943 /* Add some version info if bge(4) supports it. */
944 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
945 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
946 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
947 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
948 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
949 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
950 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
951 BGE_APE_HOST_DRVR_STATE_START);
952 event = BGE_APE_EVENT_STATUS_STATE_START;
954 case BGE_RESET_SHUTDOWN:
955 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
956 BGE_APE_HOST_DRVR_STATE_UNLOAD);
957 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
959 case BGE_RESET_SUSPEND:
960 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
966 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
967 BGE_APE_EVENT_STATUS_STATE_CHNGE);
971 * Map a single buffer address.
975 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
977 struct bge_dmamap_arg *ctx;
982 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
985 ctx->bge_busaddr = segs->ds_addr;
989 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
991 uint32_t access, byte = 0;
995 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
996 for (i = 0; i < 8000; i++) {
997 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1004 /* Enable access. */
1005 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1006 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1008 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1009 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1010 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1012 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1018 if (i == BGE_TIMEOUT * 10) {
1019 if_printf(sc->bge_ifp, "nvram read timed out\n");
1024 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1026 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1028 /* Disable access. */
1029 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1032 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1033 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1039 * Read a sequence of bytes from NVRAM.
1042 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1047 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1050 for (i = 0; i < cnt; i++) {
1051 err = bge_nvram_getbyte(sc, off + i, &byte);
1057 return (err ? 1 : 0);
1061 * Read a byte of data stored in the EEPROM at address 'addr.' The
1062 * BCM570x supports both the traditional bitbang interface and an
1063 * auto access interface for reading the EEPROM. We use the auto
1067 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1073 * Enable use of auto EEPROM access so we can avoid
1074 * having to use the bitbang method.
1076 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1078 /* Reset the EEPROM, load the clock period. */
1079 CSR_WRITE_4(sc, BGE_EE_ADDR,
1080 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1083 /* Issue the read EEPROM command. */
1084 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1086 /* Wait for completion */
1087 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1089 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1093 if (i == BGE_TIMEOUT * 10) {
1094 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1099 byte = CSR_READ_4(sc, BGE_EE_DATA);
1101 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1107 * Read a sequence of bytes from the EEPROM.
1110 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1115 for (i = 0; i < cnt; i++) {
1116 error = bge_eeprom_getbyte(sc, off + i, &byte);
1122 return (error ? 1 : 0);
1126 bge_miibus_readreg(device_t dev, int phy, int reg)
1128 struct bge_softc *sc;
1132 sc = device_get_softc(dev);
1134 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1137 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1138 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1139 CSR_WRITE_4(sc, BGE_MI_MODE,
1140 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1144 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1145 BGE_MIPHY(phy) | BGE_MIREG(reg));
1147 /* Poll for the PHY register access to complete. */
1148 for (i = 0; i < BGE_TIMEOUT; i++) {
1150 val = CSR_READ_4(sc, BGE_MI_COMM);
1151 if ((val & BGE_MICOMM_BUSY) == 0) {
1153 val = CSR_READ_4(sc, BGE_MI_COMM);
1158 if (i == BGE_TIMEOUT) {
1159 device_printf(sc->bge_dev,
1160 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1165 /* Restore the autopoll bit if necessary. */
1166 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1167 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1171 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1173 if (val & BGE_MICOMM_READFAIL)
1176 return (val & 0xFFFF);
1180 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1182 struct bge_softc *sc;
1185 sc = device_get_softc(dev);
1187 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1188 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1191 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1194 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1195 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1196 CSR_WRITE_4(sc, BGE_MI_MODE,
1197 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1201 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1202 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1204 for (i = 0; i < BGE_TIMEOUT; i++) {
1206 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1208 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1213 /* Restore the autopoll bit if necessary. */
1214 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1215 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1219 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1221 if (i == BGE_TIMEOUT)
1222 device_printf(sc->bge_dev,
1223 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1230 bge_miibus_statchg(device_t dev)
1232 struct bge_softc *sc;
1233 struct mii_data *mii;
1234 uint32_t mac_mode, rx_mode, tx_mode;
1236 sc = device_get_softc(dev);
1237 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1239 mii = device_get_softc(sc->bge_miibus);
1241 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1242 (IFM_ACTIVE | IFM_AVALID)) {
1243 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1251 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1262 if (sc->bge_link == 0)
1266 * APE firmware touches these registers to keep the MAC
1267 * connected to the outside world. Try to keep the
1271 /* Set the port mode (MII/GMII) to match the link speed. */
1272 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1273 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1274 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1275 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1277 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1278 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1279 mac_mode |= BGE_PORTMODE_GMII;
1281 mac_mode |= BGE_PORTMODE_MII;
1283 /* Set MAC flow control behavior to match link flow control settings. */
1284 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1285 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1286 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
1287 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1288 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1289 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1290 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1292 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1294 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1296 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1297 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1301 * Intialize a standard receive ring descriptor.
1304 bge_newbuf_std(struct bge_softc *sc, int i)
1307 struct bge_rx_bd *r;
1308 bus_dma_segment_t segs[1];
1312 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1313 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1314 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1315 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1318 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1320 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1323 m->m_len = m->m_pkthdr.len = MCLBYTES;
1325 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1326 m_adj(m, ETHER_ALIGN);
1328 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1329 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1334 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1335 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1336 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1337 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1338 sc->bge_cdata.bge_rx_std_dmamap[i]);
1340 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1341 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1342 sc->bge_cdata.bge_rx_std_sparemap = map;
1343 sc->bge_cdata.bge_rx_std_chain[i] = m;
1344 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1345 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1346 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1347 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1348 r->bge_flags = BGE_RXBDFLAG_END;
1349 r->bge_len = segs[0].ds_len;
1352 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1353 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1359 * Initialize a jumbo receive ring descriptor. This allocates
1360 * a jumbo buffer from the pool managed internally by the driver.
1363 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1365 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1367 struct bge_extrx_bd *r;
1371 MGETHDR(m, M_NOWAIT, MT_DATA);
1375 m_cljget(m, M_NOWAIT, MJUM9BYTES);
1376 if (!(m->m_flags & M_EXT)) {
1380 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1381 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1382 m_adj(m, ETHER_ALIGN);
1384 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1385 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1391 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1392 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1393 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1394 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1395 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1397 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1398 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1399 sc->bge_cdata.bge_rx_jumbo_sparemap;
1400 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1401 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1402 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1403 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1404 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1405 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1408 * Fill in the extended RX buffer descriptor.
1410 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1411 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1413 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1416 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1417 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1418 r->bge_len3 = segs[3].ds_len;
1419 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1421 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1422 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1423 r->bge_len2 = segs[2].ds_len;
1424 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1426 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1427 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1428 r->bge_len1 = segs[1].ds_len;
1429 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1431 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1432 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1433 r->bge_len0 = segs[0].ds_len;
1434 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1437 panic("%s: %d segments\n", __func__, nsegs);
1440 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1441 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1447 bge_init_rx_ring_std(struct bge_softc *sc)
1451 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1453 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1454 if ((error = bge_newbuf_std(sc, i)) != 0)
1456 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1459 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1460 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1463 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1469 bge_free_rx_ring_std(struct bge_softc *sc)
1473 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1474 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1475 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1476 sc->bge_cdata.bge_rx_std_dmamap[i],
1477 BUS_DMASYNC_POSTREAD);
1478 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1479 sc->bge_cdata.bge_rx_std_dmamap[i]);
1480 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1481 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1483 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1484 sizeof(struct bge_rx_bd));
1489 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1491 struct bge_rcb *rcb;
1494 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1496 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1497 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1499 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1502 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1503 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1507 /* Enable the jumbo receive producer ring. */
1508 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1509 rcb->bge_maxlen_flags =
1510 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1511 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1513 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1519 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1523 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1524 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1525 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1526 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1527 BUS_DMASYNC_POSTREAD);
1528 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1529 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1530 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1531 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1533 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1534 sizeof(struct bge_extrx_bd));
1539 bge_free_tx_ring(struct bge_softc *sc)
1543 if (sc->bge_ldata.bge_tx_ring == NULL)
1546 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1547 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1548 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1549 sc->bge_cdata.bge_tx_dmamap[i],
1550 BUS_DMASYNC_POSTWRITE);
1551 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1552 sc->bge_cdata.bge_tx_dmamap[i]);
1553 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1554 sc->bge_cdata.bge_tx_chain[i] = NULL;
1556 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1557 sizeof(struct bge_tx_bd));
1562 bge_init_tx_ring(struct bge_softc *sc)
1565 sc->bge_tx_saved_considx = 0;
1567 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1568 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1569 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1571 /* Initialize transmit producer index for host-memory send ring. */
1572 sc->bge_tx_prodidx = 0;
1573 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1575 /* 5700 b2 errata */
1576 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1577 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1579 /* NIC-memory send ring not used; initialize to zero. */
1580 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1581 /* 5700 b2 errata */
1582 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1583 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1589 bge_setpromisc(struct bge_softc *sc)
1593 BGE_LOCK_ASSERT(sc);
1597 /* Enable or disable promiscuous mode as needed. */
1598 if (ifp->if_flags & IFF_PROMISC)
1599 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1601 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1605 bge_setmulti(struct bge_softc *sc)
1608 struct ifmultiaddr *ifma;
1609 uint32_t hashes[4] = { 0, 0, 0, 0 };
1612 BGE_LOCK_ASSERT(sc);
1616 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1617 for (i = 0; i < 4; i++)
1618 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1622 /* First, zot all the existing filters. */
1623 for (i = 0; i < 4; i++)
1624 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1626 /* Now program new ones. */
1627 if_maddr_rlock(ifp);
1628 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1629 if (ifma->ifma_addr->sa_family != AF_LINK)
1631 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1632 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1633 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1635 if_maddr_runlock(ifp);
1637 for (i = 0; i < 4; i++)
1638 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1642 bge_setvlan(struct bge_softc *sc)
1646 BGE_LOCK_ASSERT(sc);
1650 /* Enable or disable VLAN tag stripping as needed. */
1651 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1652 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1654 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1658 bge_sig_pre_reset(struct bge_softc *sc, int type)
1662 * Some chips don't like this so only do this if ASF is enabled
1664 if (sc->bge_asf_mode)
1665 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1667 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1669 case BGE_RESET_START:
1670 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1671 BGE_FW_DRV_STATE_START);
1673 case BGE_RESET_SHUTDOWN:
1674 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1675 BGE_FW_DRV_STATE_UNLOAD);
1677 case BGE_RESET_SUSPEND:
1678 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1679 BGE_FW_DRV_STATE_SUSPEND);
1684 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1685 bge_ape_driver_state_change(sc, type);
1689 bge_sig_post_reset(struct bge_softc *sc, int type)
1692 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1694 case BGE_RESET_START:
1695 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1696 BGE_FW_DRV_STATE_START_DONE);
1699 case BGE_RESET_SHUTDOWN:
1700 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1701 BGE_FW_DRV_STATE_UNLOAD_DONE);
1705 if (type == BGE_RESET_SHUTDOWN)
1706 bge_ape_driver_state_change(sc, type);
1710 bge_sig_legacy(struct bge_softc *sc, int type)
1713 if (sc->bge_asf_mode) {
1715 case BGE_RESET_START:
1716 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1717 BGE_FW_DRV_STATE_START);
1719 case BGE_RESET_SHUTDOWN:
1720 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1721 BGE_FW_DRV_STATE_UNLOAD);
1728 bge_stop_fw(struct bge_softc *sc)
1732 if (sc->bge_asf_mode) {
1733 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1734 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1735 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1737 for (i = 0; i < 100; i++ ) {
1738 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1739 BGE_RX_CPU_DRV_EVENT))
1747 bge_dma_swap_options(struct bge_softc *sc)
1749 uint32_t dma_options;
1751 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1752 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1753 #if BYTE_ORDER == BIG_ENDIAN
1754 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1756 return (dma_options);
1760 * Do endian, PCI and DMA initialization.
1763 bge_chipinit(struct bge_softc *sc)
1765 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1769 /* Set endianness before we access any non-PCI registers. */
1770 misc_ctl = BGE_INIT;
1771 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1772 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1773 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1776 * Clear the MAC statistics block in the NIC's
1779 for (i = BGE_STATS_BLOCK;
1780 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1781 BGE_MEMWIN_WRITE(sc, i, 0);
1783 for (i = BGE_STATUS_BLOCK;
1784 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1785 BGE_MEMWIN_WRITE(sc, i, 0);
1787 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1789 * Fix data corruption caused by non-qword write with WB.
1790 * Fix master abort in PCI mode.
1791 * Fix PCI latency timer.
1793 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1794 val |= (1 << 10) | (1 << 12) | (1 << 13);
1795 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1799 * Set up the PCI DMA control register.
1801 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1802 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1803 if (sc->bge_flags & BGE_FLAG_PCIE) {
1804 if (sc->bge_mps >= 256)
1805 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1807 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1808 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1809 if (BGE_IS_5714_FAMILY(sc)) {
1810 /* 256 bytes for read and write. */
1811 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1812 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1813 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1814 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1815 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1816 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1818 * In the BCM5703, the DMA read watermark should
1819 * be set to less than or equal to the maximum
1820 * memory read byte count of the PCI-X command
1823 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1824 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1825 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1826 /* 1536 bytes for read, 384 bytes for write. */
1827 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1828 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1830 /* 384 bytes for read and write. */
1831 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1832 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1835 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1836 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1839 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1840 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1841 if (tmp == 6 || tmp == 7)
1843 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1845 /* Set PCI-X DMA write workaround. */
1846 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1849 /* Conventional PCI bus: 256 bytes for read and write. */
1850 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1851 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1853 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1854 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1857 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1858 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1859 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1860 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1861 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1862 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1863 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1864 if (BGE_IS_5717_PLUS(sc)) {
1865 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1866 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1867 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1869 * Enable HW workaround for controllers that misinterpret
1870 * a status tag update and leave interrupts permanently
1873 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1874 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1875 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1877 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1880 * Set up general mode register.
1882 mode_ctl = bge_dma_swap_options(sc);
1883 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
1884 /* Retain Host-2-BMC settings written by APE firmware. */
1885 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1886 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1887 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1888 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1890 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1891 BGE_MODECTL_TX_NO_PHDR_CSUM;
1894 * BCM5701 B5 have a bug causing data corruption when using
1895 * 64-bit DMA reads, which can be terminated early and then
1896 * completed later as 32-bit accesses, in combination with
1899 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1900 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1901 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1904 * Tell the firmware the driver is running
1906 if (sc->bge_asf_mode & ASF_STACKUP)
1907 mode_ctl |= BGE_MODECTL_STACKUP;
1909 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1912 * Disable memory write invalidate. Apparently it is not supported
1913 * properly by these devices. Also ensure that INTx isn't disabled,
1914 * as these chips need it even when using MSI.
1916 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1917 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1919 /* Set the timer prescaler (always 66Mhz) */
1920 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1922 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1923 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1924 DELAY(40); /* XXX */
1926 /* Put PHY into ready state */
1927 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1928 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1936 bge_blockinit(struct bge_softc *sc)
1938 struct bge_rcb *rcb;
1941 uint32_t dmactl, val;
1945 * Initialize the memory window pointer register so that
1946 * we can access the first 32K of internal NIC RAM. This will
1947 * allow us to set up the TX send ring RCBs and the RX return
1948 * ring RCBs, plus other things which live in NIC memory.
1950 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1952 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1954 if (!(BGE_IS_5705_PLUS(sc))) {
1955 /* Configure mbuf memory pool */
1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1957 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1958 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1962 /* Configure DMA resource pool */
1963 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1964 BGE_DMA_DESCRIPTORS);
1965 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1968 /* Configure mbuf pool watermarks */
1969 if (BGE_IS_5717_PLUS(sc)) {
1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1971 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1978 } else if (!BGE_IS_5705_PLUS(sc)) {
1979 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1982 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1992 /* Configure DMA resource watermarks */
1993 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1994 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1996 /* Enable buffer manager */
1997 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1999 * Change the arbitration algorithm of TXMBUF read request to
2000 * round-robin instead of priority based for BCM5719. When
2001 * TXFIFO is almost empty, RDMA will hold its request until
2002 * TXFIFO is not almost empty.
2004 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2005 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2006 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2008 /* Poll for buffer manager start indication */
2009 for (i = 0; i < BGE_TIMEOUT; i++) {
2011 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2015 if (i == BGE_TIMEOUT) {
2016 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2020 /* Enable flow-through queues */
2021 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2024 /* Wait until queue initialization is complete */
2025 for (i = 0; i < BGE_TIMEOUT; i++) {
2027 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2031 if (i == BGE_TIMEOUT) {
2032 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2037 * Summary of rings supported by the controller:
2039 * Standard Receive Producer Ring
2040 * - This ring is used to feed receive buffers for "standard"
2041 * sized frames (typically 1536 bytes) to the controller.
2043 * Jumbo Receive Producer Ring
2044 * - This ring is used to feed receive buffers for jumbo sized
2045 * frames (i.e. anything bigger than the "standard" frames)
2046 * to the controller.
2048 * Mini Receive Producer Ring
2049 * - This ring is used to feed receive buffers for "mini"
2050 * sized frames to the controller.
2051 * - This feature required external memory for the controller
2052 * but was never used in a production system. Should always
2055 * Receive Return Ring
2056 * - After the controller has placed an incoming frame into a
2057 * receive buffer that buffer is moved into a receive return
2058 * ring. The driver is then responsible to passing the
2059 * buffer up to the stack. Many versions of the controller
2060 * support multiple RR rings.
2063 * - This ring is used for outgoing frames. Many versions of
2064 * the controller support multiple send rings.
2067 /* Initialize the standard receive producer ring control block. */
2068 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2069 rcb->bge_hostaddr.bge_addr_lo =
2070 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2071 rcb->bge_hostaddr.bge_addr_hi =
2072 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2073 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2074 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2075 if (BGE_IS_5717_PLUS(sc)) {
2077 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2078 * Bits 15-2 : Maximum RX frame size
2079 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2082 rcb->bge_maxlen_flags =
2083 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2084 } else if (BGE_IS_5705_PLUS(sc)) {
2086 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2087 * Bits 15-2 : Reserved (should be 0)
2088 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2091 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2094 * Ring size is always XXX entries
2095 * Bits 31-16: Maximum RX frame size
2096 * Bits 15-2 : Reserved (should be 0)
2097 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2100 rcb->bge_maxlen_flags =
2101 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2103 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2104 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2105 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2106 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2108 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2109 /* Write the standard receive producer ring control block. */
2110 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2111 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2112 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2113 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2115 /* Reset the standard receive producer ring producer index. */
2116 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2119 * Initialize the jumbo RX producer ring control
2120 * block. We set the 'ring disabled' bit in the
2121 * flags field until we're actually ready to start
2122 * using this ring (i.e. once we set the MTU
2123 * high enough to require it).
2125 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2126 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2127 /* Get the jumbo receive producer ring RCB parameters. */
2128 rcb->bge_hostaddr.bge_addr_lo =
2129 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2130 rcb->bge_hostaddr.bge_addr_hi =
2131 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2132 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2133 sc->bge_cdata.bge_rx_jumbo_ring_map,
2134 BUS_DMASYNC_PREREAD);
2135 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2136 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2137 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2138 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2139 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2140 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2142 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2143 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2144 rcb->bge_hostaddr.bge_addr_hi);
2145 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2146 rcb->bge_hostaddr.bge_addr_lo);
2147 /* Program the jumbo receive producer ring RCB parameters. */
2148 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2149 rcb->bge_maxlen_flags);
2150 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2151 /* Reset the jumbo receive producer ring producer index. */
2152 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2155 /* Disable the mini receive producer ring RCB. */
2156 if (BGE_IS_5700_FAMILY(sc)) {
2157 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2158 rcb->bge_maxlen_flags =
2159 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2160 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2161 rcb->bge_maxlen_flags);
2162 /* Reset the mini receive producer ring producer index. */
2163 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2166 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2167 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2168 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2169 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2170 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2171 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2172 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2175 * The BD ring replenish thresholds control how often the
2176 * hardware fetches new BD's from the producer rings in host
2177 * memory. Setting the value too low on a busy system can
2178 * starve the hardware and recue the throughpout.
2180 * Set the BD ring replentish thresholds. The recommended
2181 * values are 1/8th the number of descriptors allocated to
2183 * XXX The 5754 requires a lower threshold, so it might be a
2184 * requirement of all 575x family chips. The Linux driver sets
2185 * the lower threshold for all 5705 family chips as well, but there
2186 * are reports that it might not need to be so strict.
2188 * XXX Linux does some extra fiddling here for the 5906 parts as
2191 if (BGE_IS_5705_PLUS(sc))
2194 val = BGE_STD_RX_RING_CNT / 8;
2195 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2196 if (BGE_IS_JUMBO_CAPABLE(sc))
2197 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2198 BGE_JUMBO_RX_RING_CNT/8);
2199 if (BGE_IS_5717_PLUS(sc)) {
2200 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2201 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2205 * Disable all send rings by setting the 'ring disabled' bit
2206 * in the flags field of all the TX send ring control blocks,
2207 * located in NIC memory.
2209 if (!BGE_IS_5705_PLUS(sc))
2210 /* 5700 to 5704 had 16 send rings. */
2211 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2214 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2215 for (i = 0; i < limit; i++) {
2216 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2217 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2218 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2219 vrcb += sizeof(struct bge_rcb);
2222 /* Configure send ring RCB 0 (we use only the first ring) */
2223 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2224 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2225 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2226 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2227 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2228 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2229 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2230 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2232 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2233 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2234 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2235 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2238 * Disable all receive return rings by setting the
2239 * 'ring diabled' bit in the flags field of all the receive
2240 * return ring control blocks, located in NIC memory.
2242 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2243 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2244 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2245 /* Should be 17, use 16 until we get an SRAM map. */
2247 } else if (!BGE_IS_5705_PLUS(sc))
2248 limit = BGE_RX_RINGS_MAX;
2249 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2250 BGE_IS_57765_PLUS(sc))
2254 /* Disable all receive return rings. */
2255 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2256 for (i = 0; i < limit; i++) {
2257 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2259 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2260 BGE_RCB_FLAG_RING_DISABLED);
2261 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2262 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2263 (i * (sizeof(uint64_t))), 0);
2264 vrcb += sizeof(struct bge_rcb);
2268 * Set up receive return ring 0. Note that the NIC address
2269 * for RX return rings is 0x0. The return rings live entirely
2270 * within the host, so the nicaddr field in the RCB isn't used.
2272 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2273 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2274 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2275 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2276 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2277 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2278 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2280 /* Set random backoff seed for TX */
2281 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2282 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2283 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2284 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
2285 BGE_TX_BACKOFF_SEED_MASK);
2287 /* Set inter-packet gap */
2289 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
2290 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2291 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2292 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2295 * Specify which ring to use for packets that don't match
2298 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2301 * Configure number of RX lists. One interrupt distribution
2302 * list, sixteen active lists, one bad frames class.
2304 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2306 /* Inialize RX list placement stats mask. */
2307 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2308 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2310 /* Disable host coalescing until we get it set up */
2311 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2313 /* Poll to make sure it's shut down. */
2314 for (i = 0; i < BGE_TIMEOUT; i++) {
2316 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2320 if (i == BGE_TIMEOUT) {
2321 device_printf(sc->bge_dev,
2322 "host coalescing engine failed to idle\n");
2326 /* Set up host coalescing defaults */
2327 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2328 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2329 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2330 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2331 if (!(BGE_IS_5705_PLUS(sc))) {
2332 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2333 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2335 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2336 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2338 /* Set up address of statistics block */
2339 if (!(BGE_IS_5705_PLUS(sc))) {
2340 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2341 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2342 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2343 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2344 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2345 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2346 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2349 /* Set up address of status block */
2350 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2351 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2352 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2353 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2355 /* Set up status block size. */
2356 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2357 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2358 val = BGE_STATBLKSZ_FULL;
2359 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2361 val = BGE_STATBLKSZ_32BYTE;
2362 bzero(sc->bge_ldata.bge_status_block, 32);
2364 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2365 sc->bge_cdata.bge_status_map,
2366 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2368 /* Turn on host coalescing state machine */
2369 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2371 /* Turn on RX BD completion state machine and enable attentions */
2372 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2373 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2375 /* Turn on RX list placement state machine */
2376 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2378 /* Turn on RX list selector state machine. */
2379 if (!(BGE_IS_5705_PLUS(sc)))
2380 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2382 /* Turn on DMA, clear stats. */
2383 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2384 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2385 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2386 BGE_MACMODE_FRMHDR_DMA_ENB;
2388 if (sc->bge_flags & BGE_FLAG_TBI)
2389 val |= BGE_PORTMODE_TBI;
2390 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2391 val |= BGE_PORTMODE_GMII;
2393 val |= BGE_PORTMODE_MII;
2395 /* Allow APE to send/receive frames. */
2396 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2397 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2399 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2402 /* Set misc. local control, enable interrupts on attentions */
2403 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2406 /* Assert GPIO pins for PHY reset */
2407 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2408 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2409 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2410 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2413 /* Turn on DMA completion state machine */
2414 if (!(BGE_IS_5705_PLUS(sc)))
2415 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2417 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2419 /* Enable host coalescing bug fix. */
2420 if (BGE_IS_5755_PLUS(sc))
2421 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2423 /* Request larger DMA burst size to get better performance. */
2424 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2425 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2427 /* Turn on write DMA state machine */
2428 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2431 /* Turn on read DMA state machine */
2432 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2434 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2435 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2437 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2438 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2439 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2440 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2441 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2442 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2443 if (sc->bge_flags & BGE_FLAG_PCIE)
2444 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2445 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2446 val |= BGE_RDMAMODE_TSO4_ENABLE;
2447 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2448 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2449 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2450 val |= BGE_RDMAMODE_TSO6_ENABLE;
2453 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2454 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2455 BGE_RDMAMODE_H2BNC_VLAN_DET;
2457 * Allow multiple outstanding read requests from
2458 * non-LSO read DMA engine.
2460 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2463 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2464 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2465 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2466 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2467 BGE_IS_5717_PLUS(sc)) {
2468 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2470 * Adjust tx margin to prevent TX data corruption and
2471 * fix internal FIFO overflow.
2473 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2474 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2475 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2477 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2478 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2479 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2480 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2483 * Enable fix for read DMA FIFO overruns.
2484 * The fix is to limit the number of RX BDs
2485 * the hardware would fetch at a fime.
2487 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2488 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2491 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2492 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2493 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2494 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2495 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2496 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2498 * Allow 4KB burst length reads for non-LSO frames.
2499 * Enable 512B burst length reads for buffer descriptors.
2501 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2502 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2503 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2504 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2507 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2510 /* Turn on RX data completion state machine */
2511 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2513 /* Turn on RX BD initiator state machine */
2514 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2516 /* Turn on RX data and RX BD initiator state machine */
2517 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2519 /* Turn on Mbuf cluster free state machine */
2520 if (!(BGE_IS_5705_PLUS(sc)))
2521 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2523 /* Turn on send BD completion state machine */
2524 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2526 /* Turn on send data completion state machine */
2527 val = BGE_SDCMODE_ENABLE;
2528 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2529 val |= BGE_SDCMODE_CDELAY;
2530 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2532 /* Turn on send data initiator state machine */
2533 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2534 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2535 BGE_SDIMODE_HW_LSO_PRE_DMA);
2537 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2539 /* Turn on send BD initiator state machine */
2540 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2542 /* Turn on send BD selector state machine */
2543 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2545 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2546 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2547 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2549 /* ack/clear link change events */
2550 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2551 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2552 BGE_MACSTAT_LINK_CHANGED);
2553 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2556 * Enable attention when the link has changed state for
2557 * devices that use auto polling.
2559 if (sc->bge_flags & BGE_FLAG_TBI) {
2560 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2562 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2563 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2566 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2567 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2568 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2569 BGE_EVTENB_MI_INTERRUPT);
2573 * Clear any pending link state attention.
2574 * Otherwise some link state change events may be lost until attention
2575 * is cleared by bge_intr() -> bge_link_upd() sequence.
2576 * It's not necessary on newer BCM chips - perhaps enabling link
2577 * state change attentions implies clearing pending attention.
2579 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2580 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2581 BGE_MACSTAT_LINK_CHANGED);
2583 /* Enable link state change attentions. */
2584 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2589 const struct bge_revision *
2590 bge_lookup_rev(uint32_t chipid)
2592 const struct bge_revision *br;
2594 for (br = bge_revisions; br->br_name != NULL; br++) {
2595 if (br->br_chipid == chipid)
2599 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2600 if (br->br_chipid == BGE_ASICREV(chipid))
2607 const struct bge_vendor *
2608 bge_lookup_vendor(uint16_t vid)
2610 const struct bge_vendor *v;
2612 for (v = bge_vendors; v->v_name != NULL; v++)
2616 panic("%s: unknown vendor %d", __func__, vid);
2621 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2622 * against our list and return its name if we find a match.
2624 * Note that since the Broadcom controller contains VPD support, we
2625 * try to get the device name string from the controller itself instead
2626 * of the compiled-in string. It guarantees we'll always announce the
2627 * right product name. We fall back to the compiled-in string when
2628 * VPD is unavailable or corrupt.
2631 bge_probe(device_t dev)
2635 const struct bge_revision *br;
2637 struct bge_softc *sc = device_get_softc(dev);
2638 const struct bge_type *t = bge_devs;
2639 const struct bge_vendor *v;
2644 vid = pci_get_vendor(dev);
2645 did = pci_get_device(dev);
2646 while(t->bge_vid != 0) {
2647 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2648 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2649 BGE_PCIMISCCTL_ASICREV_SHIFT;
2650 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2652 * Find the ASCI revision. Different chips
2653 * use different registers.
2655 switch (pci_get_device(dev)) {
2656 case BCOM_DEVICEID_BCM5717:
2657 case BCOM_DEVICEID_BCM5718:
2658 case BCOM_DEVICEID_BCM5719:
2659 case BCOM_DEVICEID_BCM5720:
2660 id = pci_read_config(dev,
2661 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2663 case BCOM_DEVICEID_BCM57761:
2664 case BCOM_DEVICEID_BCM57762:
2665 case BCOM_DEVICEID_BCM57765:
2666 case BCOM_DEVICEID_BCM57766:
2667 case BCOM_DEVICEID_BCM57781:
2668 case BCOM_DEVICEID_BCM57785:
2669 case BCOM_DEVICEID_BCM57791:
2670 case BCOM_DEVICEID_BCM57795:
2671 id = pci_read_config(dev,
2672 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2675 id = pci_read_config(dev,
2676 BGE_PCI_PRODID_ASICREV, 4);
2679 br = bge_lookup_rev(id);
2680 v = bge_lookup_vendor(vid);
2681 if (bge_has_eaddr(sc) &&
2682 pci_get_vpd_ident(dev, &pname) == 0)
2683 snprintf(model, 64, "%s", pname);
2685 snprintf(model, 64, "%s %s", v->v_name,
2686 br != NULL ? br->br_name :
2687 "NetXtreme Ethernet Controller");
2688 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2689 br != NULL ? "" : "unknown ", id);
2690 device_set_desc_copy(dev, buf);
2700 bge_dma_free(struct bge_softc *sc)
2704 /* Destroy DMA maps for RX buffers. */
2705 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2706 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2707 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2708 sc->bge_cdata.bge_rx_std_dmamap[i]);
2710 if (sc->bge_cdata.bge_rx_std_sparemap)
2711 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2712 sc->bge_cdata.bge_rx_std_sparemap);
2714 /* Destroy DMA maps for jumbo RX buffers. */
2715 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2716 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2717 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2718 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2720 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2721 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2722 sc->bge_cdata.bge_rx_jumbo_sparemap);
2724 /* Destroy DMA maps for TX buffers. */
2725 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2726 if (sc->bge_cdata.bge_tx_dmamap[i])
2727 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2728 sc->bge_cdata.bge_tx_dmamap[i]);
2731 if (sc->bge_cdata.bge_rx_mtag)
2732 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2733 if (sc->bge_cdata.bge_mtag_jumbo)
2734 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2735 if (sc->bge_cdata.bge_tx_mtag)
2736 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2738 /* Destroy standard RX ring. */
2739 if (sc->bge_cdata.bge_rx_std_ring_map)
2740 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2741 sc->bge_cdata.bge_rx_std_ring_map);
2742 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2743 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2744 sc->bge_ldata.bge_rx_std_ring,
2745 sc->bge_cdata.bge_rx_std_ring_map);
2747 if (sc->bge_cdata.bge_rx_std_ring_tag)
2748 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2750 /* Destroy jumbo RX ring. */
2751 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2752 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2753 sc->bge_cdata.bge_rx_jumbo_ring_map);
2755 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2756 sc->bge_ldata.bge_rx_jumbo_ring)
2757 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2758 sc->bge_ldata.bge_rx_jumbo_ring,
2759 sc->bge_cdata.bge_rx_jumbo_ring_map);
2761 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2762 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2764 /* Destroy RX return ring. */
2765 if (sc->bge_cdata.bge_rx_return_ring_map)
2766 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2767 sc->bge_cdata.bge_rx_return_ring_map);
2769 if (sc->bge_cdata.bge_rx_return_ring_map &&
2770 sc->bge_ldata.bge_rx_return_ring)
2771 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2772 sc->bge_ldata.bge_rx_return_ring,
2773 sc->bge_cdata.bge_rx_return_ring_map);
2775 if (sc->bge_cdata.bge_rx_return_ring_tag)
2776 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2778 /* Destroy TX ring. */
2779 if (sc->bge_cdata.bge_tx_ring_map)
2780 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2781 sc->bge_cdata.bge_tx_ring_map);
2783 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2784 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2785 sc->bge_ldata.bge_tx_ring,
2786 sc->bge_cdata.bge_tx_ring_map);
2788 if (sc->bge_cdata.bge_tx_ring_tag)
2789 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2791 /* Destroy status block. */
2792 if (sc->bge_cdata.bge_status_map)
2793 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2794 sc->bge_cdata.bge_status_map);
2796 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2797 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2798 sc->bge_ldata.bge_status_block,
2799 sc->bge_cdata.bge_status_map);
2801 if (sc->bge_cdata.bge_status_tag)
2802 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2804 /* Destroy statistics block. */
2805 if (sc->bge_cdata.bge_stats_map)
2806 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2807 sc->bge_cdata.bge_stats_map);
2809 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2810 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2811 sc->bge_ldata.bge_stats,
2812 sc->bge_cdata.bge_stats_map);
2814 if (sc->bge_cdata.bge_stats_tag)
2815 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2817 if (sc->bge_cdata.bge_buffer_tag)
2818 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2820 /* Destroy the parent tag. */
2821 if (sc->bge_cdata.bge_parent_tag)
2822 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2826 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2827 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2828 bus_addr_t *paddr, const char *msg)
2830 struct bge_dmamap_arg ctx;
2832 bus_size_t ring_end;
2835 lowaddr = BUS_SPACE_MAXADDR;
2837 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2838 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2839 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2841 device_printf(sc->bge_dev,
2842 "could not create %s dma tag\n", msg);
2845 /* Allocate DMA'able memory for ring. */
2846 error = bus_dmamem_alloc(*tag, (void **)ring,
2847 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2849 device_printf(sc->bge_dev,
2850 "could not allocate DMA'able memory for %s\n", msg);
2853 /* Load the address of the ring. */
2854 ctx.bge_busaddr = 0;
2855 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2856 &ctx, BUS_DMA_NOWAIT);
2858 device_printf(sc->bge_dev,
2859 "could not load DMA'able memory for %s\n", msg);
2862 *paddr = ctx.bge_busaddr;
2863 ring_end = *paddr + maxsize;
2864 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2865 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2867 * 4GB boundary crossed. Limit maximum allowable DMA
2868 * address space to 32bit and try again.
2870 bus_dmamap_unload(*tag, *map);
2871 bus_dmamem_free(*tag, *ring, *map);
2872 bus_dma_tag_destroy(*tag);
2874 device_printf(sc->bge_dev, "4GB boundary crossed, "
2875 "limit DMA address space to 32bit for %s\n", msg);
2879 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2886 bge_dma_alloc(struct bge_softc *sc)
2889 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2892 lowaddr = BUS_SPACE_MAXADDR;
2893 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2894 lowaddr = BGE_DMA_MAXADDR;
2896 * Allocate the parent bus DMA tag appropriate for PCI.
2898 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2899 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2900 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2901 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2903 device_printf(sc->bge_dev,
2904 "could not allocate parent dma tag\n");
2908 /* Create tag for standard RX ring. */
2909 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2910 &sc->bge_cdata.bge_rx_std_ring_tag,
2911 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2912 &sc->bge_cdata.bge_rx_std_ring_map,
2913 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2917 /* Create tag for RX return ring. */
2918 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2919 &sc->bge_cdata.bge_rx_return_ring_tag,
2920 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2921 &sc->bge_cdata.bge_rx_return_ring_map,
2922 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2926 /* Create tag for TX ring. */
2927 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2928 &sc->bge_cdata.bge_tx_ring_tag,
2929 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2930 &sc->bge_cdata.bge_tx_ring_map,
2931 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2936 * Create tag for status block.
2937 * Because we only use single Tx/Rx/Rx return ring, use
2938 * minimum status block size except BCM5700 AX/BX which
2939 * seems to want to see full status block size regardless
2940 * of configured number of ring.
2942 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2943 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2944 sbsz = BGE_STATUS_BLK_SZ;
2947 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2948 &sc->bge_cdata.bge_status_tag,
2949 (uint8_t **)&sc->bge_ldata.bge_status_block,
2950 &sc->bge_cdata.bge_status_map,
2951 &sc->bge_ldata.bge_status_block_paddr, "status block");
2955 /* Create tag for statistics block. */
2956 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2957 &sc->bge_cdata.bge_stats_tag,
2958 (uint8_t **)&sc->bge_ldata.bge_stats,
2959 &sc->bge_cdata.bge_stats_map,
2960 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2964 /* Create tag for jumbo RX ring. */
2965 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2966 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2967 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2968 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2969 &sc->bge_cdata.bge_rx_jumbo_ring_map,
2970 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2975 /* Create parent tag for buffers. */
2977 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2978 boundary = BGE_DMA_BNDRY;
2981 * watchdog timeout issue was observed on BCM5704 which
2982 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2983 * Both limiting DMA address space to 32bits and flushing
2984 * mailbox write seem to address the issue.
2986 if (sc->bge_pcixcap != 0)
2987 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2989 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2990 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
2991 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2992 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2994 device_printf(sc->bge_dev,
2995 "could not allocate buffer dma tag\n");
2998 /* Create tag for Tx mbufs. */
2999 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3000 txsegsz = BGE_TSOSEG_SZ;
3001 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3004 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3006 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3007 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3008 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3009 &sc->bge_cdata.bge_tx_mtag);
3012 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3016 /* Create tag for Rx mbufs. */
3017 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3018 rxmaxsegsz = MJUM9BYTES;
3020 rxmaxsegsz = MCLBYTES;
3021 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3022 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3023 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3026 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3030 /* Create DMA maps for RX buffers. */
3031 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3032 &sc->bge_cdata.bge_rx_std_sparemap);
3034 device_printf(sc->bge_dev,
3035 "can't create spare DMA map for RX\n");
3038 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3039 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3040 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3042 device_printf(sc->bge_dev,
3043 "can't create DMA map for RX\n");
3048 /* Create DMA maps for TX buffers. */
3049 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3050 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3051 &sc->bge_cdata.bge_tx_dmamap[i]);
3053 device_printf(sc->bge_dev,
3054 "can't create DMA map for TX\n");
3059 /* Create tags for jumbo RX buffers. */
3060 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3061 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3062 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3063 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3064 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3066 device_printf(sc->bge_dev,
3067 "could not allocate jumbo dma tag\n");
3070 /* Create DMA maps for jumbo RX buffers. */
3071 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3072 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3074 device_printf(sc->bge_dev,
3075 "can't create spare DMA map for jumbo RX\n");
3078 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3079 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3080 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3082 device_printf(sc->bge_dev,
3083 "can't create DMA map for jumbo RX\n");
3093 * Return true if this device has more than one port.
3096 bge_has_multiple_ports(struct bge_softc *sc)
3098 device_t dev = sc->bge_dev;
3099 u_int b, d, f, fscan, s;
3101 d = pci_get_domain(dev);
3102 b = pci_get_bus(dev);
3103 s = pci_get_slot(dev);
3104 f = pci_get_function(dev);
3105 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3106 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3112 * Return true if MSI can be used with this device.
3115 bge_can_use_msi(struct bge_softc *sc)
3117 int can_use_msi = 0;
3119 if (sc->bge_msi == 0)
3122 /* Disable MSI for polling(4). */
3123 #ifdef DEVICE_POLLING
3126 switch (sc->bge_asicrev) {
3127 case BGE_ASICREV_BCM5714_A0:
3128 case BGE_ASICREV_BCM5714:
3130 * Apparently, MSI doesn't work when these chips are
3131 * configured in single-port mode.
3133 if (bge_has_multiple_ports(sc))
3136 case BGE_ASICREV_BCM5750:
3137 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3138 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3142 if (BGE_IS_575X_PLUS(sc))
3145 return (can_use_msi);
3149 bge_mbox_reorder(struct bge_softc *sc)
3151 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3152 static const struct mbox_reorder {
3153 const uint16_t vendor;
3154 const uint16_t device;
3156 } mbox_reorder_lists[] = {
3157 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3159 devclass_t pci, pcib;
3163 pci = devclass_find("pci");
3164 pcib = devclass_find("pcib");
3166 bus = device_get_parent(dev);
3168 dev = device_get_parent(bus);
3169 bus = device_get_parent(dev);
3170 if (device_get_devclass(dev) != pcib)
3172 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3173 if (pci_get_vendor(dev) ==
3174 mbox_reorder_lists[i].vendor &&
3175 pci_get_device(dev) ==
3176 mbox_reorder_lists[i].device) {
3177 device_printf(sc->bge_dev,
3178 "enabling MBOX workaround for %s\n",
3179 mbox_reorder_lists[i].desc);
3183 if (device_get_devclass(bus) != pci)
3190 bge_devinfo(struct bge_softc *sc)
3194 device_printf(sc->bge_dev,
3195 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3196 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3197 if (sc->bge_flags & BGE_FLAG_PCIE)
3199 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3201 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3202 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3205 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3224 printf("%u MHz\n", clk);
3226 if (sc->bge_pcixcap != 0)
3227 printf("PCI on PCI-X ");
3230 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3231 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3235 if (cfg & BGE_PCISTATE_32BIT_BUS)
3236 printf("%u MHz; 32bit\n", clk);
3238 printf("%u MHz; 64bit\n", clk);
3243 bge_attach(device_t dev)
3246 struct bge_softc *sc;
3247 uint32_t hwcfg = 0, misccfg, pcistate;
3248 u_char eaddr[ETHER_ADDR_LEN];
3249 int capmask, error, msicount, reg, rid, trys;
3251 sc = device_get_softc(dev);
3254 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3255 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3256 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3259 * Map control/status registers.
3261 pci_enable_busmaster(dev);
3264 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3267 if (sc->bge_res == NULL) {
3268 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3273 /* Save various chip information. */
3274 sc->bge_func_addr = pci_get_function(dev);
3276 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
3277 BGE_PCIMISCCTL_ASICREV_SHIFT;
3278 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
3280 * Find the ASCI revision. Different chips use different
3283 switch (pci_get_device(dev)) {
3284 case BCOM_DEVICEID_BCM5717:
3285 case BCOM_DEVICEID_BCM5718:
3286 case BCOM_DEVICEID_BCM5719:
3287 case BCOM_DEVICEID_BCM5720:
3288 sc->bge_chipid = pci_read_config(dev,
3289 BGE_PCI_GEN2_PRODID_ASICREV, 4);
3291 case BCOM_DEVICEID_BCM57761:
3292 case BCOM_DEVICEID_BCM57762:
3293 case BCOM_DEVICEID_BCM57765:
3294 case BCOM_DEVICEID_BCM57766:
3295 case BCOM_DEVICEID_BCM57781:
3296 case BCOM_DEVICEID_BCM57785:
3297 case BCOM_DEVICEID_BCM57791:
3298 case BCOM_DEVICEID_BCM57795:
3299 sc->bge_chipid = pci_read_config(dev,
3300 BGE_PCI_GEN15_PRODID_ASICREV, 4);
3303 sc->bge_chipid = pci_read_config(dev,
3304 BGE_PCI_PRODID_ASICREV, 4);
3307 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3308 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3310 /* Set default PHY address. */
3311 sc->bge_phy_addr = 1;
3313 * PHY address mapping for various devices.
3315 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3316 * ---------+-------+-------+-------+-------+
3317 * BCM57XX | 1 | X | X | X |
3318 * BCM5704 | 1 | X | 1 | X |
3319 * BCM5717 | 1 | 8 | 2 | 9 |
3320 * BCM5719 | 1 | 8 | 2 | 9 |
3321 * BCM5720 | 1 | 8 | 2 | 9 |
3323 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3324 * ---------+-------+-------+-------+-------+
3325 * BCM57XX | X | X | X | X |
3326 * BCM5704 | X | X | X | X |
3327 * BCM5717 | X | X | X | X |
3328 * BCM5719 | 3 | 10 | 4 | 11 |
3329 * BCM5720 | X | X | X | X |
3331 * Other addresses may respond but they are not
3332 * IEEE compliant PHYs and should be ignored.
3334 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3335 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3336 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3337 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3338 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3339 BGE_SGDIGSTS_IS_SERDES)
3340 sc->bge_phy_addr = sc->bge_func_addr + 8;
3342 sc->bge_phy_addr = sc->bge_func_addr + 1;
3344 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3345 BGE_CPMU_PHY_STRAP_IS_SERDES)
3346 sc->bge_phy_addr = sc->bge_func_addr + 8;
3348 sc->bge_phy_addr = sc->bge_func_addr + 1;
3352 if (bge_has_eaddr(sc))
3353 sc->bge_flags |= BGE_FLAG_EADDR;
3355 /* Save chipset family. */
3356 switch (sc->bge_asicrev) {
3357 case BGE_ASICREV_BCM57765:
3358 case BGE_ASICREV_BCM57766:
3359 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3361 case BGE_ASICREV_BCM5717:
3362 case BGE_ASICREV_BCM5719:
3363 case BGE_ASICREV_BCM5720:
3364 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3365 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3366 BGE_FLAG_JUMBO_FRAME;
3367 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3368 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3369 /* Jumbo frame on BCM5719 A0 does not work. */
3370 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3373 case BGE_ASICREV_BCM5755:
3374 case BGE_ASICREV_BCM5761:
3375 case BGE_ASICREV_BCM5784:
3376 case BGE_ASICREV_BCM5785:
3377 case BGE_ASICREV_BCM5787:
3378 case BGE_ASICREV_BCM57780:
3379 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3382 case BGE_ASICREV_BCM5700:
3383 case BGE_ASICREV_BCM5701:
3384 case BGE_ASICREV_BCM5703:
3385 case BGE_ASICREV_BCM5704:
3386 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3388 case BGE_ASICREV_BCM5714_A0:
3389 case BGE_ASICREV_BCM5780:
3390 case BGE_ASICREV_BCM5714:
3391 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3393 case BGE_ASICREV_BCM5750:
3394 case BGE_ASICREV_BCM5752:
3395 case BGE_ASICREV_BCM5906:
3396 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3398 case BGE_ASICREV_BCM5705:
3399 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3403 /* Identify chips with APE processor. */
3404 switch (sc->bge_asicrev) {
3405 case BGE_ASICREV_BCM5717:
3406 case BGE_ASICREV_BCM5719:
3407 case BGE_ASICREV_BCM5720:
3408 case BGE_ASICREV_BCM5761:
3409 sc->bge_flags |= BGE_FLAG_APE;
3413 /* Chips with APE need BAR2 access for APE registers/memory. */
3414 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3416 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3418 if (sc->bge_res2 == NULL) {
3419 device_printf (sc->bge_dev,
3420 "couldn't map BAR2 memory\n");
3425 /* Enable APE register/memory access by host driver. */
3426 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3427 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3428 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3429 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3430 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3432 bge_ape_lock_init(sc);
3433 bge_ape_read_fw_ver(sc);
3436 /* Add SYSCTLs, requires the chipset family to be set. */
3437 bge_add_sysctls(sc);
3439 /* Identify the chips that use an CPMU. */
3440 if (BGE_IS_5717_PLUS(sc) ||
3441 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3442 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3443 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3444 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3445 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3446 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3447 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3449 sc->bge_mi_mode = BGE_MIMODE_BASE;
3450 /* Enable auto polling for BCM570[0-5]. */
3451 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3452 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3455 * All Broadcom controllers have 4GB boundary DMA bug.
3456 * Whenever an address crosses a multiple of the 4GB boundary
3457 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3458 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3459 * state machine will lockup and cause the device to hang.
3461 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3463 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3464 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3465 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3468 * BCM5719 cannot handle DMA requests for DMA segments that
3469 * have larger than 4KB in size. However the maximum DMA
3470 * segment size created in DMA tag is 4KB for TSO, so we
3471 * wouldn't encounter the issue here.
3473 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3474 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3476 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3477 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3478 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3479 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3480 sc->bge_flags |= BGE_FLAG_5788;
3483 capmask = BMSR_DEFCAPMASK;
3484 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3485 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3486 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3487 pci_get_vendor(dev) == BCOM_VENDORID &&
3488 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3489 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3490 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3491 (pci_get_vendor(dev) == BCOM_VENDORID &&
3492 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3493 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3494 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3495 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3496 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3497 /* These chips are 10/100 only. */
3498 capmask &= ~BMSR_EXTSTAT;
3499 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3503 * Some controllers seem to require a special firmware to use
3504 * TSO. But the firmware is not available to FreeBSD and Linux
3505 * claims that the TSO performed by the firmware is slower than
3506 * hardware based TSO. Moreover the firmware based TSO has one
3507 * known bug which can't handle TSO if ethernet header + IP/TCP
3508 * header is greater than 80 bytes. The workaround for the TSO
3509 * bug exist but it seems it's too expensive than not using
3510 * TSO at all. Some hardwares also have the TSO bug so limit
3511 * the TSO to the controllers that are not affected TSO issues
3512 * (e.g. 5755 or higher).
3514 if (BGE_IS_5717_PLUS(sc)) {
3515 /* BCM5717 requires different TSO configuration. */
3516 sc->bge_flags |= BGE_FLAG_TSO3;
3517 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3518 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3519 /* TSO on BCM5719 A0 does not work. */
3520 sc->bge_flags &= ~BGE_FLAG_TSO3;
3522 } else if (BGE_IS_5755_PLUS(sc)) {
3524 * BCM5754 and BCM5787 shares the same ASIC id so
3525 * explicit device id check is required.
3526 * Due to unknown reason TSO does not work on BCM5755M.
3528 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3529 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3530 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3531 sc->bge_flags |= BGE_FLAG_TSO;
3535 * Check if this is a PCI-X or PCI Express device.
3537 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3539 * Found a PCI Express capabilities register, this
3540 * must be a PCI Express device.
3542 sc->bge_flags |= BGE_FLAG_PCIE;
3543 sc->bge_expcap = reg;
3544 /* Extract supported maximum payload size. */
3545 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3546 PCIER_DEVICE_CAP, 2);
3547 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3548 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3549 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3550 sc->bge_expmrq = 2048;
3552 sc->bge_expmrq = 4096;
3553 pci_set_max_read_req(dev, sc->bge_expmrq);
3556 * Check if the device is in PCI-X Mode.
3557 * (This bit is not valid on PCI Express controllers.)
3559 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3560 sc->bge_pcixcap = reg;
3561 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3562 BGE_PCISTATE_PCI_BUSMODE) == 0)
3563 sc->bge_flags |= BGE_FLAG_PCIX;
3567 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3568 * not actually a MAC controller bug but an issue with the embedded
3569 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3571 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3572 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3574 * Some PCI-X bridges are known to trigger write reordering to
3575 * the mailbox registers. Typical phenomena is watchdog timeouts
3576 * caused by out-of-order TX completions. Enable workaround for
3577 * PCI-X devices that live behind these bridges.
3578 * Note, PCI-X controllers can run in PCI mode so we can't use
3579 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3581 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3582 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3584 * Allocate the interrupt, using MSI if possible. These devices
3585 * support 8 MSI messages, but only the first one is used in
3589 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3590 sc->bge_msicap = reg;
3591 if (bge_can_use_msi(sc)) {
3592 msicount = pci_msi_count(dev);
3597 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3599 sc->bge_flags |= BGE_FLAG_MSI;
3604 * All controllers except BCM5700 supports tagged status but
3605 * we use tagged status only for MSI case on BCM5717. Otherwise
3606 * MSI on BCM5717 does not work.
3608 #ifndef DEVICE_POLLING
3609 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3610 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3613 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3614 RF_SHAREABLE | RF_ACTIVE);
3616 if (sc->bge_irq == NULL) {
3617 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3624 sc->bge_asf_mode = 0;
3625 /* No ASF if APE present. */
3626 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3627 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3628 BGE_SRAM_DATA_SIG_MAGIC)) {
3629 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3631 sc->bge_asf_mode |= ASF_ENABLE;
3632 sc->bge_asf_mode |= ASF_STACKUP;
3633 if (BGE_IS_575X_PLUS(sc))
3634 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3640 bge_sig_pre_reset(sc, BGE_RESET_START);
3641 if (bge_reset(sc)) {
3642 device_printf(sc->bge_dev, "chip reset failed\n");
3647 bge_sig_legacy(sc, BGE_RESET_START);
3648 bge_sig_post_reset(sc, BGE_RESET_START);
3650 if (bge_chipinit(sc)) {
3651 device_printf(sc->bge_dev, "chip initialization failed\n");
3656 error = bge_get_eaddr(sc, eaddr);
3658 device_printf(sc->bge_dev,
3659 "failed to read station address\n");
3664 /* 5705 limits RX return ring to 512 entries. */
3665 if (BGE_IS_5717_PLUS(sc))
3666 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3667 else if (BGE_IS_5705_PLUS(sc))
3668 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3670 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3672 if (bge_dma_alloc(sc)) {
3673 device_printf(sc->bge_dev,
3674 "failed to allocate DMA resources\n");
3679 /* Set default tuneable values. */
3680 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3681 sc->bge_rx_coal_ticks = 150;
3682 sc->bge_tx_coal_ticks = 150;
3683 sc->bge_rx_max_coal_bds = 10;
3684 sc->bge_tx_max_coal_bds = 10;
3686 /* Initialize checksum features to use. */
3687 sc->bge_csum_features = BGE_CSUM_FEATURES;
3688 if (sc->bge_forced_udpcsum != 0)
3689 sc->bge_csum_features |= CSUM_UDP;
3691 /* Set up ifnet structure */
3692 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3694 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3699 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3700 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3701 ifp->if_ioctl = bge_ioctl;
3702 ifp->if_start = bge_start;
3703 ifp->if_init = bge_init;
3704 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3705 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3706 IFQ_SET_READY(&ifp->if_snd);
3707 ifp->if_hwassist = sc->bge_csum_features;
3708 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3710 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3711 ifp->if_hwassist |= CSUM_TSO;
3712 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3714 #ifdef IFCAP_VLAN_HWCSUM
3715 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3717 ifp->if_capenable = ifp->if_capabilities;
3718 #ifdef DEVICE_POLLING
3719 ifp->if_capabilities |= IFCAP_POLLING;
3723 * 5700 B0 chips do not support checksumming correctly due
3726 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3727 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3728 ifp->if_capenable &= ~IFCAP_HWCSUM;
3729 ifp->if_hwassist = 0;
3733 * Figure out what sort of media we have by checking the
3734 * hardware config word in the first 32k of NIC internal memory,
3735 * or fall back to examining the EEPROM if necessary.
3736 * Note: on some BCM5700 cards, this value appears to be unset.
3737 * If that's the case, we have to rely on identifying the NIC
3738 * by its PCI subsystem ID, as we do below for the SysKonnect
3741 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3742 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3743 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3744 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3745 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3747 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3751 hwcfg = ntohl(hwcfg);
3754 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3755 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3756 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3757 if (BGE_IS_5705_PLUS(sc)) {
3758 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3759 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3761 sc->bge_flags |= BGE_FLAG_TBI;
3764 /* Set various PHY bug flags. */
3765 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3766 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3767 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3768 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3769 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3770 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3771 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3772 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3773 if (pci_get_subvendor(dev) == DELL_VENDORID)
3774 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3775 if ((BGE_IS_5705_PLUS(sc)) &&
3776 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3777 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3778 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3779 !BGE_IS_5717_PLUS(sc)) {
3780 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3781 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3782 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3783 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3784 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3785 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3786 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3787 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3788 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3790 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3794 * Don't enable Ethernet@WireSpeed for the 5700 or the
3795 * 5705 A0 and A1 chips.
3797 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3798 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3799 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3800 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3801 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3803 if (sc->bge_flags & BGE_FLAG_TBI) {
3804 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3806 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3807 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3809 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3810 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3811 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3814 * Do transceiver setup and tell the firmware the
3815 * driver is down so we can try to get access the
3816 * probe if ASF is running. Retry a couple of times
3817 * if we get a conflict with the ASF firmware accessing
3821 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3823 bge_asf_driver_up(sc);
3825 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3826 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3830 device_printf(sc->bge_dev, "Try again\n");
3831 bge_miibus_writereg(sc->bge_dev,
3832 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3835 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3840 * Now tell the firmware we are going up after probing the PHY
3842 if (sc->bge_asf_mode & ASF_STACKUP)
3843 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3847 * When using the BCM5701 in PCI-X mode, data corruption has
3848 * been observed in the first few bytes of some received packets.
3849 * Aligning the packet buffer in memory eliminates the corruption.
3850 * Unfortunately, this misaligns the packet payloads. On platforms
3851 * which do not support unaligned accesses, we will realign the
3852 * payloads by copying the received packets.
3854 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3855 sc->bge_flags & BGE_FLAG_PCIX)
3856 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3859 * Call MI attach routine.
3861 ether_ifattach(ifp, eaddr);
3863 /* Tell upper layer we support long frames. */
3864 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3869 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3870 /* Take advantage of single-shot MSI. */
3871 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3872 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3873 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3874 taskqueue_thread_enqueue, &sc->bge_tq);
3875 if (sc->bge_tq == NULL) {
3876 device_printf(dev, "could not create taskqueue.\n");
3877 ether_ifdetach(ifp);
3881 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3882 device_get_nameunit(sc->bge_dev));
3883 error = bus_setup_intr(dev, sc->bge_irq,
3884 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3887 error = bus_setup_intr(dev, sc->bge_irq,
3888 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3892 ether_ifdetach(ifp);
3893 device_printf(sc->bge_dev, "couldn't set up irq\n");
3903 bge_detach(device_t dev)
3905 struct bge_softc *sc;
3908 sc = device_get_softc(dev);
3911 #ifdef DEVICE_POLLING
3912 if (ifp->if_capenable & IFCAP_POLLING)
3913 ether_poll_deregister(ifp);
3916 if (device_is_attached(dev)) {
3917 ether_ifdetach(ifp);
3921 callout_drain(&sc->bge_stat_ch);
3925 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3927 if (sc->bge_flags & BGE_FLAG_TBI) {
3928 ifmedia_removeall(&sc->bge_ifmedia);
3930 bus_generic_detach(dev);
3931 device_delete_child(dev, sc->bge_miibus);
3934 bge_release_resources(sc);
3940 bge_release_resources(struct bge_softc *sc)
3946 if (sc->bge_tq != NULL)
3947 taskqueue_free(sc->bge_tq);
3949 if (sc->bge_intrhand != NULL)
3950 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3952 if (sc->bge_irq != NULL)
3953 bus_release_resource(dev, SYS_RES_IRQ,
3954 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3956 if (sc->bge_flags & BGE_FLAG_MSI)
3957 pci_release_msi(dev);
3959 if (sc->bge_res != NULL)
3960 bus_release_resource(dev, SYS_RES_MEMORY,
3961 PCIR_BAR(0), sc->bge_res);
3963 if (sc->bge_res2 != NULL)
3964 bus_release_resource(dev, SYS_RES_MEMORY,
3965 PCIR_BAR(2), sc->bge_res2);
3967 if (sc->bge_ifp != NULL)
3968 if_free(sc->bge_ifp);
3972 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3973 BGE_LOCK_DESTROY(sc);
3977 bge_reset(struct bge_softc *sc)
3980 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
3981 void (*write_op)(struct bge_softc *, int, int);
3987 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
3988 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
3989 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
3990 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
3992 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3993 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3994 if (sc->bge_flags & BGE_FLAG_PCIE)
3995 write_op = bge_writemem_direct;
3997 write_op = bge_writemem_ind;
3999 write_op = bge_writereg_ind;
4001 /* Take APE lock when performing reset. */
4002 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4004 /* Save some important PCI state. */
4005 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4006 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4008 pci_write_config(dev, BGE_PCI_MISC_CTL,
4009 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4010 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4012 /* Disable fastboot on controllers that support it. */
4013 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4014 BGE_IS_5755_PLUS(sc)) {
4016 device_printf(dev, "Disabling fastboot\n");
4017 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4021 * Write the magic number to SRAM at offset 0xB50.
4022 * When firmware finishes its initialization it will
4023 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4025 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4027 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4029 /* XXX: Broadcom Linux driver. */
4030 if (sc->bge_flags & BGE_FLAG_PCIE) {
4031 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4032 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4033 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4034 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4036 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4037 /* Prevent PCIE link training during global reset */
4038 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4043 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4044 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4045 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4046 val | BGE_VCPU_STATUS_DRV_RESET);
4047 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4048 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4049 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4053 * Set GPHY Power Down Override to leave GPHY
4054 * powered up in D0 uninitialized.
4056 if (BGE_IS_5705_PLUS(sc) &&
4057 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4058 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4060 /* Issue global reset */
4061 write_op(sc, BGE_MISC_CFG, reset);
4063 if (sc->bge_flags & BGE_FLAG_PCIE)
4068 /* XXX: Broadcom Linux driver. */
4069 if (sc->bge_flags & BGE_FLAG_PCIE) {
4070 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4071 DELAY(500000); /* wait for link training to complete */
4072 val = pci_read_config(dev, 0xC4, 4);
4073 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4075 devctl = pci_read_config(dev,
4076 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4077 /* Clear enable no snoop and disable relaxed ordering. */
4078 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4079 PCIEM_CTL_NOSNOOP_ENABLE);
4080 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4082 pci_set_max_read_req(dev, sc->bge_expmrq);
4083 /* Clear error status. */
4084 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4085 PCIEM_STA_CORRECTABLE_ERROR |
4086 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4087 PCIEM_STA_UNSUPPORTED_REQ, 2);
4090 /* Reset some of the PCI state that got zapped by reset. */
4091 pci_write_config(dev, BGE_PCI_MISC_CTL,
4092 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4093 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4094 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4095 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4096 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4097 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4098 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4099 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4100 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4101 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4102 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4103 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4104 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4106 * Disable PCI-X relaxed ordering to ensure status block update
4107 * comes first then packet buffer DMA. Otherwise driver may
4108 * read stale status block.
4110 if (sc->bge_flags & BGE_FLAG_PCIX) {
4111 devctl = pci_read_config(dev,
4112 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4113 devctl &= ~PCIXM_COMMAND_ERO;
4114 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4115 devctl &= ~PCIXM_COMMAND_MAX_READ;
4116 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4117 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4118 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4119 PCIXM_COMMAND_MAX_READ);
4120 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4122 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4125 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4126 if (BGE_IS_5714_FAMILY(sc)) {
4127 /* This chip disables MSI on reset. */
4128 if (sc->bge_flags & BGE_FLAG_MSI) {
4129 val = pci_read_config(dev,
4130 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4131 pci_write_config(dev,
4132 sc->bge_msicap + PCIR_MSI_CTRL,
4133 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4134 val = CSR_READ_4(sc, BGE_MSI_MODE);
4135 CSR_WRITE_4(sc, BGE_MSI_MODE,
4136 val | BGE_MSIMODE_ENABLE);
4138 val = CSR_READ_4(sc, BGE_MARB_MODE);
4139 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4141 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4143 /* Fix up byte swapping. */
4144 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4146 val = CSR_READ_4(sc, BGE_MAC_MODE);
4147 val = (val & ~mac_mode_mask) | mac_mode;
4148 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4151 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4153 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4154 for (i = 0; i < BGE_TIMEOUT; i++) {
4155 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4156 if (val & BGE_VCPU_STATUS_INIT_DONE)
4160 if (i == BGE_TIMEOUT) {
4161 device_printf(dev, "reset timed out\n");
4166 * Poll until we see the 1's complement of the magic number.
4167 * This indicates that the firmware initialization is complete.
4168 * We expect this to fail if no chip containing the Ethernet
4169 * address is fitted though.
4171 for (i = 0; i < BGE_TIMEOUT; i++) {
4173 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4174 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4178 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4180 "firmware handshake timed out, found 0x%08x\n",
4182 /* BCM57765 A0 needs additional time before accessing. */
4183 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4184 DELAY(10 * 1000); /* XXX */
4188 * The 5704 in TBI mode apparently needs some special
4189 * adjustment to insure the SERDES drive level is set
4192 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4193 sc->bge_flags & BGE_FLAG_TBI) {
4194 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4195 val = (val & ~0xFFF) | 0x880;
4196 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4199 /* XXX: Broadcom Linux driver. */
4200 if (sc->bge_flags & BGE_FLAG_PCIE &&
4201 !BGE_IS_5717_PLUS(sc) &&
4202 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4203 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4204 /* Enable Data FIFO protection. */
4205 val = CSR_READ_4(sc, 0x7C00);
4206 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4209 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4210 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4211 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4216 static __inline void
4217 bge_rxreuse_std(struct bge_softc *sc, int i)
4219 struct bge_rx_bd *r;
4221 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4222 r->bge_flags = BGE_RXBDFLAG_END;
4223 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4225 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4228 static __inline void
4229 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4231 struct bge_extrx_bd *r;
4233 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4234 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4235 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4236 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4237 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4238 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4240 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4244 * Frame reception handling. This is called if there's a frame
4245 * on the receive return list.
4247 * Note: we have to be able to handle two possibilities here:
4248 * 1) the frame is from the jumbo receive ring
4249 * 2) the frame is from the standard receive ring
4253 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4256 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4259 rx_cons = sc->bge_rx_saved_considx;
4261 /* Nothing to do. */
4262 if (rx_cons == rx_prod)
4267 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4268 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4269 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4270 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4271 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4272 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4273 (MCLBYTES - ETHER_ALIGN))
4274 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4275 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4277 while (rx_cons != rx_prod) {
4278 struct bge_rx_bd *cur_rx;
4280 struct mbuf *m = NULL;
4281 uint16_t vlan_tag = 0;
4284 #ifdef DEVICE_POLLING
4285 if (ifp->if_capenable & IFCAP_POLLING) {
4286 if (sc->rxcycles <= 0)
4292 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4294 rxidx = cur_rx->bge_idx;
4295 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4297 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4298 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4300 vlan_tag = cur_rx->bge_vlan_tag;
4303 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4305 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4306 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4307 bge_rxreuse_jumbo(sc, rxidx);
4310 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4311 bge_rxreuse_jumbo(sc, rxidx);
4315 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4318 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4319 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4320 bge_rxreuse_std(sc, rxidx);
4323 if (bge_newbuf_std(sc, rxidx) != 0) {
4324 bge_rxreuse_std(sc, rxidx);
4328 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4332 #ifndef __NO_STRICT_ALIGNMENT
4334 * For architectures with strict alignment we must make sure
4335 * the payload is aligned.
4337 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4338 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4340 m->m_data += ETHER_ALIGN;
4343 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4344 m->m_pkthdr.rcvif = ifp;
4346 if (ifp->if_capenable & IFCAP_RXCSUM)
4347 bge_rxcsum(sc, cur_rx, m);
4350 * If we received a packet with a vlan tag,
4351 * attach that information to the packet.
4354 m->m_pkthdr.ether_vtag = vlan_tag;
4355 m->m_flags |= M_VLANTAG;
4360 (*ifp->if_input)(ifp, m);
4363 (*ifp->if_input)(ifp, m);
4366 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4370 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4371 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4373 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4374 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4377 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4378 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4380 sc->bge_rx_saved_considx = rx_cons;
4381 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4383 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4384 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4386 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4387 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4390 * This register wraps very quickly under heavy packet drops.
4391 * If you need correct statistics, you can enable this check.
4393 if (BGE_IS_5705_PLUS(sc))
4394 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4400 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4403 if (BGE_IS_5717_PLUS(sc)) {
4404 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4405 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4406 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4407 if ((cur_rx->bge_error_flag &
4408 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4409 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4411 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4412 m->m_pkthdr.csum_data =
4413 cur_rx->bge_tcp_udp_csum;
4414 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4419 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4420 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4421 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4422 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4424 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4425 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4426 m->m_pkthdr.csum_data =
4427 cur_rx->bge_tcp_udp_csum;
4428 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4435 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4437 struct bge_tx_bd *cur_tx;
4440 BGE_LOCK_ASSERT(sc);
4442 /* Nothing to do. */
4443 if (sc->bge_tx_saved_considx == tx_cons)
4448 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4449 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4451 * Go through our tx ring and free mbufs for those
4452 * frames that have been sent.
4454 while (sc->bge_tx_saved_considx != tx_cons) {
4457 idx = sc->bge_tx_saved_considx;
4458 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4459 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4461 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4462 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4463 sc->bge_cdata.bge_tx_dmamap[idx],
4464 BUS_DMASYNC_POSTWRITE);
4465 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4466 sc->bge_cdata.bge_tx_dmamap[idx]);
4467 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4468 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4471 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4474 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4475 if (sc->bge_txcnt == 0)
4479 #ifdef DEVICE_POLLING
4481 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4483 struct bge_softc *sc = ifp->if_softc;
4484 uint16_t rx_prod, tx_cons;
4485 uint32_t statusword;
4489 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4494 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4495 sc->bge_cdata.bge_status_map,
4496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4497 /* Fetch updates from the status block. */
4498 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4499 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4501 statusword = sc->bge_ldata.bge_status_block->bge_status;
4502 /* Clear the status so the next pass only sees the changes. */
4503 sc->bge_ldata.bge_status_block->bge_status = 0;
4505 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4506 sc->bge_cdata.bge_status_map,
4507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4509 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4510 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4513 if (cmd == POLL_AND_CHECK_STATUS)
4514 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4515 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4516 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4519 sc->rxcycles = count;
4520 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4521 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4525 bge_txeof(sc, tx_cons);
4526 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4527 bge_start_locked(ifp);
4532 #endif /* DEVICE_POLLING */
4535 bge_msi_intr(void *arg)
4537 struct bge_softc *sc;
4539 sc = (struct bge_softc *)arg;
4541 * This interrupt is not shared and controller already
4542 * disabled further interrupt.
4544 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4545 return (FILTER_HANDLED);
4549 bge_intr_task(void *arg, int pending)
4551 struct bge_softc *sc;
4553 uint32_t status, status_tag;
4554 uint16_t rx_prod, tx_cons;
4556 sc = (struct bge_softc *)arg;
4560 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4565 /* Get updated status block. */
4566 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4567 sc->bge_cdata.bge_status_map,
4568 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4570 /* Save producer/consumer indices. */
4571 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4572 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4573 status = sc->bge_ldata.bge_status_block->bge_status;
4574 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4575 /* Dirty the status flag. */
4576 sc->bge_ldata.bge_status_block->bge_status = 0;
4577 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4578 sc->bge_cdata.bge_status_map,
4579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4580 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4583 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4586 /* Let controller work. */
4587 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4589 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4590 sc->bge_rx_saved_considx != rx_prod) {
4591 /* Check RX return ring producer/consumer. */
4593 bge_rxeof(sc, rx_prod, 0);
4596 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4597 /* Check TX ring producer/consumer. */
4598 bge_txeof(sc, tx_cons);
4599 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4600 bge_start_locked(ifp);
4608 struct bge_softc *sc;
4610 uint32_t statusword;
4611 uint16_t rx_prod, tx_cons;
4619 #ifdef DEVICE_POLLING
4620 if (ifp->if_capenable & IFCAP_POLLING) {
4627 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4628 * disable interrupts by writing nonzero like we used to, since with
4629 * our current organization this just gives complications and
4630 * pessimizations for re-enabling interrupts. We used to have races
4631 * instead of the necessary complications. Disabling interrupts
4632 * would just reduce the chance of a status update while we are
4633 * running (by switching to the interrupt-mode coalescence
4634 * parameters), but this chance is already very low so it is more
4635 * efficient to get another interrupt than prevent it.
4637 * We do the ack first to ensure another interrupt if there is a
4638 * status update after the ack. We don't check for the status
4639 * changing later because it is more efficient to get another
4640 * interrupt than prevent it, not quite as above (not checking is
4641 * a smaller optimization than not toggling the interrupt enable,
4642 * since checking doesn't involve PCI accesses and toggling require
4643 * the status check). So toggling would probably be a pessimization
4644 * even with MSI. It would only be needed for using a task queue.
4646 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4649 * Do the mandatory PCI flush as well as get the link status.
4651 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4653 /* Make sure the descriptor ring indexes are coherent. */
4654 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4655 sc->bge_cdata.bge_status_map,
4656 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4657 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4658 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4659 sc->bge_ldata.bge_status_block->bge_status = 0;
4660 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4661 sc->bge_cdata.bge_status_map,
4662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4664 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4665 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4666 statusword || sc->bge_link_evt)
4669 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4670 /* Check RX return ring producer/consumer. */
4671 bge_rxeof(sc, rx_prod, 1);
4674 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4675 /* Check TX ring producer/consumer. */
4676 bge_txeof(sc, tx_cons);
4679 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4680 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4681 bge_start_locked(ifp);
4687 bge_asf_driver_up(struct bge_softc *sc)
4689 if (sc->bge_asf_mode & ASF_STACKUP) {
4690 /* Send ASF heartbeat aprox. every 2s */
4691 if (sc->bge_asf_count)
4692 sc->bge_asf_count --;
4694 sc->bge_asf_count = 2;
4695 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4696 BGE_FW_CMD_DRV_ALIVE);
4697 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4698 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4699 BGE_FW_HB_TIMEOUT_SEC);
4700 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4701 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4702 BGE_RX_CPU_DRV_EVENT);
4710 struct bge_softc *sc = xsc;
4711 struct mii_data *mii = NULL;
4713 BGE_LOCK_ASSERT(sc);
4715 /* Synchronize with possible callout reset/stop. */
4716 if (callout_pending(&sc->bge_stat_ch) ||
4717 !callout_active(&sc->bge_stat_ch))
4720 if (BGE_IS_5705_PLUS(sc))
4721 bge_stats_update_regs(sc);
4723 bge_stats_update(sc);
4725 /* XXX Add APE heartbeat check here? */
4727 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4728 mii = device_get_softc(sc->bge_miibus);
4730 * Do not touch PHY if we have link up. This could break
4731 * IPMI/ASF mode or produce extra input errors
4732 * (extra errors was reported for bcm5701 & bcm5704).
4738 * Since in TBI mode auto-polling can't be used we should poll
4739 * link status manually. Here we register pending link event
4740 * and trigger interrupt.
4742 #ifdef DEVICE_POLLING
4743 /* In polling mode we poll link state in bge_poll(). */
4744 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4748 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4749 sc->bge_flags & BGE_FLAG_5788)
4750 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4752 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4756 bge_asf_driver_up(sc);
4759 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4763 bge_stats_update_regs(struct bge_softc *sc)
4766 struct bge_mac_stats *stats;
4769 stats = &sc->bge_mac_stats;
4771 stats->ifHCOutOctets +=
4772 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4773 stats->etherStatsCollisions +=
4774 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4775 stats->outXonSent +=
4776 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4777 stats->outXoffSent +=
4778 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4779 stats->dot3StatsInternalMacTransmitErrors +=
4780 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4781 stats->dot3StatsSingleCollisionFrames +=
4782 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4783 stats->dot3StatsMultipleCollisionFrames +=
4784 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4785 stats->dot3StatsDeferredTransmissions +=
4786 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4787 stats->dot3StatsExcessiveCollisions +=
4788 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4789 stats->dot3StatsLateCollisions +=
4790 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4791 stats->ifHCOutUcastPkts +=
4792 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4793 stats->ifHCOutMulticastPkts +=
4794 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4795 stats->ifHCOutBroadcastPkts +=
4796 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4798 stats->ifHCInOctets +=
4799 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4800 stats->etherStatsFragments +=
4801 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4802 stats->ifHCInUcastPkts +=
4803 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4804 stats->ifHCInMulticastPkts +=
4805 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4806 stats->ifHCInBroadcastPkts +=
4807 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4808 stats->dot3StatsFCSErrors +=
4809 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4810 stats->dot3StatsAlignmentErrors +=
4811 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4812 stats->xonPauseFramesReceived +=
4813 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4814 stats->xoffPauseFramesReceived +=
4815 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4816 stats->macControlFramesReceived +=
4817 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4818 stats->xoffStateEntered +=
4819 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4820 stats->dot3StatsFramesTooLong +=
4821 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4822 stats->etherStatsJabbers +=
4823 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4824 stats->etherStatsUndersizePkts +=
4825 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4827 stats->FramesDroppedDueToFilters +=
4828 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4829 stats->DmaWriteQueueFull +=
4830 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4831 stats->DmaWriteHighPriQueueFull +=
4832 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4833 stats->NoMoreRxBDs +=
4834 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4837 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4838 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4839 * includes number of unwanted multicast frames. This comes
4840 * from silicon bug and known workaround to get rough(not
4841 * exact) counter is to enable interrupt on MBUF low water
4842 * attention. This can be accomplished by setting
4843 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4844 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4845 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4846 * However that change would generate more interrupts and
4847 * there are still possibilities of losing multiple frames
4848 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4849 * Given that the workaround still would not get correct
4850 * counter I don't think it's worth to implement it. So
4851 * ignore reading the counter on controllers that have the
4854 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4855 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4856 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4857 stats->InputDiscards +=
4858 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4859 stats->InputErrors +=
4860 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4861 stats->RecvThresholdHit +=
4862 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4864 ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4865 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4866 stats->InputErrors);
4870 bge_stats_clear_regs(struct bge_softc *sc)
4873 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4874 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4875 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4876 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4877 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4878 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4879 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4880 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4881 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4882 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4883 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4884 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4885 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4887 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4888 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4889 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4890 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4891 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4892 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4893 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4894 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4895 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4896 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4897 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4898 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4899 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4900 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4902 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4903 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4904 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4905 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4906 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4907 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4908 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4912 bge_stats_update(struct bge_softc *sc)
4916 uint32_t cnt; /* current register value */
4920 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4922 #define READ_STAT(sc, stats, stat) \
4923 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4925 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4926 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4927 sc->bge_tx_collisions = cnt;
4929 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4930 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
4931 sc->bge_rx_nobds = cnt;
4932 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4933 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
4934 sc->bge_rx_inerrs = cnt;
4935 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4936 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4937 sc->bge_rx_discards = cnt;
4939 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4940 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4941 sc->bge_tx_discards = cnt;
4947 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4948 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4949 * but when such padded frames employ the bge IP/TCP checksum offload,
4950 * the hardware checksum assist gives incorrect results (possibly
4951 * from incorporating its own padding into the UDP/TCP checksum; who knows).
4952 * If we pad such runts with zeros, the onboard checksum comes out correct.
4955 bge_cksum_pad(struct mbuf *m)
4957 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4960 /* If there's only the packet-header and we can pad there, use it. */
4961 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4962 M_TRAILINGSPACE(m) >= padlen) {
4966 * Walk packet chain to find last mbuf. We will either
4967 * pad there, or append a new mbuf and pad it.
4969 for (last = m; last->m_next != NULL; last = last->m_next);
4970 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4971 /* Allocate new empty mbuf, pad it. Compact later. */
4974 MGET(n, M_NOWAIT, MT_DATA);
4983 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4984 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4985 last->m_len += padlen;
4986 m->m_pkthdr.len += padlen;
4991 static struct mbuf *
4992 bge_check_short_dma(struct mbuf *m)
4998 * If device receive two back-to-back send BDs with less than
4999 * or equal to 8 total bytes then the device may hang. The two
5000 * back-to-back send BDs must in the same frame for this failure
5001 * to occur. Scan mbuf chains and see whether two back-to-back
5002 * send BDs are there. If this is the case, allocate new mbuf
5003 * and copy the frame to workaround the silicon bug.
5005 for (n = m, found = 0; n != NULL; n = n->m_next) {
5016 n = m_defrag(m, M_NOWAIT);
5024 static struct mbuf *
5025 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5034 if (M_WRITABLE(m) == 0) {
5035 /* Get a writable copy. */
5036 n = m_dup(m, M_NOWAIT);
5042 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5045 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5046 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5047 m = m_pullup(m, poff + sizeof(struct tcphdr));
5050 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5051 m = m_pullup(m, poff + (tcp->th_off << 2));
5055 * It seems controller doesn't modify IP length and TCP pseudo
5056 * checksum. These checksum computed by upper stack should be 0.
5058 *mss = m->m_pkthdr.tso_segsz;
5059 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5061 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5062 /* Clear pseudo checksum computed by TCP stack. */
5063 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5066 * Broadcom controllers uses different descriptor format for
5067 * TSO depending on ASIC revision. Due to TSO-capable firmware
5068 * license issue and lower performance of firmware based TSO
5069 * we only support hardware based TSO.
5071 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5072 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5073 if (sc->bge_flags & BGE_FLAG_TSO3) {
5075 * For BCM5717 and newer controllers, hardware based TSO
5076 * uses the 14 lower bits of the bge_mss field to store the
5077 * MSS and the upper 2 bits to store the lowest 2 bits of
5078 * the IP/TCP header length. The upper 6 bits of the header
5079 * length are stored in the bge_flags[14:10,4] field. Jumbo
5080 * frames are supported.
5082 *mss |= ((hlen & 0x3) << 14);
5083 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5086 * For BCM5755 and newer controllers, hardware based TSO uses
5087 * the lower 11 bits to store the MSS and the upper 5 bits to
5088 * store the IP/TCP header length. Jumbo frames are not
5091 *mss |= (hlen << 11);
5097 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5098 * pointers to descriptors.
5101 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5103 bus_dma_segment_t segs[BGE_NSEG_NEW];
5105 struct bge_tx_bd *d;
5106 struct mbuf *m = *m_head;
5107 uint32_t idx = *txidx;
5108 uint16_t csum_flags, mss, vlan_tag;
5109 int nsegs, i, error;
5114 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5115 m->m_next != NULL) {
5116 *m_head = bge_check_short_dma(m);
5117 if (*m_head == NULL)
5121 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5122 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5123 if (*m_head == NULL)
5125 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5126 BGE_TXBDFLAG_CPU_POST_DMA;
5127 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5128 if (m->m_pkthdr.csum_flags & CSUM_IP)
5129 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5130 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5131 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5132 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5133 (error = bge_cksum_pad(m)) != 0) {
5141 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5142 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5143 m->m_pkthdr.len > ETHER_MAX_LEN)
5144 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5145 if (sc->bge_forced_collapse > 0 &&
5146 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5148 * Forcedly collapse mbuf chains to overcome hardware
5149 * limitation which only support a single outstanding
5150 * DMA read operation.
5152 if (sc->bge_forced_collapse == 1)
5153 m = m_defrag(m, M_NOWAIT);
5155 m = m_collapse(m, M_NOWAIT,
5156 sc->bge_forced_collapse);
5163 map = sc->bge_cdata.bge_tx_dmamap[idx];
5164 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5165 &nsegs, BUS_DMA_NOWAIT);
5166 if (error == EFBIG) {
5167 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5174 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5175 m, segs, &nsegs, BUS_DMA_NOWAIT);
5181 } else if (error != 0)
5184 /* Check if we have enough free send BDs. */
5185 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5186 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5190 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5192 if (m->m_flags & M_VLANTAG) {
5193 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5194 vlan_tag = m->m_pkthdr.ether_vtag;
5196 for (i = 0; ; i++) {
5197 d = &sc->bge_ldata.bge_tx_ring[idx];
5198 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5199 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5200 d->bge_len = segs[i].ds_len;
5201 d->bge_flags = csum_flags;
5202 d->bge_vlan_tag = vlan_tag;
5206 BGE_INC(idx, BGE_TX_RING_CNT);
5209 /* Mark the last segment as end of packet... */
5210 d->bge_flags |= BGE_TXBDFLAG_END;
5213 * Insure that the map for this transmission
5214 * is placed at the array index of the last descriptor
5217 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5218 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5219 sc->bge_cdata.bge_tx_chain[idx] = m;
5220 sc->bge_txcnt += nsegs;
5222 BGE_INC(idx, BGE_TX_RING_CNT);
5229 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5230 * to the mbuf data regions directly in the transmit descriptors.
5233 bge_start_locked(struct ifnet *ifp)
5235 struct bge_softc *sc;
5236 struct mbuf *m_head;
5241 BGE_LOCK_ASSERT(sc);
5243 if (!sc->bge_link ||
5244 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5248 prodidx = sc->bge_tx_prodidx;
5250 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5251 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5252 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5255 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5260 * Pack the data into the transmit ring. If we
5261 * don't have room, set the OACTIVE flag and wait
5262 * for the NIC to drain the ring.
5264 if (bge_encap(sc, &m_head, &prodidx)) {
5267 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5268 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5274 * If there's a BPF listener, bounce a copy of this frame
5277 #ifdef ETHER_BPF_MTAP
5278 ETHER_BPF_MTAP(ifp, m_head);
5280 BPF_MTAP(ifp, m_head);
5285 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5286 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5288 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5289 /* 5700 b2 errata */
5290 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5291 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5293 sc->bge_tx_prodidx = prodidx;
5296 * Set a timeout in case the chip goes out to lunch.
5303 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5304 * to the mbuf data regions directly in the transmit descriptors.
5307 bge_start(struct ifnet *ifp)
5309 struct bge_softc *sc;
5313 bge_start_locked(ifp);
5318 bge_init_locked(struct bge_softc *sc)
5324 BGE_LOCK_ASSERT(sc);
5328 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5331 /* Cancel pending I/O and flush buffers. */
5335 bge_sig_pre_reset(sc, BGE_RESET_START);
5337 bge_sig_legacy(sc, BGE_RESET_START);
5338 bge_sig_post_reset(sc, BGE_RESET_START);
5343 * Init the various state machines, ring
5344 * control blocks and firmware.
5346 if (bge_blockinit(sc)) {
5347 device_printf(sc->bge_dev, "initialization failure\n");
5354 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5355 ETHER_HDR_LEN + ETHER_CRC_LEN +
5356 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5358 /* Load our MAC address. */
5359 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5360 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5361 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5363 /* Program promiscuous mode. */
5366 /* Program multicast filter. */
5369 /* Program VLAN tag stripping. */
5372 /* Override UDP checksum offloading. */
5373 if (sc->bge_forced_udpcsum == 0)
5374 sc->bge_csum_features &= ~CSUM_UDP;
5376 sc->bge_csum_features |= CSUM_UDP;
5377 if (ifp->if_capabilities & IFCAP_TXCSUM &&
5378 ifp->if_capenable & IFCAP_TXCSUM) {
5379 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5380 ifp->if_hwassist |= sc->bge_csum_features;
5384 if (bge_init_rx_ring_std(sc) != 0) {
5385 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5391 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5392 * memory to insure that the chip has in fact read the first
5393 * entry of the ring.
5395 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5397 for (i = 0; i < 10; i++) {
5399 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5400 if (v == (MCLBYTES - ETHER_ALIGN))
5404 device_printf (sc->bge_dev,
5405 "5705 A0 chip failed to load RX ring\n");
5408 /* Init jumbo RX ring. */
5409 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5410 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5411 (MCLBYTES - ETHER_ALIGN)) {
5412 if (bge_init_rx_ring_jumbo(sc) != 0) {
5413 device_printf(sc->bge_dev,
5414 "no memory for jumbo Rx buffers.\n");
5420 /* Init our RX return ring index. */
5421 sc->bge_rx_saved_considx = 0;
5423 /* Init our RX/TX stat counters. */
5424 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5427 bge_init_tx_ring(sc);
5429 /* Enable TX MAC state machine lockup fix. */
5430 mode = CSR_READ_4(sc, BGE_TX_MODE);
5431 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5432 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5433 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
5434 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5435 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5436 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5438 /* Turn on transmitter. */
5439 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5442 /* Turn on receiver. */
5443 mode = CSR_READ_4(sc, BGE_RX_MODE);
5444 if (BGE_IS_5755_PLUS(sc))
5445 mode |= BGE_RXMODE_IPV6_ENABLE;
5446 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5450 * Set the number of good frames to receive after RX MBUF
5451 * Low Watermark has been reached. After the RX MAC receives
5452 * this number of frames, it will drop subsequent incoming
5453 * frames until the MBUF High Watermark is reached.
5455 if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
5456 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5458 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5460 /* Clear MAC statistics. */
5461 if (BGE_IS_5705_PLUS(sc))
5462 bge_stats_clear_regs(sc);
5464 /* Tell firmware we're alive. */
5465 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5467 #ifdef DEVICE_POLLING
5468 /* Disable interrupts if we are polling. */
5469 if (ifp->if_capenable & IFCAP_POLLING) {
5470 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5471 BGE_PCIMISCCTL_MASK_PCI_INTR);
5472 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5476 /* Enable host interrupts. */
5478 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5479 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5480 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5483 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5484 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5486 bge_ifmedia_upd_locked(ifp);
5488 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5494 struct bge_softc *sc = xsc;
5497 bge_init_locked(sc);
5502 * Set media options.
5505 bge_ifmedia_upd(struct ifnet *ifp)
5507 struct bge_softc *sc = ifp->if_softc;
5511 res = bge_ifmedia_upd_locked(ifp);
5518 bge_ifmedia_upd_locked(struct ifnet *ifp)
5520 struct bge_softc *sc = ifp->if_softc;
5521 struct mii_data *mii;
5522 struct mii_softc *miisc;
5523 struct ifmedia *ifm;
5525 BGE_LOCK_ASSERT(sc);
5527 ifm = &sc->bge_ifmedia;
5529 /* If this is a 1000baseX NIC, enable the TBI port. */
5530 if (sc->bge_flags & BGE_FLAG_TBI) {
5531 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5533 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5536 * The BCM5704 ASIC appears to have a special
5537 * mechanism for programming the autoneg
5538 * advertisement registers in TBI mode.
5540 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5542 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5543 if (sgdig & BGE_SGDIGSTS_DONE) {
5544 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5545 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5546 sgdig |= BGE_SGDIGCFG_AUTO |
5547 BGE_SGDIGCFG_PAUSE_CAP |
5548 BGE_SGDIGCFG_ASYM_PAUSE;
5549 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5550 sgdig | BGE_SGDIGCFG_SEND);
5552 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5557 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5558 BGE_CLRBIT(sc, BGE_MAC_MODE,
5559 BGE_MACMODE_HALF_DUPLEX);
5561 BGE_SETBIT(sc, BGE_MAC_MODE,
5562 BGE_MACMODE_HALF_DUPLEX);
5573 mii = device_get_softc(sc->bge_miibus);
5574 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5579 * Force an interrupt so that we will call bge_link_upd
5580 * if needed and clear any pending link state attention.
5581 * Without this we are not getting any further interrupts
5582 * for link state changes and thus will not UP the link and
5583 * not be able to send in bge_start_locked. The only
5584 * way to get things working was to receive a packet and
5586 * bge_tick should help for fiber cards and we might not
5587 * need to do this here if BGE_FLAG_TBI is set but as
5588 * we poll for fiber anyway it should not harm.
5590 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5591 sc->bge_flags & BGE_FLAG_5788)
5592 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5594 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5600 * Report current media status.
5603 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5605 struct bge_softc *sc = ifp->if_softc;
5606 struct mii_data *mii;
5610 if (sc->bge_flags & BGE_FLAG_TBI) {
5611 ifmr->ifm_status = IFM_AVALID;
5612 ifmr->ifm_active = IFM_ETHER;
5613 if (CSR_READ_4(sc, BGE_MAC_STS) &
5614 BGE_MACSTAT_TBI_PCS_SYNCHED)
5615 ifmr->ifm_status |= IFM_ACTIVE;
5617 ifmr->ifm_active |= IFM_NONE;
5621 ifmr->ifm_active |= IFM_1000_SX;
5622 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5623 ifmr->ifm_active |= IFM_HDX;
5625 ifmr->ifm_active |= IFM_FDX;
5630 mii = device_get_softc(sc->bge_miibus);
5632 ifmr->ifm_active = mii->mii_media_active;
5633 ifmr->ifm_status = mii->mii_media_status;
5639 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5641 struct bge_softc *sc = ifp->if_softc;
5642 struct ifreq *ifr = (struct ifreq *) data;
5643 struct mii_data *mii;
5644 int flags, mask, error = 0;
5648 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5649 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5650 if (ifr->ifr_mtu < ETHERMIN ||
5651 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5655 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5660 if (ifp->if_mtu != ifr->ifr_mtu) {
5661 ifp->if_mtu = ifr->ifr_mtu;
5662 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5663 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5664 bge_init_locked(sc);
5671 if (ifp->if_flags & IFF_UP) {
5673 * If only the state of the PROMISC flag changed,
5674 * then just use the 'set promisc mode' command
5675 * instead of reinitializing the entire NIC. Doing
5676 * a full re-init means reloading the firmware and
5677 * waiting for it to start up, which may take a
5678 * second or two. Similarly for ALLMULTI.
5680 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5681 flags = ifp->if_flags ^ sc->bge_if_flags;
5682 if (flags & IFF_PROMISC)
5684 if (flags & IFF_ALLMULTI)
5687 bge_init_locked(sc);
5689 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5693 sc->bge_if_flags = ifp->if_flags;
5699 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5708 if (sc->bge_flags & BGE_FLAG_TBI) {
5709 error = ifmedia_ioctl(ifp, ifr,
5710 &sc->bge_ifmedia, command);
5712 mii = device_get_softc(sc->bge_miibus);
5713 error = ifmedia_ioctl(ifp, ifr,
5714 &mii->mii_media, command);
5718 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5719 #ifdef DEVICE_POLLING
5720 if (mask & IFCAP_POLLING) {
5721 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5722 error = ether_poll_register(bge_poll, ifp);
5726 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5727 BGE_PCIMISCCTL_MASK_PCI_INTR);
5728 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5729 ifp->if_capenable |= IFCAP_POLLING;
5732 error = ether_poll_deregister(ifp);
5733 /* Enable interrupt even in error case */
5735 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5736 BGE_PCIMISCCTL_MASK_PCI_INTR);
5737 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5738 ifp->if_capenable &= ~IFCAP_POLLING;
5743 if ((mask & IFCAP_TXCSUM) != 0 &&
5744 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5745 ifp->if_capenable ^= IFCAP_TXCSUM;
5746 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5747 ifp->if_hwassist |= sc->bge_csum_features;
5749 ifp->if_hwassist &= ~sc->bge_csum_features;
5752 if ((mask & IFCAP_RXCSUM) != 0 &&
5753 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5754 ifp->if_capenable ^= IFCAP_RXCSUM;
5756 if ((mask & IFCAP_TSO4) != 0 &&
5757 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5758 ifp->if_capenable ^= IFCAP_TSO4;
5759 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5760 ifp->if_hwassist |= CSUM_TSO;
5762 ifp->if_hwassist &= ~CSUM_TSO;
5765 if (mask & IFCAP_VLAN_MTU) {
5766 ifp->if_capenable ^= IFCAP_VLAN_MTU;
5767 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5771 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5772 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5773 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5774 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5775 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5776 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5777 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5778 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5783 #ifdef VLAN_CAPABILITIES
5784 VLAN_CAPABILITIES(ifp);
5788 error = ether_ioctl(ifp, command, data);
5796 bge_watchdog(struct bge_softc *sc)
5800 BGE_LOCK_ASSERT(sc);
5802 if (sc->bge_timer == 0 || --sc->bge_timer)
5807 if_printf(ifp, "watchdog timeout -- resetting\n");
5809 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5810 bge_init_locked(sc);
5816 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5820 BGE_CLRBIT(sc, reg, bit);
5822 for (i = 0; i < BGE_TIMEOUT; i++) {
5823 if ((CSR_READ_4(sc, reg) & bit) == 0)
5830 * Stop the adapter and free any mbufs allocated to the
5834 bge_stop(struct bge_softc *sc)
5838 BGE_LOCK_ASSERT(sc);
5842 callout_stop(&sc->bge_stat_ch);
5844 /* Disable host interrupts. */
5845 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5846 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5849 * Tell firmware we're shutting down.
5852 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5855 * Disable all of the receiver blocks.
5857 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5858 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5859 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5860 if (BGE_IS_5700_FAMILY(sc))
5861 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5862 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5863 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5864 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5867 * Disable all of the transmit blocks.
5869 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5870 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5871 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5872 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5873 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5874 if (BGE_IS_5700_FAMILY(sc))
5875 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5876 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5879 * Shut down all of the memory managers and related
5882 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5883 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5884 if (BGE_IS_5700_FAMILY(sc))
5885 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5887 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5888 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5889 if (!(BGE_IS_5705_PLUS(sc))) {
5890 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5891 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5893 /* Update MAC statistics. */
5894 if (BGE_IS_5705_PLUS(sc))
5895 bge_stats_update_regs(sc);
5898 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
5899 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
5902 * Keep the ASF firmware running if up.
5904 if (sc->bge_asf_mode & ASF_STACKUP)
5905 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5907 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5909 /* Free the RX lists. */
5910 bge_free_rx_ring_std(sc);
5912 /* Free jumbo RX list. */
5913 if (BGE_IS_JUMBO_CAPABLE(sc))
5914 bge_free_rx_ring_jumbo(sc);
5916 /* Free TX buffers. */
5917 bge_free_tx_ring(sc);
5919 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5921 /* Clear MAC's link state (PHY may still have link UP). */
5922 if (bootverbose && sc->bge_link)
5923 if_printf(sc->bge_ifp, "link DOWN\n");
5926 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5930 * Stop all chip I/O so that the kernel's probe routines don't
5931 * get confused by errant DMAs when rebooting.
5934 bge_shutdown(device_t dev)
5936 struct bge_softc *sc;
5938 sc = device_get_softc(dev);
5947 bge_suspend(device_t dev)
5949 struct bge_softc *sc;
5951 sc = device_get_softc(dev);
5960 bge_resume(device_t dev)
5962 struct bge_softc *sc;
5965 sc = device_get_softc(dev);
5968 if (ifp->if_flags & IFF_UP) {
5969 bge_init_locked(sc);
5970 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5971 bge_start_locked(ifp);
5979 bge_link_upd(struct bge_softc *sc)
5981 struct mii_data *mii;
5982 uint32_t link, status;
5984 BGE_LOCK_ASSERT(sc);
5986 /* Clear 'pending link event' flag. */
5987 sc->bge_link_evt = 0;
5990 * Process link state changes.
5991 * Grrr. The link status word in the status block does
5992 * not work correctly on the BCM5700 rev AX and BX chips,
5993 * according to all available information. Hence, we have
5994 * to enable MII interrupts in order to properly obtain
5995 * async link changes. Unfortunately, this also means that
5996 * we have to read the MAC status register to detect link
5997 * changes, thereby adding an additional register access to
5998 * the interrupt handler.
6000 * XXX: perhaps link state detection procedure used for
6001 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6004 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6005 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6006 status = CSR_READ_4(sc, BGE_MAC_STS);
6007 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6008 mii = device_get_softc(sc->bge_miibus);
6010 if (!sc->bge_link &&
6011 mii->mii_media_status & IFM_ACTIVE &&
6012 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6015 if_printf(sc->bge_ifp, "link UP\n");
6016 } else if (sc->bge_link &&
6017 (!(mii->mii_media_status & IFM_ACTIVE) ||
6018 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6021 if_printf(sc->bge_ifp, "link DOWN\n");
6024 /* Clear the interrupt. */
6025 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6026 BGE_EVTENB_MI_INTERRUPT);
6027 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6029 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6030 BRGPHY_MII_IMR, BRGPHY_INTRS);
6035 if (sc->bge_flags & BGE_FLAG_TBI) {
6036 status = CSR_READ_4(sc, BGE_MAC_STS);
6037 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6038 if (!sc->bge_link) {
6040 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6041 BGE_CLRBIT(sc, BGE_MAC_MODE,
6042 BGE_MACMODE_TBI_SEND_CFGS);
6045 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6047 if_printf(sc->bge_ifp, "link UP\n");
6048 if_link_state_change(sc->bge_ifp,
6051 } else if (sc->bge_link) {
6054 if_printf(sc->bge_ifp, "link DOWN\n");
6055 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6057 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6059 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6060 * in status word always set. Workaround this bug by reading
6061 * PHY link status directly.
6063 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6065 if (link != sc->bge_link ||
6066 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6067 mii = device_get_softc(sc->bge_miibus);
6069 if (!sc->bge_link &&
6070 mii->mii_media_status & IFM_ACTIVE &&
6071 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6074 if_printf(sc->bge_ifp, "link UP\n");
6075 } else if (sc->bge_link &&
6076 (!(mii->mii_media_status & IFM_ACTIVE) ||
6077 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6080 if_printf(sc->bge_ifp, "link DOWN\n");
6085 * For controllers that call mii_tick, we have to poll
6088 mii = device_get_softc(sc->bge_miibus);
6090 bge_miibus_statchg(sc->bge_dev);
6093 /* Disable MAC attention when link is up. */
6094 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6095 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6096 BGE_MACSTAT_LINK_CHANGED);
6100 bge_add_sysctls(struct bge_softc *sc)
6102 struct sysctl_ctx_list *ctx;
6103 struct sysctl_oid_list *children;
6107 ctx = device_get_sysctl_ctx(sc->bge_dev);
6108 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6110 #ifdef BGE_REGISTER_DEBUG
6111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6112 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6113 "Debug Information");
6115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6116 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6117 "MAC Register Read");
6119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6120 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6121 "APE Register Read");
6123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6124 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6129 unit = device_get_unit(sc->bge_dev);
6131 * A common design characteristic for many Broadcom client controllers
6132 * is that they only support a single outstanding DMA read operation
6133 * on the PCIe bus. This means that it will take twice as long to fetch
6134 * a TX frame that is split into header and payload buffers as it does
6135 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6136 * these controllers, coalescing buffers to reduce the number of memory
6137 * reads is effective way to get maximum performance(about 940Mbps).
6138 * Without collapsing TX buffers the maximum TCP bulk transfer
6139 * performance is about 850Mbps. However forcing coalescing mbufs
6140 * consumes a lot of CPU cycles, so leave it off by default.
6142 sc->bge_forced_collapse = 0;
6143 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6144 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6145 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6146 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6147 "Number of fragmented TX buffers of a frame allowed before "
6148 "forced collapsing");
6151 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6152 TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6153 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6154 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6157 * It seems all Broadcom controllers have a bug that can generate UDP
6158 * datagrams with checksum value 0 when TX UDP checksum offloading is
6159 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6160 * Even though the probability of generating such UDP datagrams is
6161 * low, I don't want to see FreeBSD boxes to inject such datagrams
6162 * into network so disable UDP checksum offloading by default. Users
6163 * still override this behavior by setting a sysctl variable,
6164 * dev.bge.0.forced_udpcsum.
6166 sc->bge_forced_udpcsum = 0;
6167 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6168 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6169 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6170 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6171 "Enable UDP checksum offloading even if controller can "
6172 "generate UDP checksum value 0");
6174 if (BGE_IS_5705_PLUS(sc))
6175 bge_add_sysctl_stats_regs(sc, ctx, children);
6177 bge_add_sysctl_stats(sc, ctx, children);
6180 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6181 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6182 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6186 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6187 struct sysctl_oid_list *parent)
6189 struct sysctl_oid *tree;
6190 struct sysctl_oid_list *children, *schildren;
6192 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6193 NULL, "BGE Statistics");
6194 schildren = children = SYSCTL_CHILDREN(tree);
6195 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6196 children, COSFramesDroppedDueToFilters,
6197 "FramesDroppedDueToFilters");
6198 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6199 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6200 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6201 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6202 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6203 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6204 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6205 children, ifInDiscards, "InputDiscards");
6206 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6207 children, ifInErrors, "InputErrors");
6208 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6209 children, nicRecvThresholdHit, "RecvThresholdHit");
6210 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6211 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6212 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6213 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6214 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6215 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6216 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6217 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6218 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6219 children, nicRingStatusUpdate, "RingStatusUpdate");
6220 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6221 children, nicInterrupts, "Interrupts");
6222 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6223 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6224 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6225 children, nicSendThresholdHit, "SendThresholdHit");
6227 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6228 NULL, "BGE RX Statistics");
6229 children = SYSCTL_CHILDREN(tree);
6230 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6231 children, rxstats.ifHCInOctets, "ifHCInOctets");
6232 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6233 children, rxstats.etherStatsFragments, "Fragments");
6234 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6235 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6236 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6237 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6238 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6239 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6240 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6241 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6242 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6243 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6244 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6245 children, rxstats.xoffPauseFramesReceived,
6246 "xoffPauseFramesReceived");
6247 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6248 children, rxstats.macControlFramesReceived,
6249 "ControlFramesReceived");
6250 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6251 children, rxstats.xoffStateEntered, "xoffStateEntered");
6252 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6253 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6254 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6255 children, rxstats.etherStatsJabbers, "Jabbers");
6256 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6257 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6258 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6259 children, rxstats.inRangeLengthError, "inRangeLengthError");
6260 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6261 children, rxstats.outRangeLengthError, "outRangeLengthError");
6263 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6264 NULL, "BGE TX Statistics");
6265 children = SYSCTL_CHILDREN(tree);
6266 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6267 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6268 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6269 children, txstats.etherStatsCollisions, "Collisions");
6270 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6271 children, txstats.outXonSent, "XonSent");
6272 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6273 children, txstats.outXoffSent, "XoffSent");
6274 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6275 children, txstats.flowControlDone, "flowControlDone");
6276 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6277 children, txstats.dot3StatsInternalMacTransmitErrors,
6278 "InternalMacTransmitErrors");
6279 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6280 children, txstats.dot3StatsSingleCollisionFrames,
6281 "SingleCollisionFrames");
6282 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6283 children, txstats.dot3StatsMultipleCollisionFrames,
6284 "MultipleCollisionFrames");
6285 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6286 children, txstats.dot3StatsDeferredTransmissions,
6287 "DeferredTransmissions");
6288 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6289 children, txstats.dot3StatsExcessiveCollisions,
6290 "ExcessiveCollisions");
6291 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6292 children, txstats.dot3StatsLateCollisions,
6294 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6295 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6296 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6297 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6298 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6299 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6300 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6301 children, txstats.dot3StatsCarrierSenseErrors,
6302 "CarrierSenseErrors");
6303 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6304 children, txstats.ifOutDiscards, "Discards");
6305 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6306 children, txstats.ifOutErrors, "Errors");
6309 #undef BGE_SYSCTL_STAT
6311 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6312 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6315 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6316 struct sysctl_oid_list *parent)
6318 struct sysctl_oid *tree;
6319 struct sysctl_oid_list *child, *schild;
6320 struct bge_mac_stats *stats;
6322 stats = &sc->bge_mac_stats;
6323 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6324 NULL, "BGE Statistics");
6325 schild = child = SYSCTL_CHILDREN(tree);
6326 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6327 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6328 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6329 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6330 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6331 &stats->DmaWriteHighPriQueueFull,
6332 "NIC DMA Write High Priority Queue Full");
6333 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6334 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6335 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6336 &stats->InputDiscards, "Discarded Input Frames");
6337 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6338 &stats->InputErrors, "Input Errors");
6339 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6340 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6342 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6343 NULL, "BGE RX Statistics");
6344 child = SYSCTL_CHILDREN(tree);
6345 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6346 &stats->ifHCInOctets, "Inbound Octets");
6347 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6348 &stats->etherStatsFragments, "Fragments");
6349 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6350 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6351 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6352 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6353 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6354 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6355 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6356 &stats->dot3StatsFCSErrors, "FCS Errors");
6357 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6358 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6359 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6360 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6361 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6362 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6363 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6364 &stats->macControlFramesReceived, "MAC Control Frames Received");
6365 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6366 &stats->xoffStateEntered, "XOFF State Entered");
6367 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6368 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6369 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6370 &stats->etherStatsJabbers, "Jabbers");
6371 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6372 &stats->etherStatsUndersizePkts, "Undersized Packets");
6374 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6375 NULL, "BGE TX Statistics");
6376 child = SYSCTL_CHILDREN(tree);
6377 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6378 &stats->ifHCOutOctets, "Outbound Octets");
6379 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6380 &stats->etherStatsCollisions, "TX Collisions");
6381 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6382 &stats->outXonSent, "XON Sent");
6383 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6384 &stats->outXoffSent, "XOFF Sent");
6385 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6386 &stats->dot3StatsInternalMacTransmitErrors,
6387 "Internal MAC TX Errors");
6388 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6389 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6390 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6391 &stats->dot3StatsMultipleCollisionFrames,
6392 "Multiple Collision Frames");
6393 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6394 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6395 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6396 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6397 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6398 &stats->dot3StatsLateCollisions, "Late Collisions");
6399 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6400 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6401 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6402 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6403 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6404 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6407 #undef BGE_SYSCTL_STAT_ADD64
6410 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6412 struct bge_softc *sc;
6416 sc = (struct bge_softc *)arg1;
6418 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6419 offsetof(bge_hostaddr, bge_addr_lo));
6420 return (sysctl_handle_int(oidp, &result, 0, req));
6423 #ifdef BGE_REGISTER_DEBUG
6425 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6427 struct bge_softc *sc;
6429 int error, result, sbsz;
6433 error = sysctl_handle_int(oidp, &result, 0, req);
6434 if (error || (req->newptr == NULL))
6438 sc = (struct bge_softc *)arg1;
6440 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6441 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6442 sbsz = BGE_STATUS_BLK_SZ;
6445 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6446 printf("Status Block:\n");
6448 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6449 sc->bge_cdata.bge_status_map,
6450 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6451 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6453 for (j = 0; j < 8; j++)
6454 printf(" %04x", sbdata[i++]);
6458 printf("Registers:\n");
6459 for (i = 0x800; i < 0xA00; ) {
6461 for (j = 0; j < 8; j++) {
6462 printf(" %08x", CSR_READ_4(sc, i));
6469 printf("Hardware Flags:\n");
6470 if (BGE_IS_5717_PLUS(sc))
6471 printf(" - 5717 Plus\n");
6472 if (BGE_IS_5755_PLUS(sc))
6473 printf(" - 5755 Plus\n");
6474 if (BGE_IS_575X_PLUS(sc))
6475 printf(" - 575X Plus\n");
6476 if (BGE_IS_5705_PLUS(sc))
6477 printf(" - 5705 Plus\n");
6478 if (BGE_IS_5714_FAMILY(sc))
6479 printf(" - 5714 Family\n");
6480 if (BGE_IS_5700_FAMILY(sc))
6481 printf(" - 5700 Family\n");
6482 if (sc->bge_flags & BGE_FLAG_JUMBO)
6483 printf(" - Supports Jumbo Frames\n");
6484 if (sc->bge_flags & BGE_FLAG_PCIX)
6485 printf(" - PCI-X Bus\n");
6486 if (sc->bge_flags & BGE_FLAG_PCIE)
6487 printf(" - PCI Express Bus\n");
6488 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6489 printf(" - No 3 LEDs\n");
6490 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6491 printf(" - RX Alignment Bug\n");
6498 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6500 struct bge_softc *sc;
6506 error = sysctl_handle_int(oidp, &result, 0, req);
6507 if (error || (req->newptr == NULL))
6510 if (result < 0x8000) {
6511 sc = (struct bge_softc *)arg1;
6512 val = CSR_READ_4(sc, result);
6513 printf("reg 0x%06X = 0x%08X\n", result, val);
6520 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6522 struct bge_softc *sc;
6528 error = sysctl_handle_int(oidp, &result, 0, req);
6529 if (error || (req->newptr == NULL))
6532 if (result < 0x8000) {
6533 sc = (struct bge_softc *)arg1;
6534 val = APE_READ_4(sc, result);
6535 printf("reg 0x%06X = 0x%08X\n", result, val);
6542 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6544 struct bge_softc *sc;
6550 error = sysctl_handle_int(oidp, &result, 0, req);
6551 if (error || (req->newptr == NULL))
6554 if (result < 0x8000) {
6555 sc = (struct bge_softc *)arg1;
6556 val = bge_readmem_ind(sc, result);
6557 printf("mem 0x%06X = 0x%08X\n", result, val);
6565 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6568 if (sc->bge_flags & BGE_FLAG_EADDR)
6572 OF_getetheraddr(sc->bge_dev, ether_addr);
6579 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6583 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6584 if ((mac_addr >> 16) == 0x484b) {
6585 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6586 ether_addr[1] = (uint8_t)mac_addr;
6587 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6588 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6589 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6590 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6591 ether_addr[5] = (uint8_t)mac_addr;
6598 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6600 int mac_offset = BGE_EE_MAC_OFFSET;
6602 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6603 mac_offset = BGE_EE_MAC_OFFSET_5906;
6605 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6610 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6613 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6616 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6621 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6623 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6624 /* NOTE: Order is critical */
6627 bge_get_eaddr_nvram,
6628 bge_get_eaddr_eeprom,
6631 const bge_eaddr_fcn_t *func;
6633 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6634 if ((*func)(sc, eaddr) == 0)
6637 return (*func == NULL ? ENXIO : 0);