2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 #include "bxe_elink.h"
39 #include "ecore_mfw_req.h"
40 #include "ecore_fw_defs.h"
41 #include "ecore_hsi.h"
42 #include "ecore_reg.h"
45 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
46 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
47 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
48 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
49 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
51 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
52 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
53 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
54 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
55 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
56 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
57 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
58 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
59 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
60 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
61 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
62 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
63 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
64 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
65 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
66 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
67 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
69 #define MDIO_REG_BANK_RX0 0x80b0
70 #define MDIO_RX0_RX_STATUS 0x10
71 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
72 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
73 #define MDIO_RX0_RX_EQ_BOOST 0x1c
74 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
75 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
77 #define MDIO_REG_BANK_RX1 0x80c0
78 #define MDIO_RX1_RX_EQ_BOOST 0x1c
79 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
80 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
82 #define MDIO_REG_BANK_RX2 0x80d0
83 #define MDIO_RX2_RX_EQ_BOOST 0x1c
84 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
85 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
87 #define MDIO_REG_BANK_RX3 0x80e0
88 #define MDIO_RX3_RX_EQ_BOOST 0x1c
89 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
90 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
92 #define MDIO_REG_BANK_RX_ALL 0x80f0
93 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
94 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
95 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
97 #define MDIO_REG_BANK_TX0 0x8060
98 #define MDIO_TX0_TX_DRIVER 0x17
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
100 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
102 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
104 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
106 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
107 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
109 #define MDIO_REG_BANK_TX1 0x8070
110 #define MDIO_TX1_TX_DRIVER 0x17
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
112 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
114 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
116 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
118 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
119 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
121 #define MDIO_REG_BANK_TX2 0x8080
122 #define MDIO_TX2_TX_DRIVER 0x17
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
124 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
126 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
128 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
130 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
131 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
133 #define MDIO_REG_BANK_TX3 0x8090
134 #define MDIO_TX3_TX_DRIVER 0x17
135 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
136 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
137 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
138 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
139 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
140 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
141 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
142 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
143 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
145 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
146 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
148 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
149 #define MDIO_BLOCK1_LANE_CTRL0 0x15
150 #define MDIO_BLOCK1_LANE_CTRL1 0x16
151 #define MDIO_BLOCK1_LANE_CTRL2 0x17
152 #define MDIO_BLOCK1_LANE_PRBS 0x19
154 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
155 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
156 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
157 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
158 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
159 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
160 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
161 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
162 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
163 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
165 #define MDIO_REG_BANK_GP_STATUS 0x8120
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
189 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
190 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
191 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
192 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
193 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
194 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
195 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
198 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
199 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
200 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
201 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
202 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
203 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
204 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
206 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
210 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
211 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
213 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
214 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
215 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
216 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
222 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
223 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
224 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
225 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
226 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
227 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
228 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
229 #define MDIO_SERDES_DIGITAL_MISC1 0x18
230 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
231 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
232 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
233 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
234 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
235 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
241 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
242 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
243 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
244 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
245 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
246 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
247 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
249 #define MDIO_REG_BANK_OVER_1G 0x8320
250 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
251 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
252 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
253 #define MDIO_OVER_1G_UP1 0x19
254 #define MDIO_OVER_1G_UP1_2_5G 0x0001
255 #define MDIO_OVER_1G_UP1_5G 0x0002
256 #define MDIO_OVER_1G_UP1_6G 0x0004
257 #define MDIO_OVER_1G_UP1_10G 0x0010
258 #define MDIO_OVER_1G_UP1_10GH 0x0008
259 #define MDIO_OVER_1G_UP1_12G 0x0020
260 #define MDIO_OVER_1G_UP1_12_5G 0x0040
261 #define MDIO_OVER_1G_UP1_13G 0x0080
262 #define MDIO_OVER_1G_UP1_15G 0x0100
263 #define MDIO_OVER_1G_UP1_16G 0x0200
264 #define MDIO_OVER_1G_UP2 0x1A
265 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
266 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
267 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
268 #define MDIO_OVER_1G_UP3 0x1B
269 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
270 #define MDIO_OVER_1G_LP_UP1 0x1C
271 #define MDIO_OVER_1G_LP_UP2 0x1D
272 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
273 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
274 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
275 #define MDIO_OVER_1G_LP_UP3 0x1E
277 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
278 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
279 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
280 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
282 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
283 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
284 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
285 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
287 #define MDIO_REG_BANK_CL73_USERB0 0x8370
288 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
289 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
290 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
291 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
292 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
293 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
294 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
295 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
296 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
297 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
298 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
300 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
301 #define MDIO_AER_BLOCK_AER_REG 0x1E
303 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
304 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
305 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
306 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
307 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
308 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
309 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
310 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
311 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
312 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
313 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
314 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
315 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
316 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
320 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
322 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
327 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
328 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
329 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
331 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
332 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
333 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
334 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
335 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
336 Theotherbitsarereservedandshouldbezero*/
337 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
340 #define MDIO_PMA_DEVAD 0x1
342 #define MDIO_PMA_REG_CTRL 0x0
343 #define MDIO_PMA_REG_STATUS 0x1
344 #define MDIO_PMA_REG_10G_CTRL2 0x7
345 #define MDIO_PMA_REG_TX_DISABLE 0x0009
346 #define MDIO_PMA_REG_RX_SD 0xa
348 #define MDIO_PMA_REG_BCM_CTRL 0x0096
349 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
350 #define MDIO_PMA_LASI_RXCTRL 0x9000
351 #define MDIO_PMA_LASI_TXCTRL 0x9001
352 #define MDIO_PMA_LASI_CTRL 0x9002
353 #define MDIO_PMA_LASI_RXSTAT 0x9003
354 #define MDIO_PMA_LASI_TXSTAT 0x9004
355 #define MDIO_PMA_LASI_STAT 0x9005
356 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
357 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
358 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
359 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
360 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
361 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
362 #define MDIO_PMA_REG_GEN_CTRL 0xca10
363 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
364 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
365 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
366 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
367 #define MDIO_PMA_REG_ROM_VER1 0xca19
368 #define MDIO_PMA_REG_ROM_VER2 0xca1a
369 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
370 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
371 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
372 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
373 #define MDIO_PMA_REG_LRM_MODE 0xca3f
374 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
375 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
378 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
379 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
380 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
381 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
382 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
383 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
384 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
385 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
386 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
387 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
388 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
390 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
391 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
392 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
393 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
394 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
395 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
396 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
397 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
398 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
399 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
401 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
402 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
403 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
404 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
405 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
407 #define MDIO_PMA_REG_7101_RESET 0xc000
408 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
409 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
410 #define MDIO_PMA_REG_7101_VER1 0xc026
411 #define MDIO_PMA_REG_7101_VER2 0xc027
413 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
414 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
415 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
416 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
417 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
418 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
419 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
420 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
421 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
422 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
426 #define MDIO_WIS_DEVAD 0x2
428 #define MDIO_WIS_REG_LASI_CNTL 0x9002
429 #define MDIO_WIS_REG_LASI_STATUS 0x9005
431 #define MDIO_PCS_DEVAD 0x3
432 #define MDIO_PCS_REG_STATUS 0x0020
433 #define MDIO_PCS_REG_LASI_STATUS 0x9005
434 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
435 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
436 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
437 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
438 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
439 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
440 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
441 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
442 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
446 #define MDIO_XS_DEVAD 0x4
447 #define MDIO_XS_REG_STATUS 0x0001
448 #define MDIO_XS_PLL_SEQUENCER 0x8000
449 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
451 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
452 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
453 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
454 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
455 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
457 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
459 #define MDIO_AN_DEVAD 0x7
461 #define MDIO_AN_REG_CTRL 0x0000
462 #define MDIO_AN_REG_STATUS 0x0001
463 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
464 #define MDIO_AN_REG_ADV_PAUSE 0x0010
465 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
466 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
467 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
468 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
469 #define MDIO_AN_REG_ADV 0x0011
470 #define MDIO_AN_REG_ADV2 0x0012
471 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
472 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
473 #define MDIO_AN_REG_MASTER_STATUS 0x0021
474 #define MDIO_AN_REG_EEE_ADV 0x003c
475 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
477 #define MDIO_AN_REG_LINK_STATUS 0x8304
478 #define MDIO_AN_REG_CL37_CL73 0x8370
479 #define MDIO_AN_REG_CL37_AN 0xffe0
480 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
481 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
482 #define MDIO_AN_REG_1000T_STATUS 0xffea
484 #define MDIO_AN_REG_8073_2_5G 0x8329
485 #define MDIO_AN_REG_8073_BAM 0x8350
487 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
488 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
489 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
490 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
491 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
492 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
493 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
494 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
495 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
496 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
497 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
498 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
499 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
502 #define MDIO_CTL_DEVAD 0x1e
503 #define MDIO_CTL_REG_84823_MEDIA 0x401a
504 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
505 /* These pins configure the BCM84823 interface to MAC after reset. */
506 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
507 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
508 /* These pins configure the BCM84823 interface to Line after reset. */
509 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
510 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
511 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
512 /* When this pin is active high during reset, 10GBASE-T core is power
513 * down, When it is active low the 10GBASE-T is power up
515 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
516 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
517 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
518 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
519 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
520 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
521 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
522 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
523 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
524 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
525 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
526 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
529 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
530 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
531 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
532 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
533 #define MDIO_84833_SUPER_ISOLATE 0x8000
534 /* These are mailbox register set used by 84833. */
535 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
536 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
537 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
538 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
539 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
540 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
541 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
542 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
543 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
544 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
545 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
546 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
547 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
548 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
549 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
550 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
551 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
552 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
554 /* Mailbox command set used by 84833. */
555 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
556 #define PHY84833_CMD_GET_EEE_MODE 0x8008
557 #define PHY84833_CMD_SET_EEE_MODE 0x8009
558 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
559 /* Mailbox status set used by 84833. */
560 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
561 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
562 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
563 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
564 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
565 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
566 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
567 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
568 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
571 /* Warpcore clause 45 addressing */
572 #define MDIO_WC_DEVAD 0x3
573 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
574 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
575 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
576 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
577 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
578 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
579 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
580 #define MDIO_WC_REG_PCS_STATUS2 0x0021
581 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
582 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
583 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
584 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
585 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
586 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
587 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
588 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
589 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
590 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
591 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
592 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
593 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
594 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
595 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
596 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
597 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
598 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
599 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
600 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
601 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
602 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
603 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
604 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
605 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
606 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
607 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
608 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
609 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
610 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
611 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
612 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
613 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
614 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
615 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
616 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
617 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
618 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
619 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
620 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
621 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
622 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
623 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
624 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
625 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
626 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
627 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
628 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
629 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
630 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
631 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
632 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
633 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
634 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
635 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
636 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
637 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
638 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
639 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
640 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
641 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
642 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
643 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
644 #define MDIO_WC_REG_DSC_SMC 0x8213
645 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
646 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
647 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
648 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
649 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
650 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
651 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
652 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
653 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
654 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
655 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
656 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
657 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
658 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
659 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
660 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
661 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
662 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
663 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
664 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
665 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
666 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
667 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
668 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
669 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
670 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
671 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
672 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
673 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
674 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
675 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
676 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
677 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
678 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
679 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
680 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
681 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
682 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
683 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
684 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
685 #define MDIO_WC_REG_RX66_SCW0 0x83c2
686 #define MDIO_WC_REG_RX66_SCW1 0x83c3
687 #define MDIO_WC_REG_RX66_SCW2 0x83c4
688 #define MDIO_WC_REG_RX66_SCW3 0x83c5
689 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
690 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
691 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
692 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
693 #define MDIO_WC_REG_FX100_CTRL1 0x8400
694 #define MDIO_WC_REG_FX100_CTRL3 0x8402
695 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
696 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
697 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
698 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
699 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
700 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
701 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
702 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
703 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
704 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
705 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
706 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
707 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
708 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
710 #define MDIO_WC_REG_AERBLK_AER 0xffde
711 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
712 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
714 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
715 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
716 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
718 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
720 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
723 #define MDIO_REG_GPHY_MII_STATUS 0x1
724 #define MDIO_REG_GPHY_PHYID_LSB 0x3
725 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
726 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
727 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
728 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
729 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
730 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
731 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
732 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
733 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
734 #define MDIO_REG_GPHY_AUX_STATUS 0x19
735 #define MDIO_REG_INTR_STATUS 0x1a
736 #define MDIO_REG_INTR_MASK 0x1b
737 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
738 #define MDIO_REG_GPHY_SHADOW 0x1c
739 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
740 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
741 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
742 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
743 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
746 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
747 struct elink_params *params,
748 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
749 uint8_t *o_buf, uint8_t);
750 /********************************************************/
751 #define ELINK_ETH_HLEN 14
752 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
753 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
754 #define ELINK_ETH_MIN_PACKET_SIZE 60
755 #define ELINK_ETH_MAX_PACKET_SIZE 1500
756 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
757 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
758 #define WC_LANE_MAX 4
759 #define I2C_SWITCH_WIDTH 2
762 #define I2C_WA_RETRY_CNT 3
763 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
764 #define MCPR_IMC_COMMAND_READ_OP 1
765 #define MCPR_IMC_COMMAND_WRITE_OP 2
767 /* LED Blink rate that will achieve ~15.9Hz */
768 #define LED_BLINK_RATE_VAL_E3 354
769 #define LED_BLINK_RATE_VAL_E1X_E2 480
770 /***********************************************************/
771 /* Shortcut definitions */
772 /***********************************************************/
774 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
776 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
777 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
778 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
779 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
780 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
781 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
782 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
783 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
784 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
785 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
786 #define ELINK_NIG_MASK_MI_INT \
787 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
788 #define ELINK_NIG_MASK_XGXS0_LINK10G \
789 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
790 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
791 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
792 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
793 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
795 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
796 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
797 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
799 #define ELINK_XGXS_RESET_BITS \
800 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
801 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
802 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
803 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
804 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
806 #define ELINK_SERDES_RESET_BITS \
807 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
808 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
809 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
810 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
812 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
813 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
814 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
815 #define ELINK_AUTONEG_PARALLEL \
816 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
817 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
818 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
819 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
821 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
822 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
823 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
824 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
825 #define ELINK_GP_STATUS_SPEED_MASK \
826 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
827 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
828 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
829 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
830 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
831 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
832 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
833 #define ELINK_GP_STATUS_10G_HIG \
834 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
835 #define ELINK_GP_STATUS_10G_CX4 \
836 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
837 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
838 #define ELINK_GP_STATUS_10G_KX4 \
839 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
840 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
841 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
842 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
843 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
844 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
845 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
846 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
847 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
848 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
849 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
850 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
851 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
852 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
853 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
854 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
855 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
856 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
857 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
858 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
859 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
861 #define ELINK_LINK_UPDATE_MASK \
862 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
863 LINK_STATUS_LINK_UP | \
864 LINK_STATUS_PHYSICAL_LINK_FLAG | \
865 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
866 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
867 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
868 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
869 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
870 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
872 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
873 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
874 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
875 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
878 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
879 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
880 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
881 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
883 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
884 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
885 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
887 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
888 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
889 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
891 #define ELINK_EDC_MODE_LINEAR 0x0022
892 #define ELINK_EDC_MODE_LIMITING 0x0044
893 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
894 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
897 #define DCBX_INVALID_COS (0xFF)
899 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
900 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
901 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
902 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
903 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
905 #define ELINK_MAX_PACKET_SIZE (9700)
906 #define MAX_KR_LINK_RETRY 4
908 /**********************************************************/
910 /**********************************************************/
912 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
913 elink_cl45_write(_sc, _phy, \
914 (_phy)->def_md_devad, \
915 (_bank + (_addr & 0xf)), \
918 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
919 elink_cl45_read(_sc, _phy, \
920 (_phy)->def_md_devad, \
921 (_bank + (_addr & 0xf)), \
924 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
926 uint32_t val = REG_RD(sc, reg);
929 REG_WR(sc, reg, val);
933 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
935 uint32_t val = REG_RD(sc, reg);
938 REG_WR(sc, reg, val);
943 * elink_check_lfa - This function checks if link reinitialization is required,
944 * or link flap can be avoided.
946 * @params: link parameters
947 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
950 static int elink_check_lfa(struct elink_params *params)
952 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
953 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
954 uint32_t saved_val, req_val, eee_status;
955 struct bxe_softc *sc = params->sc;
958 REG_RD(sc, params->lfa_base +
959 offsetof(struct shmem_lfa, additional_config));
961 /* NOTE: must be first condition checked -
962 * to verify DCC bit is cleared in any case!
964 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
965 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n");
966 REG_WR(sc, params->lfa_base +
967 offsetof(struct shmem_lfa, additional_config),
968 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
969 return LFA_DCC_LFA_DISABLED;
972 /* Verify that link is up */
973 link_status = REG_RD(sc, params->shmem_base +
974 offsetof(struct shmem_region,
975 port_mb[params->port].link_status));
976 if (!(link_status & LINK_STATUS_LINK_UP))
977 return LFA_LINK_DOWN;
979 /* if loaded after BOOT from SAN, don't flap the link in any case and
980 * rely on link set by preboot driver
982 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
985 /* Verify that loopback mode is not set */
986 if (params->loopback_mode)
987 return LFA_LOOPBACK_ENABLED;
989 /* Verify that MFW supports LFA */
990 if (!params->lfa_base)
991 return LFA_MFW_IS_TOO_OLD;
993 if (params->num_phys == 3) {
995 lfa_mask = 0xffffffff;
1001 /* Compare Duplex */
1002 saved_val = REG_RD(sc, params->lfa_base +
1003 offsetof(struct shmem_lfa, req_duplex));
1004 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
1005 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1006 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n",
1007 (saved_val & lfa_mask), (req_val & lfa_mask));
1008 return LFA_DUPLEX_MISMATCH;
1010 /* Compare Flow Control */
1011 saved_val = REG_RD(sc, params->lfa_base +
1012 offsetof(struct shmem_lfa, req_flow_ctrl));
1013 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1014 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1015 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n",
1016 (saved_val & lfa_mask), (req_val & lfa_mask));
1017 return LFA_FLOW_CTRL_MISMATCH;
1019 /* Compare Link Speed */
1020 saved_val = REG_RD(sc, params->lfa_base +
1021 offsetof(struct shmem_lfa, req_line_speed));
1022 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1023 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1024 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n",
1025 (saved_val & lfa_mask), (req_val & lfa_mask));
1026 return LFA_LINK_SPEED_MISMATCH;
1029 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1030 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1031 offsetof(struct shmem_lfa,
1032 speed_cap_mask[cfg_idx]));
1034 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1035 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n",
1037 params->speed_cap_mask[cfg_idx]);
1038 return LFA_SPEED_CAP_MISMATCH;
1042 cur_req_fc_auto_adv =
1043 REG_RD(sc, params->lfa_base +
1044 offsetof(struct shmem_lfa, additional_config)) &
1045 REQ_FC_AUTO_ADV_MASK;
1047 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1048 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n",
1049 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1050 return LFA_FLOW_CTRL_MISMATCH;
1053 eee_status = REG_RD(sc, params->shmem2_base +
1054 offsetof(struct shmem2_region,
1055 eee_status[params->port]));
1057 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1058 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1059 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1060 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1061 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode,
1063 return LFA_EEE_MISMATCH;
1066 /* LFA conditions are met */
1069 /******************************************************************/
1070 /* EPIO/GPIO section */
1071 /******************************************************************/
1072 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en)
1074 uint32_t epio_mask, gp_oenable;
1077 if (epio_pin > 31) {
1078 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin);
1082 epio_mask = 1 << epio_pin;
1083 /* Set this EPIO to output */
1084 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1085 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1087 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1089 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en)
1091 uint32_t epio_mask, gp_output, gp_oenable;
1094 if (epio_pin > 31) {
1095 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin);
1098 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en);
1099 epio_mask = 1 << epio_pin;
1100 /* Set this EPIO to output */
1101 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1103 gp_output |= epio_mask;
1105 gp_output &= ~epio_mask;
1107 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1109 /* Set the value for this EPIO */
1110 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1111 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1114 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val)
1116 if (pin_cfg == PIN_CFG_NA)
1118 if (pin_cfg >= PIN_CFG_EPIO0) {
1119 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1121 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1122 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1123 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
1127 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val)
1129 if (pin_cfg == PIN_CFG_NA)
1130 return ELINK_STATUS_ERROR;
1131 if (pin_cfg >= PIN_CFG_EPIO0) {
1132 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1134 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1135 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1136 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1138 return ELINK_STATUS_OK;
1141 /******************************************************************/
1143 /******************************************************************/
1144 static void elink_ets_e2e3a0_disabled(struct elink_params *params)
1146 /* ETS disabled configuration*/
1147 struct bxe_softc *sc = params->sc;
1149 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n");
1151 /* mapping between entry priority to client number (0,1,2 -debug and
1152 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1154 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1155 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
1158 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1159 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1160 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1161 * COS0 entry, 4 - COS1 entry.
1162 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1163 * bit4 bit3 bit2 bit1 bit0
1164 * MCP and debug are strict
1167 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1168 /* defines which entries (clients) are subjected to WFQ arbitration */
1169 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1170 /* For strict priority entries defines the number of consecutive
1171 * slots for the highest priority.
1173 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1174 /* mapping between the CREDIT_WEIGHT registers and actual client
1177 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1178 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1179 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1181 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1182 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1183 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1184 /* ETS mode disable */
1185 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1186 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
1187 * weight for COS0/COS1.
1189 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1190 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1191 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
1192 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1193 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1194 /* Defines the number of consecutive slots for the strict priority */
1195 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1197 /******************************************************************************
1199 * Getting min_w_val will be set according to line speed .
1201 ******************************************************************************/
1202 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
1204 uint32_t min_w_val = 0;
1205 /* Calculate min_w_val.*/
1206 if (vars->link_up) {
1207 if (vars->line_speed == ELINK_SPEED_20000)
1208 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1210 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
1212 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1213 /* If the link isn't up (static configuration for example ) The
1214 * link will be according to 20GBPS.
1218 /******************************************************************************
1220 * Getting credit upper bound form min_w_val.
1222 ******************************************************************************/
1223 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
1225 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val),
1226 ELINK_MAX_PACKET_SIZE);
1227 return credit_upper_bound;
1229 /******************************************************************************
1231 * Set credit upper bound for NIG.
1233 ******************************************************************************/
1234 static void elink_ets_e3b0_set_credit_upper_bound_nig(
1235 const struct elink_params *params,
1236 const uint32_t min_w_val)
1238 struct bxe_softc *sc = params->sc;
1239 const uint8_t port = params->port;
1240 const uint32_t credit_upper_bound =
1241 elink_ets_get_credit_upper_bound(min_w_val);
1243 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1244 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
1245 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1246 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
1247 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1248 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
1249 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1250 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
1251 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1252 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
1253 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1254 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
1257 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1258 credit_upper_bound);
1259 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1260 credit_upper_bound);
1261 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1262 credit_upper_bound);
1265 /******************************************************************************
1267 * Will return the NIG ETS registers to init values.Except
1268 * credit_upper_bound.
1269 * That isn't used in this configuration (No WFQ is enabled) and will be
1270 * configured acording to spec
1272 ******************************************************************************/
1273 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
1274 const struct elink_vars *vars)
1276 struct bxe_softc *sc = params->sc;
1277 const uint8_t port = params->port;
1278 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
1279 /* Mapping between entry priority to client number (0,1,2 -debug and
1280 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
1281 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
1282 * reset value or init tool
1285 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1286 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1289 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1291 /* For strict priority entries defines the number of consecutive
1292 * slots for the highest priority.
1294 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1295 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1296 /* Mapping between the CREDIT_WEIGHT registers and actual client
1300 /*Port 1 has 6 COS*/
1301 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1302 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1304 /*Port 0 has 9 COS*/
1305 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1307 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1310 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1311 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1312 * COS0 entry, 4 - COS1 entry.
1313 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1314 * bit4 bit3 bit2 bit1 bit0
1315 * MCP and debug are strict
1318 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1320 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1321 /* defines which entries (clients) are subjected to WFQ arbitration */
1322 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1323 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1325 /* Please notice the register address are note continuous and a
1326 * for here is note appropriate.In 2 port mode port0 only COS0-5
1327 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
1328 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1329 * are never used for WFQ
1331 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1332 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
1333 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1334 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
1335 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1336 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
1337 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1338 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
1339 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1340 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
1341 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1342 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
1344 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1345 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1346 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1349 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
1351 /******************************************************************************
1353 * Set credit upper bound for PBF.
1355 ******************************************************************************/
1356 static void elink_ets_e3b0_set_credit_upper_bound_pbf(
1357 const struct elink_params *params,
1358 const uint32_t min_w_val)
1360 struct bxe_softc *sc = params->sc;
1361 const uint32_t credit_upper_bound =
1362 elink_ets_get_credit_upper_bound(min_w_val);
1363 const uint8_t port = params->port;
1364 uint32_t base_upper_bound = 0;
1365 uint8_t max_cos = 0;
1367 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1368 * port mode port1 has COS0-2 that can be used for WFQ.
1371 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
1372 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1374 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
1375 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1378 for (i = 0; i < max_cos; i++)
1379 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1382 /******************************************************************************
1384 * Will return the PBF ETS registers to init values.Except
1385 * credit_upper_bound.
1386 * That isn't used in this configuration (No WFQ is enabled) and will be
1387 * configured acording to spec
1389 ******************************************************************************/
1390 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
1392 struct bxe_softc *sc = params->sc;
1393 const uint8_t port = params->port;
1394 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1396 uint32_t base_weight = 0;
1397 uint8_t max_cos = 0;
1399 /* Mapping between entry priority to client number 0 - COS0
1400 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
1401 * TODO_ETS - Should be done by reset value or init tool
1404 /* 0x688 (|011|0 10|00 1|000) */
1405 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1407 /* (10 1|100 |011|0 10|00 1|000) */
1408 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1410 /* TODO_ETS - Should be done by reset value or init tool */
1412 /* 0x688 (|011|0 10|00 1|000)*/
1413 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1415 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
1416 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1418 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1419 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
1422 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1423 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
1425 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1426 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
1427 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1428 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1431 base_weight = PBF_REG_COS0_WEIGHT_P0;
1432 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1434 base_weight = PBF_REG_COS0_WEIGHT_P1;
1435 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1438 for (i = 0; i < max_cos; i++)
1439 REG_WR(sc, base_weight + (0x4 * i), 0);
1441 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1443 /******************************************************************************
1445 * E3B0 disable will return basicly the values to init values.
1447 ******************************************************************************/
1448 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
1449 const struct elink_vars *vars)
1451 struct bxe_softc *sc = params->sc;
1453 if (!CHIP_IS_E3B0(sc)) {
1455 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1456 return ELINK_STATUS_ERROR;
1459 elink_ets_e3b0_nig_disabled(params, vars);
1461 elink_ets_e3b0_pbf_disabled(params);
1463 return ELINK_STATUS_OK;
1466 /******************************************************************************
1468 * Disable will return basicly the values to init values.
1470 ******************************************************************************/
1471 elink_status_t elink_ets_disabled(struct elink_params *params,
1472 struct elink_vars *vars)
1474 struct bxe_softc *sc = params->sc;
1475 elink_status_t elink_status = ELINK_STATUS_OK;
1477 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc)))
1478 elink_ets_e2e3a0_disabled(params);
1479 else if (CHIP_IS_E3B0(sc))
1480 elink_status = elink_ets_e3b0_disabled(params, vars);
1482 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n");
1483 return ELINK_STATUS_ERROR;
1486 return elink_status;
1489 /******************************************************************************
1491 * Set the COS mappimg to SP and BW until this point all the COS are not
1493 ******************************************************************************/
1494 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
1495 const struct elink_ets_params *ets_params,
1496 const uint8_t cos_sp_bitmap,
1497 const uint8_t cos_bw_bitmap)
1499 struct bxe_softc *sc = params->sc;
1500 const uint8_t port = params->port;
1501 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
1502 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
1503 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
1504 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
1506 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1507 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
1509 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1510 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
1512 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1513 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1514 nig_cli_subject2wfq_bitmap);
1516 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1517 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
1518 pbf_cli_subject2wfq_bitmap);
1520 return ELINK_STATUS_OK;
1523 /******************************************************************************
1525 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1526 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1527 ******************************************************************************/
1528 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc,
1529 const uint8_t cos_entry,
1530 const uint32_t min_w_val_nig,
1531 const uint32_t min_w_val_pbf,
1532 const uint16_t total_bw,
1536 uint32_t nig_reg_adress_crd_weight = 0;
1537 uint32_t pbf_reg_adress_crd_weight = 0;
1538 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
1539 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
1540 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
1542 switch (cos_entry) {
1544 nig_reg_adress_crd_weight =
1545 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1546 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
1547 pbf_reg_adress_crd_weight = (port) ?
1548 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
1551 nig_reg_adress_crd_weight = (port) ?
1552 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1553 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
1554 pbf_reg_adress_crd_weight = (port) ?
1555 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
1558 nig_reg_adress_crd_weight = (port) ?
1559 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1560 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
1562 pbf_reg_adress_crd_weight = (port) ?
1563 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
1567 return ELINK_STATUS_ERROR;
1568 nig_reg_adress_crd_weight =
1569 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
1570 pbf_reg_adress_crd_weight =
1571 PBF_REG_COS3_WEIGHT_P0;
1575 return ELINK_STATUS_ERROR;
1576 nig_reg_adress_crd_weight =
1577 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
1578 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
1582 return ELINK_STATUS_ERROR;
1583 nig_reg_adress_crd_weight =
1584 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
1585 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
1589 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1591 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1593 return ELINK_STATUS_OK;
1595 /******************************************************************************
1597 * Calculate the total BW.A value of 0 isn't legal.
1599 ******************************************************************************/
1600 static elink_status_t elink_ets_e3b0_get_total_bw(
1601 const struct elink_params *params,
1602 struct elink_ets_params *ets_params,
1605 struct bxe_softc *sc = params->sc;
1606 uint8_t cos_idx = 0;
1607 uint8_t is_bw_cos_exist = 0;
1610 /* Calculate total BW requested */
1611 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
1612 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
1613 is_bw_cos_exist = 1;
1614 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
1615 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
1617 /* This is to prevent a state when ramrods
1620 ets_params->cos[cos_idx].params.bw_params.bw
1624 ets_params->cos[cos_idx].params.bw_params.bw;
1628 /* Check total BW is valid */
1629 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
1630 if (*total_bw == 0) {
1632 "elink_ets_E3B0_config total BW shouldn't be 0\n");
1633 return ELINK_STATUS_ERROR;
1636 "elink_ets_E3B0_config total BW should be 100\n");
1637 /* We can handle a case whre the BW isn't 100 this can happen
1638 * if the TC are joined.
1641 return ELINK_STATUS_OK;
1644 /******************************************************************************
1646 * Invalidate all the sp_pri_to_cos.
1648 ******************************************************************************/
1649 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
1652 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
1653 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
1655 /******************************************************************************
1657 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1658 * according to sp_pri_to_cos.
1660 ******************************************************************************/
1661 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
1662 uint8_t *sp_pri_to_cos, const uint8_t pri,
1663 const uint8_t cos_entry)
1665 struct bxe_softc *sc = params->sc;
1666 const uint8_t port = params->port;
1667 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1668 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1670 if (pri >= max_num_of_cos) {
1671 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1672 "parameter Illegal strict priority\n");
1673 return ELINK_STATUS_ERROR;
1676 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
1677 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1678 "parameter There can't be two COS's with "
1679 "the same strict pri\n");
1680 return ELINK_STATUS_ERROR;
1683 sp_pri_to_cos[pri] = cos_entry;
1684 return ELINK_STATUS_OK;
1688 /******************************************************************************
1690 * Returns the correct value according to COS and priority in
1691 * the sp_pri_cli register.
1693 ******************************************************************************/
1694 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset,
1695 const uint8_t pri_set,
1696 const uint8_t pri_offset,
1697 const uint8_t entry_size)
1699 uint64_t pri_cli_nig = 0;
1700 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
1701 (pri_set + pri_offset));
1705 /******************************************************************************
1707 * Returns the correct value according to COS and priority in the
1708 * sp_pri_cli register for NIG.
1710 ******************************************************************************/
1711 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set)
1713 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1714 const uint8_t nig_cos_offset = 3;
1715 const uint8_t nig_pri_offset = 3;
1717 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1721 /******************************************************************************
1723 * Returns the correct value according to COS and priority in the
1724 * sp_pri_cli register for PBF.
1726 ******************************************************************************/
1727 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set)
1729 const uint8_t pbf_cos_offset = 0;
1730 const uint8_t pbf_pri_offset = 0;
1732 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1737 /******************************************************************************
1739 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1740 * according to sp_pri_to_cos.(which COS has higher priority)
1742 ******************************************************************************/
1743 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
1744 uint8_t *sp_pri_to_cos)
1746 struct bxe_softc *sc = params->sc;
1748 const uint8_t port = params->port;
1749 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1750 uint64_t pri_cli_nig = 0x210;
1751 uint32_t pri_cli_pbf = 0x0;
1752 uint8_t pri_set = 0;
1753 uint8_t pri_bitmask = 0;
1754 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1755 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1757 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
1759 /* Set all the strict priority first */
1760 for (i = 0; i < max_num_of_cos; i++) {
1761 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1762 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
1764 "elink_ets_e3b0_sp_set_pri_cli_reg "
1765 "invalid cos entry\n");
1766 return ELINK_STATUS_ERROR;
1769 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1770 sp_pri_to_cos[i], pri_set);
1772 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1773 sp_pri_to_cos[i], pri_set);
1774 pri_bitmask = 1 << sp_pri_to_cos[i];
1775 /* COS is used remove it from bitmap.*/
1776 if (!(pri_bitmask & cos_bit_to_set)) {
1778 "elink_ets_e3b0_sp_set_pri_cli_reg "
1779 "invalid There can't be two COS's with"
1780 " the same strict pri\n");
1781 return ELINK_STATUS_ERROR;
1783 cos_bit_to_set &= ~pri_bitmask;
1788 /* Set all the Non strict priority i= COS*/
1789 for (i = 0; i < max_num_of_cos; i++) {
1790 pri_bitmask = 1 << i;
1791 /* Check if COS was already used for SP */
1792 if (pri_bitmask & cos_bit_to_set) {
1793 /* COS wasn't used for SP */
1794 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1797 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1799 /* COS is used remove it from bitmap.*/
1800 cos_bit_to_set &= ~pri_bitmask;
1805 if (pri_set != max_num_of_cos) {
1806 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1807 "entries were set\n");
1808 return ELINK_STATUS_ERROR;
1812 /* Only 6 usable clients*/
1813 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1814 (uint32_t)pri_cli_nig);
1816 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1818 /* Only 9 usable clients*/
1819 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig);
1820 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);
1822 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1824 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1827 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1829 return ELINK_STATUS_OK;
1832 /******************************************************************************
1834 * Configure the COS to ETS according to BW and SP settings.
1835 ******************************************************************************/
1836 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
1837 const struct elink_vars *vars,
1838 struct elink_ets_params *ets_params)
1840 struct bxe_softc *sc = params->sc;
1841 elink_status_t elink_status = ELINK_STATUS_OK;
1842 const uint8_t port = params->port;
1843 uint16_t total_bw = 0;
1844 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
1845 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1846 uint8_t cos_bw_bitmap = 0;
1847 uint8_t cos_sp_bitmap = 0;
1848 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
1849 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1850 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1851 uint8_t cos_entry = 0;
1853 if (!CHIP_IS_E3B0(sc)) {
1855 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1856 return ELINK_STATUS_ERROR;
1859 if ((ets_params->num_of_cos > max_num_of_cos)) {
1860 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
1861 "isn't supported\n");
1862 return ELINK_STATUS_ERROR;
1865 /* Prepare sp strict priority parameters*/
1866 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1868 /* Prepare BW parameters*/
1869 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
1871 if (elink_status != ELINK_STATUS_OK) {
1873 "elink_ets_E3B0_config get_total_bw failed\n");
1874 return ELINK_STATUS_ERROR;
1877 /* Upper bound is set according to current link speed (min_w_val
1878 * should be the same for upper bound and COS credit val).
1880 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1881 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1884 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1885 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
1886 cos_bw_bitmap |= (1 << cos_entry);
1887 /* The function also sets the BW in HW(not the mappin
1890 elink_status = elink_ets_e3b0_set_cos_bw(
1891 sc, cos_entry, min_w_val_nig, min_w_val_pbf,
1893 ets_params->cos[cos_entry].params.bw_params.bw,
1895 } else if (elink_cos_state_strict ==
1896 ets_params->cos[cos_entry].state){
1897 cos_sp_bitmap |= (1 << cos_entry);
1899 elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
1902 ets_params->cos[cos_entry].params.sp_params.pri,
1907 "elink_ets_e3b0_config cos state not valid\n");
1908 return ELINK_STATUS_ERROR;
1910 if (elink_status != ELINK_STATUS_OK) {
1912 "elink_ets_e3b0_config set cos bw failed\n");
1913 return elink_status;
1917 /* Set SP register (which COS has higher priority) */
1918 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
1921 if (elink_status != ELINK_STATUS_OK) {
1923 "elink_ets_E3B0_config set_pri_cli_reg failed\n");
1924 return elink_status;
1927 /* Set client mapping of BW and strict */
1928 elink_status = elink_ets_e3b0_cli_map(params, ets_params,
1932 if (elink_status != ELINK_STATUS_OK) {
1933 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n");
1934 return elink_status;
1936 return ELINK_STATUS_OK;
1938 static void elink_ets_bw_limit_common(const struct elink_params *params)
1940 /* ETS disabled configuration */
1941 struct bxe_softc *sc = params->sc;
1942 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1943 /* Defines which entries (clients) are subjected to WFQ arbitration
1947 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1948 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1949 * client numbers (WEIGHT_0 does not actually have to represent
1951 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1952 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1954 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1956 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1957 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1958 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1959 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1961 /* ETS mode enabled*/
1962 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1964 /* Defines the number of consecutive slots for the strict priority */
1965 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1966 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1967 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1968 * entry, 4 - COS1 entry.
1969 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1970 * bit4 bit3 bit2 bit1 bit0
1971 * MCP and debug are strict
1973 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1975 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1976 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
1977 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1978 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
1979 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1982 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
1983 const uint32_t cos1_bw)
1985 /* ETS disabled configuration*/
1986 struct bxe_softc *sc = params->sc;
1987 const uint32_t total_bw = cos0_bw + cos1_bw;
1988 uint32_t cos0_credit_weight = 0;
1989 uint32_t cos1_credit_weight = 0;
1991 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1996 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n");
2000 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2002 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2005 elink_ets_bw_limit_common(params);
2007 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2008 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2010 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2011 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2014 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos)
2016 /* ETS disabled configuration*/
2017 struct bxe_softc *sc = params->sc;
2020 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n");
2021 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2022 * as strict. Bits 0,1,2 - debug and management entries,
2023 * 3 - COS0 entry, 4 - COS1 entry.
2024 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
2025 * bit4 bit3 bit2 bit1 bit0
2026 * MCP and debug are strict
2028 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2029 /* For strict priority entries defines the number of consecutive slots
2030 * for the highest priority.
2032 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2033 /* ETS mode disable */
2034 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2035 /* Defines the number of consecutive slots for the strict priority */
2036 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2038 /* Defines the number of consecutive slots for the strict priority */
2039 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2041 /* Mapping between entry priority to client number (0,1,2 -debug and
2042 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
2044 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
2045 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
2046 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
2048 val = (!strict_cos) ? 0x2318 : 0x22E0;
2049 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2051 return ELINK_STATUS_OK;
2054 /******************************************************************/
2056 /******************************************************************/
2057 static void elink_update_pfc_xmac(struct elink_params *params,
2058 struct elink_vars *vars,
2061 struct bxe_softc *sc = params->sc;
2063 uint32_t pause_val, pfc0_val, pfc1_val;
2065 /* XMAC base adrr */
2066 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2068 /* Initialize pause and pfc registers */
2069 pause_val = 0x18000;
2070 pfc0_val = 0xFFFF8000;
2073 /* No PFC support */
2074 if (!(params->feature_config_flags &
2075 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2077 /* RX flow control - Process pause frame in receive direction
2079 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2080 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
2082 /* TX flow control - Send pause packet when buffer is full */
2083 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2084 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
2085 } else {/* PFC support */
2086 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
2087 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
2088 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
2089 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
2090 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2091 /* Write pause and PFC registers */
2092 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2093 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2094 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2095 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2099 /* Write pause and PFC registers */
2100 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2101 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2102 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2105 /* Set MAC address for source TX Pause/PFC frames */
2106 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2107 ((params->mac_addr[2] << 24) |
2108 (params->mac_addr[3] << 16) |
2109 (params->mac_addr[4] << 8) |
2110 (params->mac_addr[5])));
2111 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2112 ((params->mac_addr[0] << 8) |
2113 (params->mac_addr[1])));
2119 static void elink_emac_get_pfc_stat(struct elink_params *params,
2120 uint32_t pfc_frames_sent[2],
2121 uint32_t pfc_frames_received[2])
2123 /* Read pfc statistic */
2124 struct bxe_softc *sc = params->sc;
2125 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2126 uint32_t val_xon = 0;
2127 uint32_t val_xoff = 0;
2129 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n");
2131 /* PFC received frames */
2132 val_xoff = REG_RD(sc, emac_base +
2133 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
2134 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
2135 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2136 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
2138 pfc_frames_received[0] = val_xon + val_xoff;
2140 /* PFC received sent */
2141 val_xoff = REG_RD(sc, emac_base +
2142 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
2143 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
2144 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2145 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
2147 pfc_frames_sent[0] = val_xon + val_xoff;
2150 /* Read pfc statistic*/
2151 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
2152 uint32_t pfc_frames_sent[2],
2153 uint32_t pfc_frames_received[2])
2155 /* Read pfc statistic */
2156 struct bxe_softc *sc = params->sc;
2158 ELINK_DEBUG_P0(sc, "pfc statistic\n");
2163 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
2164 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n");
2165 elink_emac_get_pfc_stat(params, pfc_frames_sent,
2166 pfc_frames_received);
2169 /******************************************************************/
2170 /* MAC/PBF section */
2171 /******************************************************************/
2172 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id,
2175 uint32_t new_mode, cur_mode;
2177 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
2178 * (a value of 49==0x31) and make sure that the AUTO poll is off
2180 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2182 if (USES_WARPCORE(sc))
2183 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2185 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2187 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
2188 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
2191 new_mode = cur_mode &
2192 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
2193 new_mode |= clc_cnt;
2194 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
2196 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",
2197 cur_mode, new_mode);
2198 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2202 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc,
2203 struct elink_params *params)
2206 /* Set mdio clock per phy */
2207 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
2209 elink_set_mdio_clk(sc, params->chip_id,
2210 params->phy[phy_index].mdio_ctrl);
2213 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc)
2215 uint32_t port4mode_ovwr_val;
2216 /* Check 4-port override enabled */
2217 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2218 if (port4mode_ovwr_val & (1<<0)) {
2219 /* Return 4-port mode override value */
2220 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
2222 /* Return 4-port mode from input pin */
2223 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2226 static void elink_emac_init(struct elink_params *params,
2227 struct elink_vars *vars)
2229 /* reset and unreset the emac core */
2230 struct bxe_softc *sc = params->sc;
2231 uint8_t port = params->port;
2232 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2236 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2237 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2239 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2242 /* init emac - use read-modify-write */
2243 /* self clear reset */
2244 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2245 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2249 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2250 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val);
2252 ELINK_DEBUG_P0(sc, "EMAC timeout!\n");
2256 } while (val & EMAC_MODE_RESET);
2258 elink_set_mdio_emac_per_phy(sc, params);
2259 /* Set mac address */
2260 val = ((params->mac_addr[0] << 8) |
2261 params->mac_addr[1]);
2262 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
2264 val = ((params->mac_addr[2] << 24) |
2265 (params->mac_addr[3] << 16) |
2266 (params->mac_addr[4] << 8) |
2267 params->mac_addr[5]);
2268 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
2271 static void elink_set_xumac_nig(struct elink_params *params,
2272 uint16_t tx_pause_en,
2275 struct bxe_softc *sc = params->sc;
2277 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2279 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2281 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2282 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
2285 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
2287 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2289 struct bxe_softc *sc = params->sc;
2290 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2291 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2293 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2295 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
2296 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2298 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
2299 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2300 /* Disable RX and TX */
2301 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2304 static void elink_umac_enable(struct elink_params *params,
2305 struct elink_vars *vars, uint8_t lb)
2308 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2309 struct bxe_softc *sc = params->sc;
2311 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2312 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2315 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2316 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2318 ELINK_DEBUG_P0(sc, "enabling UMAC\n");
2320 /* This register opens the gate for the UMAC despite its name */
2321 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2323 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
2324 UMAC_COMMAND_CONFIG_REG_PAD_EN |
2325 UMAC_COMMAND_CONFIG_REG_SW_RESET |
2326 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
2327 switch (vars->line_speed) {
2328 case ELINK_SPEED_10:
2331 case ELINK_SPEED_100:
2334 case ELINK_SPEED_1000:
2337 case ELINK_SPEED_2500:
2341 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n",
2345 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2346 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
2348 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2349 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
2351 if (vars->duplex == DUPLEX_HALF)
2352 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
2354 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2357 /* Configure UMAC for EEE */
2358 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2359 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n");
2360 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2361 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
2362 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2364 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2367 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
2368 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2369 ((params->mac_addr[2] << 24) |
2370 (params->mac_addr[3] << 16) |
2371 (params->mac_addr[4] << 8) |
2372 (params->mac_addr[5])));
2373 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2374 ((params->mac_addr[0] << 8) |
2375 (params->mac_addr[1])));
2377 /* Enable RX and TX */
2378 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
2379 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
2380 UMAC_COMMAND_CONFIG_REG_RX_ENA;
2381 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2384 /* Remove SW Reset */
2385 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
2387 /* Check loopback mode */
2389 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
2390 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2392 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
2393 * length used by the MAC receive logic to check frames.
2395 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2396 elink_set_xumac_nig(params,
2397 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2398 vars->mac_type = ELINK_MAC_TYPE_UMAC;
2402 /* Define the XMAC mode */
2403 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
2405 struct bxe_softc *sc = params->sc;
2406 uint32_t is_port4mode = elink_is_4_port_mode(sc);
2408 /* In 4-port mode, need to set the mode only once, so if XMAC is
2409 * already out of reset, it means the mode has already been set,
2410 * and it must not* reset the XMAC again, since it controls both
2414 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
2415 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
2416 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
2418 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2419 MISC_REGISTERS_RESET_REG_2_XMAC)) {
2421 "XMAC already out of reset in 4-port mode\n");
2426 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2427 MISC_REGISTERS_RESET_REG_2_XMAC);
2430 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2431 MISC_REGISTERS_RESET_REG_2_XMAC);
2433 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n");
2435 /* Set the number of ports on the system side to up to 2 */
2436 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2438 /* Set the number of ports on the Warp Core to 10G */
2439 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2441 /* Set the number of ports on the system side to 1 */
2442 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2443 if (max_speed == ELINK_SPEED_10000) {
2445 "Init XMAC to 10G x 1 port per path\n");
2446 /* Set the number of ports on the Warp Core to 10G */
2447 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2450 "Init XMAC to 20G x 2 ports per path\n");
2451 /* Set the number of ports on the Warp Core to 20G */
2452 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2456 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2457 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2460 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2461 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2465 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
2467 uint8_t port = params->port;
2468 struct bxe_softc *sc = params->sc;
2469 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2472 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2473 MISC_REGISTERS_RESET_REG_2_XMAC) {
2474 /* Send an indication to change the state in the NIG back to XON
2475 * Clearing this bit enables the next set of this bit to get
2478 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2479 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2480 (pfc_ctrl & ~(1<<1)));
2481 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2482 (pfc_ctrl | (1<<1)));
2483 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2484 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2486 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2488 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2489 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2493 static elink_status_t elink_xmac_enable(struct elink_params *params,
2494 struct elink_vars *vars, uint8_t lb)
2496 uint32_t val, xmac_base;
2497 struct bxe_softc *sc = params->sc;
2498 ELINK_DEBUG_P0(sc, "enabling XMAC\n");
2500 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2502 elink_xmac_init(params, vars->line_speed);
2504 /* This register determines on which events the MAC will assert
2505 * error on the i/f to the NIG along w/ EOP.
2508 /* This register tells the NIG whether to send traffic to UMAC
2511 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2513 /* When XMAC is in XLGMII mode, disable sending idles for fault
2516 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2517 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2518 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
2519 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
2520 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2521 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2522 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
2523 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
2525 /* Set Max packet size */
2526 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2528 /* CRC append for Tx packets */
2529 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2532 elink_update_pfc_xmac(params, vars, 0);
2534 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2535 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n");
2536 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2537 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2539 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2542 /* Enable TX and RX */
2543 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
2545 /* Set MAC in XLGMII mode for dual-mode */
2546 if ((vars->line_speed == ELINK_SPEED_20000) &&
2547 (params->phy[ELINK_INT_PHY].supported &
2548 ELINK_SUPPORTED_20000baseKR2_Full))
2549 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
2551 /* Check loopback mode */
2553 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
2554 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2555 elink_set_xumac_nig(params,
2556 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2558 vars->mac_type = ELINK_MAC_TYPE_XMAC;
2560 return ELINK_STATUS_OK;
2563 static elink_status_t elink_emac_enable(struct elink_params *params,
2564 struct elink_vars *vars, uint8_t lb)
2566 struct bxe_softc *sc = params->sc;
2567 uint8_t port = params->port;
2568 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2571 ELINK_DEBUG_P0(sc, "enabling EMAC\n");
2574 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2575 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2577 /* enable emac and not bmac */
2578 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2580 #ifdef ELINK_INCLUDE_EMUL
2582 if (CHIP_REV_IS_EMUL(sc)) {
2583 /* Use lane 1 (of lanes 0-3) */
2584 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2585 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2590 #ifdef ELINK_INCLUDE_FPGA
2591 if (CHIP_REV_IS_FPGA(sc)) {
2592 /* Use lane 1 (of lanes 0-3) */
2593 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n");
2595 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2596 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2600 if (vars->phy_flags & PHY_XGXS_FLAG) {
2601 uint32_t ser_lane = ((params->lane_config &
2602 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2603 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2605 ELINK_DEBUG_P0(sc, "XGXS\n");
2606 /* select the master lanes (out of 0-3) */
2607 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2609 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2611 } else { /* SerDes */
2612 ELINK_DEBUG_P0(sc, "SerDes\n");
2614 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2617 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2618 EMAC_RX_MODE_RESET);
2619 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2620 EMAC_TX_MODE_RESET);
2622 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2623 if (CHIP_REV_IS_SLOW(sc)) {
2624 /* config GMII mode */
2625 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2626 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2629 /* pause enable/disable */
2630 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2631 EMAC_RX_MODE_FLOW_EN);
2633 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2634 (EMAC_TX_MODE_EXT_PAUSE_EN |
2635 EMAC_TX_MODE_FLOW_EN));
2636 if (!(params->feature_config_flags &
2637 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2638 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2639 elink_bits_en(sc, emac_base +
2640 EMAC_REG_EMAC_RX_MODE,
2641 EMAC_RX_MODE_FLOW_EN);
2643 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2644 elink_bits_en(sc, emac_base +
2645 EMAC_REG_EMAC_TX_MODE,
2646 (EMAC_TX_MODE_EXT_PAUSE_EN |
2647 EMAC_TX_MODE_FLOW_EN));
2649 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2650 EMAC_TX_MODE_FLOW_EN);
2651 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2655 /* KEEP_VLAN_TAG, promiscuous */
2656 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2657 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2659 /* Setting this bit causes MAC control frames (except for pause
2660 * frames) to be passed on for processing. This setting has no
2661 * affect on the operation of the pause frames. This bit effects
2662 * all packets regardless of RX Parser packet sorting logic.
2663 * Turn the PFC off to make sure we are in Xon state before
2666 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
2667 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2668 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2669 /* Enable PFC again */
2670 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
2671 EMAC_REG_RX_PFC_MODE_RX_EN |
2672 EMAC_REG_RX_PFC_MODE_TX_EN |
2673 EMAC_REG_RX_PFC_MODE_PRIORITIES);
2675 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
2677 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
2679 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
2680 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
2682 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
2685 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2690 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
2693 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2695 /* Enable emac for jumbo packets */
2696 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
2697 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2698 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
2701 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2703 /* Disable the NIG in/out to the bmac */
2704 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2705 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2706 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2708 /* Enable the NIG in/out to the emac */
2709 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2711 if ((params->feature_config_flags &
2712 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2713 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2716 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2717 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2719 #ifdef ELINK_INCLUDE_EMUL
2720 if (CHIP_REV_IS_EMUL(sc)) {
2721 /* Take the BigMac out of reset */
2722 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2723 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2725 /* Enable access for bmac registers */
2726 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2729 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2731 vars->mac_type = ELINK_MAC_TYPE_EMAC;
2732 return ELINK_STATUS_OK;
2735 static void elink_update_pfc_bmac1(struct elink_params *params,
2736 struct elink_vars *vars)
2738 uint32_t wb_data[2];
2739 struct bxe_softc *sc = params->sc;
2740 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2741 NIG_REG_INGRESS_BMAC0_MEM;
2743 uint32_t val = 0x14;
2744 if ((!(params->feature_config_flags &
2745 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2746 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2747 /* Enable BigMAC to react on received Pause packets */
2751 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2755 if (!(params->feature_config_flags &
2756 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2757 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2761 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2764 static void elink_update_pfc_bmac2(struct elink_params *params,
2765 struct elink_vars *vars,
2768 /* Set rx control: Strip CRC and enable BigMAC to relay
2769 * control packets to the system as well
2771 uint32_t wb_data[2];
2772 struct bxe_softc *sc = params->sc;
2773 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2774 NIG_REG_INGRESS_BMAC0_MEM;
2775 uint32_t val = 0x14;
2777 if ((!(params->feature_config_flags &
2778 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2779 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2780 /* Enable BigMAC to react on received Pause packets */
2784 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2789 if (!(params->feature_config_flags &
2790 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2791 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2795 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2797 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2798 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2799 /* Enable PFC RX & TX & STATS and set 8 COS */
2801 wb_data[0] |= (1<<0); /* RX */
2802 wb_data[0] |= (1<<1); /* TX */
2803 wb_data[0] |= (1<<2); /* Force initial Xon */
2804 wb_data[0] |= (1<<3); /* 8 cos */
2805 wb_data[0] |= (1<<5); /* STATS */
2807 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2809 /* Clear the force Xon */
2810 wb_data[0] &= ~(1<<2);
2812 ELINK_DEBUG_P0(sc, "PFC is disabled\n");
2813 /* Disable PFC RX & TX & STATS and set 8 COS */
2818 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2820 /* Set Time (based unit is 512 bit time) between automatic
2821 * re-sending of PP packets amd enable automatic re-send of
2822 * Per-Priroity Packet as long as pp_gen is asserted and
2823 * pp_disable is low.
2826 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2827 val |= (1<<16); /* enable automatic re-send */
2831 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2835 val = 0x3; /* Enable RX and TX */
2837 val |= 0x4; /* Local loopback */
2838 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
2840 /* When PFC enabled, Pass pause frames towards the NIG. */
2841 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2842 val |= ((1<<6)|(1<<5));
2846 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2849 /******************************************************************************
2851 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2852 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2853 ******************************************************************************/
2854 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc,
2856 uint32_t priority_mask, uint8_t port)
2858 uint32_t nig_reg_rx_priority_mask_add = 0;
2860 switch (cos_entry) {
2862 nig_reg_rx_priority_mask_add = (port) ?
2863 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2864 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2867 nig_reg_rx_priority_mask_add = (port) ?
2868 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2869 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2872 nig_reg_rx_priority_mask_add = (port) ?
2873 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2874 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2878 return ELINK_STATUS_ERROR;
2879 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2883 return ELINK_STATUS_ERROR;
2884 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2888 return ELINK_STATUS_ERROR;
2889 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2893 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2895 return ELINK_STATUS_OK;
2897 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
2899 struct bxe_softc *sc = params->sc;
2901 REG_WR(sc, params->shmem_base +
2902 offsetof(struct shmem_region,
2903 port_mb[params->port].link_status), link_status);
2906 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr)
2908 struct bxe_softc *sc = params->sc;
2910 if (SHMEM2_HAS(sc, link_attr_sync))
2911 REG_WR(sc, params->shmem2_base +
2912 offsetof(struct shmem2_region,
2913 link_attr_sync[params->port]), link_attr);
2916 static void elink_update_pfc_nig(struct elink_params *params,
2917 struct elink_vars *vars,
2918 struct elink_nig_brb_pfc_port_params *nig_params)
2920 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2921 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2922 uint32_t pkt_priority_to_cos = 0;
2923 struct bxe_softc *sc = params->sc;
2924 uint8_t port = params->port;
2926 int set_pfc = params->feature_config_flags &
2927 ELINK_FEATURE_CONFIG_PFC_ENABLED;
2928 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n");
2930 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2931 * MAC control frames (that are not pause packets)
2932 * will be forwarded to the XCM.
2934 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2935 NIG_REG_LLH0_XCM_MASK);
2936 /* NIG params will override non PFC params, since it's possible to
2937 * do transition from PFC to SAFC
2947 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2948 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2953 llfc_out_en = nig_params->llfc_out_en;
2954 llfc_enable = nig_params->llfc_enable;
2955 pause_enable = nig_params->pause_enable;
2956 } else /* Default non PFC mode - PAUSE */
2959 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2960 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2965 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2966 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2967 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2968 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2969 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2970 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2971 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2972 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2974 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2975 NIG_REG_PPP_ENABLE_0, ppp_enable);
2977 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2978 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2980 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2981 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2983 /* Output enable for RX_XCM # IF */
2984 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
2985 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2987 /* HW PFC TX enable */
2988 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
2989 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2993 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2995 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2996 elink_pfc_nig_rx_priority_mask(sc, i,
2997 nig_params->rx_cos_priority_mask[i], port);
2999 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
3000 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
3001 nig_params->llfc_high_priority_classes);
3003 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3004 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
3005 nig_params->llfc_low_priority_classes);
3007 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3008 NIG_REG_P0_PKT_PRIORITY_TO_COS,
3009 pkt_priority_to_cos);
3012 elink_status_t elink_update_pfc(struct elink_params *params,
3013 struct elink_vars *vars,
3014 struct elink_nig_brb_pfc_port_params *pfc_params)
3016 /* The PFC and pause are orthogonal to one another, meaning when
3017 * PFC is enabled, the pause are disabled, and when PFC is
3018 * disabled, pause are set according to the pause result.
3021 struct bxe_softc *sc = params->sc;
3022 elink_status_t elink_status = ELINK_STATUS_OK;
3023 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
3025 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
3026 vars->link_status |= LINK_STATUS_PFC_ENABLED;
3028 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
3030 elink_update_mng(params, vars->link_status);
3032 /* Update NIG params */
3033 elink_update_pfc_nig(params, vars, pfc_params);
3036 return elink_status;
3038 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n");
3040 if (CHIP_IS_E3(sc)) {
3041 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
3042 elink_update_pfc_xmac(params, vars, 0);
3044 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3046 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3048 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n");
3049 elink_emac_enable(params, vars, 0);
3050 return elink_status;
3053 elink_update_pfc_bmac2(params, vars, bmac_loopback);
3055 elink_update_pfc_bmac1(params, vars);
3058 if ((params->feature_config_flags &
3059 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3060 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3062 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3064 return elink_status;
3067 static elink_status_t elink_bmac1_enable(struct elink_params *params,
3068 struct elink_vars *vars,
3071 struct bxe_softc *sc = params->sc;
3072 uint8_t port = params->port;
3073 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3074 NIG_REG_INGRESS_BMAC0_MEM;
3075 uint32_t wb_data[2];
3078 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n");
3083 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
3087 wb_data[0] = ((params->mac_addr[2] << 24) |
3088 (params->mac_addr[3] << 16) |
3089 (params->mac_addr[4] << 8) |
3090 params->mac_addr[5]);
3091 wb_data[1] = ((params->mac_addr[0] << 8) |
3092 params->mac_addr[1]);
3093 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3099 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
3103 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3106 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3108 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3110 elink_update_pfc_bmac1(params, vars);
3113 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3115 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3117 /* Set cnt max size */
3118 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3120 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3122 /* Configure SAFC */
3123 wb_data[0] = 0x1000200;
3125 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
3127 #ifdef ELINK_INCLUDE_EMUL
3128 /* Fix for emulation */
3129 if (CHIP_REV_IS_EMUL(sc)) {
3130 wb_data[0] = 0xf000;
3132 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
3137 return ELINK_STATUS_OK;
3140 static elink_status_t elink_bmac2_enable(struct elink_params *params,
3141 struct elink_vars *vars,
3144 struct bxe_softc *sc = params->sc;
3145 uint8_t port = params->port;
3146 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3147 NIG_REG_INGRESS_BMAC0_MEM;
3148 uint32_t wb_data[2];
3150 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n");
3154 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3157 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3160 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
3166 wb_data[0] = ((params->mac_addr[2] << 24) |
3167 (params->mac_addr[3] << 16) |
3168 (params->mac_addr[4] << 8) |
3169 params->mac_addr[5]);
3170 wb_data[1] = ((params->mac_addr[0] << 8) |
3171 params->mac_addr[1]);
3172 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
3177 /* Configure SAFC */
3178 wb_data[0] = 0x1000200;
3180 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
3185 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3187 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3191 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3193 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3195 /* Set cnt max size */
3196 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3198 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3200 elink_update_pfc_bmac2(params, vars, is_lb);
3202 return ELINK_STATUS_OK;
3205 static elink_status_t elink_bmac_enable(struct elink_params *params,
3206 struct elink_vars *vars,
3207 uint8_t is_lb, uint8_t reset_bmac)
3209 elink_status_t rc = ELINK_STATUS_OK;
3210 uint8_t port = params->port;
3211 struct bxe_softc *sc = params->sc;
3213 /* Reset and unreset the BigMac */
3215 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3216 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3220 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3221 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3223 /* Enable access for bmac registers */
3224 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3226 /* Enable BMAC according to BMAC type*/
3228 rc = elink_bmac2_enable(params, vars, is_lb);
3230 rc = elink_bmac1_enable(params, vars, is_lb);
3231 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3232 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3233 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3235 if ((params->feature_config_flags &
3236 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3237 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3239 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3240 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3241 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3242 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3243 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3244 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3246 vars->mac_type = ELINK_MAC_TYPE_BMAC;
3250 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3252 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3253 NIG_REG_INGRESS_BMAC0_MEM;
3254 uint32_t wb_data[2];
3255 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3258 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
3260 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
3261 /* Only if the bmac is out of reset */
3262 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3263 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3265 /* Clear Rx Enable bit in BMAC_CONTROL register */
3266 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3268 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3270 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3271 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
3276 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl,
3277 uint32_t line_speed)
3279 struct bxe_softc *sc = params->sc;
3280 uint8_t port = params->port;
3281 uint32_t init_crd, crd;
3282 uint32_t count = 1000;
3285 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3287 /* Wait for init credit */
3288 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3289 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3290 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
3292 while ((init_crd != crd) && count) {
3294 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3297 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3298 if (init_crd != crd) {
3299 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",
3301 return ELINK_STATUS_ERROR;
3304 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
3305 line_speed == ELINK_SPEED_10 ||
3306 line_speed == ELINK_SPEED_100 ||
3307 line_speed == ELINK_SPEED_1000 ||
3308 line_speed == ELINK_SPEED_2500) {
3309 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3310 /* Update threshold */
3311 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3312 /* Update init credit */
3313 init_crd = 778; /* (800-18-4) */
3316 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
3317 ELINK_ETH_OVREHEAD)/16;
3318 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3319 /* Update threshold */
3320 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3321 /* Update init credit */
3322 switch (line_speed) {
3323 case ELINK_SPEED_10000:
3324 init_crd = thresh + 553 - 22;
3327 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
3329 return ELINK_STATUS_ERROR;
3332 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3333 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n",
3334 line_speed, init_crd);
3336 /* Probe the credit changes */
3337 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3339 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3342 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3343 return ELINK_STATUS_OK;
3347 * elink_get_emac_base - retrive emac base address
3349 * @bp: driver handle
3350 * @mdc_mdio_access: access type
3353 * This function selects the MDC/MDIO access (through emac0 or
3354 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3355 * phy has a default access mode, which could also be overridden
3356 * by nvram configuration. This parameter, whether this is the
3357 * default phy configuration, or the nvram overrun
3358 * configuration, is passed here as mdc_mdio_access and selects
3359 * the emac_base for the CL45 read/writes operations
3361 static uint32_t elink_get_emac_base(struct bxe_softc *sc,
3362 uint32_t mdc_mdio_access, uint8_t port)
3364 uint32_t emac_base = 0;
3365 switch (mdc_mdio_access) {
3366 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3368 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3369 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3370 emac_base = GRCBASE_EMAC1;
3372 emac_base = GRCBASE_EMAC0;
3374 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3375 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3376 emac_base = GRCBASE_EMAC0;
3378 emac_base = GRCBASE_EMAC1;
3380 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3381 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3383 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3384 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3393 /******************************************************************/
3394 /* CL22 access functions */
3395 /******************************************************************/
3396 static elink_status_t elink_cl22_write(struct bxe_softc *sc,
3397 struct elink_phy *phy,
3398 uint16_t reg, uint16_t val)
3402 elink_status_t rc = ELINK_STATUS_OK;
3403 /* Switch to CL22 */
3404 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3405 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3406 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3409 tmp = ((phy->addr << 21) | (reg << 16) | val |
3410 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3411 EMAC_MDIO_COMM_START_BUSY);
3412 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3414 for (i = 0; i < 50; i++) {
3417 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3418 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3423 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3424 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3425 rc = ELINK_STATUS_TIMEOUT;
3427 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3431 static elink_status_t elink_cl22_read(struct bxe_softc *sc,
3432 struct elink_phy *phy,
3433 uint16_t reg, uint16_t *ret_val)
3437 elink_status_t rc = ELINK_STATUS_OK;
3439 /* Switch to CL22 */
3440 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3441 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3442 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3445 val = ((phy->addr << 21) | (reg << 16) |
3446 EMAC_MDIO_COMM_COMMAND_READ_22 |
3447 EMAC_MDIO_COMM_START_BUSY);
3448 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3450 for (i = 0; i < 50; i++) {
3453 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3454 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3455 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3460 if (val & EMAC_MDIO_COMM_START_BUSY) {
3461 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3464 rc = ELINK_STATUS_TIMEOUT;
3466 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3470 /******************************************************************/
3471 /* CL45 access functions */
3472 /******************************************************************/
3473 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3474 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3478 elink_status_t rc = ELINK_STATUS_OK;
3480 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3481 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3482 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3483 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3486 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3487 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3488 EMAC_MDIO_STATUS_10MB);
3490 val = ((phy->addr << 21) | (devad << 16) | reg |
3491 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3492 EMAC_MDIO_COMM_START_BUSY);
3493 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3495 for (i = 0; i < 50; i++) {
3498 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3499 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3504 if (val & EMAC_MDIO_COMM_START_BUSY) {
3505 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3506 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3509 rc = ELINK_STATUS_TIMEOUT;
3512 val = ((phy->addr << 21) | (devad << 16) |
3513 EMAC_MDIO_COMM_COMMAND_READ_45 |
3514 EMAC_MDIO_COMM_START_BUSY);
3515 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3517 for (i = 0; i < 50; i++) {
3520 val = REG_RD(sc, phy->mdio_ctrl +
3521 EMAC_REG_EMAC_MDIO_COMM);
3522 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3523 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3527 if (val & EMAC_MDIO_COMM_START_BUSY) {
3528 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3529 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3532 rc = ELINK_STATUS_TIMEOUT;
3535 /* Work around for E3 A0 */
3536 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3537 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3538 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3540 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3544 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3545 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3546 EMAC_MDIO_STATUS_10MB);
3550 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3551 uint8_t devad, uint16_t reg, uint16_t val)
3555 elink_status_t rc = ELINK_STATUS_OK;
3557 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3558 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3559 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3560 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3563 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3564 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3565 EMAC_MDIO_STATUS_10MB);
3568 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3569 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3570 EMAC_MDIO_COMM_START_BUSY);
3571 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3573 for (i = 0; i < 50; i++) {
3576 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3577 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3582 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3583 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3584 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3586 rc = ELINK_STATUS_TIMEOUT;
3589 tmp = ((phy->addr << 21) | (devad << 16) | val |
3590 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3591 EMAC_MDIO_COMM_START_BUSY);
3592 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3594 for (i = 0; i < 50; i++) {
3597 tmp = REG_RD(sc, phy->mdio_ctrl +
3598 EMAC_REG_EMAC_MDIO_COMM);
3599 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3604 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3605 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3606 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3608 rc = ELINK_STATUS_TIMEOUT;
3611 /* Work around for E3 A0 */
3612 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3613 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3614 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3616 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3619 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3620 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3621 EMAC_MDIO_STATUS_10MB);
3625 /******************************************************************/
3627 /******************************************************************/
3628 static uint8_t elink_eee_has_cap(struct elink_params *params)
3630 struct bxe_softc *sc = params->sc;
3632 if (REG_RD(sc, params->shmem2_base) <=
3633 offsetof(struct shmem2_region, eee_status[params->port]))
3639 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer)
3641 switch (nvram_mode) {
3642 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3643 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
3645 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3646 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3648 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3649 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
3656 return ELINK_STATUS_OK;
3659 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode)
3661 switch (idle_timer) {
3662 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
3663 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3665 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3666 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3668 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
3669 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3672 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3676 return ELINK_STATUS_OK;
3679 static uint32_t elink_eee_calc_timer(struct elink_params *params)
3681 uint32_t eee_mode, eee_idle;
3682 struct bxe_softc *sc = params->sc;
3684 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
3685 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3686 /* time value in eee_mode --> used directly*/
3687 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
3689 /* hsi value in eee_mode --> time */
3690 if (elink_eee_nvram_to_time(params->eee_mode &
3691 ELINK_EEE_MODE_NVRAM_MASK,
3696 /* hsi values in nvram --> time*/
3697 eee_mode = ((REG_RD(sc, params->shmem_base +
3698 offsetof(struct shmem_region, dev_info.
3699 port_feature_config[params->port].
3701 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3702 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3704 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
3711 static elink_status_t elink_eee_set_timers(struct elink_params *params,
3712 struct elink_vars *vars)
3714 uint32_t eee_idle = 0, eee_mode;
3715 struct bxe_softc *sc = params->sc;
3717 eee_idle = elink_eee_calc_timer(params);
3720 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3722 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
3723 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
3724 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
3725 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");
3726 return ELINK_STATUS_ERROR;
3729 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3730 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3731 /* eee_idle in 1u --> eee_status in 16u */
3733 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3734 SHMEM_EEE_TIME_OUTPUT_BIT;
3736 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
3737 return ELINK_STATUS_ERROR;
3738 vars->eee_status |= eee_mode;
3741 return ELINK_STATUS_OK;
3744 static elink_status_t elink_eee_initial_config(struct elink_params *params,
3745 struct elink_vars *vars, uint8_t mode)
3747 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3749 /* Propogate params' bits --> vars (for migration exposure) */
3750 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
3751 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3753 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3755 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
3756 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3758 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3760 return elink_eee_set_timers(params, vars);
3763 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3764 struct elink_params *params,
3765 struct elink_vars *vars)
3767 struct bxe_softc *sc = params->sc;
3769 /* Make Certain LPI is disabled */
3770 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3772 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3774 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3776 return ELINK_STATUS_OK;
3779 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3780 struct elink_params *params,
3781 struct elink_vars *vars, uint8_t modes)
3783 struct bxe_softc *sc = params->sc;
3786 /* Mask events preventing LPI generation */
3787 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3789 if (modes & SHMEM_EEE_10G_ADV) {
3790 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n");
3793 if (modes & SHMEM_EEE_1G_ADV) {
3794 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n");
3798 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3800 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3801 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3803 return ELINK_STATUS_OK;
3806 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status)
3808 struct bxe_softc *sc = params->sc;
3810 if (elink_eee_has_cap(params))
3811 REG_WR(sc, params->shmem2_base +
3812 offsetof(struct shmem2_region,
3813 eee_status[params->port]), eee_status);
3816 static void elink_eee_an_resolve(struct elink_phy *phy,
3817 struct elink_params *params,
3818 struct elink_vars *vars)
3820 struct bxe_softc *sc = params->sc;
3821 uint16_t adv = 0, lp = 0;
3822 uint32_t lp_adv = 0;
3825 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3826 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3829 lp_adv |= SHMEM_EEE_100M_ADV;
3831 if (vars->line_speed == ELINK_SPEED_100)
3833 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n");
3837 lp_adv |= SHMEM_EEE_1G_ADV;
3839 if (vars->line_speed == ELINK_SPEED_1000)
3841 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n");
3845 lp_adv |= SHMEM_EEE_10G_ADV;
3847 if (vars->line_speed == ELINK_SPEED_10000)
3849 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n");
3853 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3854 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3857 ELINK_DEBUG_P0(sc, "EEE is active\n");
3858 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3862 /******************************************************************/
3863 /* BSC access functions from E3 */
3864 /******************************************************************/
3865 static void elink_bsc_module_sel(struct elink_params *params)
3868 uint32_t board_cfg, sfp_ctrl;
3869 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3870 struct bxe_softc *sc = params->sc;
3871 uint8_t port = params->port;
3872 /* Read I2C output PINs */
3873 board_cfg = REG_RD(sc, params->shmem_base +
3874 offsetof(struct shmem_region,
3875 dev_info.shared_hw_config.board));
3876 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3877 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3878 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3880 /* Read I2C output value */
3881 sfp_ctrl = REG_RD(sc, params->shmem_base +
3882 offsetof(struct shmem_region,
3883 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3884 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3885 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3886 ELINK_DEBUG_P0(sc, "Setting BSC switch\n");
3887 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3888 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
3891 static elink_status_t elink_bsc_read(struct elink_params *params,
3892 struct bxe_softc *sc,
3897 uint32_t *data_array)
3900 elink_status_t rc = ELINK_STATUS_OK;
3902 if (xfer_cnt > 16) {
3903 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n",
3905 return ELINK_STATUS_ERROR;
3908 elink_bsc_module_sel(params);
3910 xfer_cnt = 16 - lc_addr;
3912 /* Enable the engine */
3913 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3914 val |= MCPR_IMC_COMMAND_ENABLE;
3915 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3917 /* Program slave device ID */
3918 val = (sl_devid << 16) | sl_addr;
3919 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3921 /* Start xfer with 0 byte to update the address pointer ???*/
3922 val = (MCPR_IMC_COMMAND_ENABLE) |
3923 (MCPR_IMC_COMMAND_WRITE_OP <<
3924 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3925 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3926 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3928 /* Poll for completion */
3930 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3931 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3933 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3935 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",
3937 rc = ELINK_STATUS_TIMEOUT;
3941 if (rc == ELINK_STATUS_TIMEOUT)
3944 /* Start xfer with read op */
3945 val = (MCPR_IMC_COMMAND_ENABLE) |
3946 (MCPR_IMC_COMMAND_READ_OP <<
3947 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3948 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3950 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3952 /* Poll for completion */
3954 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3955 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3957 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3959 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i);
3960 rc = ELINK_STATUS_TIMEOUT;
3964 if (rc == ELINK_STATUS_TIMEOUT)
3967 for (i = (lc_addr >> 2); i < 4; i++) {
3968 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3970 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3971 ((data_array[i] & 0x0000ff00) << 8) |
3972 ((data_array[i] & 0x00ff0000) >> 8) |
3973 ((data_array[i] & 0xff000000) >> 24);
3979 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3980 uint8_t devad, uint16_t reg, uint16_t or_val)
3983 elink_cl45_read(sc, phy, devad, reg, &val);
3984 elink_cl45_write(sc, phy, devad, reg, val | or_val);
3987 static void elink_cl45_read_and_write(struct bxe_softc *sc,
3988 struct elink_phy *phy,
3989 uint8_t devad, uint16_t reg, uint16_t and_val)
3992 elink_cl45_read(sc, phy, devad, reg, &val);
3993 elink_cl45_write(sc, phy, devad, reg, val & and_val);
3996 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
3997 uint8_t devad, uint16_t reg, uint16_t *ret_val)
4000 /* Probe for the phy according to the given phy_addr, and execute
4001 * the read request on it
4003 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4004 if (params->phy[phy_index].addr == phy_addr) {
4005 return elink_cl45_read(params->sc,
4006 ¶ms->phy[phy_index], devad,
4010 return ELINK_STATUS_ERROR;
4013 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
4014 uint8_t devad, uint16_t reg, uint16_t val)
4017 /* Probe for the phy according to the given phy_addr, and execute
4018 * the write request on it
4020 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4021 if (params->phy[phy_index].addr == phy_addr) {
4022 return elink_cl45_write(params->sc,
4023 ¶ms->phy[phy_index], devad,
4027 return ELINK_STATUS_ERROR;
4029 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4030 struct elink_params *params)
4033 struct bxe_softc *sc = params->sc;
4034 uint32_t path_swap, path_swap_ovr;
4038 port = params->port;
4040 if (elink_is_4_port_mode(sc)) {
4041 uint32_t port_swap, port_swap_ovr;
4043 /* Figure out path swap value */
4044 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4045 if (path_swap_ovr & 0x1)
4046 path_swap = (path_swap_ovr & 0x2);
4048 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4053 /* Figure out port swap value */
4054 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4055 if (port_swap_ovr & 0x1)
4056 port_swap = (port_swap_ovr & 0x2);
4058 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4063 lane = (port<<1) + path;
4064 } else { /* Two port mode - no port swap */
4066 /* Figure out path swap value */
4068 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4069 if (path_swap_ovr & 0x1) {
4070 path_swap = (path_swap_ovr & 0x2);
4073 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4083 static void elink_set_aer_mmd(struct elink_params *params,
4084 struct elink_phy *phy)
4087 uint16_t offset, aer_val;
4088 struct bxe_softc *sc = params->sc;
4089 ser_lane = ((params->lane_config &
4090 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4091 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4093 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4094 (phy->addr + ser_lane) : 0;
4096 if (USES_WARPCORE(sc)) {
4097 aer_val = elink_get_warpcore_lane(phy, params);
4098 /* In Dual-lane mode, two lanes are joined together,
4099 * so in order to configure them, the AER broadcast method is
4101 * 0x200 is the broadcast address for lanes 0,1
4102 * 0x201 is the broadcast address for lanes 2,3
4104 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4105 aer_val = (aer_val >> 1) | 0x200;
4106 } else if (CHIP_IS_E2(sc))
4107 aer_val = 0x3800 + offset - 1;
4109 aer_val = 0x3800 + offset;
4111 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4112 MDIO_AER_BLOCK_AER_REG, aer_val);
4116 /******************************************************************/
4117 /* Internal phy section */
4118 /******************************************************************/
4120 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4122 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4125 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4126 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4128 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4131 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4134 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4138 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n");
4140 val = ELINK_SERDES_RESET_BITS << (port*16);
4142 /* Reset and unreset the SerDes/XGXS */
4143 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4145 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4147 elink_set_serdes_access(sc, port);
4149 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4150 ELINK_DEFAULT_PHY_DEV_ADDR);
4153 static void elink_xgxs_specific_func(struct elink_phy *phy,
4154 struct elink_params *params,
4157 struct bxe_softc *sc = params->sc;
4159 case ELINK_PHY_INIT:
4160 /* Set correct devad */
4161 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4162 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4168 static void elink_xgxs_deassert(struct elink_params *params)
4170 struct bxe_softc *sc = params->sc;
4173 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n");
4174 port = params->port;
4176 val = ELINK_XGXS_RESET_BITS << (port*16);
4178 /* Reset and unreset the SerDes/XGXS */
4179 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4181 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4182 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4186 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4187 struct elink_params *params, uint16_t *ieee_fc)
4189 struct bxe_softc *sc = params->sc;
4190 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
4191 /* Resolve pause mode and advertisement Please refer to Table
4192 * 28B-3 of the 802.3ab-1999 spec
4195 switch (phy->req_flow_ctrl) {
4196 case ELINK_FLOW_CTRL_AUTO:
4197 switch (params->req_fc_auto_adv) {
4198 case ELINK_FLOW_CTRL_BOTH:
4199 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4201 case ELINK_FLOW_CTRL_RX:
4202 case ELINK_FLOW_CTRL_TX:
4204 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4210 case ELINK_FLOW_CTRL_TX:
4211 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4214 case ELINK_FLOW_CTRL_RX:
4215 case ELINK_FLOW_CTRL_BOTH:
4216 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4219 case ELINK_FLOW_CTRL_NONE:
4221 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
4224 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);
4227 static void set_phy_vars(struct elink_params *params,
4228 struct elink_vars *vars)
4230 struct bxe_softc *sc = params->sc;
4231 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
4232 uint8_t phy_config_swapped = params->multi_phy_config &
4233 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
4234 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
4236 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
4237 actual_phy_idx = phy_index;
4238 if (phy_config_swapped) {
4239 if (phy_index == ELINK_EXT_PHY1)
4240 actual_phy_idx = ELINK_EXT_PHY2;
4241 else if (phy_index == ELINK_EXT_PHY2)
4242 actual_phy_idx = ELINK_EXT_PHY1;
4244 params->phy[actual_phy_idx].req_flow_ctrl =
4245 params->req_flow_ctrl[link_cfg_idx];
4247 params->phy[actual_phy_idx].req_line_speed =
4248 params->req_line_speed[link_cfg_idx];
4250 params->phy[actual_phy_idx].speed_cap_mask =
4251 params->speed_cap_mask[link_cfg_idx];
4253 params->phy[actual_phy_idx].req_duplex =
4254 params->req_duplex[link_cfg_idx];
4256 if (params->req_line_speed[link_cfg_idx] ==
4257 ELINK_SPEED_AUTO_NEG)
4258 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
4260 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
4261 " speed_cap_mask %x\n",
4262 params->phy[actual_phy_idx].req_flow_ctrl,
4263 params->phy[actual_phy_idx].req_line_speed,
4264 params->phy[actual_phy_idx].speed_cap_mask);
4268 static void elink_ext_phy_set_pause(struct elink_params *params,
4269 struct elink_phy *phy,
4270 struct elink_vars *vars)
4273 struct bxe_softc *sc = params->sc;
4274 /* Read modify write pause advertizing */
4275 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4277 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
4279 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4280 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4281 if ((vars->ieee_fc &
4282 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4283 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4284 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
4286 if ((vars->ieee_fc &
4287 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4288 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4289 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
4291 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4292 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4295 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
4297 switch (pause_result) { /* ASYM P ASYM P */
4298 case 0xb: /* 1 0 1 1 */
4299 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
4302 case 0xe: /* 1 1 1 0 */
4303 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4306 case 0x5: /* 0 1 0 1 */
4307 case 0x7: /* 0 1 1 1 */
4308 case 0xd: /* 1 1 0 1 */
4309 case 0xf: /* 1 1 1 1 */
4310 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
4316 if (pause_result & (1<<0))
4317 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
4318 if (pause_result & (1<<1))
4319 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
4323 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4324 struct elink_params *params,
4325 struct elink_vars *vars)
4327 uint16_t ld_pause; /* local */
4328 uint16_t lp_pause; /* link partner */
4329 uint16_t pause_result;
4330 struct bxe_softc *sc = params->sc;
4331 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4332 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4333 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4334 } else if (CHIP_IS_E3(sc) &&
4335 ELINK_SINGLE_MEDIA_DIRECT(params)) {
4336 uint8_t lane = elink_get_warpcore_lane(phy, params);
4337 uint16_t gp_status, gp_mask;
4338 elink_cl45_read(sc, phy,
4339 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
4341 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
4342 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
4344 if ((gp_status & gp_mask) == gp_mask) {
4345 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4346 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4347 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4348 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4350 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4351 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4352 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4353 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4354 ld_pause = ((ld_pause &
4355 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4357 lp_pause = ((lp_pause &
4358 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4362 elink_cl45_read(sc, phy,
4364 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4365 elink_cl45_read(sc, phy,
4367 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4369 pause_result = (ld_pause &
4370 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
4371 pause_result |= (lp_pause &
4372 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
4373 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);
4374 elink_pause_resolve(vars, pause_result);
4378 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4379 struct elink_params *params,
4380 struct elink_vars *vars)
4383 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4384 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4385 /* Update the advertised flow-controled of LD/LP in AN */
4386 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4387 elink_ext_phy_update_adv_fc(phy, params, vars);
4388 /* But set the flow-control result as the requested one */
4389 vars->flow_ctrl = phy->req_flow_ctrl;
4390 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4391 vars->flow_ctrl = params->req_fc_auto_adv;
4392 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
4394 elink_ext_phy_update_adv_fc(phy, params, vars);
4398 /******************************************************************/
4399 /* Warpcore section */
4400 /******************************************************************/
4401 /* The init_internal_warpcore should mirror the xgxs,
4402 * i.e. reset the lane (if needed), set aer for the
4403 * init configuration, and set/clear SGMII flag. Internal
4404 * phy init is done purely in phy_init stage.
4406 #define WC_TX_DRIVER(post2, idriver, ipre) \
4407 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
4408 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
4409 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
4411 #define WC_TX_FIR(post, main, pre) \
4412 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
4413 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
4414 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
4416 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4417 struct elink_params *params,
4418 struct elink_vars *vars)
4420 struct bxe_softc *sc = params->sc;
4422 static struct elink_reg_set reg_set[] = {
4423 /* Step 1 - Program the TX/RX alignment markers */
4424 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
4425 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
4426 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
4427 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
4428 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
4429 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
4430 /* Step 2 - Configure the NP registers */
4431 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
4432 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
4433 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
4434 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
4435 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
4436 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
4437 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
4438 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
4439 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
4441 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n");
4443 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4444 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
4446 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4447 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4450 /* Start KR2 work-around timer which handles BCM8073 link-parner */
4451 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
4452 elink_update_link_attr(params, vars->link_attr_sync);
4455 static void elink_disable_kr2(struct elink_params *params,
4456 struct elink_vars *vars,
4457 struct elink_phy *phy)
4459 struct bxe_softc *sc = params->sc;
4461 static struct elink_reg_set reg_set[] = {
4462 /* Step 1 - Program the TX/RX alignment markers */
4463 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
4464 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
4465 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
4466 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
4467 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
4468 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
4474 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
4475 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
4477 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
4479 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n");
4481 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4482 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4484 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
4485 elink_update_link_attr(params, vars->link_attr_sync);
4487 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
4490 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4491 struct elink_params *params)
4493 struct bxe_softc *sc = params->sc;
4495 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n");
4496 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4497 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
4498 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4499 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4502 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4503 struct elink_params *params)
4505 /* Restart autoneg on the leading lane only */
4506 struct bxe_softc *sc = params->sc;
4507 uint16_t lane = elink_get_warpcore_lane(phy, params);
4508 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4509 MDIO_AER_BLOCK_AER_REG, lane);
4510 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4511 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4514 elink_set_aer_mmd(params, phy);
4517 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4518 struct elink_params *params,
4519 struct elink_vars *vars) {
4520 uint16_t lane, i, cl72_ctrl, an_adv = 0;
4521 struct bxe_softc *sc = params->sc;
4522 static struct elink_reg_set reg_set[] = {
4523 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4524 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
4525 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
4526 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
4527 /* Disable Autoneg: re-enable it after adv is done. */
4528 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
4529 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
4530 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
4532 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n");
4533 /* Set to default registers that may be overriden by 10G force */
4534 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4535 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4538 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4539 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4540 cl72_ctrl &= 0x08ff;
4541 cl72_ctrl |= 0x3800;
4542 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4543 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
4545 /* Check adding advertisement for 1G KX */
4546 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4547 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4548 (vars->line_speed == ELINK_SPEED_1000)) {
4549 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
4552 /* Enable CL37 1G Parallel Detect */
4553 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4554 ELINK_DEBUG_P0(sc, "Advertize 1G\n");
4556 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4557 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4558 (vars->line_speed == ELINK_SPEED_10000)) {
4559 /* Check adding advertisement for 10G KR */
4561 /* Enable 10G Parallel Detect */
4562 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4563 MDIO_AER_BLOCK_AER_REG, 0);
4565 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4566 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
4567 elink_set_aer_mmd(params, phy);
4568 ELINK_DEBUG_P0(sc, "Advertize 10G\n");
4571 /* Set Transmit PMD settings */
4572 lane = elink_get_warpcore_lane(phy, params);
4573 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4574 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4575 WC_TX_DRIVER(0x02, 0x06, 0x09));
4576 /* Configure the next lane if dual mode */
4577 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4578 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4579 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4580 WC_TX_DRIVER(0x02, 0x06, 0x09));
4581 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4582 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
4584 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4585 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
4588 /* Advertised speeds */
4589 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4590 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
4592 /* Advertised and set FEC (Forward Error Correction) */
4593 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4594 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
4595 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
4596 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
4598 /* Enable CL37 BAM */
4599 if (REG_RD(sc, params->shmem_base +
4600 offsetof(struct shmem_region, dev_info.
4601 port_hw_config[params->port].default_cfg)) &
4602 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4603 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4604 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
4606 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
4609 /* Advertise pause */
4610 elink_ext_phy_set_pause(params, phy, vars);
4611 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4612 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4613 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4615 /* Over 1G - AN local device user page 1 */
4616 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4617 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4619 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4620 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4621 (phy->req_line_speed == ELINK_SPEED_20000)) {
4623 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4624 MDIO_AER_BLOCK_AER_REG, lane);
4626 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4627 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4630 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4632 elink_set_aer_mmd(params, phy);
4634 elink_warpcore_enable_AN_KR2(phy, params, vars);
4636 /* Enable Auto-Detect to support 1G over CL37 as well */
4637 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4638 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
4640 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
4641 * parallel-detect loop when CL73 and CL37 are enabled.
4643 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4644 MDIO_AER_BLOCK_AER_REG, 0);
4645 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4646 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
4647 elink_set_aer_mmd(params, phy);
4649 elink_disable_kr2(params, vars, phy);
4652 /* Enable Autoneg: only on the main lane */
4653 elink_warpcore_restart_AN_KR(phy, params);
4656 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4657 struct elink_params *params,
4658 struct elink_vars *vars)
4660 struct bxe_softc *sc = params->sc;
4661 uint16_t val16, i, lane;
4662 static struct elink_reg_set reg_set[] = {
4663 /* Disable Autoneg */
4664 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4665 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4667 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4668 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4669 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4670 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4671 /* Leave cl72 training enable, needed for KR */
4672 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
4675 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4676 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4679 lane = elink_get_warpcore_lane(phy, params);
4680 /* Global registers */
4681 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4682 MDIO_AER_BLOCK_AER_REG, 0);
4683 /* Disable CL36 PCS Tx */
4684 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4685 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4686 val16 &= ~(0x0011 << lane);
4687 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4688 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4690 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4691 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4692 val16 |= (0x0303 << (lane << 1));
4693 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4694 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4696 elink_set_aer_mmd(params, phy);
4697 /* Set speed via PMA/PMD register */
4698 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4699 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4701 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4702 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4704 /* Enable encoded forced speed */
4705 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4706 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4708 /* Turn TX scramble payload only the 64/66 scrambler */
4709 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4710 MDIO_WC_REG_TX66_CONTROL, 0x9);
4712 /* Turn RX scramble payload only the 64/66 scrambler */
4713 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4714 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4716 /* Set and clear loopback to cause a reset to 64/66 decoder */
4717 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4718 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4719 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4720 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4724 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4725 struct elink_params *params,
4728 struct bxe_softc *sc = params->sc;
4729 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4730 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
4732 /* Hold rxSeqStart */
4733 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4734 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4736 /* Hold tx_fifo_reset */
4737 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4738 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4740 /* Disable CL73 AN */
4741 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4743 /* Disable 100FX Enable and Auto-Detect */
4744 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4745 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
4747 /* Disable 100FX Idle detect */
4748 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4749 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4751 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4752 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4753 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
4755 /* Turn off auto-detect & fiber mode */
4756 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4757 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4760 /* Set filter_force_link, disable_false_link and parallel_detect */
4761 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4762 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4763 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4764 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4765 ((val | 0x0006) & 0xFFFE));
4768 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4769 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4771 misc1_val &= ~(0x1f);
4775 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4776 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
4778 cfg_tap_val = REG_RD(sc, params->shmem_base +
4779 offsetof(struct shmem_region, dev_info.
4780 port_hw_config[params->port].
4783 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4785 tx_drv_brdct = (cfg_tap_val &
4786 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4787 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4791 /* TAP values are controlled by nvram, if value there isn't 0 */
4793 tap_val = (uint16_t)tx_equal;
4795 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4798 tx_driver_val = WC_TX_DRIVER(0x03, (uint16_t)tx_drv_brdct,
4801 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4803 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4804 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4806 /* Set Transmit PMD settings */
4807 lane = elink_get_warpcore_lane(phy, params);
4808 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4809 MDIO_WC_REG_TX_FIR_TAP,
4810 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4811 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4812 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4815 /* Enable fiber mode, enable and invert sig_det */
4816 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4817 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4819 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4820 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4821 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4823 elink_warpcore_set_lpi_passthrough(phy, params);
4825 /* 10G XFI Full Duplex */
4826 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4827 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4829 /* Release tx_fifo_reset */
4830 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4831 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4833 /* Release rxSeqStart */
4834 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4835 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4838 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4839 struct elink_params *params)
4842 struct bxe_softc *sc = params->sc;
4843 /* Set global registers, so set AER lane to 0 */
4844 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4845 MDIO_AER_BLOCK_AER_REG, 0);
4847 /* Disable sequencer */
4848 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4849 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4851 elink_set_aer_mmd(params, phy);
4853 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4854 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4855 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4856 MDIO_AN_REG_CTRL, 0);
4858 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4859 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4862 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4863 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4865 /* Set 20G KR2 force speed */
4866 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4867 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4869 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4870 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4872 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4873 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4876 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4877 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4878 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4879 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4881 /* Enable sequencer (over lane 0) */
4882 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4883 MDIO_AER_BLOCK_AER_REG, 0);
4885 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4886 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4888 elink_set_aer_mmd(params, phy);
4891 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc,
4892 struct elink_phy *phy,
4895 /* Rx0 anaRxControl1G */
4896 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4897 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4899 /* Rx2 anaRxControl1G */
4900 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4901 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4903 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4904 MDIO_WC_REG_RX66_SCW0, 0xE070);
4906 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4907 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4909 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4910 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4912 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4913 MDIO_WC_REG_RX66_SCW3, 0x8090);
4915 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4916 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4918 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4919 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4921 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4922 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4924 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4925 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4927 /* Serdes Digital Misc1 */
4928 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4929 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4931 /* Serdes Digital4 Misc3 */
4932 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4933 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4935 /* Set Transmit PMD settings */
4936 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4937 MDIO_WC_REG_TX_FIR_TAP,
4938 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4939 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4940 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4941 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4942 WC_TX_DRIVER(0x02, 0x02, 0x02));
4945 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
4946 struct elink_params *params,
4948 uint8_t always_autoneg)
4950 struct bxe_softc *sc = params->sc;
4951 uint16_t val16, digctrl_kx1, digctrl_kx2;
4953 /* Clear XFI clock comp in non-10G single lane mode. */
4954 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4955 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4957 elink_warpcore_set_lpi_passthrough(phy, params);
4959 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
4961 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4962 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4964 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
4966 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4967 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4969 switch (phy->req_line_speed) {
4970 case ELINK_SPEED_10:
4972 case ELINK_SPEED_100:
4975 case ELINK_SPEED_1000:
4980 "Speed not supported: 0x%x\n", phy->req_line_speed);
4984 if (phy->req_duplex == DUPLEX_FULL)
4987 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4988 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4990 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n",
4991 phy->req_line_speed);
4992 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4993 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4994 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16);
4997 /* SGMII Slave mode and disable signal detect */
4998 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4999 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
5003 digctrl_kx1 &= 0xff4a;
5005 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5006 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5009 /* Turn off parallel detect */
5010 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5011 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
5012 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5013 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5014 (digctrl_kx2 & ~(1<<2)));
5016 /* Re-enable parallel detect */
5017 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5018 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5019 (digctrl_kx2 | (1<<2)));
5021 /* Enable autodet */
5022 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5023 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5024 (digctrl_kx1 | 0x10));
5028 static void elink_warpcore_reset_lane(struct bxe_softc *sc,
5029 struct elink_phy *phy,
5033 /* Take lane out of reset after configuration is finished */
5034 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5035 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5040 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5041 MDIO_WC_REG_DIGITAL5_MISC6, val);
5042 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5043 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5046 /* Clear SFI/XFI link settings registers */
5047 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5048 struct elink_params *params,
5051 struct bxe_softc *sc = params->sc;
5053 static struct elink_reg_set wc_regs[] = {
5054 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
5055 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
5056 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
5057 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
5058 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5060 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5062 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
5064 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
5065 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
5066 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
5067 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
5069 /* Set XFI clock comp as default. */
5070 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5071 MDIO_WC_REG_RX66_CONTROL, (3<<13));
5073 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
5074 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5077 lane = elink_get_warpcore_lane(phy, params);
5078 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5079 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5083 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc,
5085 uint32_t shmem_base, uint8_t port,
5086 uint8_t *gpio_num, uint8_t *gpio_port)
5091 if (CHIP_IS_E3(sc)) {
5092 cfg_pin = (REG_RD(sc, shmem_base +
5093 offsetof(struct shmem_region,
5094 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5095 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
5096 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
5098 /* Should not happen. This function called upon interrupt
5099 * triggered by GPIO ( since EPIO can only generate interrupts
5101 * So if this function was called and none of the GPIOs was set,
5102 * it means the shit hit the fan.
5104 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
5105 (cfg_pin > PIN_CFG_GPIO3_P1)) {
5107 "No cfg pin %x for module detect indication\n",
5109 return ELINK_STATUS_ERROR;
5112 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
5113 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
5115 *gpio_num = MISC_REGISTERS_GPIO_3;
5119 return ELINK_STATUS_OK;
5122 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5123 struct elink_params *params)
5125 struct bxe_softc *sc = params->sc;
5126 uint8_t gpio_num, gpio_port;
5128 if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
5129 params->shmem_base, params->port,
5130 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
5132 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
5134 /* Call the handling function in case module is detected */
5140 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5141 struct elink_params *params)
5143 uint16_t gp2_status_reg0, lane;
5144 struct bxe_softc *sc = params->sc;
5146 lane = elink_get_warpcore_lane(phy, params);
5148 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5151 return (gp2_status_reg0 >> (8+lane)) & 0x1;
5154 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5155 struct elink_params *params,
5156 struct elink_vars *vars)
5158 struct bxe_softc *sc = params->sc;
5159 uint32_t serdes_net_if;
5160 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
5162 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
5164 if (!vars->turn_to_run_wc_rt)
5167 if (vars->rx_tx_asic_rst) {
5168 uint16_t lane = elink_get_warpcore_lane(phy, params);
5169 serdes_net_if = (REG_RD(sc, params->shmem_base +
5170 offsetof(struct shmem_region, dev_info.
5171 port_hw_config[params->port].default_cfg)) &
5172 PORT_HW_CFG_NET_SERDES_IF_MASK);
5174 switch (serdes_net_if) {
5175 case PORT_HW_CFG_NET_SERDES_IF_KR:
5176 /* Do we get link yet? */
5177 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5179 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5181 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5183 if (lnkup_kr || lnkup) {
5184 vars->rx_tx_asic_rst = 0;
5186 /* Reset the lane to see if link comes up.*/
5187 elink_warpcore_reset_lane(sc, phy, 1);
5188 elink_warpcore_reset_lane(sc, phy, 0);
5190 /* Restart Autoneg */
5191 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5192 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
5194 vars->rx_tx_asic_rst--;
5195 ELINK_DEBUG_P1(sc, "0x%x retry left\n",
5196 vars->rx_tx_asic_rst);
5204 } /*params->rx_tx_asic_rst*/
5207 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5208 struct elink_params *params)
5210 uint16_t lane = elink_get_warpcore_lane(phy, params);
5211 struct bxe_softc *sc = params->sc;
5212 elink_warpcore_clear_regs(phy, params, lane);
5213 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
5214 ELINK_SPEED_10000) &&
5215 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5216 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n");
5217 elink_warpcore_set_10G_XFI(phy, params, 0);
5219 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n");
5220 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5224 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
5225 struct elink_phy *phy,
5228 struct bxe_softc *sc = params->sc;
5230 uint8_t port = params->port;
5232 cfg_pin = REG_RD(sc, params->shmem_base +
5233 offsetof(struct shmem_region,
5234 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5235 PORT_HW_CFG_E3_TX_LASER_MASK;
5236 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
5237 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en);
5239 /* For 20G, the expected pin to be used is 3 pins after the current */
5240 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
5241 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5242 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
5245 static void elink_warpcore_config_init(struct elink_phy *phy,
5246 struct elink_params *params,
5247 struct elink_vars *vars)
5249 struct bxe_softc *sc = params->sc;
5250 uint32_t serdes_net_if;
5252 uint16_t lane = elink_get_warpcore_lane(phy, params);
5253 serdes_net_if = (REG_RD(sc, params->shmem_base +
5254 offsetof(struct shmem_region, dev_info.
5255 port_hw_config[params->port].default_cfg)) &
5256 PORT_HW_CFG_NET_SERDES_IF_MASK);
5257 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
5258 "serdes_net_if = 0x%x\n",
5259 vars->line_speed, serdes_net_if);
5260 elink_set_aer_mmd(params, phy);
5261 elink_warpcore_reset_lane(sc, phy, 1);
5262 vars->phy_flags |= PHY_XGXS_FLAG;
5263 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
5264 (phy->req_line_speed &&
5265 ((phy->req_line_speed == ELINK_SPEED_100) ||
5266 (phy->req_line_speed == ELINK_SPEED_10)))) {
5267 vars->phy_flags |= PHY_SGMII_FLAG;
5268 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n");
5269 elink_warpcore_clear_regs(phy, params, lane);
5270 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5272 switch (serdes_net_if) {
5273 case PORT_HW_CFG_NET_SERDES_IF_KR:
5274 /* Enable KR Auto Neg */
5275 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
5276 elink_warpcore_enable_AN_KR(phy, params, vars);
5278 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n");
5279 elink_warpcore_set_10G_KR(phy, params, vars);
5283 case PORT_HW_CFG_NET_SERDES_IF_XFI:
5284 elink_warpcore_clear_regs(phy, params, lane);
5285 if (vars->line_speed == ELINK_SPEED_10000) {
5286 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n");
5287 elink_warpcore_set_10G_XFI(phy, params, 1);
5289 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5290 ELINK_DEBUG_P0(sc, "1G Fiber\n");
5293 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n");
5296 elink_warpcore_set_sgmii_speed(phy,
5304 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5305 /* Issue Module detection if module is plugged, or
5306 * enabled transmitter to avoid current leakage in case
5307 * no module is connected
5309 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
5310 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5311 if (elink_is_sfp_module_plugged(phy, params))
5312 elink_sfp_module_detection(phy, params);
5314 elink_sfp_e3_set_transmitter(params,
5318 elink_warpcore_config_sfi(phy, params);
5321 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
5322 if (vars->line_speed != ELINK_SPEED_20000) {
5323 ELINK_DEBUG_P0(sc, "Speed not supported yet\n");
5326 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n");
5327 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5328 /* Issue Module detection */
5330 elink_sfp_module_detection(phy, params);
5332 case PORT_HW_CFG_NET_SERDES_IF_KR2:
5333 if (!params->loopback_mode) {
5334 elink_warpcore_enable_AN_KR(phy, params, vars);
5336 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n");
5337 elink_warpcore_set_20G_force_KR2(phy, params);
5342 "Unsupported Serdes Net Interface 0x%x\n",
5348 /* Take lane out of reset after configuration is finished */
5349 elink_warpcore_reset_lane(sc, phy, 0);
5350 ELINK_DEBUG_P0(sc, "Exit config init\n");
5353 static void elink_warpcore_link_reset(struct elink_phy *phy,
5354 struct elink_params *params)
5356 struct bxe_softc *sc = params->sc;
5357 uint16_t val16, lane;
5358 elink_sfp_e3_set_transmitter(params, phy, 0);
5359 elink_set_mdio_emac_per_phy(sc, params);
5360 elink_set_aer_mmd(params, phy);
5361 /* Global register */
5362 elink_warpcore_reset_lane(sc, phy, 1);
5364 /* Clear loopback settings (if any) */
5366 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5367 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
5369 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5370 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
5372 /* Update those 1-copy registers */
5373 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5374 MDIO_AER_BLOCK_AER_REG, 0);
5375 /* Enable 1G MDIO (1-copy) */
5376 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5377 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5380 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5381 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
5382 lane = elink_get_warpcore_lane(phy, params);
5383 /* Disable CL36 PCS Tx */
5384 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5385 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
5386 val16 |= (0x11 << lane);
5387 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5388 val16 |= (0x22 << lane);
5389 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5390 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
5392 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5393 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
5394 val16 &= ~(0x0303 << (lane << 1));
5395 val16 |= (0x0101 << (lane << 1));
5396 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5397 val16 &= ~(0x0c0c << (lane << 1));
5398 val16 |= (0x0404 << (lane << 1));
5401 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5402 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
5404 elink_set_aer_mmd(params, phy);
5408 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5409 struct elink_params *params)
5411 struct bxe_softc *sc = params->sc;
5414 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n",
5415 params->loopback_mode, phy->req_line_speed);
5417 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5418 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5419 /* 10/100/1000/20G-KR2 */
5421 /* Update those 1-copy registers */
5422 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5423 MDIO_AER_BLOCK_AER_REG, 0);
5424 /* Enable 1G MDIO (1-copy) */
5425 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5426 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5428 /* Set 1G loopback based on lane (1-copy) */
5429 lane = elink_get_warpcore_lane(phy, params);
5430 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5431 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
5433 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5435 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5436 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
5439 /* Switch back to 4-copy registers */
5440 elink_set_aer_mmd(params, phy);
5442 /* 10G / 20G-DXGXS */
5443 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5444 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5446 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5447 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
5453 static void elink_sync_link(struct elink_params *params,
5454 struct elink_vars *vars)
5456 struct bxe_softc *sc = params->sc;
5457 uint8_t link_10g_plus;
5458 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5459 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
5460 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
5461 if (vars->link_up) {
5462 ELINK_DEBUG_P0(sc, "phy link up\n");
5464 vars->phy_link_up = 1;
5465 vars->duplex = DUPLEX_FULL;
5466 switch (vars->link_status &
5467 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
5468 case ELINK_LINK_10THD:
5469 vars->duplex = DUPLEX_HALF;
5471 case ELINK_LINK_10TFD:
5472 vars->line_speed = ELINK_SPEED_10;
5475 case ELINK_LINK_100TXHD:
5476 vars->duplex = DUPLEX_HALF;
5478 case ELINK_LINK_100T4:
5479 case ELINK_LINK_100TXFD:
5480 vars->line_speed = ELINK_SPEED_100;
5483 case ELINK_LINK_1000THD:
5484 vars->duplex = DUPLEX_HALF;
5486 case ELINK_LINK_1000TFD:
5487 vars->line_speed = ELINK_SPEED_1000;
5490 case ELINK_LINK_2500THD:
5491 vars->duplex = DUPLEX_HALF;
5493 case ELINK_LINK_2500TFD:
5494 vars->line_speed = ELINK_SPEED_2500;
5497 case ELINK_LINK_10GTFD:
5498 vars->line_speed = ELINK_SPEED_10000;
5500 case ELINK_LINK_20GTFD:
5501 vars->line_speed = ELINK_SPEED_20000;
5506 vars->flow_ctrl = 0;
5507 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
5508 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
5510 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
5511 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
5513 if (!vars->flow_ctrl)
5514 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5516 if (vars->line_speed &&
5517 ((vars->line_speed == ELINK_SPEED_10) ||
5518 (vars->line_speed == ELINK_SPEED_100))) {
5519 vars->phy_flags |= PHY_SGMII_FLAG;
5521 vars->phy_flags &= ~PHY_SGMII_FLAG;
5523 if (vars->line_speed &&
5524 USES_WARPCORE(sc) &&
5525 (vars->line_speed == ELINK_SPEED_1000))
5526 vars->phy_flags |= PHY_SGMII_FLAG;
5527 /* Anything 10 and over uses the bmac */
5528 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
5530 if (link_10g_plus) {
5531 if (USES_WARPCORE(sc))
5532 vars->mac_type = ELINK_MAC_TYPE_XMAC;
5534 vars->mac_type = ELINK_MAC_TYPE_BMAC;
5536 if (USES_WARPCORE(sc))
5537 vars->mac_type = ELINK_MAC_TYPE_UMAC;
5539 vars->mac_type = ELINK_MAC_TYPE_EMAC;
5541 } else { /* Link down */
5542 ELINK_DEBUG_P0(sc, "phy link down\n");
5544 vars->phy_link_up = 0;
5546 vars->line_speed = 0;
5547 vars->duplex = DUPLEX_FULL;
5548 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5550 /* Indicate no mac active */
5551 vars->mac_type = ELINK_MAC_TYPE_NONE;
5552 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5553 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
5554 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
5555 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
5559 void elink_link_status_update(struct elink_params *params,
5560 struct elink_vars *vars)
5562 struct bxe_softc *sc = params->sc;
5563 uint8_t port = params->port;
5564 uint32_t sync_offset, media_types;
5565 /* Update PHY configuration */
5566 set_phy_vars(params, vars);
5568 vars->link_status = REG_RD(sc, params->shmem_base +
5569 offsetof(struct shmem_region,
5570 port_mb[port].link_status));
5572 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
5573 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
5574 params->loopback_mode != ELINK_LOOPBACK_EXT)
5575 vars->link_status |= LINK_STATUS_LINK_UP;
5577 if (elink_eee_has_cap(params))
5578 vars->eee_status = REG_RD(sc, params->shmem2_base +
5579 offsetof(struct shmem2_region,
5580 eee_status[params->port]));
5582 vars->phy_flags = PHY_XGXS_FLAG;
5583 elink_sync_link(params, vars);
5584 /* Sync media type */
5585 sync_offset = params->shmem_base +
5586 offsetof(struct shmem_region,
5587 dev_info.port_hw_config[port].media_type);
5588 media_types = REG_RD(sc, sync_offset);
5590 params->phy[ELINK_INT_PHY].media_type =
5591 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
5592 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
5593 params->phy[ELINK_EXT_PHY1].media_type =
5594 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
5595 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
5596 params->phy[ELINK_EXT_PHY2].media_type =
5597 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
5598 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
5599 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);
5601 /* Sync AEU offset */
5602 sync_offset = params->shmem_base +
5603 offsetof(struct shmem_region,
5604 dev_info.port_hw_config[port].aeu_int_mask);
5606 vars->aeu_int_mask = REG_RD(sc, sync_offset);
5608 /* Sync PFC status */
5609 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
5610 params->feature_config_flags |=
5611 ELINK_FEATURE_CONFIG_PFC_ENABLED;
5613 params->feature_config_flags &=
5614 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
5616 if (SHMEM2_HAS(sc, link_attr_sync))
5617 vars->link_attr_sync = SHMEM2_RD(sc,
5618 link_attr_sync[params->port]);
5620 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5621 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
5622 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5623 vars->line_speed, vars->duplex, vars->flow_ctrl);
5626 static void elink_set_master_ln(struct elink_params *params,
5627 struct elink_phy *phy)
5629 struct bxe_softc *sc = params->sc;
5630 uint16_t new_master_ln, ser_lane;
5631 ser_lane = ((params->lane_config &
5632 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5633 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5635 /* Set the master_ln for AN */
5636 CL22_RD_OVER_CL45(sc, phy,
5637 MDIO_REG_BANK_XGXS_BLOCK2,
5638 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5641 CL22_WR_OVER_CL45(sc, phy,
5642 MDIO_REG_BANK_XGXS_BLOCK2 ,
5643 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5644 (new_master_ln | ser_lane));
5647 static elink_status_t elink_reset_unicore(struct elink_params *params,
5648 struct elink_phy *phy,
5651 struct bxe_softc *sc = params->sc;
5652 uint16_t mii_control;
5654 CL22_RD_OVER_CL45(sc, phy,
5655 MDIO_REG_BANK_COMBO_IEEE0,
5656 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
5658 /* Reset the unicore */
5659 CL22_WR_OVER_CL45(sc, phy,
5660 MDIO_REG_BANK_COMBO_IEEE0,
5661 MDIO_COMBO_IEEE0_MII_CONTROL,
5663 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
5665 elink_set_serdes_access(sc, params->port);
5667 /* Wait for the reset to self clear */
5668 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
5671 /* The reset erased the previous bank value */
5672 CL22_RD_OVER_CL45(sc, phy,
5673 MDIO_REG_BANK_COMBO_IEEE0,
5674 MDIO_COMBO_IEEE0_MII_CONTROL,
5677 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
5679 return ELINK_STATUS_OK;
5683 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5686 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n");
5687 return ELINK_STATUS_ERROR;
5691 static void elink_set_swap_lanes(struct elink_params *params,
5692 struct elink_phy *phy)
5694 struct bxe_softc *sc = params->sc;
5695 /* Each two bits represents a lane number:
5696 * No swap is 0123 => 0x1b no need to enable the swap
5698 uint16_t rx_lane_swap, tx_lane_swap;
5700 rx_lane_swap = ((params->lane_config &
5701 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
5702 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
5703 tx_lane_swap = ((params->lane_config &
5704 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
5705 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
5707 if (rx_lane_swap != 0x1b) {
5708 CL22_WR_OVER_CL45(sc, phy,
5709 MDIO_REG_BANK_XGXS_BLOCK2,
5710 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
5712 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5713 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5715 CL22_WR_OVER_CL45(sc, phy,
5716 MDIO_REG_BANK_XGXS_BLOCK2,
5717 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5720 if (tx_lane_swap != 0x1b) {
5721 CL22_WR_OVER_CL45(sc, phy,
5722 MDIO_REG_BANK_XGXS_BLOCK2,
5723 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5725 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5727 CL22_WR_OVER_CL45(sc, phy,
5728 MDIO_REG_BANK_XGXS_BLOCK2,
5729 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5733 static void elink_set_parallel_detection(struct elink_phy *phy,
5734 struct elink_params *params)
5736 struct bxe_softc *sc = params->sc;
5738 CL22_RD_OVER_CL45(sc, phy,
5739 MDIO_REG_BANK_SERDES_DIGITAL,
5740 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5742 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5743 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5745 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5746 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5747 phy->speed_cap_mask, control2);
5748 CL22_WR_OVER_CL45(sc, phy,
5749 MDIO_REG_BANK_SERDES_DIGITAL,
5750 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5753 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5754 (phy->speed_cap_mask &
5755 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5756 ELINK_DEBUG_P0(sc, "XGXS\n");
5758 CL22_WR_OVER_CL45(sc, phy,
5759 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5760 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5761 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5763 CL22_RD_OVER_CL45(sc, phy,
5764 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5765 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5770 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5772 CL22_WR_OVER_CL45(sc, phy,
5773 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5774 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5777 /* Disable parallel detection of HiG */
5778 CL22_WR_OVER_CL45(sc, phy,
5779 MDIO_REG_BANK_XGXS_BLOCK2,
5780 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5781 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5782 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5786 static void elink_set_autoneg(struct elink_phy *phy,
5787 struct elink_params *params,
5788 struct elink_vars *vars,
5789 uint8_t enable_cl73)
5791 struct bxe_softc *sc = params->sc;
5795 CL22_RD_OVER_CL45(sc, phy,
5796 MDIO_REG_BANK_COMBO_IEEE0,
5797 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5799 /* CL37 Autoneg Enabled */
5800 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5801 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5802 else /* CL37 Autoneg Disabled */
5803 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5804 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5806 CL22_WR_OVER_CL45(sc, phy,
5807 MDIO_REG_BANK_COMBO_IEEE0,
5808 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5810 /* Enable/Disable Autodetection */
5812 CL22_RD_OVER_CL45(sc, phy,
5813 MDIO_REG_BANK_SERDES_DIGITAL,
5814 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5815 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5816 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5817 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5818 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5819 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5821 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5823 CL22_WR_OVER_CL45(sc, phy,
5824 MDIO_REG_BANK_SERDES_DIGITAL,
5825 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5827 /* Enable TetonII and BAM autoneg */
5828 CL22_RD_OVER_CL45(sc, phy,
5829 MDIO_REG_BANK_BAM_NEXT_PAGE,
5830 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5832 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
5833 /* Enable BAM aneg Mode and TetonII aneg Mode */
5834 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5835 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5837 /* TetonII and BAM Autoneg Disabled */
5838 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5839 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5841 CL22_WR_OVER_CL45(sc, phy,
5842 MDIO_REG_BANK_BAM_NEXT_PAGE,
5843 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5847 /* Enable Cl73 FSM status bits */
5848 CL22_WR_OVER_CL45(sc, phy,
5849 MDIO_REG_BANK_CL73_USERB0,
5850 MDIO_CL73_USERB0_CL73_UCTRL,
5853 /* Enable BAM Station Manager*/
5854 CL22_WR_OVER_CL45(sc, phy,
5855 MDIO_REG_BANK_CL73_USERB0,
5856 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5857 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5858 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5859 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5861 /* Advertise CL73 link speeds */
5862 CL22_RD_OVER_CL45(sc, phy,
5863 MDIO_REG_BANK_CL73_IEEEB1,
5864 MDIO_CL73_IEEEB1_AN_ADV2,
5866 if (phy->speed_cap_mask &
5867 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5868 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5869 if (phy->speed_cap_mask &
5870 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5871 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5873 CL22_WR_OVER_CL45(sc, phy,
5874 MDIO_REG_BANK_CL73_IEEEB1,
5875 MDIO_CL73_IEEEB1_AN_ADV2,
5878 /* CL73 Autoneg Enabled */
5879 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5881 } else /* CL73 Autoneg Disabled */
5884 CL22_WR_OVER_CL45(sc, phy,
5885 MDIO_REG_BANK_CL73_IEEEB0,
5886 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5889 /* Program SerDes, forced speed */
5890 static void elink_program_serdes(struct elink_phy *phy,
5891 struct elink_params *params,
5892 struct elink_vars *vars)
5894 struct bxe_softc *sc = params->sc;
5897 /* Program duplex, disable autoneg and sgmii*/
5898 CL22_RD_OVER_CL45(sc, phy,
5899 MDIO_REG_BANK_COMBO_IEEE0,
5900 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5901 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5902 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5903 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5904 if (phy->req_duplex == DUPLEX_FULL)
5905 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5906 CL22_WR_OVER_CL45(sc, phy,
5907 MDIO_REG_BANK_COMBO_IEEE0,
5908 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5911 * - needed only if the speed is greater than 1G (2.5G or 10G)
5913 CL22_RD_OVER_CL45(sc, phy,
5914 MDIO_REG_BANK_SERDES_DIGITAL,
5915 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5916 /* Clearing the speed value before setting the right speed */
5917 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5919 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5920 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5922 if (!((vars->line_speed == ELINK_SPEED_1000) ||
5923 (vars->line_speed == ELINK_SPEED_100) ||
5924 (vars->line_speed == ELINK_SPEED_10))) {
5926 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5927 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5928 if (vars->line_speed == ELINK_SPEED_10000)
5930 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5933 CL22_WR_OVER_CL45(sc, phy,
5934 MDIO_REG_BANK_SERDES_DIGITAL,
5935 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5939 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
5940 struct elink_params *params)
5942 struct bxe_softc *sc = params->sc;
5945 /* Set extended capabilities */
5946 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5947 val |= MDIO_OVER_1G_UP1_2_5G;
5948 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5949 val |= MDIO_OVER_1G_UP1_10G;
5950 CL22_WR_OVER_CL45(sc, phy,
5951 MDIO_REG_BANK_OVER_1G,
5952 MDIO_OVER_1G_UP1, val);
5954 CL22_WR_OVER_CL45(sc, phy,
5955 MDIO_REG_BANK_OVER_1G,
5956 MDIO_OVER_1G_UP3, 0x400);
5959 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
5960 struct elink_params *params,
5963 struct bxe_softc *sc = params->sc;
5965 /* For AN, we are always publishing full duplex */
5967 CL22_WR_OVER_CL45(sc, phy,
5968 MDIO_REG_BANK_COMBO_IEEE0,
5969 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5970 CL22_RD_OVER_CL45(sc, phy,
5971 MDIO_REG_BANK_CL73_IEEEB1,
5972 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5973 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5974 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5975 CL22_WR_OVER_CL45(sc, phy,
5976 MDIO_REG_BANK_CL73_IEEEB1,
5977 MDIO_CL73_IEEEB1_AN_ADV1, val);
5980 static void elink_restart_autoneg(struct elink_phy *phy,
5981 struct elink_params *params,
5982 uint8_t enable_cl73)
5984 struct bxe_softc *sc = params->sc;
5985 uint16_t mii_control;
5987 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n");
5988 /* Enable and restart BAM/CL37 aneg */
5991 CL22_RD_OVER_CL45(sc, phy,
5992 MDIO_REG_BANK_CL73_IEEEB0,
5993 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5996 CL22_WR_OVER_CL45(sc, phy,
5997 MDIO_REG_BANK_CL73_IEEEB0,
5998 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6000 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
6001 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
6004 CL22_RD_OVER_CL45(sc, phy,
6005 MDIO_REG_BANK_COMBO_IEEE0,
6006 MDIO_COMBO_IEEE0_MII_CONTROL,
6009 "elink_restart_autoneg mii_control before = 0x%x\n",
6011 CL22_WR_OVER_CL45(sc, phy,
6012 MDIO_REG_BANK_COMBO_IEEE0,
6013 MDIO_COMBO_IEEE0_MII_CONTROL,
6015 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6016 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
6020 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6021 struct elink_params *params,
6022 struct elink_vars *vars)
6024 struct bxe_softc *sc = params->sc;
6027 /* In SGMII mode, the unicore is always slave */
6029 CL22_RD_OVER_CL45(sc, phy,
6030 MDIO_REG_BANK_SERDES_DIGITAL,
6031 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6033 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
6034 /* Set sgmii mode (and not fiber) */
6035 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
6036 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
6037 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
6038 CL22_WR_OVER_CL45(sc, phy,
6039 MDIO_REG_BANK_SERDES_DIGITAL,
6040 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6043 /* If forced speed */
6044 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
6045 /* Set speed, disable autoneg */
6046 uint16_t mii_control;
6048 CL22_RD_OVER_CL45(sc, phy,
6049 MDIO_REG_BANK_COMBO_IEEE0,
6050 MDIO_COMBO_IEEE0_MII_CONTROL,
6052 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6053 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
6054 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
6056 switch (vars->line_speed) {
6057 case ELINK_SPEED_100:
6059 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
6061 case ELINK_SPEED_1000:
6063 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
6065 case ELINK_SPEED_10:
6066 /* There is nothing to set for 10M */
6069 /* Invalid speed for SGMII */
6070 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6075 /* Setting the full duplex */
6076 if (phy->req_duplex == DUPLEX_FULL)
6078 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
6079 CL22_WR_OVER_CL45(sc, phy,
6080 MDIO_REG_BANK_COMBO_IEEE0,
6081 MDIO_COMBO_IEEE0_MII_CONTROL,
6084 } else { /* AN mode */
6085 /* Enable and restart AN */
6086 elink_restart_autoneg(phy, params, 0);
6092 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6093 struct elink_params *params)
6095 struct bxe_softc *sc = params->sc;
6096 uint16_t pd_10g, status2_1000x;
6097 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6098 return ELINK_STATUS_OK;
6099 CL22_RD_OVER_CL45(sc, phy,
6100 MDIO_REG_BANK_SERDES_DIGITAL,
6101 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6103 CL22_RD_OVER_CL45(sc, phy,
6104 MDIO_REG_BANK_SERDES_DIGITAL,
6105 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6107 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
6108 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6113 CL22_RD_OVER_CL45(sc, phy,
6114 MDIO_REG_BANK_10G_PARALLEL_DETECT,
6115 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
6118 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
6119 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6123 return ELINK_STATUS_OK;
6126 static void elink_update_adv_fc(struct elink_phy *phy,
6127 struct elink_params *params,
6128 struct elink_vars *vars,
6131 uint16_t ld_pause; /* local driver */
6132 uint16_t lp_pause; /* link partner */
6133 uint16_t pause_result;
6134 struct bxe_softc *sc = params->sc;
6136 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6137 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
6138 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6139 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
6141 CL22_RD_OVER_CL45(sc, phy,
6142 MDIO_REG_BANK_CL73_IEEEB1,
6143 MDIO_CL73_IEEEB1_AN_ADV1,
6145 CL22_RD_OVER_CL45(sc, phy,
6146 MDIO_REG_BANK_CL73_IEEEB1,
6147 MDIO_CL73_IEEEB1_AN_LP_ADV1,
6149 pause_result = (ld_pause &
6150 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
6151 pause_result |= (lp_pause &
6152 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
6153 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);
6155 CL22_RD_OVER_CL45(sc, phy,
6156 MDIO_REG_BANK_COMBO_IEEE0,
6157 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
6159 CL22_RD_OVER_CL45(sc, phy,
6160 MDIO_REG_BANK_COMBO_IEEE0,
6161 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
6163 pause_result = (ld_pause &
6164 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
6165 pause_result |= (lp_pause &
6166 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
6167 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);
6169 elink_pause_resolve(vars, pause_result);
6173 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6174 struct elink_params *params,
6175 struct elink_vars *vars,
6178 struct bxe_softc *sc = params->sc;
6179 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6181 /* Resolve from gp_status in case of AN complete and not sgmii */
6182 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6183 /* Update the advertised flow-controled of LD/LP in AN */
6184 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6185 elink_update_adv_fc(phy, params, vars, gp_status);
6186 /* But set the flow-control result as the requested one */
6187 vars->flow_ctrl = phy->req_flow_ctrl;
6188 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6189 vars->flow_ctrl = params->req_fc_auto_adv;
6190 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
6191 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
6192 if (elink_direct_parallel_detect_used(phy, params)) {
6193 vars->flow_ctrl = params->req_fc_auto_adv;
6196 elink_update_adv_fc(phy, params, vars, gp_status);
6198 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6201 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6202 struct elink_params *params)
6204 struct bxe_softc *sc = params->sc;
6205 uint16_t rx_status, ustat_val, cl37_fsm_received;
6206 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n");
6207 /* Step 1: Make sure signal is detected */
6208 CL22_RD_OVER_CL45(sc, phy,
6212 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
6213 (MDIO_RX0_RX_STATUS_SIGDET)) {
6214 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
6215 "rx_status(0x80b0) = 0x%x\n", rx_status);
6216 CL22_WR_OVER_CL45(sc, phy,
6217 MDIO_REG_BANK_CL73_IEEEB0,
6218 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6219 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
6222 /* Step 2: Check CL73 state machine */
6223 CL22_RD_OVER_CL45(sc, phy,
6224 MDIO_REG_BANK_CL73_USERB0,
6225 MDIO_CL73_USERB0_CL73_USTAT1,
6228 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6229 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
6230 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6231 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
6232 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
6233 "ustat_val(0x8371) = 0x%x\n", ustat_val);
6236 /* Step 3: Check CL37 Message Pages received to indicate LP
6237 * supports only CL37
6239 CL22_RD_OVER_CL45(sc, phy,
6240 MDIO_REG_BANK_REMOTE_PHY,
6241 MDIO_REMOTE_PHY_MISC_RX_STATUS,
6242 &cl37_fsm_received);
6243 if ((cl37_fsm_received &
6244 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6245 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
6246 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6247 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
6248 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
6249 "misc_rx_status(0x8330) = 0x%x\n",
6253 /* The combined cl37/cl73 fsm state information indicating that
6254 * we are connected to a device which does not support cl73, but
6255 * does support cl37 BAM. In this case we disable cl73 and
6256 * restart cl37 auto-neg
6260 CL22_WR_OVER_CL45(sc, phy,
6261 MDIO_REG_BANK_CL73_IEEEB0,
6262 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6264 /* Restart CL37 autoneg */
6265 elink_restart_autoneg(phy, params, 0);
6266 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n");
6269 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6270 struct elink_params *params,
6271 struct elink_vars *vars,
6274 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
6275 vars->link_status |=
6276 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6278 if (elink_direct_parallel_detect_used(phy, params))
6279 vars->link_status |=
6280 LINK_STATUS_PARALLEL_DETECTION_USED;
6282 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6283 struct elink_params *params,
6284 struct elink_vars *vars,
6285 uint16_t is_link_up,
6286 uint16_t speed_mask,
6289 struct bxe_softc *sc = params->sc;
6290 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6291 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
6293 ELINK_DEBUG_P0(sc, "phy link up\n");
6295 vars->phy_link_up = 1;
6296 vars->link_status |= LINK_STATUS_LINK_UP;
6298 switch (speed_mask) {
6299 case ELINK_GP_STATUS_10M:
6300 vars->line_speed = ELINK_SPEED_10;
6301 if (is_duplex == DUPLEX_FULL)
6302 vars->link_status |= ELINK_LINK_10TFD;
6304 vars->link_status |= ELINK_LINK_10THD;
6307 case ELINK_GP_STATUS_100M:
6308 vars->line_speed = ELINK_SPEED_100;
6309 if (is_duplex == DUPLEX_FULL)
6310 vars->link_status |= ELINK_LINK_100TXFD;
6312 vars->link_status |= ELINK_LINK_100TXHD;
6315 case ELINK_GP_STATUS_1G:
6316 case ELINK_GP_STATUS_1G_KX:
6317 vars->line_speed = ELINK_SPEED_1000;
6318 if (is_duplex == DUPLEX_FULL)
6319 vars->link_status |= ELINK_LINK_1000TFD;
6321 vars->link_status |= ELINK_LINK_1000THD;
6324 case ELINK_GP_STATUS_2_5G:
6325 vars->line_speed = ELINK_SPEED_2500;
6326 if (is_duplex == DUPLEX_FULL)
6327 vars->link_status |= ELINK_LINK_2500TFD;
6329 vars->link_status |= ELINK_LINK_2500THD;
6332 case ELINK_GP_STATUS_5G:
6333 case ELINK_GP_STATUS_6G:
6335 "link speed unsupported gp_status 0x%x\n",
6337 return ELINK_STATUS_ERROR;
6339 case ELINK_GP_STATUS_10G_KX4:
6340 case ELINK_GP_STATUS_10G_HIG:
6341 case ELINK_GP_STATUS_10G_CX4:
6342 case ELINK_GP_STATUS_10G_KR:
6343 case ELINK_GP_STATUS_10G_SFI:
6344 case ELINK_GP_STATUS_10G_XFI:
6345 vars->line_speed = ELINK_SPEED_10000;
6346 vars->link_status |= ELINK_LINK_10GTFD;
6348 case ELINK_GP_STATUS_20G_DXGXS:
6349 case ELINK_GP_STATUS_20G_KR2:
6350 vars->line_speed = ELINK_SPEED_20000;
6351 vars->link_status |= ELINK_LINK_20GTFD;
6355 "link speed unsupported gp_status 0x%x\n",
6357 return ELINK_STATUS_ERROR;
6359 } else { /* link_down */
6360 ELINK_DEBUG_P0(sc, "phy link down\n");
6362 vars->phy_link_up = 0;
6364 vars->duplex = DUPLEX_FULL;
6365 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6366 vars->mac_type = ELINK_MAC_TYPE_NONE;
6368 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n",
6369 vars->phy_link_up, vars->line_speed);
6370 return ELINK_STATUS_OK;
6373 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6374 struct elink_params *params,
6375 struct elink_vars *vars)
6377 struct bxe_softc *sc = params->sc;
6379 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
6380 elink_status_t rc = ELINK_STATUS_OK;
6382 /* Read gp_status */
6383 CL22_RD_OVER_CL45(sc, phy,
6384 MDIO_REG_BANK_GP_STATUS,
6385 MDIO_GP_STATUS_TOP_AN_STATUS1,
6387 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
6388 duplex = DUPLEX_FULL;
6389 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
6391 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
6392 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6393 gp_status, link_up, speed_mask);
6394 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6396 if (rc == ELINK_STATUS_ERROR)
6399 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
6400 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6401 vars->duplex = duplex;
6402 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6403 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6404 elink_xgxs_an_resolve(phy, params, vars,
6407 } else { /* Link_down */
6408 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6409 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6410 /* Check signal is detected */
6411 elink_check_fallback_to_cl37(phy, params);
6415 /* Read LP advertised speeds*/
6416 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6417 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
6420 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6421 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
6423 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6424 vars->link_status |=
6425 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6426 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6427 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6428 vars->link_status |=
6429 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6431 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6432 MDIO_OVER_1G_LP_UP1, &val);
6434 if (val & MDIO_OVER_1G_UP1_2_5G)
6435 vars->link_status |=
6436 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6437 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6438 vars->link_status |=
6439 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6442 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6443 vars->duplex, vars->flow_ctrl, vars->link_status);
6447 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6448 struct elink_params *params,
6449 struct elink_vars *vars)
6451 struct bxe_softc *sc = params->sc;
6453 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
6454 elink_status_t rc = ELINK_STATUS_OK;
6455 lane = elink_get_warpcore_lane(phy, params);
6456 /* Read gp_status */
6457 if ((params->loopback_mode) &&
6458 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6459 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6460 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6461 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6462 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6464 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6465 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6466 uint16_t temp_link_up;
6467 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6469 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6471 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",
6472 temp_link_up, link_up);
6475 elink_ext_phy_resolve_fc(phy, params, vars);
6477 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6478 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6480 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);
6481 /* Check for either KR, 1G, or AN up. */
6482 link_up = ((gp_status1 >> 8) |
6483 (gp_status1 >> 12) |
6486 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6488 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6489 MDIO_AN_REG_STATUS, &an_link);
6490 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6491 MDIO_AN_REG_STATUS, &an_link);
6492 link_up |= (an_link & (1<<2));
6494 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
6495 uint16_t pd, gp_status4;
6496 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6497 /* Check Autoneg complete */
6498 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6499 MDIO_WC_REG_GP2_STATUS_GP_2_4,
6501 if (gp_status4 & ((1<<12)<<lane))
6502 vars->link_status |=
6503 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6505 /* Check parallel detect used */
6506 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6507 MDIO_WC_REG_PAR_DET_10G_STATUS,
6510 vars->link_status |=
6511 LINK_STATUS_PARALLEL_DETECTION_USED;
6513 elink_ext_phy_resolve_fc(phy, params, vars);
6514 vars->duplex = duplex;
6518 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
6519 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6522 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6523 MDIO_AN_REG_LP_AUTO_NEG2, &val);
6525 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6526 vars->link_status |=
6527 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6528 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6529 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6530 vars->link_status |=
6531 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6533 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6534 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
6536 if (val & MDIO_OVER_1G_UP1_2_5G)
6537 vars->link_status |=
6538 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6539 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6540 vars->link_status |=
6541 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6547 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6548 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
6550 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6551 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
6553 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6555 if ((lane & 1) == 0)
6558 link_up = !!link_up;
6560 /* Reset the TX FIFO to fix SGMII issue */
6561 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6564 /* In case of KR link down, start up the recovering procedure */
6565 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6566 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6567 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
6569 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6570 vars->duplex, vars->flow_ctrl, vars->link_status);
6573 static void elink_set_gmii_tx_driver(struct elink_params *params)
6575 struct bxe_softc *sc = params->sc;
6576 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6582 CL22_RD_OVER_CL45(sc, phy,
6583 MDIO_REG_BANK_OVER_1G,
6584 MDIO_OVER_1G_LP_UP2, &lp_up2);
6586 /* Bits [10:7] at lp_up2, positioned at [15:12] */
6587 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
6588 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
6589 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
6594 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
6595 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
6596 CL22_RD_OVER_CL45(sc, phy,
6598 MDIO_TX0_TX_DRIVER, &tx_driver);
6600 /* Replace tx_driver bits [15:12] */
6602 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
6603 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
6604 tx_driver |= lp_up2;
6605 CL22_WR_OVER_CL45(sc, phy,
6607 MDIO_TX0_TX_DRIVER, tx_driver);
6612 static elink_status_t elink_emac_program(struct elink_params *params,
6613 struct elink_vars *vars)
6615 struct bxe_softc *sc = params->sc;
6616 uint8_t port = params->port;
6619 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n");
6620 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6622 (EMAC_MODE_25G_MODE |
6623 EMAC_MODE_PORT_MII_10M |
6624 EMAC_MODE_HALF_DUPLEX));
6625 switch (vars->line_speed) {
6626 case ELINK_SPEED_10:
6627 mode |= EMAC_MODE_PORT_MII_10M;
6630 case ELINK_SPEED_100:
6631 mode |= EMAC_MODE_PORT_MII;
6634 case ELINK_SPEED_1000:
6635 mode |= EMAC_MODE_PORT_GMII;
6638 case ELINK_SPEED_2500:
6639 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
6643 /* 10G not valid for EMAC */
6644 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6646 return ELINK_STATUS_ERROR;
6649 if (vars->duplex == DUPLEX_HALF)
6650 mode |= EMAC_MODE_HALF_DUPLEX;
6652 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6655 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
6656 return ELINK_STATUS_OK;
6659 static void elink_set_preemphasis(struct elink_phy *phy,
6660 struct elink_params *params)
6663 uint16_t bank, i = 0;
6664 struct bxe_softc *sc = params->sc;
6666 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
6667 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
6668 CL22_WR_OVER_CL45(sc, phy,
6670 MDIO_RX0_RX_EQ_BOOST,
6671 phy->rx_preemphasis[i]);
6674 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
6675 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
6676 CL22_WR_OVER_CL45(sc, phy,
6679 phy->tx_preemphasis[i]);
6683 static void elink_xgxs_config_init(struct elink_phy *phy,
6684 struct elink_params *params,
6685 struct elink_vars *vars)
6687 struct bxe_softc *sc = params->sc;
6688 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6689 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6690 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
6691 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6692 (params->feature_config_flags &
6693 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
6694 elink_set_preemphasis(phy, params);
6696 /* Forced speed requested? */
6697 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
6698 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6699 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
6700 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n");
6702 /* Disable autoneg */
6703 elink_set_autoneg(phy, params, vars, 0);
6705 /* Program speed and duplex */
6706 elink_program_serdes(phy, params, vars);
6708 } else { /* AN_mode */
6709 ELINK_DEBUG_P0(sc, "not SGMII, AN\n");
6712 elink_set_brcm_cl37_advertisement(phy, params);
6714 /* Program duplex & pause advertisement (for aneg) */
6715 elink_set_ieee_aneg_advertisement(phy, params,
6718 /* Enable autoneg */
6719 elink_set_autoneg(phy, params, vars, enable_cl73);
6721 /* Enable and restart AN */
6722 elink_restart_autoneg(phy, params, enable_cl73);
6725 } else { /* SGMII mode */
6726 ELINK_DEBUG_P0(sc, "SGMII\n");
6728 elink_initialize_sgmii_process(phy, params, vars);
6732 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6733 struct elink_params *params,
6734 struct elink_vars *vars)
6737 vars->phy_flags |= PHY_XGXS_FLAG;
6738 if ((phy->req_line_speed &&
6739 ((phy->req_line_speed == ELINK_SPEED_100) ||
6740 (phy->req_line_speed == ELINK_SPEED_10))) ||
6741 (!phy->req_line_speed &&
6742 (phy->speed_cap_mask >=
6743 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6744 (phy->speed_cap_mask <
6745 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6746 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6747 vars->phy_flags |= PHY_SGMII_FLAG;
6749 vars->phy_flags &= ~PHY_SGMII_FLAG;
6751 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6752 elink_set_aer_mmd(params, phy);
6753 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6754 elink_set_master_ln(params, phy);
6756 rc = elink_reset_unicore(params, phy, 0);
6757 /* Reset the SerDes and wait for reset bit return low */
6758 if (rc != ELINK_STATUS_OK)
6761 elink_set_aer_mmd(params, phy);
6762 /* Setting the masterLn_def again after the reset */
6763 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6764 elink_set_master_ln(params, phy);
6765 elink_set_swap_lanes(params, phy);
6771 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc,
6772 struct elink_phy *phy,
6773 struct elink_params *params)
6776 /* Wait for soft reset to get cleared up to 1 sec */
6777 for (cnt = 0; cnt < 1000; cnt++) {
6778 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6779 elink_cl22_read(sc, phy,
6780 MDIO_PMA_REG_CTRL, &ctrl);
6782 elink_cl45_read(sc, phy,
6784 MDIO_PMA_REG_CTRL, &ctrl);
6785 if (!(ctrl & (1<<15)))
6791 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6794 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6798 static void elink_link_int_enable(struct elink_params *params)
6800 uint8_t port = params->port;
6802 struct bxe_softc *sc = params->sc;
6804 /* Setting the status to report on link up for either XGXS or SerDes */
6805 if (CHIP_IS_E3(sc)) {
6806 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
6807 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
6808 mask |= ELINK_NIG_MASK_MI_INT;
6809 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6810 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
6811 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
6812 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n");
6813 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6814 params->phy[ELINK_INT_PHY].type !=
6815 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6816 mask |= ELINK_NIG_MASK_MI_INT;
6817 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6820 } else { /* SerDes */
6821 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
6822 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n");
6823 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6824 params->phy[ELINK_INT_PHY].type !=
6825 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6826 mask |= ELINK_NIG_MASK_MI_INT;
6827 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6831 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6834 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6835 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
6836 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6837 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6838 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6839 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6840 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6841 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
6842 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6843 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6846 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6849 uint32_t latch_status = 0;
6851 /* Disable the MI INT ( external phy int ) by writing 1 to the
6852 * status register. Link down indication is high-active-signal,
6853 * so in this case we need to write the status to clear the XOR
6855 /* Read Latched signals */
6856 latch_status = REG_RD(sc,
6857 NIG_REG_LATCH_STATUS_0 + port*8);
6858 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);
6859 /* Handle only those with latched-signal=up.*/
6862 NIG_REG_STATUS_INTERRUPT_PORT0
6864 ELINK_NIG_STATUS_EMAC0_MI_INT);
6867 NIG_REG_STATUS_INTERRUPT_PORT0
6869 ELINK_NIG_STATUS_EMAC0_MI_INT);
6871 if (latch_status & 1) {
6873 /* For all latched-signal=up : Re-Arm Latch signals */
6874 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6875 (latch_status & 0xfffe) | (latch_status & 1));
6877 /* For all latched-signal=up,Write original_signal to status */
6880 static void elink_link_int_ack(struct elink_params *params,
6881 struct elink_vars *vars, uint8_t is_10g_plus)
6883 struct bxe_softc *sc = params->sc;
6884 uint8_t port = params->port;
6886 /* First reset all status we assume only one line will be
6889 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6890 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6891 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6892 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
6893 if (vars->phy_link_up) {
6894 if (USES_WARPCORE(sc))
6895 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
6898 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
6899 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6900 /* Disable the link interrupt by writing 1 to
6901 * the relevant lane in the status register
6904 ((params->lane_config &
6905 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6906 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6907 mask = ((1 << ser_lane) <<
6908 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6910 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
6912 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",
6915 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6920 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len)
6922 uint8_t *str_ptr = str;
6923 uint32_t mask = 0xf0000000;
6924 uint8_t shift = 8*4;
6926 uint8_t remove_leading_zeros = 1;
6928 /* Need more than 10chars for this format */
6931 return ELINK_STATUS_ERROR;
6936 digit = ((num & mask) >> shift);
6937 if (digit == 0 && remove_leading_zeros) {
6940 } else if (digit < 0xa)
6941 *str_ptr = digit + '0';
6943 *str_ptr = digit - 0xa + 'a';
6944 remove_leading_zeros = 0;
6952 remove_leading_zeros = 1;
6955 return ELINK_STATUS_OK;
6959 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
6963 return ELINK_STATUS_OK;
6966 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
6969 struct bxe_softc *sc;
6970 uint32_t spirom_ver = 0;
6971 elink_status_t status = ELINK_STATUS_OK;
6972 uint8_t *ver_p = version;
6973 uint16_t remain_len = len;
6974 if (version == NULL || params == NULL)
6975 return ELINK_STATUS_ERROR;
6978 /* Extract first external phy*/
6980 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
6982 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
6983 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
6986 ver_p += (len - remain_len);
6988 if ((params->num_phys == ELINK_MAX_PHYS) &&
6989 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
6990 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
6991 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
6995 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
6999 ver_p = version + (len - remain_len);
7006 static void elink_set_xgxs_loopback(struct elink_phy *phy,
7007 struct elink_params *params)
7009 uint8_t port = params->port;
7010 struct bxe_softc *sc = params->sc;
7012 if (phy->req_line_speed != ELINK_SPEED_1000) {
7013 uint32_t md_devad = 0;
7015 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n");
7017 if (!CHIP_IS_E3(sc)) {
7018 /* Change the uni_phy_addr in the nig */
7019 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7022 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7026 elink_cl45_write(sc, phy,
7028 (MDIO_REG_BANK_AER_BLOCK +
7029 (MDIO_AER_BLOCK_AER_REG & 0xf)),
7032 elink_cl45_write(sc, phy,
7034 (MDIO_REG_BANK_CL73_IEEEB0 +
7035 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
7038 /* Set aer mmd back */
7039 elink_set_aer_mmd(params, phy);
7041 if (!CHIP_IS_E3(sc)) {
7043 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7048 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n");
7049 elink_cl45_read(sc, phy, 5,
7050 (MDIO_REG_BANK_COMBO_IEEE0 +
7051 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7053 elink_cl45_write(sc, phy, 5,
7054 (MDIO_REG_BANK_COMBO_IEEE0 +
7055 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7057 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
7061 elink_status_t elink_set_led(struct elink_params *params,
7062 struct elink_vars *vars, uint8_t mode, uint32_t speed)
7064 uint8_t port = params->port;
7065 uint16_t hw_led_mode = params->hw_led_mode;
7066 elink_status_t rc = ELINK_STATUS_OK;
7069 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7070 struct bxe_softc *sc = params->sc;
7071 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7072 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",
7073 speed, hw_led_mode);
7075 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7076 if (params->phy[phy_idx].set_link_led) {
7077 params->phy[phy_idx].set_link_led(
7078 ¶ms->phy[phy_idx], params, mode);
7081 #ifdef ELINK_INCLUDE_EMUL
7082 if (params->feature_config_flags &
7083 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
7088 case ELINK_LED_MODE_FRONT_PANEL_OFF:
7089 case ELINK_LED_MODE_OFF:
7090 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7091 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7092 SHARED_HW_CFG_LED_MAC1);
7094 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7095 if (params->phy[ELINK_EXT_PHY1].type ==
7096 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
7097 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
7098 EMAC_LED_100MB_OVERRIDE |
7099 EMAC_LED_10MB_OVERRIDE);
7101 tmp |= EMAC_LED_OVERRIDE;
7103 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
7106 case ELINK_LED_MODE_OPER:
7107 /* For all other phys, OPER mode is same as ON, so in case
7108 * link is down, do nothing
7112 case ELINK_LED_MODE_ON:
7113 if (((params->phy[ELINK_EXT_PHY1].type ==
7114 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
7115 (params->phy[ELINK_EXT_PHY1].type ==
7116 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
7117 CHIP_IS_E2(sc) && params->num_phys == 2) {
7118 /* This is a work-around for E2+8727 Configurations */
7119 if (mode == ELINK_LED_MODE_ON ||
7120 speed == ELINK_SPEED_10000){
7121 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7122 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7124 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7125 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7126 (tmp | EMAC_LED_OVERRIDE));
7127 /* Return here without enabling traffic
7128 * LED blink and setting rate in ON mode.
7129 * In oper mode, enabling LED blink
7130 * and setting rate is needed.
7132 if (mode == ELINK_LED_MODE_ON)
7135 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
7136 /* This is a work-around for HW issue found when link
7139 if ((!CHIP_IS_E3(sc)) ||
7141 mode == ELINK_LED_MODE_ON))
7142 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7144 if (CHIP_IS_E1x(sc) ||
7146 (mode == ELINK_LED_MODE_ON))
7147 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7149 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7151 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7152 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
7153 (mode == ELINK_LED_MODE_ON)) {
7154 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7155 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7156 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp |
7157 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
7158 /* Break here; otherwise, it'll disable the
7159 * intended override.
7163 uint32_t nig_led_mode = ((params->hw_led_mode <<
7164 SHARED_HW_CFG_LED_MODE_SHIFT) ==
7165 SHARED_HW_CFG_LED_EXTPHY2) ?
7166 (SHARED_HW_CFG_LED_PHY1 >>
7167 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
7168 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7172 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7173 /* Set blinking rate to ~15.9Hz */
7175 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7176 LED_BLINK_RATE_VAL_E3);
7178 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7179 LED_BLINK_RATE_VAL_E1X_E2);
7180 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7182 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7183 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7184 (tmp & (~EMAC_LED_OVERRIDE)));
7186 if (CHIP_IS_E1(sc) &&
7187 ((speed == ELINK_SPEED_2500) ||
7188 (speed == ELINK_SPEED_1000) ||
7189 (speed == ELINK_SPEED_100) ||
7190 (speed == ELINK_SPEED_10))) {
7191 /* For speeds less than 10G LED scheme is different */
7192 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7194 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7196 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7202 rc = ELINK_STATUS_ERROR;
7203 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n",
7211 /* This function comes to reflect the actual link state read DIRECTLY from the
7214 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
7217 struct bxe_softc *sc = params->sc;
7218 uint16_t gp_status = 0, phy_index = 0;
7219 uint8_t ext_phy_link_up = 0, serdes_phy_type;
7220 struct elink_vars temp_vars;
7221 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7222 #ifdef ELINK_INCLUDE_FPGA
7223 if (CHIP_REV_IS_FPGA(sc))
7224 return ELINK_STATUS_OK;
7226 #ifdef ELINK_INCLUDE_EMUL
7227 if (CHIP_REV_IS_EMUL(sc))
7228 return ELINK_STATUS_OK;
7231 if (CHIP_IS_E3(sc)) {
7233 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
7234 > ELINK_SPEED_10000) {
7235 /* Check 20G link */
7236 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7238 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7242 /* Check 10G link and below*/
7243 uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7244 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7245 MDIO_WC_REG_GP2_STATUS_GP_2_1,
7247 gp_status = ((gp_status >> 8) & 0xf) |
7248 ((gp_status >> 12) & 0xf);
7249 link_up = gp_status & (1 << lane);
7252 return ELINK_STATUS_NO_LINK;
7254 CL22_RD_OVER_CL45(sc, int_phy,
7255 MDIO_REG_BANK_GP_STATUS,
7256 MDIO_GP_STATUS_TOP_AN_STATUS1,
7258 /* Link is up only if both local phy and external phy are up */
7259 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
7260 return ELINK_STATUS_NO_LINK;
7262 /* In XGXS loopback mode, do not check external PHY */
7263 if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
7264 return ELINK_STATUS_OK;
7266 switch (params->num_phys) {
7268 /* No external PHY */
7269 return ELINK_STATUS_OK;
7271 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7272 ¶ms->phy[ELINK_EXT_PHY1],
7273 params, &temp_vars);
7275 case 3: /* Dual Media */
7276 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7278 serdes_phy_type = ((params->phy[phy_index].media_type ==
7279 ELINK_ETH_PHY_SFPP_10G_FIBER) ||
7280 (params->phy[phy_index].media_type ==
7281 ELINK_ETH_PHY_SFP_1G_FIBER) ||
7282 (params->phy[phy_index].media_type ==
7283 ELINK_ETH_PHY_XFP_FIBER) ||
7284 (params->phy[phy_index].media_type ==
7285 ELINK_ETH_PHY_DA_TWINAX));
7287 if (is_serdes != serdes_phy_type)
7289 if (params->phy[phy_index].read_status) {
7291 params->phy[phy_index].read_status(
7292 ¶ms->phy[phy_index],
7293 params, &temp_vars);
7298 if (ext_phy_link_up)
7299 return ELINK_STATUS_OK;
7300 return ELINK_STATUS_NO_LINK;
7303 static elink_status_t elink_link_initialize(struct elink_params *params,
7304 struct elink_vars *vars)
7306 elink_status_t rc = ELINK_STATUS_OK;
7307 uint8_t phy_index, non_ext_phy;
7308 struct bxe_softc *sc = params->sc;
7309 /* In case of external phy existence, the line speed would be the
7310 * line speed linked up by the external phy. In case it is direct
7311 * only, then the line_speed during initialization will be
7312 * equal to the req_line_speed
7314 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7316 /* Initialize the internal phy in case this is a direct board
7317 * (no external phys), or this board has external phy which requires
7320 if (!USES_WARPCORE(sc))
7321 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7322 /* init ext phy and enable link state int */
7323 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
7324 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
7327 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7328 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7329 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7330 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7333 elink_set_parallel_detection(phy, params);
7334 if (params->phy[ELINK_INT_PHY].config_init)
7335 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7338 /* Re-read this value in case it was changed inside config_init due to
7339 * limitations of optic module
7341 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7343 /* Init external phy*/
7345 if (params->phy[ELINK_INT_PHY].supported &
7346 ELINK_SUPPORTED_FIBRE)
7347 vars->link_status |= LINK_STATUS_SERDES_LINK;
7349 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7351 /* No need to initialize second phy in case of first
7352 * phy only selection. In case of second phy, we do
7353 * need to initialize the first phy, since they are
7356 if (params->phy[phy_index].supported &
7357 ELINK_SUPPORTED_FIBRE)
7358 vars->link_status |= LINK_STATUS_SERDES_LINK;
7360 if (phy_index == ELINK_EXT_PHY2 &&
7361 (elink_phy_selection(params) ==
7362 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
7364 "Not initializing second phy\n");
7367 params->phy[phy_index].config_init(
7368 ¶ms->phy[phy_index],
7372 /* Reset the interrupt indication after phy was initialized */
7373 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
7375 (ELINK_NIG_STATUS_XGXS0_LINK10G |
7376 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
7377 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
7378 ELINK_NIG_MASK_MI_INT));
7382 static void elink_int_link_reset(struct elink_phy *phy,
7383 struct elink_params *params)
7385 /* Reset the SerDes/XGXS */
7386 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7387 (0x1ff << (params->port*16)));
7390 static void elink_common_ext_link_reset(struct elink_phy *phy,
7391 struct elink_params *params)
7393 struct bxe_softc *sc = params->sc;
7397 gpio_port = SC_PATH(sc);
7399 gpio_port = params->port;
7400 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7401 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7403 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7404 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7406 ELINK_DEBUG_P0(sc, "reset external PHY\n");
7409 static elink_status_t elink_update_link_down(struct elink_params *params,
7410 struct elink_vars *vars)
7412 struct bxe_softc *sc = params->sc;
7413 uint8_t port = params->port;
7415 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7416 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
7417 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
7418 /* Indicate no mac active */
7419 vars->mac_type = ELINK_MAC_TYPE_NONE;
7421 /* Update shared memory */
7422 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7423 vars->line_speed = 0;
7424 elink_update_mng(params, vars->link_status);
7426 /* Activate nig drain */
7427 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7430 if (!CHIP_IS_E3(sc))
7431 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7434 /* Reset BigMac/Xmac */
7435 if (CHIP_IS_E1x(sc) ||
7437 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7439 if (CHIP_IS_E3(sc)) {
7440 /* Prevent LPI Generation by chip */
7441 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7443 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7445 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
7446 SHMEM_EEE_ACTIVE_BIT);
7448 elink_update_mng_eee(params, vars->eee_status);
7449 elink_set_xmac_rxtx(params, 0);
7450 elink_set_umac_rxtx(params, 0);
7453 return ELINK_STATUS_OK;
7456 static elink_status_t elink_update_link_up(struct elink_params *params,
7457 struct elink_vars *vars,
7460 struct bxe_softc *sc = params->sc;
7461 uint8_t phy_idx, port = params->port;
7462 elink_status_t rc = ELINK_STATUS_OK;
7464 vars->link_status |= (LINK_STATUS_LINK_UP |
7465 LINK_STATUS_PHYSICAL_LINK_FLAG);
7466 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7468 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
7469 vars->link_status |=
7470 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
7472 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
7473 vars->link_status |=
7474 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7475 if (USES_WARPCORE(sc)) {
7477 if (elink_xmac_enable(params, vars, 0) ==
7478 ELINK_STATUS_NO_LINK) {
7479 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n");
7481 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7482 vars->link_status &= ~LINK_STATUS_LINK_UP;
7485 elink_umac_enable(params, vars, 0);
7486 elink_set_led(params, vars,
7487 ELINK_LED_MODE_OPER, vars->line_speed);
7489 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
7490 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
7491 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n");
7492 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7493 (params->port << 2), 1);
7494 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7495 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7496 (params->port << 2), 0xfc20);
7499 if ((CHIP_IS_E1x(sc) ||
7502 if (elink_bmac_enable(params, vars, 0, 1) ==
7503 ELINK_STATUS_NO_LINK) {
7504 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n");
7506 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7507 vars->link_status &= ~LINK_STATUS_LINK_UP;
7510 elink_set_led(params, vars,
7511 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
7513 rc = elink_emac_program(params, vars);
7514 elink_emac_enable(params, vars, 0);
7517 if ((vars->link_status &
7518 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
7519 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
7520 ELINK_SINGLE_MEDIA_DIRECT(params))
7521 elink_set_gmii_tx_driver(params);
7526 if (CHIP_IS_E1x(sc))
7527 rc |= elink_pbf_update(params, vars->flow_ctrl,
7531 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7533 /* Update shared memory */
7534 elink_update_mng(params, vars->link_status);
7535 elink_update_mng_eee(params, vars->eee_status);
7536 /* Check remote fault */
7537 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7538 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7539 elink_check_half_open_conn(params, vars, 0);
7546 /* The elink_link_update function should be called upon link
7548 * Link is considered up as follows:
7549 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7551 * - SINGLE_MEDIA - The link between the 577xx and the external
7552 * phy (XGXS) need to up as well as the external link of the
7554 * - DUAL_MEDIA - The link between the 577xx and the first
7555 * external phy needs to be up, and at least one of the 2
7556 * external phy link must be up.
7558 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
7560 struct bxe_softc *sc = params->sc;
7561 struct elink_vars phy_vars[ELINK_MAX_PHYS];
7562 uint8_t port = params->port;
7563 uint8_t link_10g_plus, phy_index;
7564 uint8_t ext_phy_link_up = 0, cur_link_up;
7565 elink_status_t rc = ELINK_STATUS_OK;
7566 uint8_t is_mi_int = 0;
7567 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
7568 uint8_t active_external_phy = ELINK_INT_PHY;
7569 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
7570 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7571 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
7573 phy_vars[phy_index].flow_ctrl = 0;
7574 phy_vars[phy_index].link_status = 0;
7575 phy_vars[phy_index].line_speed = 0;
7576 phy_vars[phy_index].duplex = DUPLEX_FULL;
7577 phy_vars[phy_index].phy_link_up = 0;
7578 phy_vars[phy_index].link_up = 0;
7579 phy_vars[phy_index].fault_detected = 0;
7580 /* different consideration, since vars holds inner state */
7581 phy_vars[phy_index].eee_status = vars->eee_status;
7584 if (USES_WARPCORE(sc))
7585 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7587 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7588 port, (vars->phy_flags & PHY_XGXS_FLAG),
7589 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7591 is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
7593 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7594 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7596 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7598 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
7599 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7600 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7603 if (!CHIP_IS_E3(sc))
7604 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7607 * Check external link change only for external phys, and apply
7608 * priority selection between them in case the link on both phys
7609 * is up. Note that instead of the common vars, a temporary
7610 * vars argument is used since each phy may have different link/
7611 * speed/duplex result
7613 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7615 struct elink_phy *phy = ¶ms->phy[phy_index];
7616 if (!phy->read_status)
7618 /* Read link status and params of this ext phy */
7619 cur_link_up = phy->read_status(phy, params,
7620 &phy_vars[phy_index]);
7622 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7625 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7630 if (!ext_phy_link_up) {
7631 ext_phy_link_up = 1;
7632 active_external_phy = phy_index;
7634 switch (elink_phy_selection(params)) {
7635 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7636 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7637 /* In this option, the first PHY makes sure to pass the
7638 * traffic through itself only.
7639 * Its not clear how to reset the link on the second phy
7641 active_external_phy = ELINK_EXT_PHY1;
7643 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7644 /* In this option, the first PHY makes sure to pass the
7645 * traffic through the second PHY.
7647 active_external_phy = ELINK_EXT_PHY2;
7650 /* Link indication on both PHYs with the following cases
7652 * - FIRST_PHY means that second phy wasn't initialized,
7653 * hence its link is expected to be down
7654 * - SECOND_PHY means that first phy should not be able
7655 * to link up by itself (using configuration)
7656 * - DEFAULT should be overriden during initialiazation
7658 ELINK_DEBUG_P1(sc, "Invalid link indication"
7659 "mpc=0x%x. DISABLING LINK !!!\n",
7660 params->multi_phy_config);
7661 ext_phy_link_up = 0;
7666 prev_line_speed = vars->line_speed;
7668 * Read the status of the internal phy. In case of
7669 * DIRECT_SINGLE_MEDIA board, this link is the external link,
7670 * otherwise this is the link between the 577xx and the first
7673 if (params->phy[ELINK_INT_PHY].read_status)
7674 params->phy[ELINK_INT_PHY].read_status(
7675 ¶ms->phy[ELINK_INT_PHY],
7677 /* The INT_PHY flow control reside in the vars. This include the
7678 * case where the speed or flow control are not set to AUTO.
7679 * Otherwise, the active external phy flow control result is set
7680 * to the vars. The ext_phy_line_speed is needed to check if the
7681 * speed is different between the internal phy and external phy.
7682 * This case may be result of intermediate link speed change.
7684 if (active_external_phy > ELINK_INT_PHY) {
7685 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
7686 /* Link speed is taken from the XGXS. AN and FC result from
7689 vars->link_status |= phy_vars[active_external_phy].link_status;
7691 /* if active_external_phy is first PHY and link is up - disable
7692 * disable TX on second external PHY
7694 if (active_external_phy == ELINK_EXT_PHY1) {
7695 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7697 "Disabling TX on EXT_PHY2\n");
7698 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7699 ¶ms->phy[ELINK_EXT_PHY2],
7700 params, ELINK_DISABLE_TX);
7704 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7705 vars->duplex = phy_vars[active_external_phy].duplex;
7706 if (params->phy[active_external_phy].supported &
7707 ELINK_SUPPORTED_FIBRE)
7708 vars->link_status |= LINK_STATUS_SERDES_LINK;
7710 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7712 vars->eee_status = phy_vars[active_external_phy].eee_status;
7714 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7715 active_external_phy);
7718 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7720 if (params->phy[phy_index].flags &
7721 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
7722 elink_rearm_latch_signal(sc, port,
7724 active_external_phy);
7728 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7729 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7730 vars->link_status, ext_phy_line_speed);
7731 /* Upon link speed change set the NIG into drain mode. Comes to
7732 * deals with possible FIFO glitch due to clk change when speed
7733 * is decreased without link down indicator
7736 if (vars->phy_link_up) {
7737 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7738 (ext_phy_line_speed != vars->line_speed)) {
7739 ELINK_DEBUG_P2(sc, "Internal link speed %d is"
7740 " different than the external"
7741 " link speed %d\n", vars->line_speed,
7742 ext_phy_line_speed);
7743 vars->phy_link_up = 0;
7744 } else if (prev_line_speed != vars->line_speed) {
7745 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7751 /* Anything 10 and over uses the bmac */
7752 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
7754 elink_link_int_ack(params, vars, link_10g_plus);
7756 /* In case external phy link is up, and internal link is down
7757 * (not initialized yet probably after link initialization, it
7758 * needs to be initialized.
7759 * Note that after link down-up as result of cable plug, the xgxs
7760 * link would probably become up again without the need
7763 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
7764 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
7765 " init_preceding = %d\n", ext_phy_link_up,
7767 params->phy[ELINK_EXT_PHY1].flags &
7768 ELINK_FLAGS_INIT_XGXS_FIRST);
7769 if (!(params->phy[ELINK_EXT_PHY1].flags &
7770 ELINK_FLAGS_INIT_XGXS_FIRST)
7771 && ext_phy_link_up && !vars->phy_link_up) {
7772 vars->line_speed = ext_phy_line_speed;
7773 if (vars->line_speed < ELINK_SPEED_1000)
7774 vars->phy_flags |= PHY_SGMII_FLAG;
7776 vars->phy_flags &= ~PHY_SGMII_FLAG;
7778 if (params->phy[ELINK_INT_PHY].config_init)
7779 params->phy[ELINK_INT_PHY].config_init(
7780 ¶ms->phy[ELINK_INT_PHY], params,
7784 /* Link is up only if both local phy and external phy (in case of
7785 * non-direct board) are up and no fault detected on active PHY.
7787 vars->link_up = (vars->phy_link_up &&
7789 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
7790 (phy_vars[active_external_phy].fault_detected == 0));
7792 /* Update the PFC configuration in case it was changed */
7793 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
7794 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7796 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7799 rc = elink_update_link_up(params, vars, link_10g_plus);
7801 rc = elink_update_link_down(params, vars);
7803 /* Update MCP link status was changed */
7804 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7805 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7810 /*****************************************************************************/
7811 /* External Phy section */
7812 /*****************************************************************************/
7813 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7815 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7816 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7818 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7819 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7822 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7823 uint32_t spirom_ver, uint32_t ver_addr)
7825 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7826 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7829 REG_WR(sc, ver_addr, spirom_ver);
7832 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc,
7833 struct elink_phy *phy,
7836 uint16_t fw_ver1, fw_ver2;
7838 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7839 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7840 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7841 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7842 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7846 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc,
7847 struct elink_phy *phy,
7848 struct elink_vars *vars)
7851 elink_cl45_read(sc, phy,
7853 MDIO_AN_REG_STATUS, &val);
7854 elink_cl45_read(sc, phy,
7856 MDIO_AN_REG_STATUS, &val);
7858 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7859 if ((val & (1<<0)) == 0)
7860 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7863 /******************************************************************/
7864 /* common BCM8073/BCM8727 PHY SECTION */
7865 /******************************************************************/
7866 static void elink_8073_resolve_fc(struct elink_phy *phy,
7867 struct elink_params *params,
7868 struct elink_vars *vars)
7870 struct bxe_softc *sc = params->sc;
7871 if (phy->req_line_speed == ELINK_SPEED_10 ||
7872 phy->req_line_speed == ELINK_SPEED_100) {
7873 vars->flow_ctrl = phy->req_flow_ctrl;
7877 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
7878 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
7879 uint16_t pause_result;
7880 uint16_t ld_pause; /* local */
7881 uint16_t lp_pause; /* link partner */
7882 elink_cl45_read(sc, phy,
7884 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7886 elink_cl45_read(sc, phy,
7888 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7889 pause_result = (ld_pause &
7890 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7891 pause_result |= (lp_pause &
7892 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7894 elink_pause_resolve(vars, pause_result);
7895 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",
7899 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc,
7900 struct elink_phy *phy,
7904 uint16_t fw_ver1, fw_msgout;
7905 elink_status_t rc = ELINK_STATUS_OK;
7907 /* Boot port from external ROM */
7909 elink_cl45_write(sc, phy,
7911 MDIO_PMA_REG_GEN_CTRL,
7914 /* Ucode reboot and rst */
7915 elink_cl45_write(sc, phy,
7917 MDIO_PMA_REG_GEN_CTRL,
7920 elink_cl45_write(sc, phy,
7922 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7924 /* Reset internal microprocessor */
7925 elink_cl45_write(sc, phy,
7927 MDIO_PMA_REG_GEN_CTRL,
7928 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7930 /* Release srst bit */
7931 elink_cl45_write(sc, phy,
7933 MDIO_PMA_REG_GEN_CTRL,
7934 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7936 /* Delay 100ms per the PHY specifications */
7939 /* 8073 sometimes taking longer to download */
7944 "elink_8073_8727_external_rom_boot port %x:"
7945 "Download failed. fw version = 0x%x\n",
7947 rc = ELINK_STATUS_ERROR;
7951 elink_cl45_read(sc, phy,
7953 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7954 elink_cl45_read(sc, phy,
7956 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7959 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7960 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7961 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7963 /* Clear ser_boot_ctl bit */
7964 elink_cl45_write(sc, phy,
7966 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7967 elink_save_bcm_spirom_ver(sc, phy, port);
7970 "elink_8073_8727_external_rom_boot port %x:"
7971 "Download complete. fw version = 0x%x\n",
7977 /******************************************************************/
7978 /* BCM8073 PHY SECTION */
7979 /******************************************************************/
7980 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
7982 /* This is only required for 8073A1, version 102 only */
7985 /* Read 8073 HW revision*/
7986 elink_cl45_read(sc, phy,
7988 MDIO_PMA_REG_8073_CHIP_REV, &val);
7991 /* No need to workaround in 8073 A1 */
7992 return ELINK_STATUS_OK;
7995 elink_cl45_read(sc, phy,
7997 MDIO_PMA_REG_ROM_VER2, &val);
7999 /* SNR should be applied only for version 0x102 */
8001 return ELINK_STATUS_OK;
8006 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
8008 uint16_t val, cnt, cnt1 ;
8010 elink_cl45_read(sc, phy,
8012 MDIO_PMA_REG_8073_CHIP_REV, &val);
8015 /* No need to workaround in 8073 A1 */
8016 return ELINK_STATUS_OK;
8018 /* XAUI workaround in 8073 A0: */
8020 /* After loading the boot ROM and restarting Autoneg, poll
8024 for (cnt = 0; cnt < 1000; cnt++) {
8025 elink_cl45_read(sc, phy,
8027 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8029 /* If bit [14] = 0 or bit [13] = 0, continue on with
8030 * system initialization (XAUI work-around not required, as
8031 * these bits indicate 2.5G or 1G link up).
8033 if (!(val & (1<<14)) || !(val & (1<<13))) {
8034 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n");
8035 return ELINK_STATUS_OK;
8036 } else if (!(val & (1<<15))) {
8037 ELINK_DEBUG_P0(sc, "bit 15 went off\n");
8038 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
8039 * MSB (bit15) goes to 1 (indicating that the XAUI
8040 * workaround has completed), then continue on with
8041 * system initialization.
8043 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
8044 elink_cl45_read(sc, phy,
8046 MDIO_PMA_REG_8073_XAUI_WA, &val);
8047 if (val & (1<<15)) {
8049 "XAUI workaround has completed\n");
8050 return ELINK_STATUS_OK;
8058 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n");
8059 return ELINK_STATUS_ERROR;
8062 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8064 /* Force KR or KX */
8065 elink_cl45_write(sc, phy,
8066 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8067 elink_cl45_write(sc, phy,
8068 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
8069 elink_cl45_write(sc, phy,
8070 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
8071 elink_cl45_write(sc, phy,
8072 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
8075 static void elink_8073_set_pause_cl37(struct elink_params *params,
8076 struct elink_phy *phy,
8077 struct elink_vars *vars)
8080 struct bxe_softc *sc = params->sc;
8081 elink_cl45_read(sc, phy,
8082 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
8084 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8085 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
8086 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8087 if ((vars->ieee_fc &
8088 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
8089 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
8090 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
8092 if ((vars->ieee_fc &
8093 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
8094 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
8095 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
8097 if ((vars->ieee_fc &
8098 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
8099 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
8100 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8103 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8105 elink_cl45_write(sc, phy,
8106 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
8110 static void elink_8073_specific_func(struct elink_phy *phy,
8111 struct elink_params *params,
8114 struct bxe_softc *sc = params->sc;
8116 case ELINK_PHY_INIT:
8118 elink_cl45_write(sc, phy,
8119 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
8120 elink_cl45_write(sc, phy,
8121 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8126 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8127 struct elink_params *params,
8128 struct elink_vars *vars)
8130 struct bxe_softc *sc = params->sc;
8131 uint16_t val = 0, tmp1;
8133 ELINK_DEBUG_P0(sc, "Init 8073\n");
8136 gpio_port = SC_PATH(sc);
8138 gpio_port = params->port;
8139 /* Restore normal power mode*/
8140 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8141 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8143 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8144 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8146 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8147 elink_8073_set_pause_cl37(params, phy, vars);
8149 elink_cl45_read(sc, phy,
8150 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8152 elink_cl45_read(sc, phy,
8153 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8155 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8157 /* Swap polarity if required - Must be done only in non-1G mode */
8158 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8159 /* Configure the 8073 to swap _P and _N of the KR lines */
8160 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n");
8161 /* 10G Rx/Tx and 1G Tx signal polarity swap */
8162 elink_cl45_read(sc, phy,
8164 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
8165 elink_cl45_write(sc, phy,
8167 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
8172 /* Enable CL37 BAM */
8173 if (REG_RD(sc, params->shmem_base +
8174 offsetof(struct shmem_region, dev_info.
8175 port_hw_config[params->port].default_cfg)) &
8176 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
8178 elink_cl45_read(sc, phy,
8180 MDIO_AN_REG_8073_BAM, &val);
8181 elink_cl45_write(sc, phy,
8183 MDIO_AN_REG_8073_BAM, val | 1);
8184 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
8186 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
8187 elink_807x_force_10G(sc, phy);
8188 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n");
8189 return ELINK_STATUS_OK;
8191 elink_cl45_write(sc, phy,
8192 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
8194 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8195 if (phy->req_line_speed == ELINK_SPEED_10000) {
8197 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8199 /* Note that 2.5G works only when used with 1G
8206 if (phy->speed_cap_mask &
8207 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
8210 /* Note that 2.5G works only when used with 1G advertisement */
8211 if (phy->speed_cap_mask &
8212 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
8213 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8215 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);
8218 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8219 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8221 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8222 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8223 (phy->req_line_speed == ELINK_SPEED_2500)) {
8225 /* Allow 2.5G for A1 and above */
8226 elink_cl45_read(sc, phy,
8227 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
8229 ELINK_DEBUG_P0(sc, "Add 2.5G\n");
8235 ELINK_DEBUG_P0(sc, "Disable 2.5G\n");
8239 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8240 /* Add support for CL37 (passive mode) II */
8242 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8243 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8244 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8247 /* Add support for CL37 (passive mode) III */
8248 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8250 /* The SNR will improve about 2db by changing BW and FEE main
8251 * tap. Rest commands are executed after link is up
8252 * Change FFE main cursor to 5 in EDC register
8254 if (elink_8073_is_snr_needed(sc, phy))
8255 elink_cl45_write(sc, phy,
8256 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
8259 /* Enable FEC (Forware Error Correction) Request in the AN */
8260 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8262 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8264 elink_ext_phy_set_pause(params, phy, vars);
8266 /* Restart autoneg */
8268 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8269 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8270 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
8271 return ELINK_STATUS_OK;
8274 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8275 struct elink_params *params,
8276 struct elink_vars *vars)
8278 struct bxe_softc *sc = params->sc;
8279 uint8_t link_up = 0;
8280 uint16_t val1, val2;
8281 uint16_t link_status = 0;
8282 uint16_t an1000_status = 0;
8284 elink_cl45_read(sc, phy,
8285 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8287 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);
8289 /* Clear the interrupt LASI status register */
8290 elink_cl45_read(sc, phy,
8291 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8292 elink_cl45_read(sc, phy,
8293 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
8294 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);
8296 elink_cl45_read(sc, phy,
8297 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8299 /* Check the LASI */
8300 elink_cl45_read(sc, phy,
8301 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8303 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);
8305 /* Check the link status */
8306 elink_cl45_read(sc, phy,
8307 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8308 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);
8310 elink_cl45_read(sc, phy,
8311 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8312 elink_cl45_read(sc, phy,
8313 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8314 link_up = ((val1 & 4) == 4);
8315 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);
8318 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8319 if (elink_8073_xaui_wa(sc, phy) != 0)
8322 elink_cl45_read(sc, phy,
8323 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8324 elink_cl45_read(sc, phy,
8325 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8327 /* Check the link status on 1.1.2 */
8328 elink_cl45_read(sc, phy,
8329 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8330 elink_cl45_read(sc, phy,
8331 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8332 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
8333 "an_link_status=0x%x\n", val2, val1, an1000_status);
8335 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
8336 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8337 /* The SNR will improve about 2dbby changing the BW and FEE main
8338 * tap. The 1st write to change FFE main tap is set before
8339 * restart AN. Change PLL Bandwidth in EDC register
8341 elink_cl45_write(sc, phy,
8342 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
8345 /* Change CDR Bandwidth in EDC register */
8346 elink_cl45_write(sc, phy,
8347 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
8350 elink_cl45_read(sc, phy,
8351 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8354 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
8355 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8357 vars->line_speed = ELINK_SPEED_10000;
8358 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8360 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
8362 vars->line_speed = ELINK_SPEED_2500;
8363 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8365 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8367 vars->line_speed = ELINK_SPEED_1000;
8368 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8372 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8377 /* Swap polarity if required */
8378 if (params->lane_config &
8379 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8380 /* Configure the 8073 to swap P and N of the KR lines */
8381 elink_cl45_read(sc, phy,
8383 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8384 /* Set bit 3 to invert Rx in 1G mode and clear this bit
8385 * when it`s in 10G mode.
8387 if (vars->line_speed == ELINK_SPEED_1000) {
8388 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
8394 elink_cl45_write(sc, phy,
8396 MDIO_XS_REG_8073_RX_CTRL_PCIE,
8399 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8400 elink_8073_resolve_fc(phy, params, vars);
8401 vars->duplex = DUPLEX_FULL;
8404 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8405 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8406 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
8409 vars->link_status |=
8410 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
8412 vars->link_status |=
8413 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
8419 static void elink_8073_link_reset(struct elink_phy *phy,
8420 struct elink_params *params)
8422 struct bxe_softc *sc = params->sc;
8425 gpio_port = SC_PATH(sc);
8427 gpio_port = params->port;
8428 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8430 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8431 MISC_REGISTERS_GPIO_OUTPUT_LOW,
8435 /******************************************************************/
8436 /* BCM8705 PHY SECTION */
8437 /******************************************************************/
8438 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8439 struct elink_params *params,
8440 struct elink_vars *vars)
8442 struct bxe_softc *sc = params->sc;
8443 ELINK_DEBUG_P0(sc, "init 8705\n");
8444 /* Restore normal power mode*/
8445 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8446 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8448 elink_ext_phy_hw_reset(sc, params->port);
8449 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8450 elink_wait_reset_complete(sc, phy, params);
8452 elink_cl45_write(sc, phy,
8453 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
8454 elink_cl45_write(sc, phy,
8455 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
8456 elink_cl45_write(sc, phy,
8457 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
8458 elink_cl45_write(sc, phy,
8459 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
8460 /* BCM8705 doesn't have microcode, hence the 0 */
8461 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8462 return ELINK_STATUS_OK;
8465 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8466 struct elink_params *params,
8467 struct elink_vars *vars)
8469 uint8_t link_up = 0;
8470 uint16_t val1, rx_sd;
8471 struct bxe_softc *sc = params->sc;
8472 ELINK_DEBUG_P0(sc, "read status 8705\n");
8473 elink_cl45_read(sc, phy,
8474 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8475 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8477 elink_cl45_read(sc, phy,
8478 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8479 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8481 elink_cl45_read(sc, phy,
8482 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8484 elink_cl45_read(sc, phy,
8485 MDIO_PMA_DEVAD, 0xc809, &val1);
8486 elink_cl45_read(sc, phy,
8487 MDIO_PMA_DEVAD, 0xc809, &val1);
8489 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);
8490 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
8492 vars->line_speed = ELINK_SPEED_10000;
8493 elink_ext_phy_resolve_fc(phy, params, vars);
8498 /******************************************************************/
8499 /* SFP+ module Section */
8500 /******************************************************************/
8501 static void elink_set_disable_pmd_transmit(struct elink_params *params,
8502 struct elink_phy *phy,
8505 struct bxe_softc *sc = params->sc;
8506 /* Disable transmitter only for bootcodes which can enable it afterwards
8510 if (params->feature_config_flags &
8511 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
8512 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n");
8514 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n");
8518 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n");
8519 elink_cl45_write(sc, phy,
8521 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
8524 static uint8_t elink_get_gpio_port(struct elink_params *params)
8527 uint32_t swap_val, swap_override;
8528 struct bxe_softc *sc = params->sc;
8530 gpio_port = SC_PATH(sc);
8532 gpio_port = params->port;
8533 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8534 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8535 return gpio_port ^ (swap_val && swap_override);
8538 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
8539 struct elink_phy *phy,
8543 uint8_t port = params->port;
8544 struct bxe_softc *sc = params->sc;
8545 uint32_t tx_en_mode;
8547 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
8548 tx_en_mode = REG_RD(sc, params->shmem_base +
8549 offsetof(struct shmem_region,
8550 dev_info.port_hw_config[port].sfp_ctrl)) &
8551 PORT_HW_CFG_TX_LASER_MASK;
8552 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8553 "mode = %x\n", tx_en, port, tx_en_mode);
8554 switch (tx_en_mode) {
8555 case PORT_HW_CFG_TX_LASER_MDIO:
8557 elink_cl45_read(sc, phy,
8559 MDIO_PMA_REG_PHY_IDENTIFIER,
8567 elink_cl45_write(sc, phy,
8569 MDIO_PMA_REG_PHY_IDENTIFIER,
8572 case PORT_HW_CFG_TX_LASER_GPIO0:
8573 case PORT_HW_CFG_TX_LASER_GPIO1:
8574 case PORT_HW_CFG_TX_LASER_GPIO2:
8575 case PORT_HW_CFG_TX_LASER_GPIO3:
8578 uint8_t gpio_port, gpio_mode;
8580 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
8582 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
8584 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
8585 gpio_port = elink_get_gpio_port(params);
8586 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8590 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8595 static void elink_sfp_set_transmitter(struct elink_params *params,
8596 struct elink_phy *phy,
8599 struct bxe_softc *sc = params->sc;
8600 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en);
8602 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8604 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8607 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8608 struct elink_params *params,
8609 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8610 uint8_t *o_buf, uint8_t is_init)
8612 struct bxe_softc *sc = params->sc;
8615 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8617 "Reading from eeprom is limited to 0xf\n");
8618 return ELINK_STATUS_ERROR;
8620 /* Set the read command byte count */
8621 elink_cl45_write(sc, phy,
8622 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8623 (byte_cnt | (dev_addr << 8)));
8625 /* Set the read command address */
8626 elink_cl45_write(sc, phy,
8627 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8630 /* Activate read command */
8631 elink_cl45_write(sc, phy,
8632 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8635 /* Wait up to 500us for command complete status */
8636 for (i = 0; i < 100; i++) {
8637 elink_cl45_read(sc, phy,
8639 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8640 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8641 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8646 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8647 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8649 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8650 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8651 return ELINK_STATUS_ERROR;
8654 /* Read the buffer */
8655 for (i = 0; i < byte_cnt; i++) {
8656 elink_cl45_read(sc, phy,
8658 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
8659 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
8662 for (i = 0; i < 100; i++) {
8663 elink_cl45_read(sc, phy,
8665 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8666 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8667 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8668 return ELINK_STATUS_OK;
8671 return ELINK_STATUS_ERROR;
8674 static void elink_warpcore_power_module(struct elink_params *params,
8678 struct bxe_softc *sc = params->sc;
8680 pin_cfg = (REG_RD(sc, params->shmem_base +
8681 offsetof(struct shmem_region,
8682 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8683 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8684 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8686 if (pin_cfg == PIN_CFG_NA)
8688 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n",
8690 /* Low ==> corresponding SFP+ module is powered
8691 * high ==> the SFP+ module is powered down
8693 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
8695 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8696 struct elink_params *params,
8698 uint16_t addr, uint8_t byte_cnt,
8699 uint8_t *o_buf, uint8_t is_init)
8701 elink_status_t rc = ELINK_STATUS_OK;
8702 uint8_t i, j = 0, cnt = 0;
8703 uint32_t data_array[4];
8705 struct bxe_softc *sc = params->sc;
8707 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8709 "Reading from eeprom is limited to 16 bytes\n");
8710 return ELINK_STATUS_ERROR;
8713 /* 4 byte aligned address */
8714 addr32 = addr & (~0x3);
8716 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8717 elink_warpcore_power_module(params, 0);
8718 /* Note that 100us are not enough here */
8720 elink_warpcore_power_module(params, 1);
8722 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
8724 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
8726 if (rc == ELINK_STATUS_OK) {
8727 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8728 o_buf[j] = *((uint8_t *)data_array + i);
8736 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8737 struct elink_params *params,
8738 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8739 uint8_t *o_buf, uint8_t is_init)
8741 struct bxe_softc *sc = params->sc;
8744 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8746 "Reading from eeprom is limited to 0xf\n");
8747 return ELINK_STATUS_ERROR;
8750 /* Set 2-wire transfer rate of SFP+ module EEPROM
8751 * to 100Khz since some DACs(direct attached cables) do
8752 * not work at 400Khz.
8754 elink_cl45_write(sc, phy,
8756 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8757 ((dev_addr << 8) | 1));
8759 /* Need to read from 1.8000 to clear it */
8760 elink_cl45_read(sc, phy,
8762 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8765 /* Set the read command byte count */
8766 elink_cl45_write(sc, phy,
8768 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8769 ((byte_cnt < 2) ? 2 : byte_cnt));
8771 /* Set the read command address */
8772 elink_cl45_write(sc, phy,
8774 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8776 /* Set the destination address */
8777 elink_cl45_write(sc, phy,
8780 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8782 /* Activate read command */
8783 elink_cl45_write(sc, phy,
8785 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8787 /* Wait appropriate time for two-wire command to finish before
8788 * polling the status register
8792 /* Wait up to 500us for command complete status */
8793 for (i = 0; i < 100; i++) {
8794 elink_cl45_read(sc, phy,
8796 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8797 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8798 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8803 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8804 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8806 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8807 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8808 return ELINK_STATUS_TIMEOUT;
8811 /* Read the buffer */
8812 for (i = 0; i < byte_cnt; i++) {
8813 elink_cl45_read(sc, phy,
8815 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8816 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8819 for (i = 0; i < 100; i++) {
8820 elink_cl45_read(sc, phy,
8822 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8823 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8824 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8825 return ELINK_STATUS_OK;
8829 return ELINK_STATUS_ERROR;
8831 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8832 struct elink_params *params, uint8_t dev_addr,
8833 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf)
8835 elink_status_t rc = 0;
8836 struct bxe_softc *sc = params->sc;
8838 uint8_t *user_data = o_buf;
8839 read_sfp_module_eeprom_func_p read_func;
8840 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8841 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);
8842 return ELINK_STATUS_ERROR;
8845 switch (phy->type) {
8846 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8847 read_func = elink_8726_read_sfp_module_eeprom;
8849 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8850 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8851 read_func = elink_8727_read_sfp_module_eeprom;
8853 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8854 read_func = elink_warpcore_read_sfp_module_eeprom;
8857 return ELINK_OP_NOT_SUPPORTED;
8860 while (!rc && (byte_cnt > 0)) {
8861 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
8862 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
8863 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8865 byte_cnt -= xfer_size;
8866 user_data += xfer_size;
8872 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
8873 struct elink_params *params,
8876 struct bxe_softc *sc = params->sc;
8877 uint32_t sync_offset = 0, phy_idx, media_types;
8878 uint8_t gport, val[2], check_limiting_mode = 0;
8879 *edc_mode = ELINK_EDC_MODE_LIMITING;
8880 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
8881 /* First check for copper cable */
8882 if (elink_read_sfp_module_eeprom(phy,
8884 ELINK_I2C_DEV_ADDR_A0,
8885 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
8887 (uint8_t *)val) != 0) {
8888 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n");
8889 return ELINK_STATUS_ERROR;
8893 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
8895 uint8_t copper_module_type;
8896 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
8897 /* Check if its active cable (includes SFP+ module)
8900 if (elink_read_sfp_module_eeprom(phy,
8902 ELINK_I2C_DEV_ADDR_A0,
8903 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
8905 &copper_module_type) != 0) {
8907 "Failed to read copper-cable-type"
8908 " from SFP+ EEPROM\n");
8909 return ELINK_STATUS_ERROR;
8912 if (copper_module_type &
8913 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8914 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
8915 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8916 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
8918 check_limiting_mode = 1;
8920 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
8921 /* Even in case PASSIVE_DAC indication is not set,
8922 * treat it as a passive DAC cable, since some cables
8923 * don't have this indication.
8925 if (copper_module_type &
8926 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8928 "Passive Copper cable detected\n");
8931 "Unknown copper-cable-type\n");
8936 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
8937 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
8938 check_limiting_mode = 1;
8939 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
8940 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
8941 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8942 ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
8943 gport = params->port;
8944 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
8945 if (phy->req_line_speed != ELINK_SPEED_1000) {
8946 phy->req_line_speed = ELINK_SPEED_1000;
8947 if (!CHIP_IS_E1x(sc)) {
8948 gport = SC_PATH(sc) +
8949 (params->port << 1);
8951 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
8952 // " Current SFP module in port %d is not"
8953 // " compliant with 10G Ethernet\n",
8957 int idx, cfg_idx = 0;
8958 ELINK_DEBUG_P0(sc, "10G Optic module detected\n");
8959 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
8960 if (params->phy[idx].type == phy->type) {
8961 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
8965 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
8966 phy->req_line_speed = params->req_line_speed[cfg_idx];
8970 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",
8972 return ELINK_STATUS_ERROR;
8974 sync_offset = params->shmem_base +
8975 offsetof(struct shmem_region,
8976 dev_info.port_hw_config[params->port].media_type);
8977 media_types = REG_RD(sc, sync_offset);
8978 /* Update media type for non-PMF sync */
8979 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
8980 if (&(params->phy[phy_idx]) == phy) {
8981 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8982 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8983 media_types |= ((phy->media_type &
8984 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8985 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8989 REG_WR(sc, sync_offset, media_types);
8990 if (check_limiting_mode) {
8991 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
8992 if (elink_read_sfp_module_eeprom(phy,
8994 ELINK_I2C_DEV_ADDR_A0,
8995 ELINK_SFP_EEPROM_OPTIONS_ADDR,
8996 ELINK_SFP_EEPROM_OPTIONS_SIZE,
8999 "Failed to read Option field from module EEPROM\n");
9000 return ELINK_STATUS_ERROR;
9002 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
9003 *edc_mode = ELINK_EDC_MODE_LINEAR;
9005 *edc_mode = ELINK_EDC_MODE_LIMITING;
9007 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);
9008 return ELINK_STATUS_OK;
9010 /* This function read the relevant field from the module (SFP+), and verify it
9011 * is compliant with this board
9013 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
9014 struct elink_params *params)
9016 struct bxe_softc *sc = params->sc;
9018 uint32_t fw_resp, fw_cmd_param;
9019 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
9020 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
9021 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9022 val = REG_RD(sc, params->shmem_base +
9023 offsetof(struct shmem_region, dev_info.
9024 port_feature_config[params->port].config));
9025 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9026 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
9027 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n");
9028 return ELINK_STATUS_OK;
9031 if (params->feature_config_flags &
9032 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
9033 /* Use specific phy request */
9034 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
9035 } else if (params->feature_config_flags &
9036 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
9037 /* Use first phy request only in case of non-dual media*/
9038 if (ELINK_DUAL_MEDIA(params)) {
9040 "FW does not support OPT MDL verification\n");
9041 return ELINK_STATUS_ERROR;
9043 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
9045 /* No support in OPT MDL detection */
9047 "FW does not support OPT MDL verification\n");
9048 return ELINK_STATUS_ERROR;
9051 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9052 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
9053 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
9054 ELINK_DEBUG_P0(sc, "Approved module\n");
9055 return ELINK_STATUS_OK;
9058 /* Format the warning message */
9059 if (elink_read_sfp_module_eeprom(phy,
9061 ELINK_I2C_DEV_ADDR_A0,
9062 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
9063 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
9064 (uint8_t *)vendor_name))
9065 vendor_name[0] = '\0';
9067 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
9068 if (elink_read_sfp_module_eeprom(phy,
9070 ELINK_I2C_DEV_ADDR_A0,
9071 ELINK_SFP_EEPROM_PART_NO_ADDR,
9072 ELINK_SFP_EEPROM_PART_NO_SIZE,
9073 (uint8_t *)vendor_pn))
9074 vendor_pn[0] = '\0';
9076 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
9078 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9079 // " Port %d from %s part number %s\n",
9081 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
9082 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
9083 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9084 return ELINK_STATUS_ERROR;
9087 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9088 struct elink_params *params)
9093 struct bxe_softc *sc = params->sc;
9095 /* Initialization time after hot-plug may take up to 300ms for
9096 * some phys type ( e.g. JDSU )
9099 for (timeout = 0; timeout < 60; timeout++) {
9100 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9101 rc = elink_warpcore_read_sfp_module_eeprom(
9102 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9105 rc = elink_read_sfp_module_eeprom(phy, params,
9106 ELINK_I2C_DEV_ADDR_A0,
9110 "SFP+ module initialization took %d ms\n",
9112 return ELINK_STATUS_OK;
9116 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9121 static void elink_8727_power_module(struct bxe_softc *sc,
9122 struct elink_phy *phy,
9123 uint8_t is_power_up) {
9124 /* Make sure GPIOs are not using for LED mode */
9126 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
9127 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
9129 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
9130 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
9131 * where the 1st bit is the over-current(only input), and 2nd bit is
9132 * for power( only output )
9134 * In case of NOC feature is disabled and power is up, set GPIO control
9135 * as input to enable listening of over-current indication
9137 if (phy->flags & ELINK_FLAGS_NOC)
9142 /* Set GPIO control to OUTPUT, and set the power bit
9143 * to according to the is_power_up
9147 elink_cl45_write(sc, phy,
9149 MDIO_PMA_REG_8727_GPIO_CTRL,
9153 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc,
9154 struct elink_phy *phy,
9157 uint16_t cur_limiting_mode;
9159 elink_cl45_read(sc, phy,
9161 MDIO_PMA_REG_ROM_VER2,
9162 &cur_limiting_mode);
9163 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",
9166 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
9167 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n");
9168 elink_cl45_write(sc, phy,
9170 MDIO_PMA_REG_ROM_VER2,
9171 ELINK_EDC_MODE_LIMITING);
9172 } else { /* LRM mode ( default )*/
9174 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n");
9176 /* Changing to LRM mode takes quite few seconds. So do it only
9177 * if current mode is limiting (default is LRM)
9179 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
9180 return ELINK_STATUS_OK;
9182 elink_cl45_write(sc, phy,
9184 MDIO_PMA_REG_LRM_MODE,
9186 elink_cl45_write(sc, phy,
9188 MDIO_PMA_REG_ROM_VER2,
9190 elink_cl45_write(sc, phy,
9192 MDIO_PMA_REG_MISC_CTRL0,
9194 elink_cl45_write(sc, phy,
9196 MDIO_PMA_REG_LRM_MODE,
9199 return ELINK_STATUS_OK;
9202 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc,
9203 struct elink_phy *phy,
9206 uint16_t phy_identifier;
9207 uint16_t rom_ver2_val;
9208 elink_cl45_read(sc, phy,
9210 MDIO_PMA_REG_PHY_IDENTIFIER,
9213 elink_cl45_write(sc, phy,
9215 MDIO_PMA_REG_PHY_IDENTIFIER,
9216 (phy_identifier & ~(1<<9)));
9218 elink_cl45_read(sc, phy,
9220 MDIO_PMA_REG_ROM_VER2,
9222 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
9223 elink_cl45_write(sc, phy,
9225 MDIO_PMA_REG_ROM_VER2,
9226 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
9228 elink_cl45_write(sc, phy,
9230 MDIO_PMA_REG_PHY_IDENTIFIER,
9231 (phy_identifier | (1<<9)));
9233 return ELINK_STATUS_OK;
9236 static void elink_8727_specific_func(struct elink_phy *phy,
9237 struct elink_params *params,
9240 struct bxe_softc *sc = params->sc;
9243 case ELINK_DISABLE_TX:
9244 elink_sfp_set_transmitter(params, phy, 0);
9246 case ELINK_ENABLE_TX:
9247 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9248 elink_sfp_set_transmitter(params, phy, 1);
9250 case ELINK_PHY_INIT:
9251 elink_cl45_write(sc, phy,
9252 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9254 elink_cl45_write(sc, phy,
9255 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9257 elink_cl45_write(sc, phy,
9258 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
9259 /* Make MOD_ABS give interrupt on change */
9260 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9261 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9264 if (phy->flags & ELINK_FLAGS_NOC)
9266 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9267 * status which reflect SFP+ module over-current
9269 if (!(phy->flags & ELINK_FLAGS_NOC))
9270 val &= 0xff8f; /* Reset bits 4-6 */
9271 elink_cl45_write(sc, phy,
9272 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9276 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",
9282 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
9285 struct bxe_softc *sc = params->sc;
9287 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9288 offsetof(struct shmem_region,
9289 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9290 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
9291 switch (fault_led_gpio) {
9292 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
9294 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
9295 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
9296 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
9297 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
9299 uint8_t gpio_port = elink_get_gpio_port(params);
9300 uint16_t gpio_pin = fault_led_gpio -
9301 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
9302 ELINK_DEBUG_P3(sc, "Set fault module-detected led "
9303 "pin %x port %x mode %x\n",
9304 gpio_pin, gpio_port, gpio_mode);
9305 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
9309 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",
9314 static void elink_set_e3_module_fault_led(struct elink_params *params,
9318 uint8_t port = params->port;
9319 struct bxe_softc *sc = params->sc;
9320 pin_cfg = (REG_RD(sc, params->shmem_base +
9321 offsetof(struct shmem_region,
9322 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9323 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
9324 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
9325 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n",
9326 gpio_mode, pin_cfg);
9327 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
9330 static void elink_set_sfp_module_fault_led(struct elink_params *params,
9333 struct bxe_softc *sc = params->sc;
9334 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9335 if (CHIP_IS_E3(sc)) {
9336 /* Low ==> if SFP+ module is supported otherwise
9337 * High ==> if SFP+ module is not on the approved vendor list
9339 elink_set_e3_module_fault_led(params, gpio_mode);
9341 elink_set_e1e2_module_fault_led(params, gpio_mode);
9344 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9345 struct elink_params *params)
9347 struct bxe_softc *sc = params->sc;
9348 elink_warpcore_power_module(params, 0);
9349 /* Put Warpcore in low power mode */
9350 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9352 /* Put LCPLL in low power mode */
9353 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9354 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9355 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9358 static void elink_power_sfp_module(struct elink_params *params,
9359 struct elink_phy *phy,
9362 struct bxe_softc *sc = params->sc;
9363 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power);
9365 switch (phy->type) {
9366 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9367 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9368 elink_8727_power_module(params->sc, phy, power);
9370 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9371 elink_warpcore_power_module(params, power);
9377 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
9378 struct elink_phy *phy,
9382 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9383 struct bxe_softc *sc = params->sc;
9385 uint8_t lane = elink_get_warpcore_lane(phy, params);
9386 /* This is a global register which controls all lanes */
9387 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9388 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9389 val &= ~(0xf << (lane << 2));
9392 case ELINK_EDC_MODE_LINEAR:
9393 case ELINK_EDC_MODE_LIMITING:
9394 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9396 case ELINK_EDC_MODE_PASSIVE_DAC:
9397 case ELINK_EDC_MODE_ACTIVE_DAC:
9398 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
9404 val |= (mode << (lane << 2));
9405 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9406 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
9408 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9409 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9411 /* Restart microcode to re-read the new mode */
9412 elink_warpcore_reset_lane(sc, phy, 1);
9413 elink_warpcore_reset_lane(sc, phy, 0);
9417 static void elink_set_limiting_mode(struct elink_params *params,
9418 struct elink_phy *phy,
9421 switch (phy->type) {
9422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9423 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9426 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9427 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9430 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9435 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9436 struct elink_params *params)
9438 struct bxe_softc *sc = params->sc;
9440 elink_status_t rc = ELINK_STATUS_OK;
9442 uint32_t val = REG_RD(sc, params->shmem_base +
9443 offsetof(struct shmem_region, dev_info.
9444 port_feature_config[params->port].config));
9445 /* Enabled transmitter by default */
9446 elink_sfp_set_transmitter(params, phy, 1);
9447 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9449 /* Power up module */
9450 elink_power_sfp_module(params, phy, 1);
9451 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9452 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n");
9453 return ELINK_STATUS_ERROR;
9454 } else if (elink_verify_sfp_module(phy, params) != 0) {
9455 /* Check SFP+ module compatibility */
9456 ELINK_DEBUG_P0(sc, "Module verification failed!!\n");
9457 rc = ELINK_STATUS_ERROR;
9458 /* Turn on fault module-detected led */
9459 elink_set_sfp_module_fault_led(params,
9460 MISC_REGISTERS_GPIO_HIGH);
9462 /* Check if need to power down the SFP+ module */
9463 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9464 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
9465 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n");
9466 elink_power_sfp_module(params, phy, 0);
9470 /* Turn off fault module-detected led */
9471 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
9474 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
9475 * is done automatically
9477 elink_set_limiting_mode(params, phy, edc_mode);
9479 /* Disable transmit for this module if the module is not approved, and
9480 * laser needs to be disabled.
9483 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9484 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
9485 elink_sfp_set_transmitter(params, phy, 0);
9490 void elink_handle_module_detect_int(struct elink_params *params)
9492 struct bxe_softc *sc = params->sc;
9493 struct elink_phy *phy;
9495 uint8_t gpio_num, gpio_port;
9496 if (CHIP_IS_E3(sc)) {
9497 phy = ¶ms->phy[ELINK_INT_PHY];
9498 /* Always enable TX laser,will be disabled in case of fault */
9499 elink_sfp_set_transmitter(params, phy, 1);
9501 phy = ¶ms->phy[ELINK_EXT_PHY1];
9503 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
9504 params->port, &gpio_num, &gpio_port) ==
9505 ELINK_STATUS_ERROR) {
9506 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n");
9510 /* Set valid module led off */
9511 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
9513 /* Get current gpio val reflecting module plugged in / out*/
9514 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
9516 /* Call the handling function in case module is detected */
9517 if (gpio_val == 0) {
9518 elink_set_mdio_emac_per_phy(sc, params);
9519 elink_set_aer_mmd(params, phy);
9521 elink_power_sfp_module(params, phy, 1);
9522 elink_cb_gpio_int_write(sc, gpio_num,
9523 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
9525 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9526 elink_sfp_module_detection(phy, params);
9527 if (CHIP_IS_E3(sc)) {
9528 uint16_t rx_tx_in_reset;
9529 /* In case WC is out of reset, reconfigure the
9530 * link speed while taking into account 1G
9531 * module limitation.
9533 elink_cl45_read(sc, phy,
9535 MDIO_WC_REG_DIGITAL5_MISC6,
9537 if ((!rx_tx_in_reset) &&
9538 (params->link_flags &
9539 ELINK_PHY_INITIALIZED)) {
9540 elink_warpcore_reset_lane(sc, phy, 1);
9541 elink_warpcore_config_sfi(phy, params);
9542 elink_warpcore_reset_lane(sc, phy, 0);
9546 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
9549 elink_cb_gpio_int_write(sc, gpio_num,
9550 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
9552 /* Module was plugged out.
9553 * Disable transmit for this module
9555 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9559 /******************************************************************/
9560 /* Used by 8706 and 8727 */
9561 /******************************************************************/
9562 static void elink_sfp_mask_fault(struct bxe_softc *sc,
9563 struct elink_phy *phy,
9564 uint16_t alarm_status_offset,
9565 uint16_t alarm_ctrl_offset)
9567 uint16_t alarm_status, val;
9568 elink_cl45_read(sc, phy,
9569 MDIO_PMA_DEVAD, alarm_status_offset,
9571 elink_cl45_read(sc, phy,
9572 MDIO_PMA_DEVAD, alarm_status_offset,
9574 /* Mask or enable the fault event. */
9575 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9576 if (alarm_status & (1<<0))
9580 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9582 /******************************************************************/
9583 /* common BCM8706/BCM8726 PHY SECTION */
9584 /******************************************************************/
9585 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9586 struct elink_params *params,
9587 struct elink_vars *vars)
9589 uint8_t link_up = 0;
9590 uint16_t val1, val2, rx_sd, pcs_status;
9591 struct bxe_softc *sc = params->sc;
9592 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n");
9594 elink_cl45_read(sc, phy,
9595 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
9597 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9598 MDIO_PMA_LASI_TXCTRL);
9600 /* Clear LASI indication*/
9601 elink_cl45_read(sc, phy,
9602 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9603 elink_cl45_read(sc, phy,
9604 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
9605 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9607 elink_cl45_read(sc, phy,
9608 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
9609 elink_cl45_read(sc, phy,
9610 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
9611 elink_cl45_read(sc, phy,
9612 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9613 elink_cl45_read(sc, phy,
9614 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9616 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9617 " link_status 0x%x\n", rx_sd, pcs_status, val2);
9618 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
9619 * are set, or if the autoneg bit 1 is set
9621 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
9624 vars->line_speed = ELINK_SPEED_1000;
9626 vars->line_speed = ELINK_SPEED_10000;
9627 elink_ext_phy_resolve_fc(phy, params, vars);
9628 vars->duplex = DUPLEX_FULL;
9631 /* Capture 10G link fault. Read twice to clear stale value. */
9632 if (vars->line_speed == ELINK_SPEED_10000) {
9633 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9634 MDIO_PMA_LASI_TXSTAT, &val1);
9635 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9636 MDIO_PMA_LASI_TXSTAT, &val1);
9638 vars->fault_detected = 1;
9644 /******************************************************************/
9645 /* BCM8706 PHY SECTION */
9646 /******************************************************************/
9647 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9648 struct elink_params *params,
9649 struct elink_vars *vars)
9651 uint32_t tx_en_mode;
9652 uint16_t cnt, val, tmp1;
9653 struct bxe_softc *sc = params->sc;
9655 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9656 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9658 elink_ext_phy_hw_reset(sc, params->port);
9659 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9660 elink_wait_reset_complete(sc, phy, params);
9662 /* Wait until fw is loaded */
9663 for (cnt = 0; cnt < 100; cnt++) {
9664 elink_cl45_read(sc, phy,
9665 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
9670 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt);
9671 if ((params->feature_config_flags &
9672 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9675 for (i = 0; i < 4; i++) {
9676 reg = MDIO_XS_8706_REG_BANK_RX0 +
9677 i*(MDIO_XS_8706_REG_BANK_RX1 -
9678 MDIO_XS_8706_REG_BANK_RX0);
9679 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9680 /* Clear first 3 bits of the control */
9682 /* Set control bits according to configuration */
9683 val |= (phy->rx_preemphasis[i] & 0x7);
9684 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706"
9685 " reg 0x%x <-- val 0x%x\n", reg, val);
9686 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9690 if (phy->req_line_speed == ELINK_SPEED_10000) {
9691 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n");
9693 elink_cl45_write(sc, phy,
9695 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9696 elink_cl45_write(sc, phy,
9697 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9699 /* Arm LASI for link and Tx fault. */
9700 elink_cl45_write(sc, phy,
9701 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9703 /* Force 1Gbps using autoneg with 1G advertisement */
9705 /* Allow CL37 through CL73 */
9706 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n");
9707 elink_cl45_write(sc, phy,
9708 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9710 /* Enable Full-Duplex advertisement on CL37 */
9711 elink_cl45_write(sc, phy,
9712 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9713 /* Enable CL37 AN */
9714 elink_cl45_write(sc, phy,
9715 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9717 elink_cl45_write(sc, phy,
9718 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9720 /* Enable clause 73 AN */
9721 elink_cl45_write(sc, phy,
9722 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9723 elink_cl45_write(sc, phy,
9724 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9726 elink_cl45_write(sc, phy,
9727 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9730 elink_save_bcm_spirom_ver(sc, phy, params->port);
9732 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9733 * power mode, if TX Laser is disabled
9736 tx_en_mode = REG_RD(sc, params->shmem_base +
9737 offsetof(struct shmem_region,
9738 dev_info.port_hw_config[params->port].sfp_ctrl))
9739 & PORT_HW_CFG_TX_LASER_MASK;
9741 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9742 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
9743 elink_cl45_read(sc, phy,
9744 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9746 elink_cl45_write(sc, phy,
9747 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9750 return ELINK_STATUS_OK;
9753 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9754 struct elink_params *params,
9755 struct elink_vars *vars)
9757 return elink_8706_8726_read_status(phy, params, vars);
9760 /******************************************************************/
9761 /* BCM8726 PHY SECTION */
9762 /******************************************************************/
9763 static void elink_8726_config_loopback(struct elink_phy *phy,
9764 struct elink_params *params)
9766 struct bxe_softc *sc = params->sc;
9767 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n");
9768 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9771 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9772 struct elink_params *params)
9774 struct bxe_softc *sc = params->sc;
9775 /* Need to wait 100ms after reset */
9778 /* Micro controller re-boot */
9779 elink_cl45_write(sc, phy,
9780 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9782 /* Set soft reset */
9783 elink_cl45_write(sc, phy,
9785 MDIO_PMA_REG_GEN_CTRL,
9786 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9788 elink_cl45_write(sc, phy,
9790 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9792 elink_cl45_write(sc, phy,
9794 MDIO_PMA_REG_GEN_CTRL,
9795 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9797 /* Wait for 150ms for microcode load */
9800 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9801 elink_cl45_write(sc, phy,
9803 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9806 elink_save_bcm_spirom_ver(sc, phy, params->port);
9809 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9810 struct elink_params *params,
9811 struct elink_vars *vars)
9813 struct bxe_softc *sc = params->sc;
9815 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9817 elink_cl45_read(sc, phy,
9818 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9820 if (val1 & (1<<15)) {
9821 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
9823 vars->line_speed = 0;
9830 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9831 struct elink_params *params,
9832 struct elink_vars *vars)
9834 struct bxe_softc *sc = params->sc;
9835 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n");
9837 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9838 elink_wait_reset_complete(sc, phy, params);
9840 elink_8726_external_rom_boot(phy, params);
9842 /* Need to call module detected on initialization since the module
9843 * detection triggered by actual module insertion might occur before
9844 * driver is loaded, and when driver is loaded, it reset all
9845 * registers, including the transmitter
9847 elink_sfp_module_detection(phy, params);
9849 if (phy->req_line_speed == ELINK_SPEED_1000) {
9850 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9851 elink_cl45_write(sc, phy,
9852 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9853 elink_cl45_write(sc, phy,
9854 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9855 elink_cl45_write(sc, phy,
9856 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9857 elink_cl45_write(sc, phy,
9858 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9860 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9861 (phy->speed_cap_mask &
9862 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9863 ((phy->speed_cap_mask &
9864 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9865 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9866 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
9867 /* Set Flow control */
9868 elink_ext_phy_set_pause(params, phy, vars);
9869 elink_cl45_write(sc, phy,
9870 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9871 elink_cl45_write(sc, phy,
9872 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9873 elink_cl45_write(sc, phy,
9874 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9875 elink_cl45_write(sc, phy,
9876 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9877 elink_cl45_write(sc, phy,
9878 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9879 /* Enable RX-ALARM control to receive interrupt for 1G speed
9882 elink_cl45_write(sc, phy,
9883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9884 elink_cl45_write(sc, phy,
9885 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9888 } else { /* Default 10G. Set only LASI control */
9889 elink_cl45_write(sc, phy,
9890 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9893 /* Set TX PreEmphasis if needed */
9894 if ((params->feature_config_flags &
9895 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9897 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9898 phy->tx_preemphasis[0],
9899 phy->tx_preemphasis[1]);
9900 elink_cl45_write(sc, phy,
9902 MDIO_PMA_REG_8726_TX_CTRL1,
9903 phy->tx_preemphasis[0]);
9905 elink_cl45_write(sc, phy,
9907 MDIO_PMA_REG_8726_TX_CTRL2,
9908 phy->tx_preemphasis[1]);
9911 return ELINK_STATUS_OK;
9915 static void elink_8726_link_reset(struct elink_phy *phy,
9916 struct elink_params *params)
9918 struct bxe_softc *sc = params->sc;
9919 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
9920 /* Set serial boot control for external load */
9921 elink_cl45_write(sc, phy,
9923 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9926 /******************************************************************/
9927 /* BCM8727 PHY SECTION */
9928 /******************************************************************/
9930 static void elink_8727_set_link_led(struct elink_phy *phy,
9931 struct elink_params *params, uint8_t mode)
9933 struct bxe_softc *sc = params->sc;
9934 uint16_t led_mode_bitmask = 0;
9935 uint16_t gpio_pins_bitmask = 0;
9937 /* Only NOC flavor requires to set the LED specifically */
9938 if (!(phy->flags & ELINK_FLAGS_NOC))
9941 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9942 case ELINK_LED_MODE_OFF:
9943 led_mode_bitmask = 0;
9944 gpio_pins_bitmask = 0x03;
9946 case ELINK_LED_MODE_ON:
9947 led_mode_bitmask = 0;
9948 gpio_pins_bitmask = 0x02;
9950 case ELINK_LED_MODE_OPER:
9951 led_mode_bitmask = 0x60;
9952 gpio_pins_bitmask = 0x11;
9955 elink_cl45_read(sc, phy,
9957 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9960 val |= led_mode_bitmask;
9961 elink_cl45_write(sc, phy,
9963 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9965 elink_cl45_read(sc, phy,
9967 MDIO_PMA_REG_8727_GPIO_CTRL,
9970 val |= gpio_pins_bitmask;
9971 elink_cl45_write(sc, phy,
9973 MDIO_PMA_REG_8727_GPIO_CTRL,
9976 static void elink_8727_hw_reset(struct elink_phy *phy,
9977 struct elink_params *params) {
9978 uint32_t swap_val, swap_override;
9980 /* The PHY reset is controlled by GPIO 1. Fake the port number
9981 * to cancel the swap done in set_gpio()
9983 struct bxe_softc *sc = params->sc;
9984 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
9985 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
9986 port = (swap_val && swap_override) ^ 1;
9987 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
9988 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9991 static void elink_8727_config_speed(struct elink_phy *phy,
9992 struct elink_params *params)
9994 struct bxe_softc *sc = params->sc;
9996 /* Set option 1G speed */
9997 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
9998 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
9999 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
10000 elink_cl45_write(sc, phy,
10001 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
10002 elink_cl45_write(sc, phy,
10003 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
10004 elink_cl45_read(sc, phy,
10005 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
10006 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
10007 /* Power down the XAUI until link is up in case of dual-media
10010 if (ELINK_DUAL_MEDIA(params)) {
10011 elink_cl45_read(sc, phy,
10013 MDIO_PMA_REG_8727_PCS_GP, &val);
10015 elink_cl45_write(sc, phy,
10017 MDIO_PMA_REG_8727_PCS_GP, val);
10019 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10020 ((phy->speed_cap_mask &
10021 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
10022 ((phy->speed_cap_mask &
10023 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10024 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10026 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10027 elink_cl45_write(sc, phy,
10028 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
10029 elink_cl45_write(sc, phy,
10030 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
10032 /* Since the 8727 has only single reset pin, need to set the 10G
10033 * registers although it is default
10035 elink_cl45_write(sc, phy,
10036 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
10038 elink_cl45_write(sc, phy,
10039 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
10040 elink_cl45_write(sc, phy,
10041 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
10042 elink_cl45_write(sc, phy,
10043 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
10048 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10049 struct elink_params *params,
10050 struct elink_vars *vars)
10052 uint32_t tx_en_mode;
10053 uint16_t tmp1, mod_abs, tmp2;
10054 struct bxe_softc *sc = params->sc;
10055 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
10057 elink_wait_reset_complete(sc, phy, params);
10059 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n");
10061 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10062 /* Initially configure MOD_ABS to interrupt when module is
10065 elink_cl45_read(sc, phy,
10066 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10067 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
10068 * When the EDC is off it locks onto a reference clock and avoids
10071 mod_abs &= ~(1<<8);
10072 if (!(phy->flags & ELINK_FLAGS_NOC))
10073 mod_abs &= ~(1<<9);
10074 elink_cl45_write(sc, phy,
10075 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10077 /* Enable/Disable PHY transmitter output */
10078 elink_set_disable_pmd_transmit(params, phy, 0);
10080 elink_8727_power_module(sc, phy, 1);
10082 elink_cl45_read(sc, phy,
10083 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
10085 elink_cl45_read(sc, phy,
10086 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
10088 elink_8727_config_speed(phy, params);
10091 /* Set TX PreEmphasis if needed */
10092 if ((params->feature_config_flags &
10093 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10094 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10095 phy->tx_preemphasis[0],
10096 phy->tx_preemphasis[1]);
10097 elink_cl45_write(sc, phy,
10098 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
10099 phy->tx_preemphasis[0]);
10101 elink_cl45_write(sc, phy,
10102 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
10103 phy->tx_preemphasis[1]);
10106 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
10107 * power mode, if TX Laser is disabled
10109 tx_en_mode = REG_RD(sc, params->shmem_base +
10110 offsetof(struct shmem_region,
10111 dev_info.port_hw_config[params->port].sfp_ctrl))
10112 & PORT_HW_CFG_TX_LASER_MASK;
10114 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
10116 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
10117 elink_cl45_read(sc, phy,
10118 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
10121 elink_cl45_write(sc, phy,
10122 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
10123 elink_cl45_read(sc, phy,
10124 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10126 elink_cl45_write(sc, phy,
10127 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10131 return ELINK_STATUS_OK;
10134 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10135 struct elink_params *params)
10137 struct bxe_softc *sc = params->sc;
10138 uint16_t mod_abs, rx_alarm_status;
10139 uint32_t val = REG_RD(sc, params->shmem_base +
10140 offsetof(struct shmem_region, dev_info.
10141 port_feature_config[params->port].
10143 elink_cl45_read(sc, phy,
10145 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10146 if (mod_abs & (1<<8)) {
10148 /* Module is absent */
10150 "MOD_ABS indication show module is absent\n");
10151 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10152 /* 1. Set mod_abs to detect next module
10154 * 2. Set EDC off by setting OPTXLOS signal input to low
10156 * When the EDC is off it locks onto a reference clock and
10157 * avoids becoming 'lost'.
10159 mod_abs &= ~(1<<8);
10160 if (!(phy->flags & ELINK_FLAGS_NOC))
10161 mod_abs &= ~(1<<9);
10162 elink_cl45_write(sc, phy,
10164 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10166 /* Clear RX alarm since it stays up as long as
10167 * the mod_abs wasn't changed
10169 elink_cl45_read(sc, phy,
10171 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10174 /* Module is present */
10176 "MOD_ABS indication show module is present\n");
10177 /* First disable transmitter, and if the module is ok, the
10178 * module_detection will enable it
10179 * 1. Set mod_abs to detect next module absent event ( bit 8)
10180 * 2. Restore the default polarity of the OPRXLOS signal and
10181 * this signal will then correctly indicate the presence or
10182 * absence of the Rx signal. (bit 9)
10185 if (!(phy->flags & ELINK_FLAGS_NOC))
10187 elink_cl45_write(sc, phy,
10189 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10191 /* Clear RX alarm since it stays up as long as the mod_abs
10192 * wasn't changed. This is need to be done before calling the
10193 * module detection, otherwise it will clear* the link update
10196 elink_cl45_read(sc, phy,
10198 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10201 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
10202 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
10203 elink_sfp_set_transmitter(params, phy, 0);
10205 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10206 elink_sfp_module_detection(phy, params);
10208 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
10210 /* Reconfigure link speed based on module type limitations */
10211 elink_8727_config_speed(phy, params);
10214 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",
10216 /* No need to check link status in case of module plugged in/out */
10219 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10220 struct elink_params *params,
10221 struct elink_vars *vars)
10224 struct bxe_softc *sc = params->sc;
10225 uint8_t link_up = 0, oc_port = params->port;
10226 uint16_t link_status = 0;
10227 uint16_t rx_alarm_status, lasi_ctrl, val1;
10229 /* If PHY is not initialized, do not check link status */
10230 elink_cl45_read(sc, phy,
10231 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
10236 /* Check the LASI on Rx */
10237 elink_cl45_read(sc, phy,
10238 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
10240 vars->line_speed = 0;
10241 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10243 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10244 MDIO_PMA_LASI_TXCTRL);
10246 elink_cl45_read(sc, phy,
10247 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10249 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);
10251 /* Clear MSG-OUT */
10252 elink_cl45_read(sc, phy,
10253 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
10255 /* If a module is present and there is need to check
10258 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10259 /* Check over-current using 8727 GPIO0 input*/
10260 elink_cl45_read(sc, phy,
10261 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
10264 if ((val1 & (1<<8)) == 0) {
10265 if (!CHIP_IS_E1x(sc))
10266 oc_port = SC_PATH(sc) + (params->port << 1);
10268 "8727 Power fault has been detected on port %d\n",
10270 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10271 // "been detected and the power to "
10272 // "that SFP+ module has been removed "
10273 // "to prevent failure of the card. "
10274 // "Please remove the SFP+ module and "
10275 // "restart the system to clear this "
10277 /* Disable all RX_ALARMs except for mod_abs */
10278 elink_cl45_write(sc, phy,
10280 MDIO_PMA_LASI_RXCTRL, (1<<5));
10282 elink_cl45_read(sc, phy,
10284 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
10285 /* Wait for module_absent_event */
10287 elink_cl45_write(sc, phy,
10289 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
10290 /* Clear RX alarm */
10291 elink_cl45_read(sc, phy,
10293 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10294 elink_8727_power_module(params->sc, phy, 0);
10297 } /* Over current check */
10299 /* When module absent bit is set, check module */
10300 if (rx_alarm_status & (1<<5)) {
10301 elink_8727_handle_mod_abs(phy, params);
10302 /* Enable all mod_abs and link detection bits */
10303 elink_cl45_write(sc, phy,
10304 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10305 ((1<<5) | (1<<2)));
10308 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10309 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n");
10310 elink_sfp_set_transmitter(params, phy, 1);
10312 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
10316 elink_cl45_read(sc, phy,
10318 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
10320 /* Bits 0..2 --> speed detected,
10321 * Bits 13..15--> link is down
10323 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
10325 vars->line_speed = ELINK_SPEED_10000;
10326 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10328 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
10330 vars->line_speed = ELINK_SPEED_1000;
10331 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10335 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10339 /* Capture 10G link fault. */
10340 if (vars->line_speed == ELINK_SPEED_10000) {
10341 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10342 MDIO_PMA_LASI_TXSTAT, &val1);
10344 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10345 MDIO_PMA_LASI_TXSTAT, &val1);
10347 if (val1 & (1<<0)) {
10348 vars->fault_detected = 1;
10353 elink_ext_phy_resolve_fc(phy, params, vars);
10354 vars->duplex = DUPLEX_FULL;
10355 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);
10358 if ((ELINK_DUAL_MEDIA(params)) &&
10359 (phy->req_line_speed == ELINK_SPEED_1000)) {
10360 elink_cl45_read(sc, phy,
10362 MDIO_PMA_REG_8727_PCS_GP, &val1);
10363 /* In case of dual-media board and 1G, power up the XAUI side,
10364 * otherwise power it down. For 10G it is done automatically
10370 elink_cl45_write(sc, phy,
10372 MDIO_PMA_REG_8727_PCS_GP, val1);
10377 static void elink_8727_link_reset(struct elink_phy *phy,
10378 struct elink_params *params)
10380 struct bxe_softc *sc = params->sc;
10382 /* Enable/Disable PHY transmitter output */
10383 elink_set_disable_pmd_transmit(params, phy, 1);
10385 /* Disable Transmitter */
10386 elink_sfp_set_transmitter(params, phy, 0);
10388 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10392 /******************************************************************/
10393 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
10394 /******************************************************************/
10395 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10396 struct bxe_softc *sc,
10399 uint16_t val, fw_ver2, cnt, i;
10400 static struct elink_reg_set reg_set[] = {
10401 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
10402 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
10403 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
10404 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
10405 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
10409 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10410 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10411 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10412 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10415 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
10416 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
10417 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10418 elink_cl45_write(sc, phy, reg_set[i].devad,
10419 reg_set[i].reg, reg_set[i].val);
10421 for (cnt = 0; cnt < 100; cnt++) {
10422 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10428 ELINK_DEBUG_P0(sc, "Unable to read 848xx "
10429 "phy fw version(1)\n");
10430 elink_save_spirom_version(sc, port, 0,
10436 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
10437 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10438 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10439 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10440 for (cnt = 0; cnt < 100; cnt++) {
10441 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10447 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10449 elink_save_spirom_version(sc, port, 0,
10454 /* lower 16 bits of the register SPI_FW_STATUS */
10455 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10456 /* upper 16 bits of register SPI_FW_STATUS */
10457 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10459 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10464 static void elink_848xx_set_led(struct bxe_softc *sc,
10465 struct elink_phy *phy)
10467 uint16_t val, offset, i;
10468 static struct elink_reg_set reg_set[] = {
10469 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
10470 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
10471 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
10472 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
10473 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
10474 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
10475 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
10477 /* PHYC_CTL_LED_CTL */
10478 elink_cl45_read(sc, phy,
10480 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10484 elink_cl45_write(sc, phy,
10486 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10488 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10489 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10492 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10493 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10494 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
10496 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
10498 /* stretch_en for LED3*/
10499 elink_cl45_read_or_write(sc, phy,
10500 MDIO_PMA_DEVAD, offset,
10501 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
10504 static void elink_848xx_specific_func(struct elink_phy *phy,
10505 struct elink_params *params,
10508 struct bxe_softc *sc = params->sc;
10510 case ELINK_PHY_INIT:
10511 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10512 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10513 /* Save spirom version */
10514 elink_save_848xx_spirom_version(phy, sc, params->port);
10516 /* This phy uses the NIG latch mechanism since link indication
10517 * arrives through its LED4 and not via its LASI signal, so we
10518 * get steady signal instead of clear on read
10520 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10521 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
10523 elink_848xx_set_led(sc, phy);
10528 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10529 struct elink_params *params,
10530 struct elink_vars *vars)
10532 struct bxe_softc *sc = params->sc;
10533 uint16_t autoneg_val, an_1000_val, an_10_100_val;
10535 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10536 elink_cl45_write(sc, phy,
10537 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
10539 /* set 1000 speed advertisement */
10540 elink_cl45_read(sc, phy,
10541 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10544 elink_ext_phy_set_pause(params, phy, vars);
10545 elink_cl45_read(sc, phy,
10547 MDIO_AN_REG_8481_LEGACY_AN_ADV,
10549 elink_cl45_read(sc, phy,
10550 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10552 /* Disable forced speed */
10553 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10554 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
10556 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10557 (phy->speed_cap_mask &
10558 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10559 (phy->req_line_speed == ELINK_SPEED_1000)) {
10560 an_1000_val |= (1<<8);
10561 autoneg_val |= (1<<9 | 1<<12);
10562 if (phy->req_duplex == DUPLEX_FULL)
10563 an_1000_val |= (1<<9);
10564 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
10566 an_1000_val &= ~((1<<8) | (1<<9));
10568 elink_cl45_write(sc, phy,
10569 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10572 /* Set 10/100 speed advertisement */
10573 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10574 if (phy->speed_cap_mask &
10575 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10576 /* Enable autoneg and restart autoneg for legacy speeds
10578 autoneg_val |= (1<<9 | 1<<12);
10579 an_10_100_val |= (1<<8);
10580 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
10583 if (phy->speed_cap_mask &
10584 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10585 /* Enable autoneg and restart autoneg for legacy speeds
10587 autoneg_val |= (1<<9 | 1<<12);
10588 an_10_100_val |= (1<<7);
10589 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
10592 if ((phy->speed_cap_mask &
10593 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
10594 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10595 an_10_100_val |= (1<<6);
10596 autoneg_val |= (1<<9 | 1<<12);
10597 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
10600 if ((phy->speed_cap_mask &
10601 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
10602 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10603 an_10_100_val |= (1<<5);
10604 autoneg_val |= (1<<9 | 1<<12);
10605 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
10609 /* Only 10/100 are allowed to work in FORCE mode */
10610 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10612 (ELINK_SUPPORTED_100baseT_Half |
10613 ELINK_SUPPORTED_100baseT_Full))) {
10614 autoneg_val |= (1<<13);
10615 /* Enabled AUTO-MDIX when autoneg is disabled */
10616 elink_cl45_write(sc, phy,
10617 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10618 (1<<15 | 1<<9 | 7<<0));
10619 /* The PHY needs this set even for forced link. */
10620 an_10_100_val |= (1<<8) | (1<<7);
10621 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
10623 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10625 (ELINK_SUPPORTED_10baseT_Half |
10626 ELINK_SUPPORTED_10baseT_Full))) {
10627 /* Enabled AUTO-MDIX when autoneg is disabled */
10628 elink_cl45_write(sc, phy,
10629 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10630 (1<<15 | 1<<9 | 7<<0));
10631 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
10634 elink_cl45_write(sc, phy,
10635 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
10638 if (phy->req_duplex == DUPLEX_FULL)
10639 autoneg_val |= (1<<8);
10641 /* Always write this if this is not 84833/4.
10642 * For 84833/4, write it only when it's a forced speed.
10644 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10645 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
10646 ((autoneg_val & (1<<12)) == 0))
10647 elink_cl45_write(sc, phy,
10649 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
10651 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10652 (phy->speed_cap_mask &
10653 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10654 (phy->req_line_speed == ELINK_SPEED_10000)) {
10655 ELINK_DEBUG_P0(sc, "Advertising 10G\n");
10656 /* Restart autoneg for 10G*/
10658 elink_cl45_read_or_write(
10661 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10663 elink_cl45_write(sc, phy,
10664 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10667 elink_cl45_write(sc, phy,
10669 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10672 return ELINK_STATUS_OK;
10675 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10676 struct elink_params *params,
10677 struct elink_vars *vars)
10679 struct bxe_softc *sc = params->sc;
10680 /* Restore normal power mode*/
10681 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10682 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10685 elink_ext_phy_hw_reset(sc, params->port);
10686 elink_wait_reset_complete(sc, phy, params);
10688 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10689 return elink_848xx_cmn_config_init(phy, params, vars);
10692 #define PHY84833_CMDHDLR_WAIT 300
10693 #define PHY84833_CMDHDLR_MAX_ARGS 5
10694 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10695 struct elink_params *params, uint16_t fw_cmd,
10696 uint16_t cmd_args[], int argc)
10700 struct bxe_softc *sc = params->sc;
10701 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10702 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10703 MDIO_84833_CMD_HDLR_STATUS,
10704 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10705 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10706 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10707 MDIO_84833_CMD_HDLR_STATUS, &val);
10708 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10712 if (idx >= PHY84833_CMDHDLR_WAIT) {
10713 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10714 return ELINK_STATUS_ERROR;
10717 /* Prepare argument(s) and issue command */
10718 for (idx = 0; idx < argc; idx++) {
10719 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10720 MDIO_84833_CMD_HDLR_DATA1 + idx,
10723 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10724 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
10725 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10726 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10727 MDIO_84833_CMD_HDLR_STATUS, &val);
10728 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10729 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10733 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
10734 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10735 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10736 return ELINK_STATUS_ERROR;
10738 /* Gather returning data */
10739 for (idx = 0; idx < argc; idx++) {
10740 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10741 MDIO_84833_CMD_HDLR_DATA1 + idx,
10744 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10745 MDIO_84833_CMD_HDLR_STATUS,
10746 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10747 return ELINK_STATUS_OK;
10750 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
10751 struct elink_params *params,
10752 struct elink_vars *vars)
10754 uint32_t pair_swap;
10755 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
10756 elink_status_t status;
10757 struct bxe_softc *sc = params->sc;
10759 /* Check for configuration. */
10760 pair_swap = REG_RD(sc, params->shmem_base +
10761 offsetof(struct shmem_region,
10762 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10763 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10765 if (pair_swap == 0)
10766 return ELINK_STATUS_OK;
10768 /* Only the second argument is used for this command */
10769 data[1] = (uint16_t)pair_swap;
10771 status = elink_84833_cmd_hdlr(phy, params,
10772 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
10773 if (status == ELINK_STATUS_OK)
10774 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);
10779 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc,
10780 uint32_t shmem_base_path[],
10783 uint32_t reset_pin[2];
10785 uint8_t reset_gpios;
10786 if (CHIP_IS_E3(sc)) {
10787 /* Assume that these will be GPIOs, not EPIOs. */
10788 for (idx = 0; idx < 2; idx++) {
10789 /* Map config param to register bit. */
10790 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10791 offsetof(struct shmem_region,
10792 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10793 reset_pin[idx] = (reset_pin[idx] &
10794 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10795 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10796 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10797 reset_pin[idx] = (1 << reset_pin[idx]);
10799 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10801 /* E2, look from diff place of shmem. */
10802 for (idx = 0; idx < 2; idx++) {
10803 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10804 offsetof(struct shmem_region,
10805 dev_info.port_hw_config[0].default_cfg));
10806 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10807 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10808 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10809 reset_pin[idx] = (1 << reset_pin[idx]);
10811 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10814 return reset_gpios;
10817 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
10818 struct elink_params *params)
10820 struct bxe_softc *sc = params->sc;
10821 uint8_t reset_gpios;
10822 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
10823 offsetof(struct shmem2_region,
10824 other_shmem_base_addr));
10826 uint32_t shmem_base_path[2];
10828 /* Work around for 84833 LED failure inside RESET status */
10829 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10830 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10831 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10832 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10833 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10834 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10836 shmem_base_path[0] = params->shmem_base;
10837 shmem_base_path[1] = other_shmem_base_addr;
10839 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
10842 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10844 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",
10847 return ELINK_STATUS_OK;
10850 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
10851 struct elink_params *params,
10852 struct elink_vars *vars)
10855 struct bxe_softc *sc = params->sc;
10856 uint16_t cmd_args = 0;
10858 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n");
10860 /* Prevent Phy from working in EEE and advertising it */
10861 rc = elink_84833_cmd_hdlr(phy, params,
10862 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10863 if (rc != ELINK_STATUS_OK) {
10864 ELINK_DEBUG_P0(sc, "EEE disable failed.\n");
10868 return elink_eee_disable(phy, params, vars);
10871 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
10872 struct elink_params *params,
10873 struct elink_vars *vars)
10876 struct bxe_softc *sc = params->sc;
10877 uint16_t cmd_args = 1;
10879 rc = elink_84833_cmd_hdlr(phy, params,
10880 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10881 if (rc != ELINK_STATUS_OK) {
10882 ELINK_DEBUG_P0(sc, "EEE enable failed.\n");
10886 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10889 #define PHY84833_CONSTANT_LATENCY 1193
10890 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
10891 struct elink_params *params,
10892 struct elink_vars *vars)
10894 struct bxe_softc *sc = params->sc;
10895 uint8_t port, initialize = 1;
10897 uint32_t actual_phy_selection;
10898 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10899 elink_status_t rc = ELINK_STATUS_OK;
10903 if (!(CHIP_IS_E1x(sc)))
10904 port = SC_PATH(sc);
10906 port = params->port;
10908 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10909 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
10910 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10914 elink_cl45_write(sc, phy,
10916 MDIO_PMA_REG_CTRL, 0x8000);
10919 elink_wait_reset_complete(sc, phy, params);
10921 /* Wait for GPHY to come out of reset */
10923 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10924 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10925 /* BCM84823 requires that XGXS links up first @ 10G for normal
10929 temp = vars->line_speed;
10930 vars->line_speed = ELINK_SPEED_10000;
10931 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
10932 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
10933 vars->line_speed = temp;
10936 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10937 MDIO_CTL_REG_84823_MEDIA, &val);
10938 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10939 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10940 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10941 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10942 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10944 if (CHIP_IS_E3(sc)) {
10945 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10946 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10948 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10949 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10952 actual_phy_selection = elink_phy_selection(params);
10954 switch (actual_phy_selection) {
10955 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10956 /* Do nothing. Essentially this is like the priority copper */
10958 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10959 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10961 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10962 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10964 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10965 /* Do nothing here. The first PHY won't be initialized at all */
10967 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10968 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10972 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
10973 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10975 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10976 MDIO_CTL_REG_84823_MEDIA, val);
10977 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10978 params->multi_phy_config, val);
10980 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10981 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10982 elink_84833_pair_swap_cfg(phy, params, vars);
10984 /* Keep AutogrEEEn disabled. */
10987 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10988 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10989 rc = elink_84833_cmd_hdlr(phy, params,
10990 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10991 PHY84833_CMDHDLR_MAX_ARGS);
10992 if (rc != ELINK_STATUS_OK)
10993 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n");
10996 rc = elink_848xx_cmn_config_init(phy, params, vars);
10998 elink_save_848xx_spirom_version(phy, sc, params->port);
10999 /* 84833 PHY has a better feature and doesn't need to support this. */
11000 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11001 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
11002 offsetof(struct shmem_region,
11003 dev_info.port_hw_config[params->port].default_cfg)) &
11004 PORT_HW_CFG_ENABLE_CMS_MASK;
11006 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11007 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
11009 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
11011 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
11012 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11013 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
11016 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11017 MDIO_84833_TOP_CFG_FW_REV, &val);
11019 /* Configure EEE support */
11020 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
11021 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
11022 elink_eee_has_cap(params)) {
11023 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
11024 if (rc != ELINK_STATUS_OK) {
11025 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11026 elink_8483x_disable_eee(phy, params, vars);
11030 if ((phy->req_duplex == DUPLEX_FULL) &&
11031 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11032 (elink_eee_calc_timer(params) ||
11033 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
11034 rc = elink_8483x_enable_eee(phy, params, vars);
11036 rc = elink_8483x_disable_eee(phy, params, vars);
11037 if (rc != ELINK_STATUS_OK) {
11038 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n");
11042 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
11045 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11046 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11047 /* Bring PHY out of super isolate mode as the final step. */
11048 elink_cl45_read_and_write(sc, phy,
11050 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
11051 (uint16_t)~MDIO_84833_SUPER_ISOLATE);
11056 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11057 struct elink_params *params,
11058 struct elink_vars *vars)
11060 struct bxe_softc *sc = params->sc;
11061 uint16_t val, val1, val2;
11062 uint8_t link_up = 0;
11065 /* Check 10G-BaseT link status */
11066 /* Check PMD signal ok */
11067 elink_cl45_read(sc, phy,
11068 MDIO_AN_DEVAD, 0xFFFA, &val1);
11069 elink_cl45_read(sc, phy,
11070 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
11072 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11074 /* Check link 10G */
11075 if (val2 & (1<<11)) {
11076 vars->line_speed = ELINK_SPEED_10000;
11077 vars->duplex = DUPLEX_FULL;
11079 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11080 } else { /* Check Legacy speed link */
11081 uint16_t legacy_status, legacy_speed, mii_ctrl;
11083 /* Enable expansion register 0x42 (Operation mode status) */
11084 elink_cl45_write(sc, phy,
11086 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
11088 /* Get legacy speed operation status */
11089 elink_cl45_read(sc, phy,
11091 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
11094 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",
11096 link_up = ((legacy_status & (1<<11)) == (1<<11));
11097 legacy_speed = (legacy_status & (3<<9));
11098 if (legacy_speed == (0<<9))
11099 vars->line_speed = ELINK_SPEED_10;
11100 else if (legacy_speed == (1<<9))
11101 vars->line_speed = ELINK_SPEED_100;
11102 else if (legacy_speed == (2<<9))
11103 vars->line_speed = ELINK_SPEED_1000;
11104 else { /* Should not happen: Treat as link down */
11105 vars->line_speed = 0;
11109 if (params->feature_config_flags &
11110 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
11111 elink_cl45_read(sc, phy,
11113 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11115 /* For IEEE testing, check for a fake link. */
11116 link_up |= ((mii_ctrl & 0x3040) == 0x40);
11120 if (legacy_status & (1<<8))
11121 vars->duplex = DUPLEX_FULL;
11123 vars->duplex = DUPLEX_HALF;
11126 "Link is up in %dMbps, is_duplex_full= %d\n",
11128 (vars->duplex == DUPLEX_FULL));
11129 /* Check legacy speed AN resolution */
11130 elink_cl45_read(sc, phy,
11132 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
11135 vars->link_status |=
11136 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11137 elink_cl45_read(sc, phy,
11139 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
11141 if ((val & (1<<0)) == 0)
11142 vars->link_status |=
11143 LINK_STATUS_PARALLEL_DETECTION_USED;
11147 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n",
11149 elink_ext_phy_resolve_fc(phy, params, vars);
11151 /* Read LP advertised speeds */
11152 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11153 MDIO_AN_REG_CL37_FC_LP, &val);
11155 vars->link_status |=
11156 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11158 vars->link_status |=
11159 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11161 vars->link_status |=
11162 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11164 vars->link_status |=
11165 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11167 vars->link_status |=
11168 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11170 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11171 MDIO_AN_REG_1000T_STATUS, &val);
11174 vars->link_status |=
11175 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11177 vars->link_status |=
11178 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11180 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11181 MDIO_AN_REG_MASTER_STATUS, &val);
11184 vars->link_status |=
11185 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11187 /* Determine if EEE was negotiated */
11188 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11189 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
11190 elink_eee_an_resolve(phy, params, vars);
11196 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len)
11198 elink_status_t status = ELINK_STATUS_OK;
11199 uint32_t spirom_ver;
11200 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
11201 status = elink_format_ver(spirom_ver, str, len);
11205 static void elink_8481_hw_reset(struct elink_phy *phy,
11206 struct elink_params *params)
11208 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11209 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
11210 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11211 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
11214 static void elink_8481_link_reset(struct elink_phy *phy,
11215 struct elink_params *params)
11217 elink_cl45_write(params->sc, phy,
11218 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
11219 elink_cl45_write(params->sc, phy,
11220 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
11223 static void elink_848x3_link_reset(struct elink_phy *phy,
11224 struct elink_params *params)
11226 struct bxe_softc *sc = params->sc;
11230 if (!(CHIP_IS_E1x(sc)))
11231 port = SC_PATH(sc);
11233 port = params->port;
11235 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11236 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11237 MISC_REGISTERS_GPIO_OUTPUT_LOW,
11240 elink_cl45_read(sc, phy,
11242 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
11243 val16 |= MDIO_84833_SUPER_ISOLATE;
11244 elink_cl45_write(sc, phy,
11246 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
11250 static void elink_848xx_set_link_led(struct elink_phy *phy,
11251 struct elink_params *params, uint8_t mode)
11253 struct bxe_softc *sc = params->sc;
11257 if (!(CHIP_IS_E1x(sc)))
11258 port = SC_PATH(sc);
11260 port = params->port;
11263 case ELINK_LED_MODE_OFF:
11265 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11267 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11268 SHARED_HW_CFG_LED_EXTPHY1) {
11270 /* Set LED masks */
11271 elink_cl45_write(sc, phy,
11273 MDIO_PMA_REG_8481_LED1_MASK,
11276 elink_cl45_write(sc, phy,
11278 MDIO_PMA_REG_8481_LED2_MASK,
11281 elink_cl45_write(sc, phy,
11283 MDIO_PMA_REG_8481_LED3_MASK,
11286 elink_cl45_write(sc, phy,
11288 MDIO_PMA_REG_8481_LED5_MASK,
11292 elink_cl45_write(sc, phy,
11294 MDIO_PMA_REG_8481_LED1_MASK,
11298 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11300 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11303 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11304 SHARED_HW_CFG_LED_EXTPHY1) {
11306 /* Set LED masks */
11307 elink_cl45_write(sc, phy,
11309 MDIO_PMA_REG_8481_LED1_MASK,
11312 elink_cl45_write(sc, phy,
11314 MDIO_PMA_REG_8481_LED2_MASK,
11317 elink_cl45_write(sc, phy,
11319 MDIO_PMA_REG_8481_LED3_MASK,
11322 elink_cl45_write(sc, phy,
11324 MDIO_PMA_REG_8481_LED5_MASK,
11328 elink_cl45_write(sc, phy,
11330 MDIO_PMA_REG_8481_LED1_MASK,
11333 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11334 /* Disable MI_INT interrupt before setting LED4
11335 * source to constant off.
11337 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11339 ELINK_NIG_MASK_MI_INT) {
11340 params->link_flags |=
11341 ELINK_LINK_FLAGS_INT_DISABLED;
11345 NIG_REG_MASK_INTERRUPT_PORT0 +
11347 ELINK_NIG_MASK_MI_INT);
11349 elink_cl45_write(sc, phy,
11351 MDIO_PMA_REG_8481_SIGNAL_MASK,
11356 case ELINK_LED_MODE_ON:
11358 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11360 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11361 SHARED_HW_CFG_LED_EXTPHY1) {
11362 /* Set control reg */
11363 elink_cl45_read(sc, phy,
11365 MDIO_PMA_REG_8481_LINK_SIGNAL,
11370 elink_cl45_write(sc, phy,
11372 MDIO_PMA_REG_8481_LINK_SIGNAL,
11375 /* Set LED masks */
11376 elink_cl45_write(sc, phy,
11378 MDIO_PMA_REG_8481_LED1_MASK,
11381 elink_cl45_write(sc, phy,
11383 MDIO_PMA_REG_8481_LED2_MASK,
11386 elink_cl45_write(sc, phy,
11388 MDIO_PMA_REG_8481_LED3_MASK,
11391 elink_cl45_write(sc, phy,
11393 MDIO_PMA_REG_8481_LED5_MASK,
11396 elink_cl45_write(sc, phy,
11398 MDIO_PMA_REG_8481_LED1_MASK,
11401 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11402 /* Disable MI_INT interrupt before setting LED4
11403 * source to constant on.
11405 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11407 ELINK_NIG_MASK_MI_INT) {
11408 params->link_flags |=
11409 ELINK_LINK_FLAGS_INT_DISABLED;
11413 NIG_REG_MASK_INTERRUPT_PORT0 +
11415 ELINK_NIG_MASK_MI_INT);
11417 elink_cl45_write(sc, phy,
11419 MDIO_PMA_REG_8481_SIGNAL_MASK,
11425 case ELINK_LED_MODE_OPER:
11427 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11429 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11430 SHARED_HW_CFG_LED_EXTPHY1) {
11432 /* Set control reg */
11433 elink_cl45_read(sc, phy,
11435 MDIO_PMA_REG_8481_LINK_SIGNAL,
11439 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
11440 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
11441 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n");
11442 elink_cl45_write(sc, phy,
11444 MDIO_PMA_REG_8481_LINK_SIGNAL,
11448 /* Set LED masks */
11449 elink_cl45_write(sc, phy,
11451 MDIO_PMA_REG_8481_LED1_MASK,
11454 elink_cl45_write(sc, phy,
11456 MDIO_PMA_REG_8481_LED2_MASK,
11459 elink_cl45_write(sc, phy,
11461 MDIO_PMA_REG_8481_LED3_MASK,
11464 elink_cl45_write(sc, phy,
11466 MDIO_PMA_REG_8481_LED5_MASK,
11470 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11471 * sources are all wired through LED1, rather than only
11472 * 10G in other modes.
11474 val = ((params->hw_led_mode <<
11475 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11476 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11478 elink_cl45_write(sc, phy,
11480 MDIO_PMA_REG_8481_LED1_MASK,
11483 /* Tell LED3 to blink on source */
11484 elink_cl45_read(sc, phy,
11486 MDIO_PMA_REG_8481_LINK_SIGNAL,
11489 val |= (1<<6); /* A83B[8:6]= 1 */
11490 elink_cl45_write(sc, phy,
11492 MDIO_PMA_REG_8481_LINK_SIGNAL,
11495 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11496 /* Restore LED4 source to external link,
11497 * and re-enable interrupts.
11499 elink_cl45_write(sc, phy,
11501 MDIO_PMA_REG_8481_SIGNAL_MASK,
11503 if (params->link_flags &
11504 ELINK_LINK_FLAGS_INT_DISABLED) {
11505 elink_link_int_enable(params);
11506 params->link_flags &=
11507 ~ELINK_LINK_FLAGS_INT_DISABLED;
11514 /* This is a workaround for E3+84833 until autoneg
11515 * restart is fixed in f/w
11517 if (CHIP_IS_E3(sc)) {
11518 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11519 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11523 /******************************************************************/
11524 /* 54618SE PHY SECTION */
11525 /******************************************************************/
11526 static void elink_54618se_specific_func(struct elink_phy *phy,
11527 struct elink_params *params,
11530 struct bxe_softc *sc = params->sc;
11533 case ELINK_PHY_INIT:
11534 /* Configure LED4: set to INTR (0x6). */
11535 /* Accessing shadow register 0xe. */
11536 elink_cl22_write(sc, phy,
11537 MDIO_REG_GPHY_SHADOW,
11538 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11539 elink_cl22_read(sc, phy,
11540 MDIO_REG_GPHY_SHADOW,
11542 temp &= ~(0xf << 4);
11543 temp |= (0x6 << 4);
11544 elink_cl22_write(sc, phy,
11545 MDIO_REG_GPHY_SHADOW,
11546 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11547 /* Configure INTR based on link status change. */
11548 elink_cl22_write(sc, phy,
11549 MDIO_REG_INTR_MASK,
11550 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11555 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11556 struct elink_params *params,
11557 struct elink_vars *vars)
11559 struct bxe_softc *sc = params->sc;
11561 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11564 ELINK_DEBUG_P0(sc, "54618SE cfg init\n");
11567 /* This works with E3 only, no need to check the chip
11568 * before determining the port.
11570 port = params->port;
11572 cfg_pin = (REG_RD(sc, params->shmem_base +
11573 offsetof(struct shmem_region,
11574 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11575 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11576 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11578 /* Drive pin high to bring the GPHY out of reset. */
11579 elink_set_cfg_pin(sc, cfg_pin, 1);
11581 /* wait for GPHY to reset */
11585 elink_cl22_write(sc, phy,
11586 MDIO_PMA_REG_CTRL, 0x8000);
11587 elink_wait_reset_complete(sc, phy, params);
11589 /* Wait for GPHY to reset */
11593 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11594 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11595 elink_cl22_write(sc, phy,
11596 MDIO_REG_GPHY_SHADOW,
11597 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11598 elink_cl22_read(sc, phy,
11599 MDIO_REG_GPHY_SHADOW,
11601 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11602 elink_cl22_write(sc, phy,
11603 MDIO_REG_GPHY_SHADOW,
11604 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11607 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11608 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11610 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11611 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11612 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11614 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11615 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11616 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11618 /* Read all advertisement */
11619 elink_cl22_read(sc, phy,
11623 elink_cl22_read(sc, phy,
11627 elink_cl22_read(sc, phy,
11631 /* Disable forced speed */
11632 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11633 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11636 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11637 (phy->speed_cap_mask &
11638 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11639 (phy->req_line_speed == ELINK_SPEED_1000)) {
11640 an_1000_val |= (1<<8);
11641 autoneg_val |= (1<<9 | 1<<12);
11642 if (phy->req_duplex == DUPLEX_FULL)
11643 an_1000_val |= (1<<9);
11644 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
11646 an_1000_val &= ~((1<<8) | (1<<9));
11648 elink_cl22_write(sc, phy,
11651 elink_cl22_read(sc, phy,
11655 /* Advertise 10/100 link speed */
11656 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11657 if (phy->speed_cap_mask &
11658 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11659 an_10_100_val |= (1<<5);
11660 autoneg_val |= (1<<9 | 1<<12);
11661 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
11663 if (phy->speed_cap_mask &
11664 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11665 an_10_100_val |= (1<<6);
11666 autoneg_val |= (1<<9 | 1<<12);
11667 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
11669 if (phy->speed_cap_mask &
11670 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11671 an_10_100_val |= (1<<7);
11672 autoneg_val |= (1<<9 | 1<<12);
11673 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
11675 if (phy->speed_cap_mask &
11676 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11677 an_10_100_val |= (1<<8);
11678 autoneg_val |= (1<<9 | 1<<12);
11679 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
11683 /* Only 10/100 are allowed to work in FORCE mode */
11684 if (phy->req_line_speed == ELINK_SPEED_100) {
11685 autoneg_val |= (1<<13);
11686 /* Enabled AUTO-MDIX when autoneg is disabled */
11687 elink_cl22_write(sc, phy,
11689 (1<<15 | 1<<9 | 7<<0));
11690 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
11692 if (phy->req_line_speed == ELINK_SPEED_10) {
11693 /* Enabled AUTO-MDIX when autoneg is disabled */
11694 elink_cl22_write(sc, phy,
11696 (1<<15 | 1<<9 | 7<<0));
11697 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
11700 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11703 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11704 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11705 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11706 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11708 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11710 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11711 if (rc != ELINK_STATUS_OK) {
11712 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11713 elink_eee_disable(phy, params, vars);
11714 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11715 (phy->req_duplex == DUPLEX_FULL) &&
11716 (elink_eee_calc_timer(params) ||
11717 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
11718 /* Need to advertise EEE only when requested,
11719 * and either no LPI assertion was requested,
11720 * or it was requested and a valid timer was set.
11721 * Also notice full duplex is required for EEE.
11723 elink_eee_advertise(phy, params, vars,
11726 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n");
11727 elink_eee_disable(phy, params, vars);
11730 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11731 SHMEM_EEE_SUPPORTED_SHIFT;
11733 if (phy->flags & ELINK_FLAGS_EEE) {
11734 /* Handle legacy auto-grEEEn */
11735 if (params->feature_config_flags &
11736 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11738 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n");
11741 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n");
11743 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11744 MDIO_AN_REG_EEE_ADV, temp);
11748 elink_cl22_write(sc, phy,
11750 an_10_100_val | fc_val);
11752 if (phy->req_duplex == DUPLEX_FULL)
11753 autoneg_val |= (1<<8);
11755 elink_cl22_write(sc, phy,
11756 MDIO_PMA_REG_CTRL, autoneg_val);
11758 return ELINK_STATUS_OK;
11762 static void elink_5461x_set_link_led(struct elink_phy *phy,
11763 struct elink_params *params, uint8_t mode)
11765 struct bxe_softc *sc = params->sc;
11768 elink_cl22_write(sc, phy,
11769 MDIO_REG_GPHY_SHADOW,
11770 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11771 elink_cl22_read(sc, phy,
11772 MDIO_REG_GPHY_SHADOW,
11776 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode);
11778 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11779 case ELINK_LED_MODE_OFF:
11782 case ELINK_LED_MODE_OPER:
11785 case ELINK_LED_MODE_ON:
11791 elink_cl22_write(sc, phy,
11792 MDIO_REG_GPHY_SHADOW,
11793 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11798 static void elink_54618se_link_reset(struct elink_phy *phy,
11799 struct elink_params *params)
11801 struct bxe_softc *sc = params->sc;
11805 /* In case of no EPIO routed to reset the GPHY, put it
11806 * in low power mode.
11808 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
11809 /* This works with E3 only, no need to check the chip
11810 * before determining the port.
11812 port = params->port;
11813 cfg_pin = (REG_RD(sc, params->shmem_base +
11814 offsetof(struct shmem_region,
11815 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11816 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11817 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11819 /* Drive pin low to put GPHY in reset. */
11820 elink_set_cfg_pin(sc, cfg_pin, 0);
11823 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
11824 struct elink_params *params,
11825 struct elink_vars *vars)
11827 struct bxe_softc *sc = params->sc;
11829 uint8_t link_up = 0;
11830 uint16_t legacy_status, legacy_speed;
11832 /* Get speed operation status */
11833 elink_cl22_read(sc, phy,
11834 MDIO_REG_GPHY_AUX_STATUS,
11836 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);
11838 /* Read status to clear the PHY interrupt. */
11839 elink_cl22_read(sc, phy,
11840 MDIO_REG_INTR_STATUS,
11843 link_up = ((legacy_status & (1<<2)) == (1<<2));
11846 legacy_speed = (legacy_status & (7<<8));
11847 if (legacy_speed == (7<<8)) {
11848 vars->line_speed = ELINK_SPEED_1000;
11849 vars->duplex = DUPLEX_FULL;
11850 } else if (legacy_speed == (6<<8)) {
11851 vars->line_speed = ELINK_SPEED_1000;
11852 vars->duplex = DUPLEX_HALF;
11853 } else if (legacy_speed == (5<<8)) {
11854 vars->line_speed = ELINK_SPEED_100;
11855 vars->duplex = DUPLEX_FULL;
11857 /* Omitting 100Base-T4 for now */
11858 else if (legacy_speed == (3<<8)) {
11859 vars->line_speed = ELINK_SPEED_100;
11860 vars->duplex = DUPLEX_HALF;
11861 } else if (legacy_speed == (2<<8)) {
11862 vars->line_speed = ELINK_SPEED_10;
11863 vars->duplex = DUPLEX_FULL;
11864 } else if (legacy_speed == (1<<8)) {
11865 vars->line_speed = ELINK_SPEED_10;
11866 vars->duplex = DUPLEX_HALF;
11867 } else /* Should not happen */
11868 vars->line_speed = 0;
11871 "Link is up in %dMbps, is_duplex_full= %d\n",
11873 (vars->duplex == DUPLEX_FULL));
11875 /* Check legacy speed AN resolution */
11876 elink_cl22_read(sc, phy,
11880 vars->link_status |=
11881 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11882 elink_cl22_read(sc, phy,
11885 if ((val & (1<<0)) == 0)
11886 vars->link_status |=
11887 LINK_STATUS_PARALLEL_DETECTION_USED;
11889 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n",
11892 elink_ext_phy_resolve_fc(phy, params, vars);
11894 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11895 /* Report LP advertised speeds */
11896 elink_cl22_read(sc, phy, 0x5, &val);
11899 vars->link_status |=
11900 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11902 vars->link_status |=
11903 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11905 vars->link_status |=
11906 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11908 vars->link_status |=
11909 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11911 vars->link_status |=
11912 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11914 elink_cl22_read(sc, phy, 0xa, &val);
11916 vars->link_status |=
11917 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11919 vars->link_status |=
11920 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11922 if ((phy->flags & ELINK_FLAGS_EEE) &&
11923 elink_eee_has_cap(params))
11924 elink_eee_an_resolve(phy, params, vars);
11930 static void elink_54618se_config_loopback(struct elink_phy *phy,
11931 struct elink_params *params)
11933 struct bxe_softc *sc = params->sc;
11935 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11937 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n");
11939 /* Enable master/slave manual mmode and set to master */
11940 /* mii write 9 [bits set 11 12] */
11941 elink_cl22_write(sc, phy, 0x09, 3<<11);
11943 /* forced 1G and disable autoneg */
11944 /* set val [mii read 0] */
11945 /* set val [expr $val & [bits clear 6 12 13]] */
11946 /* set val [expr $val | [bits set 6 8]] */
11947 /* mii write 0 $val */
11948 elink_cl22_read(sc, phy, 0x00, &val);
11949 val &= ~((1<<6) | (1<<12) | (1<<13));
11950 val |= (1<<6) | (1<<8);
11951 elink_cl22_write(sc, phy, 0x00, val);
11953 /* Set external loopback and Tx using 6dB coding */
11954 /* mii write 0x18 7 */
11955 /* set val [mii read 0x18] */
11956 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11957 elink_cl22_write(sc, phy, 0x18, 7);
11958 elink_cl22_read(sc, phy, 0x18, &val);
11959 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
11961 /* This register opens the gate for the UMAC despite its name */
11962 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11964 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11965 * length used by the MAC receive logic to check frames.
11967 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
11970 /******************************************************************/
11971 /* SFX7101 PHY SECTION */
11972 /******************************************************************/
11973 static void elink_7101_config_loopback(struct elink_phy *phy,
11974 struct elink_params *params)
11976 struct bxe_softc *sc = params->sc;
11977 /* SFX7101_XGXS_TEST1 */
11978 elink_cl45_write(sc, phy,
11979 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11982 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
11983 struct elink_params *params,
11984 struct elink_vars *vars)
11986 uint16_t fw_ver1, fw_ver2, val;
11987 struct bxe_softc *sc = params->sc;
11988 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n");
11990 /* Restore normal power mode*/
11991 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
11992 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11994 elink_ext_phy_hw_reset(sc, params->port);
11995 elink_wait_reset_complete(sc, phy, params);
11997 elink_cl45_write(sc, phy,
11998 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11999 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n");
12000 elink_cl45_write(sc, phy,
12001 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
12003 elink_ext_phy_set_pause(params, phy, vars);
12004 /* Restart autoneg */
12005 elink_cl45_read(sc, phy,
12006 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
12008 elink_cl45_write(sc, phy,
12009 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
12011 /* Save spirom version */
12012 elink_cl45_read(sc, phy,
12013 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
12015 elink_cl45_read(sc, phy,
12016 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
12017 elink_save_spirom_version(sc, params->port,
12018 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12019 return ELINK_STATUS_OK;
12022 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12023 struct elink_params *params,
12024 struct elink_vars *vars)
12026 struct bxe_softc *sc = params->sc;
12028 uint16_t val1, val2;
12029 elink_cl45_read(sc, phy,
12030 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
12031 elink_cl45_read(sc, phy,
12032 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
12033 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",
12035 elink_cl45_read(sc, phy,
12036 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
12037 elink_cl45_read(sc, phy,
12038 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
12039 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",
12041 link_up = ((val1 & 4) == 4);
12042 /* If link is up print the AN outcome of the SFX7101 PHY */
12044 elink_cl45_read(sc, phy,
12045 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
12047 vars->line_speed = ELINK_SPEED_10000;
12048 vars->duplex = DUPLEX_FULL;
12049 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",
12050 val2, (val2 & (1<<14)));
12051 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12052 elink_ext_phy_resolve_fc(phy, params, vars);
12054 /* Read LP advertised speeds */
12055 if (val2 & (1<<11))
12056 vars->link_status |=
12057 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
12062 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
12065 return ELINK_STATUS_ERROR;
12066 str[0] = (spirom_ver & 0xFF);
12067 str[1] = (spirom_ver & 0xFF00) >> 8;
12068 str[2] = (spirom_ver & 0xFF0000) >> 16;
12069 str[3] = (spirom_ver & 0xFF000000) >> 24;
12072 return ELINK_STATUS_OK;
12075 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12079 elink_cl45_read(sc, phy,
12081 MDIO_PMA_REG_7101_RESET, &val);
12083 for (cnt = 0; cnt < 10; cnt++) {
12085 /* Writes a self-clearing reset */
12086 elink_cl45_write(sc, phy,
12088 MDIO_PMA_REG_7101_RESET,
12090 /* Wait for clear */
12091 elink_cl45_read(sc, phy,
12093 MDIO_PMA_REG_7101_RESET, &val);
12095 if ((val & (1<<15)) == 0)
12100 static void elink_7101_hw_reset(struct elink_phy *phy,
12101 struct elink_params *params) {
12102 /* Low power mode is controlled by GPIO 2 */
12103 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
12104 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12105 /* The PHY reset is controlled by GPIO 1 */
12106 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
12107 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12110 static void elink_7101_set_link_led(struct elink_phy *phy,
12111 struct elink_params *params, uint8_t mode)
12114 struct bxe_softc *sc = params->sc;
12116 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12117 case ELINK_LED_MODE_OFF:
12120 case ELINK_LED_MODE_ON:
12123 case ELINK_LED_MODE_OPER:
12127 elink_cl45_write(sc, phy,
12129 MDIO_PMA_REG_7107_LINK_LED_CNTL,
12133 /******************************************************************/
12134 /* STATIC PHY DECLARATION */
12135 /******************************************************************/
12137 static const struct elink_phy phy_null = {
12138 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
12141 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12142 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12143 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12146 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12148 .req_flow_ctrl = 0,
12149 .req_line_speed = 0,
12150 .speed_cap_mask = 0,
12153 .config_init = (config_init_t)NULL,
12154 .read_status = (read_status_t)NULL,
12155 .link_reset = (link_reset_t)NULL,
12156 .config_loopback = (config_loopback_t)NULL,
12157 .format_fw_ver = (format_fw_ver_t)NULL,
12158 .hw_reset = (hw_reset_t)NULL,
12159 .set_link_led = (set_link_led_t)NULL,
12160 .phy_specific_func = (phy_specific_func_t)NULL
12163 static const struct elink_phy phy_serdes = {
12164 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
12168 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12169 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12171 .supported = (ELINK_SUPPORTED_10baseT_Half |
12172 ELINK_SUPPORTED_10baseT_Full |
12173 ELINK_SUPPORTED_100baseT_Half |
12174 ELINK_SUPPORTED_100baseT_Full |
12175 ELINK_SUPPORTED_1000baseT_Full |
12176 ELINK_SUPPORTED_2500baseX_Full |
12177 ELINK_SUPPORTED_TP |
12178 ELINK_SUPPORTED_Autoneg |
12179 ELINK_SUPPORTED_Pause |
12180 ELINK_SUPPORTED_Asym_Pause),
12181 .media_type = ELINK_ETH_PHY_BASE_T,
12183 .req_flow_ctrl = 0,
12184 .req_line_speed = 0,
12185 .speed_cap_mask = 0,
12188 .config_init = (config_init_t)elink_xgxs_config_init,
12189 .read_status = (read_status_t)elink_link_settings_status,
12190 .link_reset = (link_reset_t)elink_int_link_reset,
12191 .config_loopback = (config_loopback_t)NULL,
12192 .format_fw_ver = (format_fw_ver_t)NULL,
12193 .hw_reset = (hw_reset_t)NULL,
12194 .set_link_led = (set_link_led_t)NULL,
12195 .phy_specific_func = (phy_specific_func_t)NULL
12198 static const struct elink_phy phy_xgxs = {
12199 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12203 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12204 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12206 .supported = (ELINK_SUPPORTED_10baseT_Half |
12207 ELINK_SUPPORTED_10baseT_Full |
12208 ELINK_SUPPORTED_100baseT_Half |
12209 ELINK_SUPPORTED_100baseT_Full |
12210 ELINK_SUPPORTED_1000baseT_Full |
12211 ELINK_SUPPORTED_2500baseX_Full |
12212 ELINK_SUPPORTED_10000baseT_Full |
12213 ELINK_SUPPORTED_FIBRE |
12214 ELINK_SUPPORTED_Autoneg |
12215 ELINK_SUPPORTED_Pause |
12216 ELINK_SUPPORTED_Asym_Pause),
12217 .media_type = ELINK_ETH_PHY_CX4,
12219 .req_flow_ctrl = 0,
12220 .req_line_speed = 0,
12221 .speed_cap_mask = 0,
12224 .config_init = (config_init_t)elink_xgxs_config_init,
12225 .read_status = (read_status_t)elink_link_settings_status,
12226 .link_reset = (link_reset_t)elink_int_link_reset,
12227 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
12228 .format_fw_ver = (format_fw_ver_t)NULL,
12229 .hw_reset = (hw_reset_t)NULL,
12230 .set_link_led = (set_link_led_t)NULL,
12231 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
12233 static const struct elink_phy phy_warpcore = {
12234 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12237 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
12238 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12239 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12241 .supported = (ELINK_SUPPORTED_10baseT_Half |
12242 ELINK_SUPPORTED_10baseT_Full |
12243 ELINK_SUPPORTED_100baseT_Half |
12244 ELINK_SUPPORTED_100baseT_Full |
12245 ELINK_SUPPORTED_1000baseT_Full |
12246 ELINK_SUPPORTED_10000baseT_Full |
12247 ELINK_SUPPORTED_20000baseKR2_Full |
12248 ELINK_SUPPORTED_20000baseMLD2_Full |
12249 ELINK_SUPPORTED_FIBRE |
12250 ELINK_SUPPORTED_Autoneg |
12251 ELINK_SUPPORTED_Pause |
12252 ELINK_SUPPORTED_Asym_Pause),
12253 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
12255 .req_flow_ctrl = 0,
12256 .req_line_speed = 0,
12257 .speed_cap_mask = 0,
12258 /* req_duplex = */0,
12260 .config_init = (config_init_t)elink_warpcore_config_init,
12261 .read_status = (read_status_t)elink_warpcore_read_status,
12262 .link_reset = (link_reset_t)elink_warpcore_link_reset,
12263 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
12264 .format_fw_ver = (format_fw_ver_t)NULL,
12265 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
12266 .set_link_led = (set_link_led_t)NULL,
12267 .phy_specific_func = (phy_specific_func_t)NULL
12271 static const struct elink_phy phy_7101 = {
12272 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
12275 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
12276 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12277 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12279 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12280 ELINK_SUPPORTED_TP |
12281 ELINK_SUPPORTED_Autoneg |
12282 ELINK_SUPPORTED_Pause |
12283 ELINK_SUPPORTED_Asym_Pause),
12284 .media_type = ELINK_ETH_PHY_BASE_T,
12286 .req_flow_ctrl = 0,
12287 .req_line_speed = 0,
12288 .speed_cap_mask = 0,
12291 .config_init = (config_init_t)elink_7101_config_init,
12292 .read_status = (read_status_t)elink_7101_read_status,
12293 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12294 .config_loopback = (config_loopback_t)elink_7101_config_loopback,
12295 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
12296 .hw_reset = (hw_reset_t)elink_7101_hw_reset,
12297 .set_link_led = (set_link_led_t)elink_7101_set_link_led,
12298 .phy_specific_func = (phy_specific_func_t)NULL
12300 static const struct elink_phy phy_8073 = {
12301 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
12305 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12306 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12308 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12309 ELINK_SUPPORTED_2500baseX_Full |
12310 ELINK_SUPPORTED_1000baseT_Full |
12311 ELINK_SUPPORTED_FIBRE |
12312 ELINK_SUPPORTED_Autoneg |
12313 ELINK_SUPPORTED_Pause |
12314 ELINK_SUPPORTED_Asym_Pause),
12315 .media_type = ELINK_ETH_PHY_KR,
12317 .req_flow_ctrl = 0,
12318 .req_line_speed = 0,
12319 .speed_cap_mask = 0,
12322 .config_init = (config_init_t)elink_8073_config_init,
12323 .read_status = (read_status_t)elink_8073_read_status,
12324 .link_reset = (link_reset_t)elink_8073_link_reset,
12325 .config_loopback = (config_loopback_t)NULL,
12326 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12327 .hw_reset = (hw_reset_t)NULL,
12328 .set_link_led = (set_link_led_t)NULL,
12329 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
12331 static const struct elink_phy phy_8705 = {
12332 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
12335 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12336 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12337 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12339 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12340 ELINK_SUPPORTED_FIBRE |
12341 ELINK_SUPPORTED_Pause |
12342 ELINK_SUPPORTED_Asym_Pause),
12343 .media_type = ELINK_ETH_PHY_XFP_FIBER,
12345 .req_flow_ctrl = 0,
12346 .req_line_speed = 0,
12347 .speed_cap_mask = 0,
12350 .config_init = (config_init_t)elink_8705_config_init,
12351 .read_status = (read_status_t)elink_8705_read_status,
12352 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12353 .config_loopback = (config_loopback_t)NULL,
12354 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
12355 .hw_reset = (hw_reset_t)NULL,
12356 .set_link_led = (set_link_led_t)NULL,
12357 .phy_specific_func = (phy_specific_func_t)NULL
12359 static const struct elink_phy phy_8706 = {
12360 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
12363 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12364 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12365 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12367 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12368 ELINK_SUPPORTED_1000baseT_Full |
12369 ELINK_SUPPORTED_FIBRE |
12370 ELINK_SUPPORTED_Pause |
12371 ELINK_SUPPORTED_Asym_Pause),
12372 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
12374 .req_flow_ctrl = 0,
12375 .req_line_speed = 0,
12376 .speed_cap_mask = 0,
12379 .config_init = (config_init_t)elink_8706_config_init,
12380 .read_status = (read_status_t)elink_8706_read_status,
12381 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12382 .config_loopback = (config_loopback_t)NULL,
12383 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12384 .hw_reset = (hw_reset_t)NULL,
12385 .set_link_led = (set_link_led_t)NULL,
12386 .phy_specific_func = (phy_specific_func_t)NULL
12389 static const struct elink_phy phy_8726 = {
12390 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
12393 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
12394 ELINK_FLAGS_TX_ERROR_CHECK),
12395 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12396 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12398 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12399 ELINK_SUPPORTED_1000baseT_Full |
12400 ELINK_SUPPORTED_Autoneg |
12401 ELINK_SUPPORTED_FIBRE |
12402 ELINK_SUPPORTED_Pause |
12403 ELINK_SUPPORTED_Asym_Pause),
12404 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12406 .req_flow_ctrl = 0,
12407 .req_line_speed = 0,
12408 .speed_cap_mask = 0,
12411 .config_init = (config_init_t)elink_8726_config_init,
12412 .read_status = (read_status_t)elink_8726_read_status,
12413 .link_reset = (link_reset_t)elink_8726_link_reset,
12414 .config_loopback = (config_loopback_t)elink_8726_config_loopback,
12415 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12416 .hw_reset = (hw_reset_t)NULL,
12417 .set_link_led = (set_link_led_t)NULL,
12418 .phy_specific_func = (phy_specific_func_t)NULL
12421 static const struct elink_phy phy_8727 = {
12422 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
12425 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12426 ELINK_FLAGS_TX_ERROR_CHECK),
12427 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12428 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12430 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12431 ELINK_SUPPORTED_1000baseT_Full |
12432 ELINK_SUPPORTED_FIBRE |
12433 ELINK_SUPPORTED_Pause |
12434 ELINK_SUPPORTED_Asym_Pause),
12435 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12437 .req_flow_ctrl = 0,
12438 .req_line_speed = 0,
12439 .speed_cap_mask = 0,
12442 .config_init = (config_init_t)elink_8727_config_init,
12443 .read_status = (read_status_t)elink_8727_read_status,
12444 .link_reset = (link_reset_t)elink_8727_link_reset,
12445 .config_loopback = (config_loopback_t)NULL,
12446 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12447 .hw_reset = (hw_reset_t)elink_8727_hw_reset,
12448 .set_link_led = (set_link_led_t)elink_8727_set_link_led,
12449 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
12451 static const struct elink_phy phy_8481 = {
12452 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12455 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12456 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12457 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12458 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12460 .supported = (ELINK_SUPPORTED_10baseT_Half |
12461 ELINK_SUPPORTED_10baseT_Full |
12462 ELINK_SUPPORTED_100baseT_Half |
12463 ELINK_SUPPORTED_100baseT_Full |
12464 ELINK_SUPPORTED_1000baseT_Full |
12465 ELINK_SUPPORTED_10000baseT_Full |
12466 ELINK_SUPPORTED_TP |
12467 ELINK_SUPPORTED_Autoneg |
12468 ELINK_SUPPORTED_Pause |
12469 ELINK_SUPPORTED_Asym_Pause),
12470 .media_type = ELINK_ETH_PHY_BASE_T,
12472 .req_flow_ctrl = 0,
12473 .req_line_speed = 0,
12474 .speed_cap_mask = 0,
12477 .config_init = (config_init_t)elink_8481_config_init,
12478 .read_status = (read_status_t)elink_848xx_read_status,
12479 .link_reset = (link_reset_t)elink_8481_link_reset,
12480 .config_loopback = (config_loopback_t)NULL,
12481 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12482 .hw_reset = (hw_reset_t)elink_8481_hw_reset,
12483 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12484 .phy_specific_func = (phy_specific_func_t)NULL
12487 static const struct elink_phy phy_84823 = {
12488 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12491 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12492 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12493 ELINK_FLAGS_TX_ERROR_CHECK),
12494 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12495 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12497 .supported = (ELINK_SUPPORTED_10baseT_Half |
12498 ELINK_SUPPORTED_10baseT_Full |
12499 ELINK_SUPPORTED_100baseT_Half |
12500 ELINK_SUPPORTED_100baseT_Full |
12501 ELINK_SUPPORTED_1000baseT_Full |
12502 ELINK_SUPPORTED_10000baseT_Full |
12503 ELINK_SUPPORTED_TP |
12504 ELINK_SUPPORTED_Autoneg |
12505 ELINK_SUPPORTED_Pause |
12506 ELINK_SUPPORTED_Asym_Pause),
12507 .media_type = ELINK_ETH_PHY_BASE_T,
12509 .req_flow_ctrl = 0,
12510 .req_line_speed = 0,
12511 .speed_cap_mask = 0,
12514 .config_init = (config_init_t)elink_848x3_config_init,
12515 .read_status = (read_status_t)elink_848xx_read_status,
12516 .link_reset = (link_reset_t)elink_848x3_link_reset,
12517 .config_loopback = (config_loopback_t)NULL,
12518 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12519 .hw_reset = (hw_reset_t)NULL,
12520 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12521 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12524 static const struct elink_phy phy_84833 = {
12525 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12528 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12529 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12530 ELINK_FLAGS_TX_ERROR_CHECK |
12531 ELINK_FLAGS_TEMPERATURE),
12532 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12533 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12535 .supported = (ELINK_SUPPORTED_100baseT_Half |
12536 ELINK_SUPPORTED_100baseT_Full |
12537 ELINK_SUPPORTED_1000baseT_Full |
12538 ELINK_SUPPORTED_10000baseT_Full |
12539 ELINK_SUPPORTED_TP |
12540 ELINK_SUPPORTED_Autoneg |
12541 ELINK_SUPPORTED_Pause |
12542 ELINK_SUPPORTED_Asym_Pause),
12543 .media_type = ELINK_ETH_PHY_BASE_T,
12545 .req_flow_ctrl = 0,
12546 .req_line_speed = 0,
12547 .speed_cap_mask = 0,
12550 .config_init = (config_init_t)elink_848x3_config_init,
12551 .read_status = (read_status_t)elink_848xx_read_status,
12552 .link_reset = (link_reset_t)elink_848x3_link_reset,
12553 .config_loopback = (config_loopback_t)NULL,
12554 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12555 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12556 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12557 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12560 static const struct elink_phy phy_84834 = {
12561 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12564 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12565 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12566 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12567 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12569 .supported = (ELINK_SUPPORTED_100baseT_Half |
12570 ELINK_SUPPORTED_100baseT_Full |
12571 ELINK_SUPPORTED_1000baseT_Full |
12572 ELINK_SUPPORTED_10000baseT_Full |
12573 ELINK_SUPPORTED_TP |
12574 ELINK_SUPPORTED_Autoneg |
12575 ELINK_SUPPORTED_Pause |
12576 ELINK_SUPPORTED_Asym_Pause),
12577 .media_type = ELINK_ETH_PHY_BASE_T,
12579 .req_flow_ctrl = 0,
12580 .req_line_speed = 0,
12581 .speed_cap_mask = 0,
12584 .config_init = (config_init_t)elink_848x3_config_init,
12585 .read_status = (read_status_t)elink_848xx_read_status,
12586 .link_reset = (link_reset_t)elink_848x3_link_reset,
12587 .config_loopback = (config_loopback_t)NULL,
12588 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12589 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12590 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12591 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12594 static const struct elink_phy phy_54618se = {
12595 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12598 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12599 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12600 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12602 .supported = (ELINK_SUPPORTED_10baseT_Half |
12603 ELINK_SUPPORTED_10baseT_Full |
12604 ELINK_SUPPORTED_100baseT_Half |
12605 ELINK_SUPPORTED_100baseT_Full |
12606 ELINK_SUPPORTED_1000baseT_Full |
12607 ELINK_SUPPORTED_TP |
12608 ELINK_SUPPORTED_Autoneg |
12609 ELINK_SUPPORTED_Pause |
12610 ELINK_SUPPORTED_Asym_Pause),
12611 .media_type = ELINK_ETH_PHY_BASE_T,
12613 .req_flow_ctrl = 0,
12614 .req_line_speed = 0,
12615 .speed_cap_mask = 0,
12616 /* req_duplex = */0,
12618 .config_init = (config_init_t)elink_54618se_config_init,
12619 .read_status = (read_status_t)elink_54618se_read_status,
12620 .link_reset = (link_reset_t)elink_54618se_link_reset,
12621 .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
12622 .format_fw_ver = (format_fw_ver_t)NULL,
12623 .hw_reset = (hw_reset_t)NULL,
12624 .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
12625 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
12627 /*****************************************************************/
12629 /* Populate the phy according. Main function: elink_populate_phy */
12631 /*****************************************************************/
12633 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base,
12634 struct elink_phy *phy, uint8_t port,
12637 /* Get the 4 lanes xgxs config rx and tx */
12638 uint32_t rx = 0, tx = 0, i;
12639 for (i = 0; i < 2; i++) {
12640 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
12641 * the shmem. When num_phys is greater than 1, than this value
12642 * applies only to ELINK_EXT_PHY1
12644 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
12645 rx = REG_RD(sc, shmem_base +
12646 offsetof(struct shmem_region,
12647 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12649 tx = REG_RD(sc, shmem_base +
12650 offsetof(struct shmem_region,
12651 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12653 rx = REG_RD(sc, shmem_base +
12654 offsetof(struct shmem_region,
12655 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12657 tx = REG_RD(sc, shmem_base +
12658 offsetof(struct shmem_region,
12659 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12662 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12663 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12665 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12666 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12670 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base,
12671 uint8_t phy_index, uint8_t port)
12673 uint32_t ext_phy_config = 0;
12674 switch (phy_index) {
12675 case ELINK_EXT_PHY1:
12676 ext_phy_config = REG_RD(sc, shmem_base +
12677 offsetof(struct shmem_region,
12678 dev_info.port_hw_config[port].external_phy_config));
12680 case ELINK_EXT_PHY2:
12681 ext_phy_config = REG_RD(sc, shmem_base +
12682 offsetof(struct shmem_region,
12683 dev_info.port_hw_config[port].external_phy_config2));
12686 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index);
12687 return ELINK_STATUS_ERROR;
12690 return ext_phy_config;
12692 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
12693 struct elink_phy *phy)
12697 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
12698 offsetof(struct shmem_region,
12699 dev_info.port_feature_config[port].link_config)) &
12700 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12701 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
12702 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
12704 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);
12705 if (USES_WARPCORE(sc)) {
12706 uint32_t serdes_net_if;
12707 phy_addr = REG_RD(sc,
12708 MISC_REG_WC0_CTRL_PHY_ADDR);
12709 *phy = phy_warpcore;
12710 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12711 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
12713 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
12714 /* Check Dual mode */
12715 serdes_net_if = (REG_RD(sc, shmem_base +
12716 offsetof(struct shmem_region, dev_info.
12717 port_hw_config[port].default_cfg)) &
12718 PORT_HW_CFG_NET_SERDES_IF_MASK);
12719 /* Set the appropriate supported and flags indications per
12720 * interface type of the chip
12722 switch (serdes_net_if) {
12723 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12724 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
12725 ELINK_SUPPORTED_10baseT_Full |
12726 ELINK_SUPPORTED_100baseT_Half |
12727 ELINK_SUPPORTED_100baseT_Full |
12728 ELINK_SUPPORTED_1000baseT_Full |
12729 ELINK_SUPPORTED_FIBRE |
12730 ELINK_SUPPORTED_Autoneg |
12731 ELINK_SUPPORTED_Pause |
12732 ELINK_SUPPORTED_Asym_Pause);
12733 phy->media_type = ELINK_ETH_PHY_BASE_T;
12735 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12736 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12737 ELINK_SUPPORTED_10000baseT_Full |
12738 ELINK_SUPPORTED_FIBRE |
12739 ELINK_SUPPORTED_Pause |
12740 ELINK_SUPPORTED_Asym_Pause);
12741 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
12743 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12744 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12745 ELINK_SUPPORTED_10000baseT_Full |
12746 ELINK_SUPPORTED_FIBRE |
12747 ELINK_SUPPORTED_Pause |
12748 ELINK_SUPPORTED_Asym_Pause);
12749 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
12751 case PORT_HW_CFG_NET_SERDES_IF_KR:
12752 phy->media_type = ELINK_ETH_PHY_KR;
12753 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12754 ELINK_SUPPORTED_10000baseT_Full |
12755 ELINK_SUPPORTED_FIBRE |
12756 ELINK_SUPPORTED_Autoneg |
12757 ELINK_SUPPORTED_Pause |
12758 ELINK_SUPPORTED_Asym_Pause);
12760 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12761 phy->media_type = ELINK_ETH_PHY_KR;
12762 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12763 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
12764 ELINK_SUPPORTED_FIBRE |
12765 ELINK_SUPPORTED_Pause |
12766 ELINK_SUPPORTED_Asym_Pause);
12768 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12769 phy->media_type = ELINK_ETH_PHY_KR;
12770 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12771 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
12772 ELINK_SUPPORTED_10000baseT_Full |
12773 ELINK_SUPPORTED_1000baseT_Full |
12774 ELINK_SUPPORTED_Autoneg |
12775 ELINK_SUPPORTED_FIBRE |
12776 ELINK_SUPPORTED_Pause |
12777 ELINK_SUPPORTED_Asym_Pause);
12778 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
12781 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",
12786 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12787 * was not set as expected. For B0, ECO will be enabled so there
12788 * won't be an issue there
12790 if (CHIP_REV(sc) == CHIP_REV_Ax)
12791 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
12793 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
12796 switch (switch_cfg) {
12797 case ELINK_SWITCH_CFG_1G:
12798 phy_addr = REG_RD(sc,
12799 NIG_REG_SERDES0_CTRL_PHY_ADDR +
12803 case ELINK_SWITCH_CFG_10G:
12804 phy_addr = REG_RD(sc,
12805 NIG_REG_XGXS0_CTRL_PHY_ADDR +
12810 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n");
12811 return ELINK_STATUS_ERROR;
12814 phy->addr = (uint8_t)phy_addr;
12815 phy->mdio_ctrl = elink_get_emac_base(sc,
12816 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12818 if (CHIP_IS_E2(sc))
12819 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
12821 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
12823 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12824 port, phy->addr, phy->mdio_ctrl);
12826 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
12827 return ELINK_STATUS_OK;
12830 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc,
12832 uint32_t shmem_base,
12833 uint32_t shmem2_base,
12835 struct elink_phy *phy)
12837 uint32_t ext_phy_config, phy_type, config2;
12838 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12839 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
12841 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12842 /* Select the phy type */
12843 switch (phy_type) {
12844 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12845 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12851 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12854 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12855 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12858 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12859 /* BCM8727_NOC => BCM8727 no over current */
12860 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12862 phy->flags |= ELINK_FLAGS_NOC;
12864 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12865 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12866 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12869 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12872 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12875 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12878 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12881 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12882 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12883 *phy = phy_54618se;
12884 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12885 phy->flags |= ELINK_FLAGS_EEE;
12887 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12890 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12892 return ELINK_STATUS_ERROR;
12895 /* In case external PHY wasn't found */
12896 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12897 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12898 return ELINK_STATUS_ERROR;
12899 return ELINK_STATUS_OK;
12902 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
12903 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
12905 /* The shmem address of the phy version is located on different
12906 * structures. In case this structure is too old, do not set
12909 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
12910 dev_info.shared_hw_config.config2));
12911 if (phy_index == ELINK_EXT_PHY1) {
12912 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12913 port_mb[port].ext_phy_fw_version);
12915 /* Check specific mdc mdio settings */
12916 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12917 mdc_mdio_access = config2 &
12918 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12920 uint32_t size = REG_RD(sc, shmem2_base);
12923 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12924 phy->ver_addr = shmem2_base +
12925 offsetof(struct shmem2_region,
12926 ext_phy_fw_version2[port]);
12928 /* Check specific mdc mdio settings */
12929 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12930 mdc_mdio_access = (config2 &
12931 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12932 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12933 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12935 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
12937 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12938 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12940 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12941 * version lower than or equal to 1.39
12943 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
12944 if (((raw_ver & 0x7F) <= 39) &&
12945 (((raw_ver & 0xF80) >> 7) <= 1))
12946 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
12947 ELINK_SUPPORTED_100baseT_Full);
12950 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
12951 phy_type, port, phy_index);
12952 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n",
12953 phy->addr, phy->mdio_ctrl);
12954 return ELINK_STATUS_OK;
12957 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base,
12958 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
12960 elink_status_t status = ELINK_STATUS_OK;
12961 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12962 if (phy_index == ELINK_INT_PHY)
12963 return elink_populate_int_phy(sc, shmem_base, port, phy);
12964 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
12969 static void elink_phy_def_cfg(struct elink_params *params,
12970 struct elink_phy *phy,
12973 struct bxe_softc *sc = params->sc;
12974 uint32_t link_config;
12975 /* Populate the default phy configuration for MF mode */
12976 if (phy_index == ELINK_EXT_PHY2) {
12977 link_config = REG_RD(sc, params->shmem_base +
12978 offsetof(struct shmem_region, dev_info.
12979 port_feature_config[params->port].link_config2));
12980 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12981 offsetof(struct shmem_region,
12983 port_hw_config[params->port].speed_capability_mask2));
12985 link_config = REG_RD(sc, params->shmem_base +
12986 offsetof(struct shmem_region, dev_info.
12987 port_feature_config[params->port].link_config));
12988 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12989 offsetof(struct shmem_region,
12991 port_hw_config[params->port].speed_capability_mask));
12994 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12995 phy_index, link_config, phy->speed_cap_mask);
12997 phy->req_duplex = DUPLEX_FULL;
12998 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12999 case PORT_FEATURE_LINK_SPEED_10M_HALF:
13000 phy->req_duplex = DUPLEX_HALF;
13001 case PORT_FEATURE_LINK_SPEED_10M_FULL:
13002 phy->req_line_speed = ELINK_SPEED_10;
13004 case PORT_FEATURE_LINK_SPEED_100M_HALF:
13005 phy->req_duplex = DUPLEX_HALF;
13006 case PORT_FEATURE_LINK_SPEED_100M_FULL:
13007 phy->req_line_speed = ELINK_SPEED_100;
13009 case PORT_FEATURE_LINK_SPEED_1G:
13010 phy->req_line_speed = ELINK_SPEED_1000;
13012 case PORT_FEATURE_LINK_SPEED_2_5G:
13013 phy->req_line_speed = ELINK_SPEED_2500;
13015 case PORT_FEATURE_LINK_SPEED_10G_CX4:
13016 phy->req_line_speed = ELINK_SPEED_10000;
13019 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13023 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
13024 case PORT_FEATURE_FLOW_CONTROL_AUTO:
13025 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13027 case PORT_FEATURE_FLOW_CONTROL_TX:
13028 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13030 case PORT_FEATURE_FLOW_CONTROL_RX:
13031 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13033 case PORT_FEATURE_FLOW_CONTROL_BOTH:
13034 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13037 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13042 uint32_t elink_phy_selection(struct elink_params *params)
13044 uint32_t phy_config_swapped, prio_cfg;
13045 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
13047 phy_config_swapped = params->multi_phy_config &
13048 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13050 prio_cfg = params->multi_phy_config &
13051 PORT_HW_CFG_PHY_SELECTION_MASK;
13053 if (phy_config_swapped) {
13054 switch (prio_cfg) {
13055 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
13056 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
13058 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
13059 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
13061 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
13062 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
13064 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
13065 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
13069 return_cfg = prio_cfg;
13074 elink_status_t elink_phy_probe(struct elink_params *params)
13076 uint8_t phy_index, actual_phy_idx;
13077 uint32_t phy_config_swapped, sync_offset, media_types;
13078 struct bxe_softc *sc = params->sc;
13079 struct elink_phy *phy;
13080 params->num_phys = 0;
13081 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13082 #ifdef ELINK_INCLUDE_EMUL
13083 if (CHIP_REV_IS_EMUL(sc))
13084 return ELINK_STATUS_OK;
13086 phy_config_swapped = params->multi_phy_config &
13087 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13089 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
13091 actual_phy_idx = phy_index;
13092 if (phy_config_swapped) {
13093 if (phy_index == ELINK_EXT_PHY1)
13094 actual_phy_idx = ELINK_EXT_PHY2;
13095 else if (phy_index == ELINK_EXT_PHY2)
13096 actual_phy_idx = ELINK_EXT_PHY1;
13098 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
13099 " actual_phy_idx %x\n", phy_config_swapped,
13100 phy_index, actual_phy_idx);
13101 phy = ¶ms->phy[actual_phy_idx];
13102 if (elink_populate_phy(sc, phy_index, params->shmem_base,
13103 params->shmem2_base, params->port,
13104 phy) != ELINK_STATUS_OK) {
13105 params->num_phys = 0;
13106 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13108 for (phy_index = ELINK_INT_PHY;
13109 phy_index < ELINK_MAX_PHYS;
13112 return ELINK_STATUS_ERROR;
13114 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13117 if (params->feature_config_flags &
13118 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
13119 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13121 if (!(params->feature_config_flags &
13122 ELINK_FEATURE_CONFIG_MT_SUPPORT))
13123 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13125 sync_offset = params->shmem_base +
13126 offsetof(struct shmem_region,
13127 dev_info.port_hw_config[params->port].media_type);
13128 media_types = REG_RD(sc, sync_offset);
13130 /* Update media type for non-PMF sync only for the first time
13131 * In case the media type changes afterwards, it will be updated
13132 * using the update_status function
13134 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
13135 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13136 actual_phy_idx))) == 0) {
13137 media_types |= ((phy->media_type &
13138 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
13139 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13142 REG_WR(sc, sync_offset, media_types);
13144 elink_phy_def_cfg(params, phy, phy_index);
13145 params->num_phys++;
13148 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13149 return ELINK_STATUS_OK;
13152 #ifdef ELINK_INCLUDE_EMUL
13153 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
13154 struct elink_vars *vars)
13156 struct bxe_softc *sc = params->sc;
13157 vars->line_speed = params->req_line_speed[0];
13158 /* In case link speed is auto, set speed the highest as possible */
13159 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
13160 if (params->feature_config_flags &
13161 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
13162 vars->line_speed = ELINK_SPEED_2500;
13163 else if (elink_is_4_port_mode(sc))
13164 vars->line_speed = ELINK_SPEED_10000;
13166 vars->line_speed = ELINK_SPEED_20000;
13168 if (vars->line_speed < ELINK_SPEED_10000) {
13169 if ((params->feature_config_flags &
13170 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
13171 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
13172 " disabled!\n", params->req_line_speed[0]);
13173 return ELINK_STATUS_ERROR;
13175 switch (vars->line_speed) {
13176 case ELINK_SPEED_10:
13177 vars->link_status = ELINK_LINK_10TFD;
13179 case ELINK_SPEED_100:
13180 vars->link_status = ELINK_LINK_100TXFD;
13182 case ELINK_SPEED_1000:
13183 vars->link_status = ELINK_LINK_1000TFD;
13185 case ELINK_SPEED_2500:
13186 vars->link_status = ELINK_LINK_2500TFD;
13189 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n",
13191 return ELINK_STATUS_ERROR;
13193 vars->link_status |= LINK_STATUS_LINK_UP;
13195 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13196 elink_umac_enable(params, vars, 1);
13198 elink_umac_enable(params, vars, 0);
13200 /* Link speed >= 10000 requires XMAC enabled */
13201 if (params->feature_config_flags &
13202 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
13203 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
13204 " disabled!\n", params->req_line_speed[0]);
13205 return ELINK_STATUS_ERROR;
13207 /* Check link speed */
13208 switch (vars->line_speed) {
13209 case ELINK_SPEED_10000:
13210 vars->link_status = ELINK_LINK_10GTFD;
13212 case ELINK_SPEED_20000:
13213 vars->link_status = ELINK_LINK_20GTFD;
13216 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n",
13218 return ELINK_STATUS_ERROR;
13220 vars->link_status |= LINK_STATUS_LINK_UP;
13221 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
13222 elink_xmac_enable(params, vars, 1);
13224 elink_xmac_enable(params, vars, 0);
13226 return ELINK_STATUS_OK;
13229 static elink_status_t elink_init_emul(struct elink_params *params,
13230 struct elink_vars *vars)
13232 struct bxe_softc *sc = params->sc;
13233 if (CHIP_IS_E3(sc)) {
13234 if (elink_init_e3_emul_mac(params, vars) !=
13236 return ELINK_STATUS_ERROR;
13238 if (params->feature_config_flags &
13239 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
13240 vars->line_speed = ELINK_SPEED_1000;
13241 vars->link_status = (LINK_STATUS_LINK_UP |
13242 ELINK_LINK_1000XFD);
13243 if (params->loopback_mode ==
13244 ELINK_LOOPBACK_EMAC)
13245 elink_emac_enable(params, vars, 1);
13247 elink_emac_enable(params, vars, 0);
13249 vars->line_speed = ELINK_SPEED_10000;
13250 vars->link_status = (LINK_STATUS_LINK_UP |
13251 ELINK_LINK_10GTFD);
13252 if (params->loopback_mode ==
13253 ELINK_LOOPBACK_BMAC)
13254 elink_bmac_enable(params, vars, 1, 1);
13256 elink_bmac_enable(params, vars, 0, 1);
13260 vars->duplex = DUPLEX_FULL;
13261 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13263 if (CHIP_IS_E1x(sc))
13264 elink_pbf_update(params, vars->flow_ctrl,
13266 /* Disable drain */
13267 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13269 /* update shared memory */
13270 elink_update_mng(params, vars->link_status);
13271 return ELINK_STATUS_OK;
13274 #ifdef ELINK_INCLUDE_FPGA
13275 static elink_status_t elink_init_fpga(struct elink_params *params,
13276 struct elink_vars *vars)
13278 /* Enable on E1.5 FPGA */
13279 struct bxe_softc *sc = params->sc;
13280 vars->duplex = DUPLEX_FULL;
13281 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13282 if (!(CHIP_IS_E1(sc))) {
13283 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
13284 ELINK_FLOW_CTRL_RX);
13285 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
13286 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
13288 if (CHIP_IS_E3(sc)) {
13289 vars->line_speed = params->req_line_speed[0];
13290 switch (vars->line_speed) {
13291 case ELINK_SPEED_AUTO_NEG:
13292 vars->line_speed = ELINK_SPEED_2500;
13293 case ELINK_SPEED_2500:
13294 vars->link_status = ELINK_LINK_2500TFD;
13296 case ELINK_SPEED_1000:
13297 vars->link_status = ELINK_LINK_1000XFD;
13299 case ELINK_SPEED_100:
13300 vars->link_status = ELINK_LINK_100TXFD;
13302 case ELINK_SPEED_10:
13303 vars->link_status = ELINK_LINK_10TFD;
13306 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n",
13307 params->req_line_speed[0]);
13308 return ELINK_STATUS_ERROR;
13310 vars->link_status |= LINK_STATUS_LINK_UP;
13311 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13312 elink_umac_enable(params, vars, 1);
13314 elink_umac_enable(params, vars, 0);
13316 vars->line_speed = ELINK_SPEED_10000;
13317 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
13318 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
13319 elink_emac_enable(params, vars, 1);
13321 elink_emac_enable(params, vars, 0);
13325 if (CHIP_IS_E1x(sc))
13326 elink_pbf_update(params, vars->flow_ctrl,
13328 /* Disable drain */
13329 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13331 /* Update shared memory */
13332 elink_update_mng(params, vars->link_status);
13333 return ELINK_STATUS_OK;
13336 static void elink_init_bmac_loopback(struct elink_params *params,
13337 struct elink_vars *vars)
13339 struct bxe_softc *sc = params->sc;
13341 vars->line_speed = ELINK_SPEED_10000;
13342 vars->duplex = DUPLEX_FULL;
13343 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13344 vars->mac_type = ELINK_MAC_TYPE_BMAC;
13346 vars->phy_flags = PHY_XGXS_FLAG;
13348 elink_xgxs_deassert(params);
13350 /* Set bmac loopback */
13351 elink_bmac_enable(params, vars, 1, 1);
13353 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13356 static void elink_init_emac_loopback(struct elink_params *params,
13357 struct elink_vars *vars)
13359 struct bxe_softc *sc = params->sc;
13361 vars->line_speed = ELINK_SPEED_1000;
13362 vars->duplex = DUPLEX_FULL;
13363 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13364 vars->mac_type = ELINK_MAC_TYPE_EMAC;
13366 vars->phy_flags = PHY_XGXS_FLAG;
13368 elink_xgxs_deassert(params);
13369 /* Set bmac loopback */
13370 elink_emac_enable(params, vars, 1);
13371 elink_emac_program(params, vars);
13372 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13375 static void elink_init_xmac_loopback(struct elink_params *params,
13376 struct elink_vars *vars)
13378 struct bxe_softc *sc = params->sc;
13380 if (!params->req_line_speed[0])
13381 vars->line_speed = ELINK_SPEED_10000;
13383 vars->line_speed = params->req_line_speed[0];
13384 vars->duplex = DUPLEX_FULL;
13385 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13386 vars->mac_type = ELINK_MAC_TYPE_XMAC;
13387 vars->phy_flags = PHY_XGXS_FLAG;
13388 /* Set WC to loopback mode since link is required to provide clock
13389 * to the XMAC in 20G mode
13391 elink_set_aer_mmd(params, ¶ms->phy[0]);
13392 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13393 params->phy[ELINK_INT_PHY].config_loopback(
13394 ¶ms->phy[ELINK_INT_PHY],
13397 elink_xmac_enable(params, vars, 1);
13398 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13401 static void elink_init_umac_loopback(struct elink_params *params,
13402 struct elink_vars *vars)
13404 struct bxe_softc *sc = params->sc;
13406 vars->line_speed = ELINK_SPEED_1000;
13407 vars->duplex = DUPLEX_FULL;
13408 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13409 vars->mac_type = ELINK_MAC_TYPE_UMAC;
13410 vars->phy_flags = PHY_XGXS_FLAG;
13411 elink_umac_enable(params, vars, 1);
13413 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13416 static void elink_init_xgxs_loopback(struct elink_params *params,
13417 struct elink_vars *vars)
13419 struct bxe_softc *sc = params->sc;
13420 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13422 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13423 vars->duplex = DUPLEX_FULL;
13424 if (params->req_line_speed[0] == ELINK_SPEED_1000)
13425 vars->line_speed = ELINK_SPEED_1000;
13426 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
13427 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
13428 vars->line_speed = ELINK_SPEED_20000;
13430 vars->line_speed = ELINK_SPEED_10000;
13432 if (!USES_WARPCORE(sc))
13433 elink_xgxs_deassert(params);
13434 elink_link_initialize(params, vars);
13436 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
13437 if (USES_WARPCORE(sc))
13438 elink_umac_enable(params, vars, 0);
13440 elink_emac_program(params, vars);
13441 elink_emac_enable(params, vars, 0);
13444 if (USES_WARPCORE(sc))
13445 elink_xmac_enable(params, vars, 0);
13447 elink_bmac_enable(params, vars, 0, 1);
13450 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
13451 /* Set 10G XGXS loopback */
13452 int_phy->config_loopback(int_phy, params);
13454 /* Set external phy loopback */
13456 for (phy_index = ELINK_EXT_PHY1;
13457 phy_index < params->num_phys; phy_index++)
13458 if (params->phy[phy_index].config_loopback)
13459 params->phy[phy_index].config_loopback(
13460 ¶ms->phy[phy_index],
13463 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13465 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
13468 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
13470 struct bxe_softc *sc = params->sc;
13471 uint8_t val = en * 0x1F;
13473 /* Open / close the gate between the NIG and the BRB */
13474 if (!CHIP_IS_E1x(sc))
13476 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13478 if (!CHIP_IS_E1(sc)) {
13479 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13483 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13484 NIG_REG_LLH0_BRB1_NOT_MCP), en);
13486 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
13487 struct elink_vars *vars)
13490 uint32_t dont_clear_stat, lfa_sts;
13491 struct bxe_softc *sc = params->sc;
13493 /* Sync the link parameters */
13494 elink_link_status_update(params, vars);
13497 * The module verification was already done by previous link owner,
13498 * so this call is meant only to get warning message
13501 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
13502 struct elink_phy *phy = ¶ms->phy[phy_idx];
13503 if (phy->phy_specific_func) {
13504 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n");
13505 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13507 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13508 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13509 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13510 elink_verify_sfp_module(phy, params);
13512 lfa_sts = REG_RD(sc, params->lfa_base +
13513 offsetof(struct shmem_lfa,
13516 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
13518 /* Re-enable the NIG/MAC */
13519 if (CHIP_IS_E3(sc)) {
13520 if (!dont_clear_stat) {
13521 REG_WR(sc, GRCBASE_MISC +
13522 MISC_REGISTERS_RESET_REG_2_CLEAR,
13523 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13525 REG_WR(sc, GRCBASE_MISC +
13526 MISC_REGISTERS_RESET_REG_2_SET,
13527 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13530 if (vars->line_speed < ELINK_SPEED_10000)
13531 elink_umac_enable(params, vars, 0);
13533 elink_xmac_enable(params, vars, 0);
13535 if (vars->line_speed < ELINK_SPEED_10000)
13536 elink_emac_enable(params, vars, 0);
13538 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
13541 /* Increment LFA count */
13542 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
13543 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
13544 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
13545 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
13546 /* Clear link flap reason */
13547 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13549 REG_WR(sc, params->lfa_base +
13550 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13552 /* Disable NIG DRAIN */
13553 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13555 /* Enable interrupts */
13556 elink_link_int_enable(params);
13557 return ELINK_STATUS_OK;
13560 static void elink_cannot_avoid_link_flap(struct elink_params *params,
13561 struct elink_vars *vars,
13564 uint32_t lfa_sts, cfg_idx, tmp_val;
13565 struct bxe_softc *sc = params->sc;
13567 elink_link_reset(params, vars, 1);
13569 if (!params->lfa_base)
13571 /* Store the new link parameters */
13572 REG_WR(sc, params->lfa_base +
13573 offsetof(struct shmem_lfa, req_duplex),
13574 params->req_duplex[0] | (params->req_duplex[1] << 16));
13576 REG_WR(sc, params->lfa_base +
13577 offsetof(struct shmem_lfa, req_flow_ctrl),
13578 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
13580 REG_WR(sc, params->lfa_base +
13581 offsetof(struct shmem_lfa, req_line_speed),
13582 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
13584 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
13585 REG_WR(sc, params->lfa_base +
13586 offsetof(struct shmem_lfa,
13587 speed_cap_mask[cfg_idx]),
13588 params->speed_cap_mask[cfg_idx]);
13591 tmp_val = REG_RD(sc, params->lfa_base +
13592 offsetof(struct shmem_lfa, additional_config));
13593 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13594 tmp_val |= params->req_fc_auto_adv;
13596 REG_WR(sc, params->lfa_base +
13597 offsetof(struct shmem_lfa, additional_config), tmp_val);
13599 lfa_sts = REG_RD(sc, params->lfa_base +
13600 offsetof(struct shmem_lfa, lfa_sts));
13602 /* Clear the "Don't Clear Statistics" bit, and set reason */
13603 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13605 /* Set link flap reason */
13606 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13607 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13608 LFA_LINK_FLAP_REASON_OFFSET);
13610 /* Increment link flap counter */
13611 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13612 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13613 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13614 << LINK_FLAP_COUNT_OFFSET));
13615 REG_WR(sc, params->lfa_base +
13616 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13617 /* Proceed with regular link initialization */
13620 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
13623 struct bxe_softc *sc = params->sc;
13624 ELINK_DEBUG_P0(sc, "Phy Initialization started\n");
13625 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n",
13626 params->req_line_speed[0], params->req_flow_ctrl[0]);
13627 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n",
13628 params->req_line_speed[1], params->req_flow_ctrl[1]);
13629 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13630 vars->link_status = 0;
13631 vars->phy_link_up = 0;
13633 vars->line_speed = 0;
13634 vars->duplex = DUPLEX_FULL;
13635 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13636 vars->mac_type = ELINK_MAC_TYPE_NONE;
13637 vars->phy_flags = 0;
13638 vars->check_kr2_recovery_cnt = 0;
13639 params->link_flags = ELINK_PHY_INITIALIZED;
13640 /* Driver opens NIG-BRB filters */
13641 elink_set_rx_filter(params, 1);
13642 /* Check if link flap can be avoided */
13643 lfa_status = elink_check_lfa(params);
13645 if (lfa_status == 0) {
13646 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n");
13647 return elink_avoid_link_flap(params, vars);
13650 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",
13652 elink_cannot_avoid_link_flap(params, vars, lfa_status);
13654 /* Disable attentions */
13655 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13656 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13657 ELINK_NIG_MASK_XGXS0_LINK10G |
13658 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13659 ELINK_NIG_MASK_MI_INT));
13660 #ifdef ELINK_INCLUDE_EMUL
13661 if (!(params->feature_config_flags &
13662 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
13665 elink_emac_init(params, vars);
13667 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
13668 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13670 if ((params->num_phys == 0) &&
13671 !CHIP_REV_IS_SLOW(sc)) {
13672 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
13673 return ELINK_STATUS_ERROR;
13675 set_phy_vars(params, vars);
13677 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys);
13678 #ifdef ELINK_INCLUDE_FPGA
13679 if (CHIP_REV_IS_FPGA(sc)) {
13680 return elink_init_fpga(params, vars);
13683 #ifdef ELINK_INCLUDE_EMUL
13684 if (CHIP_REV_IS_EMUL(sc)) {
13685 return elink_init_emul(params, vars);
13688 switch (params->loopback_mode) {
13689 case ELINK_LOOPBACK_BMAC:
13690 elink_init_bmac_loopback(params, vars);
13692 case ELINK_LOOPBACK_EMAC:
13693 elink_init_emac_loopback(params, vars);
13695 case ELINK_LOOPBACK_XMAC:
13696 elink_init_xmac_loopback(params, vars);
13698 case ELINK_LOOPBACK_UMAC:
13699 elink_init_umac_loopback(params, vars);
13701 case ELINK_LOOPBACK_XGXS:
13702 case ELINK_LOOPBACK_EXT_PHY:
13703 elink_init_xgxs_loopback(params, vars);
13706 if (!CHIP_IS_E3(sc)) {
13707 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
13708 elink_xgxs_deassert(params);
13710 elink_serdes_deassert(sc, params->port);
13712 elink_link_initialize(params, vars);
13714 elink_link_int_enable(params);
13717 elink_update_mng(params, vars->link_status);
13719 elink_update_mng_eee(params, vars->eee_status);
13720 return ELINK_STATUS_OK;
13723 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
13724 uint8_t reset_ext_phy)
13726 struct bxe_softc *sc = params->sc;
13727 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
13728 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
13729 /* Disable attentions */
13730 vars->link_status = 0;
13731 elink_update_mng(params, vars->link_status);
13732 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13733 SHMEM_EEE_ACTIVE_BIT);
13734 elink_update_mng_eee(params, vars->eee_status);
13735 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13736 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13737 ELINK_NIG_MASK_XGXS0_LINK10G |
13738 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13739 ELINK_NIG_MASK_MI_INT));
13741 /* Activate nig drain */
13742 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13744 /* Disable nig egress interface */
13745 if (!CHIP_IS_E3(sc)) {
13746 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13747 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13750 #ifdef ELINK_INCLUDE_EMUL
13751 /* Stop BigMac rx */
13752 if (!(params->feature_config_flags &
13753 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
13755 if (!CHIP_IS_E3(sc))
13756 elink_set_bmac_rx(sc, params->chip_id, port, 0);
13757 #ifdef ELINK_INCLUDE_EMUL
13758 /* Stop XMAC/UMAC rx */
13759 if (!(params->feature_config_flags &
13760 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
13762 if (CHIP_IS_E3(sc) &&
13763 !CHIP_REV_IS_FPGA(sc)) {
13764 elink_set_xmac_rxtx(params, 0);
13765 elink_set_umac_rxtx(params, 0);
13768 if (!CHIP_IS_E3(sc))
13769 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13772 /* The PHY reset is controlled by GPIO 1
13773 * Hold it as vars low
13775 /* Clear link led */
13776 elink_set_mdio_emac_per_phy(sc, params);
13777 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
13779 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
13780 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
13782 if (params->phy[phy_index].link_reset) {
13783 elink_set_aer_mmd(params,
13784 ¶ms->phy[phy_index]);
13785 params->phy[phy_index].link_reset(
13786 ¶ms->phy[phy_index],
13789 if (params->phy[phy_index].flags &
13790 ELINK_FLAGS_REARM_LATCH_SIGNAL)
13791 clear_latch_ind = 1;
13795 if (clear_latch_ind) {
13796 /* Clear latching indication */
13797 elink_rearm_latch_signal(sc, port, 0);
13798 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
13799 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
13801 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
13802 if (!CHIP_REV_IS_SLOW(sc))
13804 if (params->phy[ELINK_INT_PHY].link_reset)
13805 params->phy[ELINK_INT_PHY].link_reset(
13806 ¶ms->phy[ELINK_INT_PHY], params);
13808 /* Disable nig ingress interface */
13809 if (!CHIP_IS_E3(sc)) {
13811 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13812 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13813 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
13814 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
13816 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13817 elink_set_xumac_nig(params, 0, 0);
13818 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
13819 MISC_REGISTERS_RESET_REG_2_XMAC)
13820 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
13821 XMAC_CTRL_REG_SOFT_RESET);
13824 vars->phy_flags = 0;
13825 return ELINK_STATUS_OK;
13827 elink_status_t elink_lfa_reset(struct elink_params *params,
13828 struct elink_vars *vars)
13830 struct bxe_softc *sc = params->sc;
13832 vars->phy_flags = 0;
13833 params->link_flags &= ~ELINK_PHY_INITIALIZED;
13834 if (!params->lfa_base)
13835 return elink_link_reset(params, vars, 1);
13837 * Activate NIG drain so that during this time the device won't send
13838 * anything while it is unable to response.
13840 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13843 * Close gracefully the gate from BMAC to NIG such that no half packets
13846 if (!CHIP_IS_E3(sc))
13847 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
13849 if (CHIP_IS_E3(sc)) {
13850 elink_set_xmac_rxtx(params, 0);
13851 elink_set_umac_rxtx(params, 0);
13853 /* Wait 10ms for the pipe to clean up*/
13856 /* Clean the NIG-BRB using the network filters in a way that will
13857 * not cut a packet in the middle.
13859 elink_set_rx_filter(params, 0);
13862 * Re-open the gate between the BMAC and the NIG, after verifying the
13863 * gate to the BRB is closed, otherwise packets may arrive to the
13864 * firmware before driver had initialized it. The target is to achieve
13865 * minimum management protocol down time.
13867 if (!CHIP_IS_E3(sc))
13868 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
13870 if (CHIP_IS_E3(sc)) {
13871 elink_set_xmac_rxtx(params, 1);
13872 elink_set_umac_rxtx(params, 1);
13874 /* Disable NIG drain */
13875 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13876 return ELINK_STATUS_OK;
13879 /****************************************************************************/
13880 /* Common function */
13881 /****************************************************************************/
13882 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc,
13883 uint32_t shmem_base_path[],
13884 uint32_t shmem2_base_path[], uint8_t phy_index,
13887 struct elink_phy phy[PORT_MAX];
13888 struct elink_phy *phy_blk[PORT_MAX];
13891 int8_t port_of_path = 0;
13892 uint32_t swap_val, swap_override;
13893 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13894 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13895 port ^= (swap_val && swap_override);
13896 elink_ext_phy_hw_reset(sc, port);
13897 /* PART1 - Reset both phys */
13898 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13899 uint32_t shmem_base, shmem2_base;
13900 /* In E2, same phy is using for port0 of the two paths */
13901 if (CHIP_IS_E1x(sc)) {
13902 shmem_base = shmem_base_path[0];
13903 shmem2_base = shmem2_base_path[0];
13904 port_of_path = port;
13906 shmem_base = shmem_base_path[port];
13907 shmem2_base = shmem2_base_path[port];
13911 /* Extract the ext phy address for the port */
13912 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13913 port_of_path, &phy[port]) !=
13915 ELINK_DEBUG_P0(sc, "populate_phy failed\n");
13916 return ELINK_STATUS_ERROR;
13918 /* Disable attentions */
13919 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
13921 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13922 ELINK_NIG_MASK_XGXS0_LINK10G |
13923 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13924 ELINK_NIG_MASK_MI_INT));
13926 /* Need to take the phy out of low power mode in order
13927 * to write to access its registers
13929 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
13930 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13933 /* Reset the phy */
13934 elink_cl45_write(sc, &phy[port],
13940 /* Add delay of 150ms after reset */
13943 if (phy[PORT_0].addr & 0x1) {
13944 phy_blk[PORT_0] = &(phy[PORT_1]);
13945 phy_blk[PORT_1] = &(phy[PORT_0]);
13947 phy_blk[PORT_0] = &(phy[PORT_0]);
13948 phy_blk[PORT_1] = &(phy[PORT_1]);
13951 /* PART2 - Download firmware to both phys */
13952 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13953 if (CHIP_IS_E1x(sc))
13954 port_of_path = port;
13958 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
13959 phy_blk[port]->addr);
13960 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
13962 return ELINK_STATUS_ERROR;
13964 /* Only set bit 10 = 1 (Tx power down) */
13965 elink_cl45_read(sc, phy_blk[port],
13967 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13969 /* Phase1 of TX_POWER_DOWN reset */
13970 elink_cl45_write(sc, phy_blk[port],
13972 MDIO_PMA_REG_TX_POWER_DOWN,
13976 /* Toggle Transmitter: Power down and then up with 600ms delay
13981 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13982 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13983 /* Phase2 of POWER_DOWN_RESET */
13984 /* Release bit 10 (Release Tx power down) */
13985 elink_cl45_read(sc, phy_blk[port],
13987 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13989 elink_cl45_write(sc, phy_blk[port],
13991 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13994 /* Read modify write the SPI-ROM version select register */
13995 elink_cl45_read(sc, phy_blk[port],
13997 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13998 elink_cl45_write(sc, phy_blk[port],
14000 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
14002 /* set GPIO2 back to LOW */
14003 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
14004 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
14006 return ELINK_STATUS_OK;
14008 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc,
14009 uint32_t shmem_base_path[],
14010 uint32_t shmem2_base_path[], uint8_t phy_index,
14015 struct elink_phy phy;
14016 /* Use port1 because of the static port-swap */
14017 /* Enable the module detection interrupt */
14018 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14019 val |= ((1<<MISC_REGISTERS_GPIO_3)|
14020 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
14021 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14023 elink_ext_phy_hw_reset(sc, 0);
14025 for (port = 0; port < PORT_MAX; port++) {
14026 uint32_t shmem_base, shmem2_base;
14028 /* In E2, same phy is using for port0 of the two paths */
14029 if (CHIP_IS_E1x(sc)) {
14030 shmem_base = shmem_base_path[0];
14031 shmem2_base = shmem2_base_path[0];
14033 shmem_base = shmem_base_path[port];
14034 shmem2_base = shmem2_base_path[port];
14036 /* Extract the ext phy address for the port */
14037 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14040 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14041 return ELINK_STATUS_ERROR;
14045 elink_cl45_write(sc, &phy,
14046 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
14049 /* Set fault module detected LED on */
14050 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
14051 MISC_REGISTERS_GPIO_HIGH,
14055 return ELINK_STATUS_OK;
14057 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base,
14058 uint8_t *io_gpio, uint8_t *io_port)
14061 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14062 offsetof(struct shmem_region,
14063 dev_info.port_hw_config[PORT_0].default_cfg));
14064 switch (phy_gpio_reset) {
14065 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
14069 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
14073 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
14077 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
14081 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
14085 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
14089 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
14093 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
14098 /* Don't override the io_gpio and io_port */
14103 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc,
14104 uint32_t shmem_base_path[],
14105 uint32_t shmem2_base_path[], uint8_t phy_index,
14108 int8_t port, reset_gpio;
14109 uint32_t swap_val, swap_override;
14110 struct elink_phy phy[PORT_MAX];
14111 struct elink_phy *phy_blk[PORT_MAX];
14112 int8_t port_of_path;
14113 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14114 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14116 reset_gpio = MISC_REGISTERS_GPIO_1;
14119 /* Retrieve the reset gpio/port which control the reset.
14120 * Default is GPIO1, PORT1
14122 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
14123 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14125 /* Calculate the port based on port swap */
14126 port ^= (swap_val && swap_override);
14128 /* Initiate PHY reset*/
14129 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14132 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14137 /* PART1 - Reset both phys */
14138 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14139 uint32_t shmem_base, shmem2_base;
14141 /* In E2, same phy is using for port0 of the two paths */
14142 if (CHIP_IS_E1x(sc)) {
14143 shmem_base = shmem_base_path[0];
14144 shmem2_base = shmem2_base_path[0];
14145 port_of_path = port;
14147 shmem_base = shmem_base_path[port];
14148 shmem2_base = shmem2_base_path[port];
14152 /* Extract the ext phy address for the port */
14153 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14154 port_of_path, &phy[port]) !=
14156 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14157 return ELINK_STATUS_ERROR;
14159 /* disable attentions */
14160 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14162 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14163 ELINK_NIG_MASK_XGXS0_LINK10G |
14164 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14165 ELINK_NIG_MASK_MI_INT));
14168 /* Reset the phy */
14169 elink_cl45_write(sc, &phy[port],
14170 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
14173 /* Add delay of 150ms after reset */
14175 if (phy[PORT_0].addr & 0x1) {
14176 phy_blk[PORT_0] = &(phy[PORT_1]);
14177 phy_blk[PORT_1] = &(phy[PORT_0]);
14179 phy_blk[PORT_0] = &(phy[PORT_0]);
14180 phy_blk[PORT_1] = &(phy[PORT_1]);
14182 /* PART2 - Download firmware to both phys */
14183 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14184 if (CHIP_IS_E1x(sc))
14185 port_of_path = port;
14188 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14189 phy_blk[port]->addr);
14190 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14192 return ELINK_STATUS_ERROR;
14193 /* Disable PHY transmitter output */
14194 elink_cl45_write(sc, phy_blk[port],
14196 MDIO_PMA_REG_TX_DISABLE, 1);
14199 return ELINK_STATUS_OK;
14202 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc,
14203 uint32_t shmem_base_path[],
14204 uint32_t shmem2_base_path[],
14208 uint8_t reset_gpios;
14209 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
14210 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14212 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14213 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",
14215 return ELINK_STATUS_OK;
14217 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[],
14218 uint32_t shmem2_base_path[], uint8_t phy_index,
14219 uint32_t ext_phy_type, uint32_t chip_id)
14221 elink_status_t rc = ELINK_STATUS_OK;
14223 switch (ext_phy_type) {
14224 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
14225 rc = elink_8073_common_init_phy(sc, shmem_base_path,
14227 phy_index, chip_id);
14229 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
14230 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
14231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
14232 rc = elink_8727_common_init_phy(sc, shmem_base_path,
14234 phy_index, chip_id);
14237 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
14238 /* GPIO1 affects both ports, so there's need to pull
14239 * it for single port alone
14241 rc = elink_8726_common_init_phy(sc, shmem_base_path,
14243 phy_index, chip_id);
14245 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
14246 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
14247 /* GPIO3's are linked, and so both need to be toggled
14248 * to obtain required 2us pulse.
14250 rc = elink_84833_common_init_phy(sc, shmem_base_path,
14252 phy_index, chip_id);
14254 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
14255 rc = ELINK_STATUS_ERROR;
14259 "ext_phy 0x%x common init not required\n",
14264 if (rc != ELINK_STATUS_OK)
14265 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14271 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
14272 uint32_t shmem2_base_path[], uint32_t chip_id,
14273 uint8_t one_port_enabled)
14275 elink_status_t rc = ELINK_STATUS_OK;
14276 uint32_t phy_ver, val;
14277 uint8_t phy_index = 0;
14278 uint32_t ext_phy_type, ext_phy_config;
14279 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14280 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
14281 return ELINK_STATUS_OK;
14284 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
14285 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
14286 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14287 if (CHIP_IS_E3(sc)) {
14289 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14290 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14292 /* Check if common init was already done */
14293 phy_ver = REG_RD(sc, shmem_base_path[0] +
14294 offsetof(struct shmem_region,
14295 port_mb[PORT_0].ext_phy_fw_version));
14297 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14299 return ELINK_STATUS_OK;
14302 /* Read the ext_phy_type for arbitrary port(0) */
14303 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14305 ext_phy_config = elink_get_ext_phy_config(sc,
14306 shmem_base_path[0],
14308 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
14309 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
14311 phy_index, ext_phy_type,
14317 static void elink_check_over_curr(struct elink_params *params,
14318 struct elink_vars *vars)
14320 struct bxe_softc *sc = params->sc;
14322 uint8_t port = params->port;
14325 cfg_pin = (REG_RD(sc, params->shmem_base +
14326 offsetof(struct shmem_region,
14327 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14328 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
14329 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
14331 /* Ignore check if no external input PIN available */
14332 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14336 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
14337 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14338 // " been detected and the power to "
14339 // "that SFP+ module has been removed"
14340 // " to prevent failure of the card."
14341 // " Please remove the SFP+ module and"
14342 // " restart the system to clear this"
14344 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
14345 elink_warpcore_power_module(params, 0);
14348 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
14351 /* Returns 0 if no change occured since last check; 1 otherwise. */
14352 static uint8_t elink_analyze_link_error(struct elink_params *params,
14353 struct elink_vars *vars, uint32_t status,
14354 uint32_t phy_flag, uint32_t link_flag, uint8_t notify)
14356 struct bxe_softc *sc = params->sc;
14357 /* Compare new value with previous value */
14359 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
14361 if ((status ^ old_status) == 0)
14364 /* If values differ */
14365 switch (phy_flag) {
14366 case PHY_HALF_OPEN_CONN_FLAG:
14367 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n");
14369 case PHY_SFP_TX_FAULT_FLAG:
14370 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14373 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14375 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14376 old_status, status);
14378 /* Do not touch the link in case physical link down */
14379 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
14382 /* a. Update shmem->link_status accordingly
14383 * b. Update elink_vars->link_up
14386 vars->link_status &= ~LINK_STATUS_LINK_UP;
14387 vars->link_status |= link_flag;
14389 vars->phy_flags |= phy_flag;
14391 /* activate nig drain */
14392 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14393 /* Set LED mode to off since the PHY doesn't know about these
14396 led_mode = ELINK_LED_MODE_OFF;
14398 vars->link_status |= LINK_STATUS_LINK_UP;
14399 vars->link_status &= ~link_flag;
14401 vars->phy_flags &= ~phy_flag;
14402 led_mode = ELINK_LED_MODE_OPER;
14404 /* Clear nig drain */
14405 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14407 elink_sync_link(params, vars);
14408 /* Update the LED according to the link state */
14409 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
14411 /* Update link status in the shared memory */
14412 elink_update_mng(params, vars->link_status);
14414 /* C. Trigger General Attention */
14415 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
14417 elink_cb_notify_link_changed(sc);
14422 /******************************************************************************
14424 * This function checks for half opened connection change indication.
14425 * When such change occurs, it calls the elink_analyze_link_error
14426 * to check if Remote Fault is set or cleared. Reception of remote fault
14427 * status message in the MAC indicates that the peer's MAC has detected
14428 * a fault, for example, due to break in the TX side of fiber.
14430 ******************************************************************************/
14431 elink_status_t elink_check_half_open_conn(struct elink_params *params,
14432 struct elink_vars *vars,
14435 struct bxe_softc *sc = params->sc;
14436 uint32_t lss_status = 0;
14438 /* In case link status is physically up @ 10G do */
14439 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
14440 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14441 return ELINK_STATUS_OK;
14443 if (CHIP_IS_E3(sc) &&
14444 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14445 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
14446 /* Check E3 XMAC */
14447 /* Note that link speed cannot be queried here, since it may be
14448 * zero while link is down. In case UMAC is active, LSS will
14449 * simply not be set
14451 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14453 /* Clear stick bits (Requires rising edge) */
14454 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14455 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
14456 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
14457 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
14458 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14461 elink_analyze_link_error(params, vars, lss_status,
14462 PHY_HALF_OPEN_CONN_FLAG,
14463 LINK_STATUS_NONE, notify);
14464 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14465 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14466 /* Check E1X / E2 BMAC */
14467 uint32_t lss_status_reg;
14468 uint32_t wb_data[2];
14469 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14470 NIG_REG_INGRESS_BMAC0_MEM;
14471 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
14472 if (CHIP_IS_E2(sc))
14473 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
14475 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
14477 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14478 lss_status = (wb_data[0] > 0);
14480 elink_analyze_link_error(params, vars, lss_status,
14481 PHY_HALF_OPEN_CONN_FLAG,
14482 LINK_STATUS_NONE, notify);
14484 return ELINK_STATUS_OK;
14486 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14487 struct elink_params *params,
14488 struct elink_vars *vars)
14490 struct bxe_softc *sc = params->sc;
14491 uint32_t cfg_pin, value = 0;
14492 uint8_t led_change, port = params->port;
14494 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
14495 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14496 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14497 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
14498 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
14500 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
14501 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);
14505 led_change = elink_analyze_link_error(params, vars, value,
14506 PHY_SFP_TX_FAULT_FLAG,
14507 LINK_STATUS_SFP_TX_FAULT, 1);
14510 /* Change TX_Fault led, set link status for further syncs */
14513 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
14514 led_mode = MISC_REGISTERS_GPIO_HIGH;
14515 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
14517 led_mode = MISC_REGISTERS_GPIO_LOW;
14518 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14521 /* If module is unapproved, led should be on regardless */
14522 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14523 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n",
14525 elink_set_e3_module_fault_led(params, led_mode);
14529 static void elink_kr2_recovery(struct elink_params *params,
14530 struct elink_vars *vars,
14531 struct elink_phy *phy)
14533 struct bxe_softc *sc = params->sc;
14534 ELINK_DEBUG_P0(sc, "KR2 recovery\n");
14535 elink_warpcore_enable_AN_KR2(phy, params, vars);
14536 elink_warpcore_restart_AN_KR(phy, params);
14539 static void elink_check_kr2_wa(struct elink_params *params,
14540 struct elink_vars *vars,
14541 struct elink_phy *phy)
14543 struct bxe_softc *sc = params->sc;
14544 uint16_t base_page, next_page, not_kr2_device, lane;
14547 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
14548 * Since some switches tend to reinit the AN process and clear the
14549 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
14550 * and recovered many times
14552 if (vars->check_kr2_recovery_cnt > 0) {
14553 vars->check_kr2_recovery_cnt--;
14557 sigdet = elink_warpcore_get_sigdet(phy, params);
14559 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14560 elink_kr2_recovery(params, vars, phy);
14561 ELINK_DEBUG_P0(sc, "No sigdet\n");
14566 lane = elink_get_warpcore_lane(phy, params);
14567 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14568 MDIO_AER_BLOCK_AER_REG, lane);
14569 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14570 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
14571 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14572 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
14573 elink_set_aer_mmd(params, phy);
14575 /* CL73 has not begun yet */
14576 if (base_page == 0) {
14577 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14578 elink_kr2_recovery(params, vars, phy);
14579 ELINK_DEBUG_P0(sc, "No BP\n");
14584 /* In case NP bit is not set in the BasePage, or it is set,
14585 * but only KX is advertised, declare this link partner as non-KR2
14588 not_kr2_device = (((base_page & 0x8000) == 0) ||
14589 (((base_page & 0x8000) &&
14590 ((next_page & 0xe0) == 0x2))));
14592 /* In case KR2 is already disabled, check if we need to re-enable it */
14593 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14594 if (!not_kr2_device) {
14595 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,
14597 elink_kr2_recovery(params, vars, phy);
14601 /* KR2 is enabled, but not KR2 device */
14602 if (not_kr2_device) {
14603 /* Disable KR2 on both lanes */
14604 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);
14605 elink_disable_kr2(params, vars, phy);
14606 /* Restart AN on leading lane */
14607 elink_warpcore_restart_AN_KR(phy, params);
14612 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
14615 struct bxe_softc *sc = params->sc;
14616 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
14617 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14618 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14619 if (elink_check_half_open_conn(params, vars, 1) !=
14621 ELINK_DEBUG_P0(sc, "Fault detection failed\n");
14626 if (CHIP_IS_E3(sc)) {
14627 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14628 elink_set_aer_mmd(params, phy);
14629 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
14630 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
14631 elink_check_kr2_wa(params, vars, phy);
14632 elink_check_over_curr(params, vars);
14633 if (vars->rx_tx_asic_rst)
14634 elink_warpcore_config_runtime(phy, params, vars);
14636 if ((REG_RD(sc, params->shmem_base +
14637 offsetof(struct shmem_region, dev_info.
14638 port_hw_config[params->port].default_cfg))
14639 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14640 PORT_HW_CFG_NET_SERDES_IF_SFI) {
14641 if (elink_is_sfp_module_plugged(phy, params)) {
14642 elink_sfp_tx_fault_detection(phy, params, vars);
14643 } else if (vars->link_status &
14644 LINK_STATUS_SFP_TX_FAULT) {
14645 /* Clean trail, interrupt corrects the leds */
14646 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14647 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
14648 /* Update link status in the shared memory */
14649 elink_update_mng(params, vars->link_status);
14655 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc,
14656 uint32_t shmem_base,
14657 uint32_t shmem2_base,
14660 uint8_t phy_index, fan_failure_det_req = 0;
14661 struct elink_phy phy;
14662 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14664 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14666 != ELINK_STATUS_OK) {
14667 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14670 fan_failure_det_req |= (phy.flags &
14671 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
14673 return fan_failure_det_req;
14676 void elink_hw_reset_phy(struct elink_params *params)
14679 struct bxe_softc *sc = params->sc;
14680 elink_update_mng(params, 0);
14681 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14682 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14683 ELINK_NIG_MASK_XGXS0_LINK10G |
14684 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14685 ELINK_NIG_MASK_MI_INT));
14687 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
14689 if (params->phy[phy_index].hw_reset) {
14690 params->phy[phy_index].hw_reset(
14691 ¶ms->phy[phy_index],
14693 params->phy[phy_index] = phy_null;
14698 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
14699 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
14702 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
14704 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
14705 if (CHIP_IS_E3(sc)) {
14706 if (elink_get_mod_abs_int_cfg(sc, chip_id,
14710 &gpio_port) != ELINK_STATUS_OK)
14713 struct elink_phy phy;
14714 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14716 if (elink_populate_phy(sc, phy_index, shmem_base,
14717 shmem2_base, port, &phy)
14718 != ELINK_STATUS_OK) {
14719 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14722 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14723 gpio_num = MISC_REGISTERS_GPIO_3;
14730 if (gpio_num == 0xff)
14733 /* Set GPIO3 to trigger SFP+ module insertion/removal */
14734 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14736 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14737 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14738 gpio_port ^= (swap_val && swap_override);
14740 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14741 (gpio_num + (gpio_port << 2));
14743 sync_offset = shmem_base +
14744 offsetof(struct shmem_region,
14745 dev_info.port_hw_config[port].aeu_int_mask);
14746 REG_WR(sc, sync_offset, vars->aeu_int_mask);
14748 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14749 gpio_num, gpio_port, vars->aeu_int_mask);
14752 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14754 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14756 /* Open appropriate AEU for interrupts */
14757 aeu_mask = REG_RD(sc, offset);
14758 aeu_mask |= vars->aeu_int_mask;
14759 REG_WR(sc, offset, aeu_mask);
14761 /* Enable the GPIO to trigger interrupt */
14762 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14763 val |= 1 << (gpio_num + (gpio_port << 2));
14764 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);