2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_IOCTL_H__
32 #define __T4_IOCTL_H__
34 #include <sys/types.h>
35 #include <net/ethernet.h>
38 * Ioctl commands specific to this driver.
41 T4_GETREG = 0x40, /* read register */
42 T4_SETREG, /* write register */
43 T4_REGDUMP, /* dump of all registers */
44 T4_GET_FILTER_MODE, /* get global filter mode */
45 T4_SET_FILTER_MODE, /* set global filter mode */
46 T4_GET_FILTER, /* get information about a filter */
47 T4_SET_FILTER, /* program a filter */
48 T4_DEL_FILTER, /* delete a filter */
49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */
50 T4_LOAD_FW, /* flash firmware */
51 T4_GET_MEM, /* read memory */
52 T4_GET_I2C, /* read from i2c addressible device */
53 T4_CLEAR_STATS, /* clear a port's MAC statistics */
54 T4_SET_OFLD_POLICY, /* Set offload policy */
55 T4_SET_SCHED_CLASS, /* set sched class */
56 T4_SET_SCHED_QUEUE, /* set queue class */
65 #define T4_REGDUMP_SIZE (160 * 1024)
66 #define T5_REGDUMP_SIZE (332 * 1024)
69 uint32_t len; /* bytes */
87 * A hardware filter is some valid combination of these.
89 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */
90 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */
91 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */
92 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */
93 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */
94 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */
95 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */
96 #define T4_FILTER_PORT 0x80 /* Physical ingress port */
97 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */
98 #define T4_FILTER_VLAN 0x200 /* VLAN ID */
99 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */
100 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */
101 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */
102 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */
103 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */
104 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */
108 FILTER_PASS = 0, /* default */
113 /* 802.1q manipulation on FILTER_SWITCH */
115 VLAN_NOCHANGE = 0, /* default */
123 UCAST_EXACT = 0, /* exact unicast match */
124 UCAST_HASH = 1, /* inexact (hashed) unicast match */
125 MCAST_EXACT = 2, /* exact multicast match */
126 MCAST_HASH = 3, /* inexact (hashed) multicast match */
127 PROMISC = 4, /* no match but port is promiscuous */
128 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */
129 BCAST = 6, /* broadcast packet */
134 DST_MODE_QUEUE, /* queue is directly specified by filter */
135 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */
136 DST_MODE_RSS, /* queue selected by default RSS hash lookup */
137 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified
141 struct t4_filter_tuple {
143 * These are always available.
145 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */
146 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */
147 uint16_t sport; /* source port */
148 uint16_t dport; /* destination port */
151 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP
152 * is used to select the global mode and all filters are limited to the
153 * set of fields allowed by the global mode.
155 uint16_t vnic; /* VNIC id or outer VLAN tag */
156 uint16_t vlan; /* VLAN tag */
157 uint16_t ethtype; /* Ethernet type */
158 uint8_t tos; /* TOS/Traffic Type */
159 uint8_t proto; /* protocol type */
160 uint32_t fcoe:1; /* FCoE packet */
161 uint32_t iport:3; /* ingress port */
162 uint32_t matchtype:3; /* MPS match type */
163 uint32_t frag:1; /* fragmentation extension header */
164 uint32_t macidx:9; /* exact match MAC index */
165 uint32_t vlan_vld:1; /* VLAN valid */
166 uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */
169 struct t4_filter_specification {
170 uint32_t hitcnts:1; /* count filter hits in TCB */
171 uint32_t prio:1; /* filter has priority over active/server */
172 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
173 uint32_t action:2; /* drop, pass, switch */
174 uint32_t rpttid:1; /* report TID in RSS hash field */
175 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
176 uint32_t iq:10; /* ingress queue */
177 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
178 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
179 /* 1 => TCB contains IQ ID */
182 * Switch proxy/rewrite fields. An ingress packet which matches a
183 * filter with "switch" set will be looped back out as an egress
184 * packet -- potentially with some Ethernet header rewriting.
186 uint32_t eport:2; /* egress port to switch packet out */
187 uint32_t newdmac:1; /* rewrite destination MAC address */
188 uint32_t newsmac:1; /* rewrite source MAC address */
189 uint32_t newvlan:2; /* rewrite VLAN Tag */
190 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */
191 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */
192 uint16_t vlan; /* VLAN Tag to insert */
195 * Filter rule value/mask pairs.
197 struct t4_filter_tuple val;
198 struct t4_filter_tuple mask;
206 struct t4_filter_specification fs;
210 * Support for "sched-class" command to allow a TX Scheduling Class to be
211 * programmed with various parameters.
213 struct t4_sched_params {
214 int8_t subcmd; /* sub-command */
215 int8_t type; /* packet or flow */
217 struct { /* sub-command SCHED_CLASS_CONFIG */
218 int8_t minmax; /* minmax enable */
220 struct { /* sub-command SCHED_CLASS_PARAMS */
221 int8_t level; /* scheduler hierarchy level */
222 int8_t mode; /* per-class or per-flow */
223 int8_t rateunit; /* bit or packet rate */
224 int8_t ratemode; /* %port relative or kbps
226 int8_t channel; /* scheduler channel [0..N] */
227 int8_t cl; /* scheduler class [0..N] */
228 int32_t minrate; /* minimum rate */
229 int32_t maxrate; /* maximum rate */
230 int16_t weight; /* percent weight */
231 int16_t pktsize; /* average packet size */
233 uint8_t reserved[6 + 8 * 8];
238 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */
239 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */
243 SCHED_CLASS_TYPE_PACKET,
247 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */
248 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */
249 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */
253 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */
254 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
258 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */
259 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */
263 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */
264 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */
268 * Support for "sched_queue" command to allow one or more NIC TX Queues to be
269 * bound to a TX Scheduling Class.
271 struct t4_sched_queue {
273 int8_t queue; /* queue index; -1 => all queues */
274 int8_t cl; /* class index; -1 => unbind */
277 #define T4_SGE_CONTEXT_SIZE 24
285 struct t4_sge_context {
288 uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
291 struct t4_mem_range {
297 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg)
298 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg)
299 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump)
300 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t)
301 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t)
302 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter)
303 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter)
304 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter)
305 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \
306 struct t4_sge_context)
307 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data)
308 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range)
309 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data)
310 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t)
311 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \
312 struct t4_sched_params)
313 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \
314 struct t4_sched_queue)