sys/dev/drm2/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  */
  53
  54 #include <sys/cdefs.h>
  55 __FBSDID("$FreeBSD$");
  56
  57 #include <dev/drm2/drmP.h>
  58 #include <dev/drm2/drm.h>
  59 #include <dev/drm2/i915/i915_drm.h>
  60 #include <dev/drm2/i915/i915_drv.h>
  61 #include <dev/drm2/i915/intel_drv.h>
  62 #include <dev/drm2/i915/intel_ringbuffer.h>
  63 #include <sys/resourcevar.h>
  64 #include <sys/sched.h>
  65 #include <sys/sf_buf.h>
  66
  67 static void i915_gem_object_flush_cpu_write_domain(
  68     struct drm_i915_gem_object *obj);
  69 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  70     int tiling_mode);
  71 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  72     uint32_t size, int tiling_mode);
  73 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  74     unsigned alignment, bool map_and_fenceable);
  75 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  76     int flags);
  77 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  78 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  79     bool write);
  80 static void i915_gem_object_set_to_full_cpu_read_domain(
  81     struct drm_i915_gem_object *obj);
  82 static int i915_gem_object_set_cpu_read_domain_range(
  83     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  84 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  85 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  86 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  87 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  88 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  89 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  90 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  91     uint32_t flush_domains);
  92 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  93     struct drm_i915_fence_reg *reg);
  94 static void i915_gem_reset_fences(struct drm_device *dev);
  95 static void i915_gem_retire_task_handler(void *arg, int pending);
  96 static int i915_gem_phys_pwrite(struct drm_device *dev,
  97     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
  98     uint64_t size, struct drm_file *file_priv);
  99 static void i915_gem_lowmem(void *arg);
 100
 101 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
 102 long i915_gem_wired_pages_cnt;
 103
 104 static void
 105 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 106 {
 107
 108         dev_priv->mm.object_count++;
 109         dev_priv->mm.object_memory += size;
 110 }
 111
 112 static void
 113 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 114 {
 115
 116         dev_priv->mm.object_count--;
 117         dev_priv->mm.object_memory -= size;
 118 }
 119
 120 static int
 121 i915_gem_wait_for_error(struct drm_device *dev)
 122 {
 123         struct drm_i915_private *dev_priv;
 124         int ret;
 125
 126         dev_priv = dev->dev_private;
 127         if (!atomic_load_acq_int(&dev_priv->mm.wedged))
 128                 return (0);
 129
 130         mtx_lock(&dev_priv->error_completion_lock);
 131         while (dev_priv->error_completion == 0) {
 132                 ret = -msleep(&dev_priv->error_completion,
 133                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 134                 if (ret != 0) {
 135                         mtx_unlock(&dev_priv->error_completion_lock);
 136                         return (ret);
 137                 }
 138         }
 139         mtx_unlock(&dev_priv->error_completion_lock);
 140
 141         if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
 142                 mtx_lock(&dev_priv->error_completion_lock);
 143                 dev_priv->error_completion++;
 144                 mtx_unlock(&dev_priv->error_completion_lock);
 145         }
 146         return (0);
 147 }
 148
 149 int
 150 i915_mutex_lock_interruptible(struct drm_device *dev)
 151 {
 152         struct drm_i915_private *dev_priv;
 153         int ret;
 154
 155         dev_priv = dev->dev_private;
 156         ret = i915_gem_wait_for_error(dev);
 157         if (ret != 0)
 158                 return (ret);
 159
 160         /*
 161          * interruptible shall it be. might indeed be if dev_lock is
 162          * changed to sx
 163          */
 164         ret = sx_xlock_sig(&dev->dev_struct_lock);
 165         if (ret != 0)
 166                 return (-ret);
 167
 168         return (0);
 169 }
 170
 171
 172 static void
 173 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 174 {
 175         struct drm_device *dev;
 176         drm_i915_private_t *dev_priv;
 177         int ret;
 178
 179         dev = obj->base.dev;
 180         dev_priv = dev->dev_private;
 181
 182         ret = i915_gem_object_unbind(obj);
 183         if (ret == -ERESTART) {
 184                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 185                 return;
 186         }
 187
 188         CTR1(KTR_DRM, "object_destroy_tail %p", obj);
 189         drm_gem_free_mmap_offset(&obj->base);
 190         drm_gem_object_release(&obj->base);
 191         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 192
 193         free(obj->page_cpu_valid, DRM_I915_GEM);
 194         free(obj->bit_17, DRM_I915_GEM);
 195         free(obj, DRM_I915_GEM);
 196 }
 197
 198 void
 199 i915_gem_free_object(struct drm_gem_object *gem_obj)
 200 {
 201         struct drm_i915_gem_object *obj;
 202         struct drm_device *dev;
 203
 204         obj = to_intel_bo(gem_obj);
 205         dev = obj->base.dev;
 206
 207         while (obj->pin_count > 0)
 208                 i915_gem_object_unpin(obj);
 209
 210         if (obj->phys_obj != NULL)
 211                 i915_gem_detach_phys_object(dev, obj);
 212
 213         i915_gem_free_object_tail(obj);
 214 }
 215
 216 static void
 217 init_ring_lists(struct intel_ring_buffer *ring)
 218 {
 219
 220         INIT_LIST_HEAD(&ring->active_list);
 221         INIT_LIST_HEAD(&ring->request_list);
 222         INIT_LIST_HEAD(&ring->gpu_write_list);
 223 }
 224
 225 void
 226 i915_gem_load(struct drm_device *dev)
 227 {
 228         drm_i915_private_t *dev_priv;
 229         int i;
 230
 231         dev_priv = dev->dev_private;
 232
 233         INIT_LIST_HEAD(&dev_priv->mm.active_list);
 234         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
 235         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
 236         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
 237         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 238         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
 239         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
 240         for (i = 0; i < I915_NUM_RINGS; i++)
 241                 init_ring_lists(&dev_priv->rings[i]);
 242         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
 243                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 244         TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
 245             i915_gem_retire_task_handler, dev_priv);
 246         dev_priv->error_completion = 0;
 247
 248         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
 249         if (IS_GEN3(dev)) {
 250                 u32 tmp = I915_READ(MI_ARB_STATE);
 251                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
 252                         /*
 253                          * arb state is a masked write, so set bit +
 254                          * bit in mask.
 255                          */
 256                         tmp = MI_ARB_C3_LP_WRITE_ENABLE |
 257                             (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
 258                         I915_WRITE(MI_ARB_STATE, tmp);
 259                 }
 260         }
 261
 262         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 263
 264         /* Old X drivers will take 0-2 for front, back, depth buffers */
 265         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 266                 dev_priv->fence_reg_start = 3;
 267
 268         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
 269             IS_G33(dev))
 270                 dev_priv->num_fence_regs = 16;
 271         else
 272                 dev_priv->num_fence_regs = 8;
 273
 274         /* Initialize fence registers to zero */
 275         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 276                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
 277         }
 278         i915_gem_detect_bit_6_swizzle(dev);
 279         dev_priv->mm.interruptible = true;
 280
 281         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
 282             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
 283 }
 284
 285 int
 286 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 287     unsigned long mappable_end, unsigned long end)
 288 {
 289         drm_i915_private_t *dev_priv;
 290         unsigned long mappable;
 291         int error;
 292
 293         dev_priv = dev->dev_private;
 294         mappable = min(end, mappable_end) - start;
 295
 296         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 297
 298         dev_priv->mm.gtt_start = start;
 299         dev_priv->mm.gtt_mappable_end = mappable_end;
 300         dev_priv->mm.gtt_end = end;
 301         dev_priv->mm.gtt_total = end - start;
 302         dev_priv->mm.mappable_gtt_total = mappable;
 303
 304         /* Take over this portion of the GTT */
 305         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 306         device_printf(dev->device,
 307             "taking over the fictitious range 0x%lx-0x%lx\n",
 308             dev->agp->base + start, dev->agp->base + start + mappable);
 309         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 310             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 311         return (error);
 312 }
 313
 314 int
 315 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 316     struct drm_file *file)
 317 {
 318         struct drm_i915_gem_init *args;
 319         drm_i915_private_t *dev_priv;
 320
 321         dev_priv = dev->dev_private;
 322         args = data;
 323
 324         if (args->gtt_start >= args->gtt_end ||
 325             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 326                 return (-EINVAL);
 327
 328         if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
 329                 return (-EBUSY);
 330         /*
 331          * XXXKIB. The second-time initialization should be guarded
 332          * against.
 333          */
 334         return (i915_gem_do_init(dev, args->gtt_start, args->gtt_end,
 335             args->gtt_end));
 336 }
 337
 338 int
 339 i915_gem_idle(struct drm_device *dev)
 340 {
 341         drm_i915_private_t *dev_priv;
 342         int ret;
 343
 344         dev_priv = dev->dev_private;
 345         if (dev_priv->mm.suspended)
 346                 return (0);
 347
 348         ret = i915_gpu_idle(dev, true);
 349         if (ret != 0)
 350                 return (ret);
 351
 352         /* Under UMS, be paranoid and evict. */
 353         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 354                 ret = i915_gem_evict_inactive(dev, false);
 355                 if (ret != 0)
 356                         return ret;
 357         }
 358
 359         i915_gem_reset_fences(dev);
 360
 361         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 362          * We need to replace this with a semaphore, or something.
 363          * And not confound mm.suspended!
 364          */
 365         dev_priv->mm.suspended = 1;
 366         callout_stop(&dev_priv->hangcheck_timer);
 367
 368         i915_kernel_lost_context(dev);
 369         i915_gem_cleanup_ringbuffer(dev);
 370
 371         /* Cancel the retire work handler, which should be idle now. */
 372         taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
 373         return (ret);
 374 }
 375
 376 void
 377 i915_gem_init_swizzling(struct drm_device *dev)
 378 {
 379         drm_i915_private_t *dev_priv;
 380
 381         dev_priv = dev->dev_private;
 382
 383         if (INTEL_INFO(dev)->gen < 5 ||
 384             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 385                 return;
 386
 387         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 388                                  DISP_TILE_SURFACE_SWIZZLING);
 389
 390         if (IS_GEN5(dev))
 391                 return;
 392
 393         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 394         if (IS_GEN6(dev))
 395                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
 396         else
 397                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 398 }
 399
 400 void
 401 i915_gem_init_ppgtt(struct drm_device *dev)
 402 {
 403         drm_i915_private_t *dev_priv;
 404         struct i915_hw_ppgtt *ppgtt;
 405         uint32_t pd_offset, pd_entry;
 406         vm_paddr_t pt_addr;
 407         struct intel_ring_buffer *ring;
 408         u_int first_pd_entry_in_global_pt, i;
 409
 410         dev_priv = dev->dev_private;
 411         ppgtt = dev_priv->mm.aliasing_ppgtt;
 412         if (ppgtt == NULL)
 413                 return;
 414
 415         first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
 416         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 417                 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
 418                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 419                 pd_entry |= GEN6_PDE_VALID;
 420                 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
 421         }
 422         intel_gtt_read_pte(first_pd_entry_in_global_pt);
 423
 424         pd_offset = ppgtt->pd_offset;
 425         pd_offset /= 64; /* in cachelines, */
 426         pd_offset <<= 16;
 427
 428         if (INTEL_INFO(dev)->gen == 6) {
 429                 uint32_t ecochk = I915_READ(GAM_ECOCHK);
 430                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 431                                        ECOCHK_PPGTT_CACHE64B);
 432                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 433         } else if (INTEL_INFO(dev)->gen >= 7) {
 434                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 435                 /* GFX_MODE is per-ring on gen7+ */
 436         }
 437
 438         for (i = 0; i < I915_NUM_RINGS; i++) {
 439                 ring = &dev_priv->rings[i];
 440
 441                 if (INTEL_INFO(dev)->gen >= 7)
 442                         I915_WRITE(RING_MODE_GEN7(ring),
 443                                    GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 444
 445                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 446                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 447         }
 448 }
 449
 450 int
 451 i915_gem_init_hw(struct drm_device *dev)
 452 {
 453         drm_i915_private_t *dev_priv;
 454         int ret;
 455
 456         dev_priv = dev->dev_private;
 457
 458         i915_gem_init_swizzling(dev);
 459
 460         ret = intel_init_render_ring_buffer(dev);
 461         if (ret != 0)
 462                 return (ret);
 463
 464         if (HAS_BSD(dev)) {
 465                 ret = intel_init_bsd_ring_buffer(dev);
 466                 if (ret != 0)
 467                         goto cleanup_render_ring;
 468         }
 469
 470         if (HAS_BLT(dev)) {
 471                 ret = intel_init_blt_ring_buffer(dev);
 472                 if (ret != 0)
 473                         goto cleanup_bsd_ring;
 474         }
 475
 476         dev_priv->next_seqno = 1;
 477         i915_gem_init_ppgtt(dev);
 478         return (0);
 479
 480 cleanup_bsd_ring:
 481         intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
 482 cleanup_render_ring:
 483         intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
 484         return (ret);
 485 }
 486
 487 int
 488 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 489     struct drm_file *file)
 490 {
 491         struct drm_i915_private *dev_priv;
 492         struct drm_i915_gem_get_aperture *args;
 493         struct drm_i915_gem_object *obj;
 494         size_t pinned;
 495
 496         dev_priv = dev->dev_private;
 497         args = data;
 498
 499         if (!(dev->driver->driver_features & DRIVER_GEM))
 500                 return (-ENODEV);
 501
 502         pinned = 0;
 503         DRM_LOCK(dev);
 504         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 505                 pinned += obj->gtt_space->size;
 506         DRM_UNLOCK(dev);
 507
 508         args->aper_size = dev_priv->mm.gtt_total;
 509         args->aper_available_size = args->aper_size - pinned;
 510
 511         return (0);
 512 }
 513
 514 int
 515 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 516      bool map_and_fenceable)
 517 {
 518         struct drm_device *dev;
 519         struct drm_i915_private *dev_priv;
 520         int ret;
 521
 522         dev = obj->base.dev;
 523         dev_priv = dev->dev_private;
 524
 525         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 526             ("Max pin count"));
 527
 528         if (obj->gtt_space != NULL) {
 529                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 530                     (map_and_fenceable && !obj->map_and_fenceable)) {
 531                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 532                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 533                              " obj->map_and_fenceable=%d\n",
 534                              obj->gtt_offset, alignment,
 535                              map_and_fenceable,
 536                              obj->map_and_fenceable);
 537                         ret = i915_gem_object_unbind(obj);
 538                         if (ret != 0)
 539                                 return (ret);
 540                 }
 541         }
 542
 543         if (obj->gtt_space == NULL) {
 544                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 545                     map_and_fenceable);
 546                 if (ret)
 547                         return (ret);
 548         }
 549
 550         if (obj->pin_count++ == 0 && !obj->active)
 551                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 552         obj->pin_mappable |= map_and_fenceable;
 553
 554 #if 1
 555         KIB_NOTYET();
 556 #else
 557         WARN_ON(i915_verify_lists(dev));
 558 #endif
 559         return (0);
 560 }
 561
 562 void
 563 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 564 {
 565         struct drm_device *dev;
 566         drm_i915_private_t *dev_priv;
 567
 568         dev = obj->base.dev;
 569         dev_priv = dev->dev_private;
 570
 571 #if 1
 572         KIB_NOTYET();
 573 #else
 574         WARN_ON(i915_verify_lists(dev));
 575 #endif
 576
 577         KASSERT(obj->pin_count != 0, ("zero pin count"));
 578         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 579
 580         if (--obj->pin_count == 0) {
 581                 if (!obj->active)
 582                         list_move_tail(&obj->mm_list,
 583                             &dev_priv->mm.inactive_list);
 584                 obj->pin_mappable = false;
 585         }
 586 #if 1
 587         KIB_NOTYET();
 588 #else
 589         WARN_ON(i915_verify_lists(dev));
 590 #endif
 591 }
 592
 593 int
 594 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 595     struct drm_file *file)
 596 {
 597         struct drm_i915_gem_pin *args;
 598         struct drm_i915_gem_object *obj;
 599         struct drm_gem_object *gobj;
 600         int ret;
 601
 602         args = data;
 603
 604         ret = i915_mutex_lock_interruptible(dev);
 605         if (ret != 0)
 606                 return ret;
 607
 608         gobj = drm_gem_object_lookup(dev, file, args->handle);
 609         if (gobj == NULL) {
 610                 ret = -ENOENT;
 611                 goto unlock;
 612         }
 613         obj = to_intel_bo(gobj);
 614
 615         if (obj->madv != I915_MADV_WILLNEED) {
 616                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 617                 ret = -EINVAL;
 618                 goto out;
 619         }
 620
 621         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 622                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 623                     args->handle);
 624                 ret = -EINVAL;
 625                 goto out;
 626         }
 627
 628         obj->user_pin_count++;
 629         obj->pin_filp = file;
 630         if (obj->user_pin_count == 1) {
 631                 ret = i915_gem_object_pin(obj, args->alignment, true);
 632                 if (ret != 0)
 633                         goto out;
 634         }
 635
 636         /* XXX - flush the CPU caches for pinned objects
 637          * as the X server doesn't manage domains yet
 638          */
 639         i915_gem_object_flush_cpu_write_domain(obj);
 640         args->offset = obj->gtt_offset;
 641 out:
 642         drm_gem_object_unreference(&obj->base);
 643 unlock:
 644         DRM_UNLOCK(dev);
 645         return (ret);
 646 }
 647
 648 int
 649 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 650     struct drm_file *file)
 651 {
 652         struct drm_i915_gem_pin *args;
 653         struct drm_i915_gem_object *obj;
 654         int ret;
 655
 656         args = data;
 657         ret = i915_mutex_lock_interruptible(dev);
 658         if (ret != 0)
 659                 return (ret);
 660
 661         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 662         if (&obj->base == NULL) {
 663                 ret = -ENOENT;
 664                 goto unlock;
 665         }
 666
 667         if (obj->pin_filp != file) {
 668                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 669                     args->handle);
 670                 ret = -EINVAL;
 671                 goto out;
 672         }
 673         obj->user_pin_count--;
 674         if (obj->user_pin_count == 0) {
 675                 obj->pin_filp = NULL;
 676                 i915_gem_object_unpin(obj);
 677         }
 678
 679 out:
 680         drm_gem_object_unreference(&obj->base);
 681 unlock:
 682         DRM_UNLOCK(dev);
 683         return (ret);
 684 }
 685
 686 int
 687 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 688     struct drm_file *file)
 689 {
 690         struct drm_i915_gem_busy *args;
 691         struct drm_i915_gem_object *obj;
 692         struct drm_i915_gem_request *request;
 693         int ret;
 694
 695         args = data;
 696
 697         ret = i915_mutex_lock_interruptible(dev);
 698         if (ret != 0)
 699                 return ret;
 700
 701         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 702         if (&obj->base == NULL) {
 703                 ret = -ENOENT;
 704                 goto unlock;
 705         }
 706
 707         args->busy = obj->active;
 708         if (args->busy) {
 709                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 710                         ret = i915_gem_flush_ring(obj->ring,
 711                             0, obj->base.write_domain);
 712                 } else if (obj->ring->outstanding_lazy_request ==
 713                     obj->last_rendering_seqno) {
 714                         request = malloc(sizeof(*request), DRM_I915_GEM,
 715                             M_WAITOK | M_ZERO);
 716                         ret = i915_add_request(obj->ring, NULL, request);
 717                         if (ret != 0)
 718                                 free(request, DRM_I915_GEM);
 719                 }
 720
 721                 i915_gem_retire_requests_ring(obj->ring);
 722                 args->busy = obj->active;
 723         }
 724
 725         drm_gem_object_unreference(&obj->base);
 726 unlock:
 727         DRM_UNLOCK(dev);
 728         return (ret);
 729 }
 730
 731 static int
 732 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 733 {
 734         struct drm_i915_private *dev_priv;
 735         struct drm_i915_file_private *file_priv;
 736         unsigned long recent_enough;
 737         struct drm_i915_gem_request *request;
 738         struct intel_ring_buffer *ring;
 739         u32 seqno;
 740         int ret;
 741
 742         dev_priv = dev->dev_private;
 743         if (atomic_load_acq_int(&dev_priv->mm.wedged))
 744                 return (-EIO);
 745
 746         file_priv = file->driver_priv;
 747         recent_enough = ticks - (20 * hz / 1000);
 748         ring = NULL;
 749         seqno = 0;
 750
 751         mtx_lock(&file_priv->mm.lck);
 752         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 753                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 754                         break;
 755                 ring = request->ring;
 756                 seqno = request->seqno;
 757         }
 758         mtx_unlock(&file_priv->mm.lck);
 759         if (seqno == 0)
 760                 return (0);
 761
 762         ret = 0;
 763         mtx_lock(&ring->irq_lock);
 764         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 765                 if (ring->irq_get(ring)) {
 766                         while (ret == 0 &&
 767                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 768                             atomic_load_acq_int(&dev_priv->mm.wedged)))
 769                                 ret = -msleep(ring, &ring->irq_lock, PCATCH,
 770                                     "915thr", 0);
 771                         ring->irq_put(ring);
 772                         if (ret == 0 && atomic_load_acq_int(&dev_priv->mm.wedged))
 773                                 ret = -EIO;
 774                 } else if (_intel_wait_for(dev,
 775                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 776                     atomic_load_acq_int(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 777                         ret = -EBUSY;
 778                 }
 779         }
 780         mtx_unlock(&ring->irq_lock);
 781
 782         if (ret == 0)
 783                 taskqueue_enqueue_timeout(dev_priv->tq,
 784                     &dev_priv->mm.retire_task, 0);
 785
 786         return (ret);
 787 }
 788
 789 int
 790 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 791     struct drm_file *file_priv)
 792 {
 793
 794         return (i915_gem_ring_throttle(dev, file_priv));
 795 }
 796
 797 int
 798 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 799     struct drm_file *file_priv)
 800 {
 801         struct drm_i915_gem_madvise *args;
 802         struct drm_i915_gem_object *obj;
 803         int ret;
 804
 805         args = data;
 806         switch (args->madv) {
 807         case I915_MADV_DONTNEED:
 808         case I915_MADV_WILLNEED:
 809                 break;
 810         default:
 811                 return (-EINVAL);
 812         }
 813
 814         ret = i915_mutex_lock_interruptible(dev);
 815         if (ret != 0)
 816                 return (ret);
 817
 818         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 819         if (&obj->base == NULL) {
 820                 ret = -ENOENT;
 821                 goto unlock;
 822         }
 823
 824         if (obj->pin_count != 0) {
 825                 ret = -EINVAL;
 826                 goto out;
 827         }
 828
 829         if (obj->madv != I915_MADV_PURGED_INTERNAL)
 830                 obj->madv = args->madv;
 831         if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
 832                 i915_gem_object_truncate(obj);
 833         args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
 834
 835 out:
 836         drm_gem_object_unreference(&obj->base);
 837 unlock:
 838         DRM_UNLOCK(dev);
 839         return (ret);
 840 }
 841
 842 void
 843 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 844 {
 845         drm_i915_private_t *dev_priv;
 846         int i;
 847
 848         dev_priv = dev->dev_private;
 849         for (i = 0; i < I915_NUM_RINGS; i++)
 850                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 851 }
 852
 853 int
 854 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 855     struct drm_file *file_priv)
 856 {
 857         drm_i915_private_t *dev_priv;
 858         int ret, i;
 859
 860         if (drm_core_check_feature(dev, DRIVER_MODESET))
 861                 return (0);
 862         dev_priv = dev->dev_private;
 863         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
 864                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 865                 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 866         }
 867
 868         dev_priv->mm.suspended = 0;
 869
 870         ret = i915_gem_init_hw(dev);
 871         if (ret != 0) {
 872                 return (ret);
 873         }
 874
 875         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 876         KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
 877         KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
 878         for (i = 0; i < I915_NUM_RINGS; i++) {
 879                 KASSERT(list_empty(&dev_priv->rings[i].active_list),
 880                     ("ring %d active list", i));
 881                 KASSERT(list_empty(&dev_priv->rings[i].request_list),
 882                     ("ring %d request list", i));
 883         }
 884
 885         DRM_UNLOCK(dev);
 886         ret = drm_irq_install(dev);
 887         DRM_LOCK(dev);
 888         if (ret)
 889                 goto cleanup_ringbuffer;
 890
 891         return (0);
 892
 893 cleanup_ringbuffer:
 894         i915_gem_cleanup_ringbuffer(dev);
 895         dev_priv->mm.suspended = 1;
 896
 897         return (ret);
 898 }
 899
 900 int
 901 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 902     struct drm_file *file_priv)
 903 {
 904
 905         if (drm_core_check_feature(dev, DRIVER_MODESET))
 906                 return 0;
 907
 908         drm_irq_uninstall(dev);
 909         return (i915_gem_idle(dev));
 910 }
 911
 912 int
 913 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 914     uint32_t *handle_p)
 915 {
 916         struct drm_i915_gem_object *obj;
 917         uint32_t handle;
 918         int ret;
 919
 920         size = roundup(size, PAGE_SIZE);
 921         if (size == 0)
 922                 return (-EINVAL);
 923
 924         obj = i915_gem_alloc_object(dev, size);
 925         if (obj == NULL)
 926                 return (-ENOMEM);
 927
 928         handle = 0;
 929         ret = drm_gem_handle_create(file, &obj->base, &handle);
 930         if (ret != 0) {
 931                 drm_gem_object_release(&obj->base);
 932                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 933                 free(obj, DRM_I915_GEM);
 934                 return (-ret);
 935         }
 936
 937         /* drop reference from allocate - handle holds it now */
 938         drm_gem_object_unreference(&obj->base);
 939         CTR2(KTR_DRM, "object_create %p %x", obj, size);
 940         *handle_p = handle;
 941         return (0);
 942 }
 943
 944 int
 945 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 946     struct drm_mode_create_dumb *args)
 947 {
 948
 949         /* have to work out size/pitch and return them */
 950         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 951         args->size = args->pitch * args->height;
 952         return (i915_gem_create(file, dev, args->size, &args->handle));
 953 }
 954
 955 int
 956 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 957     uint32_t handle)
 958 {
 959
 960         return (drm_gem_handle_delete(file, handle));
 961 }
 962
 963 int
 964 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 965     struct drm_file *file)
 966 {
 967         struct drm_i915_gem_create *args = data;
 968
 969         return (i915_gem_create(file, dev, args->size, &args->handle));
 970 }
 971
 972 static int
 973 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 974     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 975     struct drm_file *file)
 976 {
 977         vm_object_t vm_obj;
 978         vm_page_t m;
 979         struct sf_buf *sf;
 980         vm_offset_t mkva;
 981         vm_pindex_t obj_pi;
 982         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 983
 984         if (obj->gtt_offset != 0 && rw == UIO_READ)
 985                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 986         else
 987                 do_bit17_swizzling = 0;
 988
 989         obj->dirty = 1;
 990         vm_obj = obj->base.vm_obj;
 991         ret = 0;
 992
 993         VM_OBJECT_LOCK(vm_obj);
 994         vm_object_pip_add(vm_obj, 1);
 995         while (size > 0) {
 996                 obj_pi = OFF_TO_IDX(offset);
 997                 obj_po = offset & PAGE_MASK;
 998
 999                 m = i915_gem_wire_page(vm_obj, obj_pi);
1000                 VM_OBJECT_UNLOCK(vm_obj);
1001
1002                 sched_pin();
1003                 sf = sf_buf_alloc(m, SFB_CPUPRIVATE);
1004                 mkva = sf_buf_kva(sf);
1005                 length = min(size, PAGE_SIZE - obj_po);
1006                 while (length > 0) {
1007                         if (do_bit17_swizzling &&
1008                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
1009                                 cnt = roundup2(obj_po + 1, 64);
1010                                 cnt = min(cnt - obj_po, length);
1011                                 swizzled_po = obj_po ^ 64;
1012                         } else {
1013                                 cnt = length;
1014                                 swizzled_po = obj_po;
1015                         }
1016                         if (rw == UIO_READ)
1017                                 ret = -copyout_nofault(
1018                                     (char *)mkva + swizzled_po,
1019                                     (void *)(uintptr_t)data_ptr, cnt);
1020                         else
1021                                 ret = -copyin_nofault(
1022                                     (void *)(uintptr_t)data_ptr,
1023                                     (char *)mkva + swizzled_po, cnt);
1024                         if (ret != 0)
1025                                 break;
1026                         data_ptr += cnt;
1027                         size -= cnt;
1028                         length -= cnt;
1029                         offset += cnt;
1030                         obj_po += cnt;
1031                 }
1032                 sf_buf_free(sf);
1033                 sched_unpin();
1034                 VM_OBJECT_LOCK(vm_obj);
1035                 if (rw == UIO_WRITE)
1036                         vm_page_dirty(m);
1037                 vm_page_reference(m);
1038                 vm_page_lock(m);
1039                 vm_page_unwire(m, 1);
1040                 vm_page_unlock(m);
1041                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1042
1043                 if (ret != 0)
1044                         break;
1045         }
1046         vm_object_pip_wakeup(vm_obj);
1047         VM_OBJECT_UNLOCK(vm_obj);
1048
1049         return (ret);
1050 }
1051
1052 static int
1053 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1054     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1055 {
1056         vm_offset_t mkva;
1057         vm_pindex_t obj_pi;
1058         int obj_po, ret;
1059
1060         obj_pi = OFF_TO_IDX(offset);
1061         obj_po = offset & PAGE_MASK;
1062
1063         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1064             IDX_TO_OFF(obj_pi), size, PAT_WRITE_COMBINING);
1065         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva +
1066             obj_po, size);
1067         pmap_unmapdev(mkva, size);
1068         return (ret);
1069 }
1070
1071 static int
1072 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1073     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1074 {
1075         struct drm_i915_gem_object *obj;
1076         vm_page_t *ma;
1077         vm_offset_t start, end;
1078         int npages, ret;
1079
1080         if (size == 0)
1081                 return (0);
1082         start = trunc_page(data_ptr);
1083         end = round_page(data_ptr + size);
1084         npages = howmany(end - start, PAGE_SIZE);
1085         ma = malloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1086             M_ZERO);
1087         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1088             (vm_offset_t)data_ptr, size,
1089             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1090         if (npages == -1) {
1091                 ret = -EFAULT;
1092                 goto free_ma;
1093         }
1094
1095         ret = i915_mutex_lock_interruptible(dev);
1096         if (ret != 0)
1097                 goto unlocked;
1098
1099         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1100         if (&obj->base == NULL) {
1101                 ret = -ENOENT;
1102                 goto unlock;
1103         }
1104         if (offset > obj->base.size || size > obj->base.size - offset) {
1105                 ret = -EINVAL;
1106                 goto out;
1107         }
1108
1109         if (rw == UIO_READ) {
1110                 CTR3(KTR_DRM, "object_pread %p %jx %jx", obj, offset, size);
1111                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1112                     offset, size);
1113                 if (ret != 0)
1114                         goto out;
1115                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1116                     UIO_READ, file);
1117         } else {
1118                 if (obj->phys_obj) {
1119                         CTR3(KTR_DRM, "object_phys_write %p %jx %jx", obj,
1120                             offset, size);
1121                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1122                             size, file);
1123                 } else if (obj->gtt_space &&
1124                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1125                         CTR3(KTR_DRM, "object_gtt_write %p %jx %jx", obj,
1126                             offset, size);
1127                         ret = i915_gem_object_pin(obj, 0, true);
1128                         if (ret != 0)
1129                                 goto out;
1130                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1131                         if (ret != 0)
1132                                 goto out_unpin;
1133                         ret = i915_gem_object_put_fence(obj);
1134                         if (ret != 0)
1135                                 goto out_unpin;
1136                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1137                             offset, file);
1138 out_unpin:
1139                         i915_gem_object_unpin(obj);
1140                 } else {
1141                         CTR3(KTR_DRM, "object_pwrite %p %jx %jx", obj,
1142                             offset, size);
1143                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1144                         if (ret != 0)
1145                                 goto out;
1146                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1147                             UIO_WRITE, file);
1148                 }
1149         }
1150 out:
1151         drm_gem_object_unreference(&obj->base);
1152 unlock:
1153         DRM_UNLOCK(dev);
1154 unlocked:
1155         vm_page_unhold_pages(ma, npages);
1156 free_ma:
1157         free(ma, DRM_I915_GEM);
1158         return (ret);
1159 }
1160
1161 int
1162 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1163 {
1164         struct drm_i915_gem_pread *args;
1165
1166         args = data;
1167         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1168             args->offset, UIO_READ, file));
1169 }
1170
1171 int
1172 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1173 {
1174         struct drm_i915_gem_pwrite *args;
1175
1176         args = data;
1177         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1178             args->offset, UIO_WRITE, file));
1179 }
1180
1181 int
1182 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1183     struct drm_file *file)
1184 {
1185         struct drm_i915_gem_set_domain *args;
1186         struct drm_i915_gem_object *obj;
1187         uint32_t read_domains;
1188         uint32_t write_domain;
1189         int ret;
1190
1191         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1192                 return (-ENODEV);
1193
1194         args = data;
1195         read_domains = args->read_domains;
1196         write_domain = args->write_domain;
1197
1198         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1199             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1200             (write_domain != 0 && read_domains != write_domain))
1201                 return (-EINVAL);
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret != 0)
1205                 return (ret);
1206
1207         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208         if (&obj->base == NULL) {
1209                 ret = -ENOENT;
1210                 goto unlock;
1211         }
1212
1213         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1214                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1215                 if (ret == -EINVAL)
1216                         ret = 0;
1217         } else
1218                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1219
1220         drm_gem_object_unreference(&obj->base);
1221 unlock:
1222         DRM_UNLOCK(dev);
1223         return (ret);
1224 }
1225
1226 int
1227 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1228     struct drm_file *file)
1229 {
1230         struct drm_i915_gem_sw_finish *args;
1231         struct drm_i915_gem_object *obj;
1232         int ret;
1233
1234         args = data;
1235         ret = 0;
1236         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1237                 return (ENODEV);
1238         ret = i915_mutex_lock_interruptible(dev);
1239         if (ret != 0)
1240                 return (ret);
1241         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1242         if (&obj->base == NULL) {
1243                 ret = -ENOENT;
1244                 goto unlock;
1245         }
1246         if (obj->pin_count != 0)
1247                 i915_gem_object_flush_cpu_write_domain(obj);
1248         drm_gem_object_unreference(&obj->base);
1249 unlock:
1250         DRM_UNLOCK(dev);
1251         return (ret);
1252 }
1253
1254 int
1255 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1256     struct drm_file *file)
1257 {
1258         struct drm_i915_gem_mmap *args;
1259         struct drm_gem_object *obj;
1260         struct proc *p;
1261         vm_map_t map;
1262         vm_offset_t addr;
1263         vm_size_t size;
1264         int error, rv;
1265
1266         args = data;
1267
1268         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1269                 return (-ENODEV);
1270
1271         obj = drm_gem_object_lookup(dev, file, args->handle);
1272         if (obj == NULL)
1273                 return (-ENOENT);
1274         error = 0;
1275         if (args->size == 0)
1276                 goto out;
1277         p = curproc;
1278         map = &p->p_vmspace->vm_map;
1279         size = round_page(args->size);
1280         PROC_LOCK(p);
1281         if (map->size + size > lim_cur(p, RLIMIT_VMEM)) {
1282                 PROC_UNLOCK(p);
1283                 error = ENOMEM;
1284                 goto out;
1285         }
1286         PROC_UNLOCK(p);
1287
1288         addr = 0;
1289         vm_object_reference(obj->vm_obj);
1290         DRM_UNLOCK(dev);
1291         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1292             VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1293             VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1294         if (rv != KERN_SUCCESS) {
1295                 vm_object_deallocate(obj->vm_obj);
1296                 error = -vm_mmap_to_errno(rv);
1297         } else {
1298                 args->addr_ptr = (uint64_t)addr;
1299         }
1300         DRM_LOCK(dev);
1301 out:
1302         drm_gem_object_unreference(obj);
1303         return (error);
1304 }
1305
1306 static int
1307 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1308     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1309 {
1310
1311         *color = 0; /* XXXKIB */
1312         return (0);
1313 }
1314
1315 int i915_intr_pf;
1316
1317 static int
1318 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1319     vm_page_t *mres)
1320 {
1321         struct drm_gem_object *gem_obj;
1322         struct drm_i915_gem_object *obj;
1323         struct drm_device *dev;
1324         drm_i915_private_t *dev_priv;
1325         vm_page_t m, oldm;
1326         int cause, ret;
1327         bool write;
1328
1329         gem_obj = vm_obj->handle;
1330         obj = to_intel_bo(gem_obj);
1331         dev = obj->base.dev;
1332         dev_priv = dev->dev_private;
1333 #if 0
1334         write = (prot & VM_PROT_WRITE) != 0;
1335 #else
1336         write = true;
1337 #endif
1338         vm_object_pip_add(vm_obj, 1);
1339
1340         /*
1341          * Remove the placeholder page inserted by vm_fault() from the
1342          * object before dropping the object lock. If
1343          * i915_gem_release_mmap() is active in parallel on this gem
1344          * object, then it owns the drm device sx and might find the
1345          * placeholder already. Then, since the page is busy,
1346          * i915_gem_release_mmap() sleeps waiting for the busy state
1347          * of the page cleared. We will be not able to acquire drm
1348          * device lock until i915_gem_release_mmap() is able to make a
1349          * progress.
1350          */
1351         if (*mres != NULL) {
1352                 oldm = *mres;
1353                 vm_page_lock(oldm);
1354                 vm_page_remove(oldm);
1355                 vm_page_unlock(oldm);
1356                 *mres = NULL;
1357         } else
1358                 oldm = NULL;
1359 retry:
1360         VM_OBJECT_UNLOCK(vm_obj);
1361 unlocked_vmobj:
1362         cause = ret = 0;
1363         m = NULL;
1364
1365         if (i915_intr_pf) {
1366                 ret = i915_mutex_lock_interruptible(dev);
1367                 if (ret != 0) {
1368                         cause = 10;
1369                         goto out;
1370                 }
1371         } else
1372                 DRM_LOCK(dev);
1373
1374         /*
1375          * Since the object lock was dropped, other thread might have
1376          * faulted on the same GTT address and instantiated the
1377          * mapping for the page.  Recheck.
1378          */
1379         VM_OBJECT_LOCK(vm_obj);
1380         m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1381         if (m != NULL) {
1382                 if ((m->flags & VPO_BUSY) != 0) {
1383                         DRM_UNLOCK(dev);
1384                         vm_page_sleep(m, "915pee");
1385                         goto retry;
1386                 }
1387                 goto have_page;
1388         } else
1389                 VM_OBJECT_UNLOCK(vm_obj);
1390
1391         /* Now bind it into the GTT if needed */
1392         if (!obj->map_and_fenceable) {
1393                 ret = i915_gem_object_unbind(obj);
1394                 if (ret != 0) {
1395                         cause = 20;
1396                         goto unlock;
1397                 }
1398         }
1399         if (!obj->gtt_space) {
1400                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1401                 if (ret != 0) {
1402                         cause = 30;
1403                         goto unlock;
1404                 }
1405
1406                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1407                 if (ret != 0) {
1408                         cause = 40;
1409                         goto unlock;
1410                 }
1411         }
1412
1413         if (obj->tiling_mode == I915_TILING_NONE)
1414                 ret = i915_gem_object_put_fence(obj);
1415         else
1416                 ret = i915_gem_object_get_fence(obj, NULL);
1417         if (ret != 0) {
1418                 cause = 50;
1419                 goto unlock;
1420         }
1421
1422         if (i915_gem_object_is_inactive(obj))
1423                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1424
1425         obj->fault_mappable = true;
1426         VM_OBJECT_LOCK(vm_obj);
1427         m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1428             offset);
1429         if (m == NULL) {
1430                 VM_OBJECT_UNLOCK(vm_obj);
1431                 cause = 60;
1432                 ret = -EFAULT;
1433                 goto unlock;
1434         }
1435         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1436             ("not fictitious %p", m));
1437         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1438
1439         if ((m->flags & VPO_BUSY) != 0) {
1440                 DRM_UNLOCK(dev);
1441                 vm_page_sleep_if_busy(m, false, "915pbs");
1442                 goto retry;
1443         }
1444         m->valid = VM_PAGE_BITS_ALL;
1445         vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1446 have_page:
1447         *mres = m;
1448         vm_page_busy(m);
1449
1450         CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1451             m->phys_addr);
1452         DRM_UNLOCK(dev);
1453         if (oldm != NULL) {
1454                 vm_page_lock(oldm);
1455                 vm_page_free(oldm);
1456                 vm_page_unlock(oldm);
1457         }
1458         vm_object_pip_wakeup(vm_obj);
1459         return (VM_PAGER_OK);
1460
1461 unlock:
1462         DRM_UNLOCK(dev);
1463 out:
1464         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1465         CTR5(KTR_DRM, "fault_fail %p %jx %x err %d %d", gem_obj, offset, prot,
1466             -ret, cause);
1467         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1468                 kern_yield(PRI_USER);
1469                 goto unlocked_vmobj;
1470         }
1471         VM_OBJECT_LOCK(vm_obj);
1472         vm_object_pip_wakeup(vm_obj);
1473         return (VM_PAGER_ERROR);
1474 }
1475
1476 static void
1477 i915_gem_pager_dtor(void *handle)
1478 {
1479         struct drm_gem_object *obj;
1480         struct drm_device *dev;
1481
1482         obj = handle;
1483         dev = obj->dev;
1484
1485         DRM_LOCK(dev);
1486         drm_gem_free_mmap_offset(obj);
1487         i915_gem_release_mmap(to_intel_bo(obj));
1488         drm_gem_object_unreference(obj);
1489         DRM_UNLOCK(dev);
1490 }
1491
1492 struct cdev_pager_ops i915_gem_pager_ops = {
1493         .cdev_pg_fault  = i915_gem_pager_fault,
1494         .cdev_pg_ctor   = i915_gem_pager_ctor,
1495         .cdev_pg_dtor   = i915_gem_pager_dtor
1496 };
1497
1498 int
1499 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1500     uint32_t handle, uint64_t *offset)
1501 {
1502         struct drm_i915_private *dev_priv;
1503         struct drm_i915_gem_object *obj;
1504         int ret;
1505
1506         if (!(dev->driver->driver_features & DRIVER_GEM))
1507                 return (-ENODEV);
1508
1509         dev_priv = dev->dev_private;
1510
1511         ret = i915_mutex_lock_interruptible(dev);
1512         if (ret != 0)
1513                 return (ret);
1514
1515         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1516         if (&obj->base == NULL) {
1517                 ret = -ENOENT;
1518                 goto unlock;
1519         }
1520
1521         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1522                 ret = -E2BIG;
1523                 goto out;
1524         }
1525
1526         if (obj->madv != I915_MADV_WILLNEED) {
1527                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1528                 ret = -EINVAL;
1529                 goto out;
1530         }
1531
1532         ret = drm_gem_create_mmap_offset(&obj->base);
1533         if (ret != 0)
1534                 goto out;
1535
1536         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1537             DRM_GEM_MAPPING_KEY;
1538 out:
1539         drm_gem_object_unreference(&obj->base);
1540 unlock:
1541         DRM_UNLOCK(dev);
1542         return (ret);
1543 }
1544
1545 int
1546 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1547     struct drm_file *file)
1548 {
1549         struct drm_i915_private *dev_priv;
1550         struct drm_i915_gem_mmap_gtt *args;
1551
1552         dev_priv = dev->dev_private;
1553         args = data;
1554
1555         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1556 }
1557
1558 struct drm_i915_gem_object *
1559 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1560 {
1561         struct drm_i915_private *dev_priv;
1562         struct drm_i915_gem_object *obj;
1563
1564         dev_priv = dev->dev_private;
1565
1566         obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1567
1568         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1569                 free(obj, DRM_I915_GEM);
1570                 return (NULL);
1571         }
1572
1573         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1574         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1575
1576         if (HAS_LLC(dev))
1577                 obj->cache_level = I915_CACHE_LLC;
1578         else
1579                 obj->cache_level = I915_CACHE_NONE;
1580         obj->base.driver_private = NULL;
1581         obj->fence_reg = I915_FENCE_REG_NONE;
1582         INIT_LIST_HEAD(&obj->mm_list);
1583         INIT_LIST_HEAD(&obj->gtt_list);
1584         INIT_LIST_HEAD(&obj->ring_list);
1585         INIT_LIST_HEAD(&obj->exec_list);
1586         INIT_LIST_HEAD(&obj->gpu_write_list);
1587         obj->madv = I915_MADV_WILLNEED;
1588         /* Avoid an unnecessary call to unbind on the first bind. */
1589         obj->map_and_fenceable = true;
1590
1591         i915_gem_info_add_obj(dev_priv, size);
1592
1593         return (obj);
1594 }
1595
1596 void
1597 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1598 {
1599
1600         /* If we don't have a page list set up, then we're not pinned
1601          * to GPU, and we can ignore the cache flush because it'll happen
1602          * again at bind time.
1603          */
1604         if (obj->pages == NULL)
1605                 return;
1606
1607         /* If the GPU is snooping the contents of the CPU cache,
1608          * we do not need to manually clear the CPU cache lines.  However,
1609          * the caches are only snooped when the render cache is
1610          * flushed/invalidated.  As we always have to emit invalidations
1611          * and flushes when moving into and out of the RENDER domain, correct
1612          * snooping behaviour occurs naturally as the result of our domain
1613          * tracking.
1614          */
1615         if (obj->cache_level != I915_CACHE_NONE)
1616                 return;
1617
1618         CTR1(KTR_DRM, "object_clflush %p", obj);
1619         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1620 }
1621
1622 static void
1623 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1624 {
1625         uint32_t old_write_domain;
1626
1627         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1628                 return;
1629
1630         i915_gem_clflush_object(obj);
1631         intel_gtt_chipset_flush();
1632         old_write_domain = obj->base.write_domain;
1633         obj->base.write_domain = 0;
1634
1635         CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
1636             obj->base.read_domains, old_write_domain);
1637 }
1638
1639 static int
1640 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1641 {
1642
1643         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1644                 return (0);
1645         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1646 }
1647
1648 static void
1649 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1650 {
1651         uint32_t old_write_domain;
1652
1653         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1654                 return;
1655
1656         wmb();
1657
1658         old_write_domain = obj->base.write_domain;
1659         obj->base.write_domain = 0;
1660
1661         CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
1662             obj->base.read_domains, old_write_domain);
1663 }
1664
1665 int
1666 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1667 {
1668         uint32_t old_write_domain, old_read_domains;
1669         int ret;
1670
1671         if (obj->gtt_space == NULL)
1672                 return (-EINVAL);
1673
1674         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1675                 return 0;
1676
1677         ret = i915_gem_object_flush_gpu_write_domain(obj);
1678         if (ret != 0)
1679                 return (ret);
1680
1681         if (obj->pending_gpu_write || write) {
1682                 ret = i915_gem_object_wait_rendering(obj);
1683                 if (ret != 0)
1684                         return (ret);
1685         }
1686
1687         i915_gem_object_flush_cpu_write_domain(obj);
1688
1689         old_write_domain = obj->base.write_domain;
1690         old_read_domains = obj->base.read_domains;
1691
1692         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1693             ("In GTT write domain"));
1694         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1695         if (write) {
1696                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1697                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1698                 obj->dirty = 1;
1699         }
1700
1701         CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
1702             old_read_domains, old_write_domain);
1703         return (0);
1704 }
1705
1706 int
1707 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1708     enum i915_cache_level cache_level)
1709 {
1710         struct drm_device *dev;
1711         drm_i915_private_t *dev_priv;
1712         int ret;
1713
1714         if (obj->cache_level == cache_level)
1715                 return 0;
1716
1717         if (obj->pin_count) {
1718                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1719                 return (-EBUSY);
1720         }
1721
1722         dev = obj->base.dev;
1723         dev_priv = dev->dev_private;
1724         if (obj->gtt_space) {
1725                 ret = i915_gem_object_finish_gpu(obj);
1726                 if (ret != 0)
1727                         return (ret);
1728
1729                 i915_gem_object_finish_gtt(obj);
1730
1731                 /* Before SandyBridge, you could not use tiling or fence
1732                  * registers with snooped memory, so relinquish any fences
1733                  * currently pointing to our region in the aperture.
1734                  */
1735                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1736                         ret = i915_gem_object_put_fence(obj);
1737                         if (ret != 0)
1738                                 return (ret);
1739                 }
1740
1741                 i915_gem_gtt_rebind_object(obj, cache_level);
1742                 if (obj->has_aliasing_ppgtt_mapping)
1743                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1744                             obj, cache_level);
1745         }
1746
1747         if (cache_level == I915_CACHE_NONE) {
1748                 u32 old_read_domains, old_write_domain;
1749
1750                 /* If we're coming from LLC cached, then we haven't
1751                  * actually been tracking whether the data is in the
1752                  * CPU cache or not, since we only allow one bit set
1753                  * in obj->write_domain and have been skipping the clflushes.
1754                  * Just set it to the CPU cache for now.
1755                  */
1756                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1757                     ("obj %p in CPU write domain", obj));
1758                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1759                     ("obj %p in CPU read domain", obj));
1760
1761                 old_read_domains = obj->base.read_domains;
1762                 old_write_domain = obj->base.write_domain;
1763
1764                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1765                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1766
1767                 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
1768                     obj, old_read_domains, old_write_domain);
1769         }
1770
1771         obj->cache_level = cache_level;
1772         return (0);
1773 }
1774
1775 int
1776 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1777     u32 alignment, struct intel_ring_buffer *pipelined)
1778 {
1779         u32 old_read_domains, old_write_domain;
1780         int ret;
1781
1782         ret = i915_gem_object_flush_gpu_write_domain(obj);
1783         if (ret != 0)
1784                 return (ret);
1785
1786         if (pipelined != obj->ring) {
1787                 ret = i915_gem_object_wait_rendering(obj);
1788                 if (ret == -ERESTART || ret == -EINTR)
1789                         return (ret);
1790         }
1791
1792         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1793         if (ret != 0)
1794                 return (ret);
1795
1796         ret = i915_gem_object_pin(obj, alignment, true);
1797         if (ret != 0)
1798                 return (ret);
1799
1800         i915_gem_object_flush_cpu_write_domain(obj);
1801
1802         old_write_domain = obj->base.write_domain;
1803         old_read_domains = obj->base.read_domains;
1804
1805         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1806             ("obj %p in GTT write domain", obj));
1807         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1808
1809         CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
1810             obj, old_read_domains, obj->base.write_domain);
1811         return (0);
1812 }
1813
1814 int
1815 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1816 {
1817         int ret;
1818
1819         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1820                 return (0);
1821
1822         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1823                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1824                 if (ret != 0)
1825                         return (ret);
1826         }
1827
1828         ret = i915_gem_object_wait_rendering(obj);
1829         if (ret != 0)
1830                 return (ret);
1831
1832         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1833
1834         return (0);
1835 }
1836
1837 static int
1838 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1839 {
1840         uint32_t old_write_domain, old_read_domains;
1841         int ret;
1842
1843         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1844                 return 0;
1845
1846         ret = i915_gem_object_flush_gpu_write_domain(obj);
1847         if (ret != 0)
1848                 return (ret);
1849
1850         ret = i915_gem_object_wait_rendering(obj);
1851         if (ret != 0)
1852                 return (ret);
1853
1854         i915_gem_object_flush_gtt_write_domain(obj);
1855         i915_gem_object_set_to_full_cpu_read_domain(obj);
1856
1857         old_write_domain = obj->base.write_domain;
1858         old_read_domains = obj->base.read_domains;
1859
1860         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1861                 i915_gem_clflush_object(obj);
1862                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1863         }
1864
1865         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1866             ("In cpu write domain"));
1867
1868         if (write) {
1869                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1870                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1871         }
1872
1873         CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
1874             old_read_domains, old_write_domain);
1875         return (0);
1876 }
1877
1878 static void
1879 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1880 {
1881         int i;
1882
1883         if (obj->page_cpu_valid == NULL)
1884                 return;
1885
1886         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1887                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1888                         if (obj->page_cpu_valid[i] != 0)
1889                                 continue;
1890                         drm_clflush_pages(obj->pages + i, 1);
1891                 }
1892         }
1893
1894         free(obj->page_cpu_valid, DRM_I915_GEM);
1895         obj->page_cpu_valid = NULL;
1896 }
1897
1898 static int
1899 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1900     uint64_t offset, uint64_t size)
1901 {
1902         uint32_t old_read_domains;
1903         int i, ret;
1904
1905         if (offset == 0 && size == obj->base.size)
1906                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1907
1908         ret = i915_gem_object_flush_gpu_write_domain(obj);
1909         if (ret != 0)
1910                 return (ret);
1911         ret = i915_gem_object_wait_rendering(obj);
1912         if (ret != 0)
1913                 return (ret);
1914
1915         i915_gem_object_flush_gtt_write_domain(obj);
1916
1917         if (obj->page_cpu_valid == NULL &&
1918             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1919                 return (0);
1920
1921         if (obj->page_cpu_valid == NULL) {
1922                 obj->page_cpu_valid = malloc(obj->base.size / PAGE_SIZE,
1923                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1924         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1925                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1926
1927         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1928              i++) {
1929                 if (obj->page_cpu_valid[i])
1930                         continue;
1931                 drm_clflush_pages(obj->pages + i, 1);
1932                 obj->page_cpu_valid[i] = 1;
1933         }
1934
1935         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1936             ("In gpu write domain"));
1937
1938         old_read_domains = obj->base.read_domains;
1939         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1940
1941         CTR3(KTR_DRM, "object_change_domain set_cpu_read %p %x %x", obj,
1942             old_read_domains, obj->base.write_domain);
1943         return (0);
1944 }
1945
1946 static uint32_t
1947 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1948 {
1949         uint32_t gtt_size;
1950
1951         if (INTEL_INFO(dev)->gen >= 4 ||
1952             tiling_mode == I915_TILING_NONE)
1953                 return (size);
1954
1955         /* Previous chips need a power-of-two fence region when tiling */
1956         if (INTEL_INFO(dev)->gen == 3)
1957                 gtt_size = 1024*1024;
1958         else
1959                 gtt_size = 512*1024;
1960
1961         while (gtt_size < size)
1962                 gtt_size <<= 1;
1963
1964         return (gtt_size);
1965 }
1966
1967 /**
1968  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1969  * @obj: object to check
1970  *
1971  * Return the required GTT alignment for an object, taking into account
1972  * potential fence register mapping.
1973  */
1974 static uint32_t
1975 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1976      int tiling_mode)
1977 {
1978
1979         /*
1980          * Minimum alignment is 4k (GTT page size), but might be greater
1981          * if a fence register is needed for the object.
1982          */
1983         if (INTEL_INFO(dev)->gen >= 4 ||
1984             tiling_mode == I915_TILING_NONE)
1985                 return (4096);
1986
1987         /*
1988          * Previous chips need to be aligned to the size of the smallest
1989          * fence register that can contain the object.
1990          */
1991         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1992 }
1993
1994 uint32_t
1995 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1996     int tiling_mode)
1997 {
1998
1999         if (tiling_mode == I915_TILING_NONE)
2000                 return (4096);
2001
2002         /*
2003          * Minimum alignment is 4k (GTT page size) for sane hw.
2004          */
2005         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
2006                 return (4096);
2007
2008         /*
2009          * Previous hardware however needs to be aligned to a power-of-two
2010          * tile height. The simplest method for determining this is to reuse
2011          * the power-of-tile object size.
2012          */
2013         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
2014 }
2015
2016 static int
2017 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2018     unsigned alignment, bool map_and_fenceable)
2019 {
2020         struct drm_device *dev;
2021         struct drm_i915_private *dev_priv;
2022         struct drm_mm_node *free_space;
2023         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2024         bool mappable, fenceable;
2025         int ret;
2026
2027         dev = obj->base.dev;
2028         dev_priv = dev->dev_private;
2029
2030         if (obj->madv != I915_MADV_WILLNEED) {
2031                 DRM_ERROR("Attempting to bind a purgeable object\n");
2032                 return (-EINVAL);
2033         }
2034
2035         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2036             obj->tiling_mode);
2037         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2038             obj->tiling_mode);
2039         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2040             obj->base.size, obj->tiling_mode);
2041         if (alignment == 0)
2042                 alignment = map_and_fenceable ? fence_alignment :
2043                     unfenced_alignment;
2044         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2045                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2046                 return (-EINVAL);
2047         }
2048
2049         size = map_and_fenceable ? fence_size : obj->base.size;
2050
2051         /* If the object is bigger than the entire aperture, reject it early
2052          * before evicting everything in a vain attempt to find space.
2053          */
2054         if (obj->base.size > (map_and_fenceable ?
2055             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2056                 DRM_ERROR(
2057 "Attempting to bind an object larger than the aperture\n");
2058                 return (-E2BIG);
2059         }
2060
2061  search_free:
2062         if (map_and_fenceable)
2063                 free_space = drm_mm_search_free_in_range(
2064                     &dev_priv->mm.gtt_space, size, alignment, 0,
2065                     dev_priv->mm.gtt_mappable_end, 0);
2066         else
2067                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2068                     size, alignment, 0);
2069         if (free_space != NULL) {
2070                 if (map_and_fenceable)
2071                         obj->gtt_space = drm_mm_get_block_range_generic(
2072                             free_space, size, alignment, 0,
2073                             dev_priv->mm.gtt_mappable_end, 1);
2074                 else
2075                         obj->gtt_space = drm_mm_get_block_generic(free_space,
2076                             size, alignment, 1);
2077         }
2078         if (obj->gtt_space == NULL) {
2079                 ret = i915_gem_evict_something(dev, size, alignment,
2080                     map_and_fenceable);
2081                 if (ret != 0)
2082                         return (ret);
2083                 goto search_free;
2084         }
2085         ret = i915_gem_object_get_pages_gtt(obj, 0);
2086         if (ret != 0) {
2087                 drm_mm_put_block(obj->gtt_space);
2088                 obj->gtt_space = NULL;
2089                 /*
2090                  * i915_gem_object_get_pages_gtt() cannot return
2091                  * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
2092                  * (which does not support operation without a flag
2093                  * anyway).
2094                  */
2095                 return (ret);
2096         }
2097
2098         ret = i915_gem_gtt_bind_object(obj);
2099         if (ret != 0) {
2100                 i915_gem_object_put_pages_gtt(obj);
2101                 drm_mm_put_block(obj->gtt_space);
2102                 obj->gtt_space = NULL;
2103                 if (i915_gem_evict_everything(dev, false))
2104                         return (ret);
2105                 goto search_free;
2106         }
2107
2108         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2109         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2110
2111         KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2112             ("Object in gpu read domain"));
2113         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2114             ("Object in gpu write domain"));
2115
2116         obj->gtt_offset = obj->gtt_space->start;
2117
2118         fenceable =
2119                 obj->gtt_space->size == fence_size &&
2120                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2121
2122         mappable =
2123                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2124         obj->map_and_fenceable = mappable && fenceable;
2125
2126         CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
2127             obj->base.size, map_and_fenceable);
2128         return (0);
2129 }
2130
2131 static void
2132 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2133 {
2134         u32 old_write_domain, old_read_domains;
2135
2136         /* Act a barrier for all accesses through the GTT */
2137         mb();
2138
2139         /* Force a pagefault for domain tracking on next user access */
2140         i915_gem_release_mmap(obj);
2141
2142         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2143                 return;
2144
2145         old_read_domains = obj->base.read_domains;
2146         old_write_domain = obj->base.write_domain;
2147
2148         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2149         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2150
2151         CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2152             obj, old_read_domains, old_write_domain);
2153 }
2154
2155 int
2156 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2157 {
2158         drm_i915_private_t *dev_priv;
2159         int ret;
2160
2161         dev_priv = obj->base.dev->dev_private;
2162         ret = 0;
2163         if (obj->gtt_space == NULL)
2164                 return (0);
2165         if (obj->pin_count != 0) {
2166                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2167                 return (-EINVAL);
2168         }
2169
2170         ret = i915_gem_object_finish_gpu(obj);
2171         if (ret == -ERESTART || ret == -EINTR)
2172                 return (ret);
2173
2174         i915_gem_object_finish_gtt(obj);
2175
2176         if (ret == 0)
2177                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2178         if (ret == -ERESTART || ret == -EINTR)
2179                 return (ret);
2180         if (ret != 0) {
2181                 i915_gem_clflush_object(obj);
2182                 obj->base.read_domains = obj->base.write_domain =
2183                     I915_GEM_DOMAIN_CPU;
2184         }
2185
2186         ret = i915_gem_object_put_fence(obj);
2187         if (ret == -ERESTART)
2188                 return (ret);
2189
2190         i915_gem_gtt_unbind_object(obj);
2191         if (obj->has_aliasing_ppgtt_mapping) {
2192                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2193                 obj->has_aliasing_ppgtt_mapping = 0;
2194         }
2195         i915_gem_object_put_pages_gtt(obj);
2196
2197         list_del_init(&obj->gtt_list);
2198         list_del_init(&obj->mm_list);
2199         obj->map_and_fenceable = true;
2200
2201         drm_mm_put_block(obj->gtt_space);
2202         obj->gtt_space = NULL;
2203         obj->gtt_offset = 0;
2204
2205         if (i915_gem_object_is_purgeable(obj))
2206                 i915_gem_object_truncate(obj);
2207         CTR1(KTR_DRM, "object_unbind %p", obj);
2208
2209         return (ret);
2210 }
2211
2212 static int
2213 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2214     int flags)
2215 {
2216         struct drm_device *dev;
2217         vm_object_t vm_obj;
2218         vm_page_t m;
2219         int page_count, i, j;
2220
2221         dev = obj->base.dev;
2222         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2223         page_count = obj->base.size / PAGE_SIZE;
2224         obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2225             M_WAITOK);
2226         vm_obj = obj->base.vm_obj;
2227         VM_OBJECT_LOCK(vm_obj);
2228         for (i = 0; i < page_count; i++) {
2229                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2230                         goto failed;
2231         }
2232         VM_OBJECT_UNLOCK(vm_obj);
2233         if (i915_gem_object_needs_bit17_swizzle(obj))
2234                 i915_gem_object_do_bit_17_swizzle(obj);
2235         return (0);
2236
2237 failed:
2238         for (j = 0; j < i; j++) {
2239                 m = obj->pages[j];
2240                 vm_page_lock(m);
2241                 vm_page_unwire(m, 0);
2242                 vm_page_unlock(m);
2243                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2244         }
2245         VM_OBJECT_UNLOCK(vm_obj);
2246         free(obj->pages, DRM_I915_GEM);
2247         obj->pages = NULL;
2248         return (-EIO);
2249 }
2250
2251 #define GEM_PARANOID_CHECK_GTT 0
2252 #if GEM_PARANOID_CHECK_GTT
2253 static void
2254 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2255     int page_count)
2256 {
2257         struct drm_i915_private *dev_priv;
2258         vm_paddr_t pa;
2259         unsigned long start, end;
2260         u_int i;
2261         int j;
2262
2263         dev_priv = dev->dev_private;
2264         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2265         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2266         for (i = start; i < end; i++) {
2267                 pa = intel_gtt_read_pte_paddr(i);
2268                 for (j = 0; j < page_count; j++) {
2269                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2270                                 panic("Page %p in GTT pte index %d pte %x",
2271                                     ma[i], i, intel_gtt_read_pte(i));
2272                         }
2273                 }
2274         }
2275 }
2276 #endif
2277
2278 static void
2279 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2280 {
2281         vm_page_t m;
2282         int page_count, i;
2283
2284         KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2285
2286         if (obj->tiling_mode != I915_TILING_NONE)
2287                 i915_gem_object_save_bit_17_swizzle(obj);
2288         if (obj->madv == I915_MADV_DONTNEED)
2289                 obj->dirty = 0;
2290         page_count = obj->base.size / PAGE_SIZE;
2291         VM_OBJECT_LOCK(obj->base.vm_obj);
2292 #if GEM_PARANOID_CHECK_GTT
2293         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2294 #endif
2295         for (i = 0; i < page_count; i++) {
2296                 m = obj->pages[i];
2297                 if (obj->dirty)
2298                         vm_page_dirty(m);
2299                 if (obj->madv == I915_MADV_WILLNEED)
2300                         vm_page_reference(m);
2301                 vm_page_lock(m);
2302                 vm_page_unwire(obj->pages[i], 1);
2303                 vm_page_unlock(m);
2304                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2305         }
2306         VM_OBJECT_UNLOCK(obj->base.vm_obj);
2307         obj->dirty = 0;
2308         free(obj->pages, DRM_I915_GEM);
2309         obj->pages = NULL;
2310 }
2311
2312 void
2313 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2314 {
2315         vm_object_t devobj;
2316         vm_page_t m;
2317         int i, page_count;
2318
2319         if (!obj->fault_mappable)
2320                 return;
2321
2322         CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
2323             OFF_TO_IDX(obj->base.size));
2324         devobj = cdev_pager_lookup(obj);
2325         if (devobj != NULL) {
2326                 page_count = OFF_TO_IDX(obj->base.size);
2327
2328                 VM_OBJECT_LOCK(devobj);
2329 retry:
2330                 for (i = 0; i < page_count; i++) {
2331                         m = vm_page_lookup(devobj, i);
2332                         if (m == NULL)
2333                                 continue;
2334                         if (vm_page_sleep_if_busy(m, true, "915unm"))
2335                                 goto retry;
2336                         cdev_pager_free_page(devobj, m);
2337                 }
2338                 VM_OBJECT_UNLOCK(devobj);
2339                 vm_object_deallocate(devobj);
2340         }
2341
2342         obj->fault_mappable = false;
2343 }
2344
2345 int
2346 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2347 {
2348         int ret;
2349
2350         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2351             ("In GPU write domain"));
2352
2353         CTR5(KTR_DRM, "object_wait_rendering %p %s %x %d %d", obj,
2354             obj->ring != NULL ? obj->ring->name : "none", obj->gtt_offset,
2355             obj->active, obj->last_rendering_seqno);
2356         if (obj->active) {
2357                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2358                     true);
2359                 if (ret != 0)
2360                         return (ret);
2361         }
2362         return (0);
2363 }
2364
2365 void
2366 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2367     struct intel_ring_buffer *ring, uint32_t seqno)
2368 {
2369         struct drm_device *dev = obj->base.dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371         struct drm_i915_fence_reg *reg;
2372
2373         obj->ring = ring;
2374         KASSERT(ring != NULL, ("NULL ring"));
2375
2376         /* Add a reference if we're newly entering the active list. */
2377         if (!obj->active) {
2378                 drm_gem_object_reference(&obj->base);
2379                 obj->active = 1;
2380         }
2381
2382         /* Move from whatever list we were on to the tail of execution. */
2383         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2384         list_move_tail(&obj->ring_list, &ring->active_list);
2385
2386         obj->last_rendering_seqno = seqno;
2387         if (obj->fenced_gpu_access) {
2388                 obj->last_fenced_seqno = seqno;
2389                 obj->last_fenced_ring = ring;
2390
2391                 /* Bump MRU to take account of the delayed flush */
2392                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2393                         reg = &dev_priv->fence_regs[obj->fence_reg];
2394                         list_move_tail(&reg->lru_list,
2395                                        &dev_priv->mm.fence_list);
2396                 }
2397         }
2398 }
2399
2400 static void
2401 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2402 {
2403         list_del_init(&obj->ring_list);
2404         obj->last_rendering_seqno = 0;
2405         obj->last_fenced_seqno = 0;
2406 }
2407
2408 static void
2409 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2410 {
2411         struct drm_device *dev = obj->base.dev;
2412         drm_i915_private_t *dev_priv = dev->dev_private;
2413
2414         KASSERT(obj->active, ("Object not active"));
2415         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2416
2417         i915_gem_object_move_off_active(obj);
2418 }
2419
2420 static void
2421 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2422 {
2423         struct drm_device *dev = obj->base.dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425
2426         if (obj->pin_count != 0)
2427                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2428         else
2429                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2430
2431         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2432         KASSERT(obj->active, ("Object not active"));
2433         obj->ring = NULL;
2434         obj->last_fenced_ring = NULL;
2435
2436         i915_gem_object_move_off_active(obj);
2437         obj->fenced_gpu_access = false;
2438
2439         obj->active = 0;
2440         obj->pending_gpu_write = false;
2441         drm_gem_object_unreference(&obj->base);
2442
2443 #if 1
2444         KIB_NOTYET();
2445 #else
2446         WARN_ON(i915_verify_lists(dev));
2447 #endif
2448 }
2449
2450 static void
2451 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2452 {
2453         vm_object_t vm_obj;
2454
2455         vm_obj = obj->base.vm_obj;
2456         VM_OBJECT_LOCK(vm_obj);
2457         vm_object_page_remove(vm_obj, 0, 0, false);
2458         VM_OBJECT_UNLOCK(vm_obj);
2459         obj->madv = I915_MADV_PURGED_INTERNAL;
2460 }
2461
2462 static inline int
2463 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2464 {
2465
2466         return (obj->madv == I915_MADV_DONTNEED);
2467 }
2468
2469 static void
2470 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2471     uint32_t flush_domains)
2472 {
2473         struct drm_i915_gem_object *obj, *next;
2474         uint32_t old_write_domain;
2475
2476         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2477             gpu_write_list) {
2478                 if (obj->base.write_domain & flush_domains) {
2479                         old_write_domain = obj->base.write_domain;
2480                         obj->base.write_domain = 0;
2481                         list_del_init(&obj->gpu_write_list);
2482                         i915_gem_object_move_to_active(obj, ring,
2483                             i915_gem_next_request_seqno(ring));
2484
2485         CTR3(KTR_DRM, "object_change_domain process_flush %p %x %x",
2486                             obj, obj->base.read_domains, old_write_domain);
2487                 }
2488         }
2489 }
2490
2491 static int
2492 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2493 {
2494         drm_i915_private_t *dev_priv;
2495
2496         dev_priv = obj->base.dev->dev_private;
2497         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2498             obj->tiling_mode != I915_TILING_NONE);
2499 }
2500
2501 static vm_page_t
2502 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2503 {
2504         vm_page_t m;
2505         int rv;
2506
2507         VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2508         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
2509         if (m->valid != VM_PAGE_BITS_ALL) {
2510                 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
2511                         rv = vm_pager_get_pages(object, &m, 1, 0);
2512                         m = vm_page_lookup(object, pindex);
2513                         if (m == NULL)
2514                                 return (NULL);
2515                         if (rv != VM_PAGER_OK) {
2516                                 vm_page_lock(m);
2517                                 vm_page_free(m);
2518                                 vm_page_unlock(m);
2519                                 return (NULL);
2520                         }
2521                 } else {
2522                         pmap_zero_page(m);
2523                         m->valid = VM_PAGE_BITS_ALL;
2524                         m->dirty = 0;
2525                 }
2526         }
2527         vm_page_lock(m);
2528         vm_page_wire(m);
2529         vm_page_unlock(m);
2530         vm_page_wakeup(m);
2531         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2532         return (m);
2533 }
2534
2535 int
2536 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2537     uint32_t flush_domains)
2538 {
2539         int ret;
2540
2541         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2542                 return 0;
2543
2544         CTR3(KTR_DRM, "ring_flush %s %x %x", ring->name, invalidate_domains,
2545             flush_domains);
2546         ret = ring->flush(ring, invalidate_domains, flush_domains);
2547         if (ret)
2548                 return ret;
2549
2550         if (flush_domains & I915_GEM_GPU_DOMAINS)
2551                 i915_gem_process_flushing_list(ring, flush_domains);
2552         return 0;
2553 }
2554
2555 static int
2556 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2557 {
2558         int ret;
2559
2560         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2561                 return 0;
2562
2563         if (!list_empty(&ring->gpu_write_list)) {
2564                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2565                     I915_GEM_GPU_DOMAINS);
2566                 if (ret != 0)
2567                         return ret;
2568         }
2569
2570         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2571             do_retire));
2572 }
2573
2574 int
2575 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2576 {
2577         drm_i915_private_t *dev_priv = dev->dev_private;
2578         int ret, i;
2579
2580         /* Flush everything onto the inactive list. */
2581         for (i = 0; i < I915_NUM_RINGS; i++) {
2582                 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2583                 if (ret)
2584                         return ret;
2585         }
2586
2587         return 0;
2588 }
2589
2590 int
2591 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2592 {
2593         drm_i915_private_t *dev_priv;
2594         struct drm_i915_gem_request *request;
2595         uint32_t ier;
2596         int flags, ret;
2597         bool recovery_complete;
2598
2599         KASSERT(seqno != 0, ("Zero seqno"));
2600
2601         dev_priv = ring->dev->dev_private;
2602         ret = 0;
2603
2604         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
2605                 /* Give the error handler a chance to run. */
2606                 mtx_lock(&dev_priv->error_completion_lock);
2607                 recovery_complete = (&dev_priv->error_completion) > 0;
2608                 mtx_unlock(&dev_priv->error_completion_lock);
2609                 return (recovery_complete ? -EIO : -EAGAIN);
2610         }
2611
2612         if (seqno == ring->outstanding_lazy_request) {
2613                 request = malloc(sizeof(*request), DRM_I915_GEM,
2614                     M_WAITOK | M_ZERO);
2615                 if (request == NULL)
2616                         return (-ENOMEM);
2617
2618                 ret = i915_add_request(ring, NULL, request);
2619                 if (ret != 0) {
2620                         free(request, DRM_I915_GEM);
2621                         return (ret);
2622                 }
2623
2624                 seqno = request->seqno;
2625         }
2626
2627         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2628                 if (HAS_PCH_SPLIT(ring->dev))
2629                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2630                 else
2631                         ier = I915_READ(IER);
2632                 if (!ier) {
2633                         DRM_ERROR("something (likely vbetool) disabled "
2634                                   "interrupts, re-enabling\n");
2635                         ring->dev->driver->irq_preinstall(ring->dev);
2636                         ring->dev->driver->irq_postinstall(ring->dev);
2637                 }
2638
2639                 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
2640
2641                 ring->waiting_seqno = seqno;
2642                 mtx_lock(&ring->irq_lock);
2643                 if (ring->irq_get(ring)) {
2644                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2645                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2646                             && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
2647                             ret == 0) {
2648                                 ret = -msleep(ring, &ring->irq_lock, flags,
2649                                     "915gwr", 0);
2650                         }
2651                         ring->irq_put(ring);
2652                         mtx_unlock(&ring->irq_lock);
2653                 } else {
2654                         mtx_unlock(&ring->irq_lock);
2655                         if (_intel_wait_for(ring->dev,
2656                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2657                             atomic_load_acq_int(&dev_priv->mm.wedged), 3000,
2658                             0, "i915wrq") != 0)
2659                                 ret = -EBUSY;
2660                 }
2661                 ring->waiting_seqno = 0;
2662
2663                 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno,
2664                     ret);
2665         }
2666         if (atomic_load_acq_int(&dev_priv->mm.wedged))
2667                 ret = -EAGAIN;
2668
2669         /* Directly dispatch request retiring.  While we have the work queue
2670          * to handle this, the waiter on a request often wants an associated
2671          * buffer to have made it to the inactive list, and we would need
2672          * a separate wait queue to handle that.
2673          */
2674         if (ret == 0 && do_retire)
2675                 i915_gem_retire_requests_ring(ring);
2676
2677         return (ret);
2678 }
2679
2680 static u32
2681 i915_gem_get_seqno(struct drm_device *dev)
2682 {
2683         drm_i915_private_t *dev_priv = dev->dev_private;
2684         u32 seqno = dev_priv->next_seqno;
2685
2686         /* reserve 0 for non-seqno */
2687         if (++dev_priv->next_seqno == 0)
2688                 dev_priv->next_seqno = 1;
2689
2690         return seqno;
2691 }
2692
2693 u32
2694 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2695 {
2696         if (ring->outstanding_lazy_request == 0)
2697                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2698
2699         return ring->outstanding_lazy_request;
2700 }
2701
2702 int
2703 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2704      struct drm_i915_gem_request *request)
2705 {
2706         drm_i915_private_t *dev_priv;
2707         struct drm_i915_file_private *file_priv;
2708         uint32_t seqno;
2709         u32 request_ring_position;
2710         int was_empty;
2711         int ret;
2712
2713         KASSERT(request != NULL, ("NULL request in add"));
2714         DRM_LOCK_ASSERT(ring->dev);
2715         dev_priv = ring->dev->dev_private;
2716
2717         seqno = i915_gem_next_request_seqno(ring);
2718         request_ring_position = intel_ring_get_tail(ring);
2719
2720         ret = ring->add_request(ring, &seqno);
2721         if (ret != 0)
2722             return ret;
2723
2724         CTR2(KTR_DRM, "request_add %s %d", ring->name, seqno);
2725
2726         request->seqno = seqno;
2727         request->ring = ring;
2728         request->tail = request_ring_position;
2729         request->emitted_jiffies = ticks;
2730         was_empty = list_empty(&ring->request_list);
2731         list_add_tail(&request->list, &ring->request_list);
2732
2733         if (file != NULL) {
2734                 file_priv = file->driver_priv;
2735
2736                 mtx_lock(&file_priv->mm.lck);
2737                 request->file_priv = file_priv;
2738                 list_add_tail(&request->client_list,
2739                     &file_priv->mm.request_list);
2740                 mtx_unlock(&file_priv->mm.lck);
2741         }
2742
2743         ring->outstanding_lazy_request = 0;
2744
2745         if (!dev_priv->mm.suspended) {
2746                 if (i915_enable_hangcheck) {
2747                         callout_schedule(&dev_priv->hangcheck_timer,
2748                             DRM_I915_HANGCHECK_PERIOD);
2749                 }
2750                 if (was_empty)
2751                         taskqueue_enqueue_timeout(dev_priv->tq,
2752                             &dev_priv->mm.retire_task, hz);
2753         }
2754         return (0);
2755 }
2756
2757 static inline void
2758 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2759 {
2760         struct drm_i915_file_private *file_priv = request->file_priv;
2761
2762         if (!file_priv)
2763                 return;
2764
2765         DRM_LOCK_ASSERT(request->ring->dev);
2766
2767         mtx_lock(&file_priv->mm.lck);
2768         if (request->file_priv != NULL) {
2769                 list_del(&request->client_list);
2770                 request->file_priv = NULL;
2771         }
2772         mtx_unlock(&file_priv->mm.lck);
2773 }
2774
2775 void
2776 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2777 {
2778         struct drm_i915_file_private *file_priv;
2779         struct drm_i915_gem_request *request;
2780
2781         file_priv = file->driver_priv;
2782
2783         /* Clean up our request list when the client is going away, so that
2784          * later retire_requests won't dereference our soon-to-be-gone
2785          * file_priv.
2786          */
2787         mtx_lock(&file_priv->mm.lck);
2788         while (!list_empty(&file_priv->mm.request_list)) {
2789                 request = list_first_entry(&file_priv->mm.request_list,
2790                                            struct drm_i915_gem_request,
2791                                            client_list);
2792                 list_del(&request->client_list);
2793                 request->file_priv = NULL;
2794         }
2795         mtx_unlock(&file_priv->mm.lck);
2796 }
2797
2798 static void
2799 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2800     struct intel_ring_buffer *ring)
2801 {
2802
2803         if (ring->dev != NULL)
2804                 DRM_LOCK_ASSERT(ring->dev);
2805
2806         while (!list_empty(&ring->request_list)) {
2807                 struct drm_i915_gem_request *request;
2808
2809                 request = list_first_entry(&ring->request_list,
2810                     struct drm_i915_gem_request, list);
2811
2812                 list_del(&request->list);
2813                 i915_gem_request_remove_from_client(request);
2814                 free(request, DRM_I915_GEM);
2815         }
2816
2817         while (!list_empty(&ring->active_list)) {
2818                 struct drm_i915_gem_object *obj;
2819
2820                 obj = list_first_entry(&ring->active_list,
2821                     struct drm_i915_gem_object, ring_list);
2822
2823                 obj->base.write_domain = 0;
2824                 list_del_init(&obj->gpu_write_list);
2825                 i915_gem_object_move_to_inactive(obj);
2826         }
2827 }
2828
2829 static void
2830 i915_gem_reset_fences(struct drm_device *dev)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         int i;
2834
2835         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2836                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2837                 struct drm_i915_gem_object *obj = reg->obj;
2838
2839                 if (!obj)
2840                         continue;
2841
2842                 if (obj->tiling_mode)
2843                         i915_gem_release_mmap(obj);
2844
2845                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2846                 reg->obj->fenced_gpu_access = false;
2847                 reg->obj->last_fenced_seqno = 0;
2848                 reg->obj->last_fenced_ring = NULL;
2849                 i915_gem_clear_fence_reg(dev, reg);
2850         }
2851 }
2852
2853 void
2854 i915_gem_reset(struct drm_device *dev)
2855 {
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         struct drm_i915_gem_object *obj;
2858         int i;
2859
2860         for (i = 0; i < I915_NUM_RINGS; i++)
2861                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2862
2863         /* Remove anything from the flushing lists. The GPU cache is likely
2864          * to be lost on reset along with the data, so simply move the
2865          * lost bo to the inactive list.
2866          */
2867         while (!list_empty(&dev_priv->mm.flushing_list)) {
2868                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2869                                       struct drm_i915_gem_object,
2870                                       mm_list);
2871
2872                 obj->base.write_domain = 0;
2873                 list_del_init(&obj->gpu_write_list);
2874                 i915_gem_object_move_to_inactive(obj);
2875         }
2876
2877         /* Move everything out of the GPU domains to ensure we do any
2878          * necessary invalidation upon reuse.
2879          */
2880         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2881                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2882         }
2883
2884         /* The fence registers are invalidated so clear them out */
2885         i915_gem_reset_fences(dev);
2886 }
2887
2888 /**
2889  * This function clears the request list as sequence numbers are passed.
2890  */
2891 void
2892 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2893 {
2894         uint32_t seqno;
2895         int i;
2896
2897         if (list_empty(&ring->request_list))
2898                 return;
2899
2900         seqno = ring->get_seqno(ring);
2901         CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2902
2903         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2904                 if (seqno >= ring->sync_seqno[i])
2905                         ring->sync_seqno[i] = 0;
2906
2907         while (!list_empty(&ring->request_list)) {
2908                 struct drm_i915_gem_request *request;
2909
2910                 request = list_first_entry(&ring->request_list,
2911                                            struct drm_i915_gem_request,
2912                                            list);
2913
2914                 if (!i915_seqno_passed(seqno, request->seqno))
2915                         break;
2916
2917                 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2918                     ring->name, seqno);
2919                 ring->last_retired_head = request->tail;
2920
2921                 list_del(&request->list);
2922                 i915_gem_request_remove_from_client(request);
2923                 free(request, DRM_I915_GEM);
2924         }
2925
2926         /* Move any buffers on the active list that are no longer referenced
2927          * by the ringbuffer to the flushing/inactive lists as appropriate.
2928          */
2929         while (!list_empty(&ring->active_list)) {
2930                 struct drm_i915_gem_object *obj;
2931
2932                 obj = list_first_entry(&ring->active_list,
2933                                       struct drm_i915_gem_object,
2934                                       ring_list);
2935
2936                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2937                         break;
2938
2939                 if (obj->base.write_domain != 0)
2940                         i915_gem_object_move_to_flushing(obj);
2941                 else
2942                         i915_gem_object_move_to_inactive(obj);
2943         }
2944
2945         if (ring->trace_irq_seqno &&
2946             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2947                 mtx_lock(&ring->irq_lock);
2948                 ring->irq_put(ring);
2949                 mtx_unlock(&ring->irq_lock);
2950                 ring->trace_irq_seqno = 0;
2951         }
2952 }
2953
2954 void
2955 i915_gem_retire_requests(struct drm_device *dev)
2956 {
2957         drm_i915_private_t *dev_priv = dev->dev_private;
2958         struct drm_i915_gem_object *obj, *next;
2959         int i;
2960
2961         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2962                 list_for_each_entry_safe(obj, next,
2963                     &dev_priv->mm.deferred_free_list, mm_list)
2964                         i915_gem_free_object_tail(obj);
2965         }
2966
2967         for (i = 0; i < I915_NUM_RINGS; i++)
2968                 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2969 }
2970
2971 static int
2972 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2973     struct intel_ring_buffer *pipelined)
2974 {
2975         struct drm_device *dev = obj->base.dev;
2976         drm_i915_private_t *dev_priv = dev->dev_private;
2977         u32 size = obj->gtt_space->size;
2978         int regnum = obj->fence_reg;
2979         uint64_t val;
2980
2981         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2982                          0xfffff000) << 32;
2983         val |= obj->gtt_offset & 0xfffff000;
2984         val |= (uint64_t)((obj->stride / 128) - 1) <<
2985                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2986
2987         if (obj->tiling_mode == I915_TILING_Y)
2988                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2989         val |= I965_FENCE_REG_VALID;
2990
2991         if (pipelined) {
2992                 int ret = intel_ring_begin(pipelined, 6);
2993                 if (ret)
2994                         return ret;
2995
2996                 intel_ring_emit(pipelined, MI_NOOP);
2997                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2998                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2999                 intel_ring_emit(pipelined, (u32)val);
3000                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
3001                 intel_ring_emit(pipelined, (u32)(val >> 32));
3002                 intel_ring_advance(pipelined);
3003         } else
3004                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
3005
3006         return 0;
3007 }
3008
3009 static int
3010 i965_write_fence_reg(struct drm_i915_gem_object *obj,
3011     struct intel_ring_buffer *pipelined)
3012 {
3013         struct drm_device *dev = obj->base.dev;
3014         drm_i915_private_t *dev_priv = dev->dev_private;
3015         u32 size = obj->gtt_space->size;
3016         int regnum = obj->fence_reg;
3017         uint64_t val;
3018
3019         val = (uint64_t)((obj->gtt_offset + size - 4096) &
3020                     0xfffff000) << 32;
3021         val |= obj->gtt_offset & 0xfffff000;
3022         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
3023         if (obj->tiling_mode == I915_TILING_Y)
3024                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3025         val |= I965_FENCE_REG_VALID;
3026
3027         if (pipelined) {
3028                 int ret = intel_ring_begin(pipelined, 6);
3029                 if (ret)
3030                         return ret;
3031
3032                 intel_ring_emit(pipelined, MI_NOOP);
3033                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
3034                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
3035                 intel_ring_emit(pipelined, (u32)val);
3036                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
3037                 intel_ring_emit(pipelined, (u32)(val >> 32));
3038                 intel_ring_advance(pipelined);
3039         } else
3040                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
3041
3042         return 0;
3043 }
3044
3045 static int
3046 i915_write_fence_reg(struct drm_i915_gem_object *obj,
3047     struct intel_ring_buffer *pipelined)
3048 {
3049         struct drm_device *dev = obj->base.dev;
3050         drm_i915_private_t *dev_priv = dev->dev_private;
3051         u32 size = obj->gtt_space->size;
3052         u32 fence_reg, val, pitch_val;
3053         int tile_width;
3054
3055         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
3056             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3057                 printf(
3058 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3059                  obj->gtt_offset, obj->map_and_fenceable, size);
3060                 return -EINVAL;
3061         }
3062
3063         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3064                 tile_width = 128;
3065         else
3066                 tile_width = 512;
3067
3068         /* Note: pitch better be a power of two tile widths */
3069         pitch_val = obj->stride / tile_width;
3070         pitch_val = ffs(pitch_val) - 1;
3071
3072         val = obj->gtt_offset;
3073         if (obj->tiling_mode == I915_TILING_Y)
3074                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3075         val |= I915_FENCE_SIZE_BITS(size);
3076         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3077         val |= I830_FENCE_REG_VALID;
3078
3079         fence_reg = obj->fence_reg;
3080         if (fence_reg < 8)
3081                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3082         else
3083                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3084
3085         if (pipelined) {
3086                 int ret = intel_ring_begin(pipelined, 4);
3087                 if (ret)
3088                         return ret;
3089
3090                 intel_ring_emit(pipelined, MI_NOOP);
3091                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3092                 intel_ring_emit(pipelined, fence_reg);
3093                 intel_ring_emit(pipelined, val);
3094                 intel_ring_advance(pipelined);
3095         } else
3096                 I915_WRITE(fence_reg, val);
3097
3098         return 0;
3099 }
3100
3101 static int
3102 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3103     struct intel_ring_buffer *pipelined)
3104 {
3105         struct drm_device *dev = obj->base.dev;
3106         drm_i915_private_t *dev_priv = dev->dev_private;
3107         u32 size = obj->gtt_space->size;
3108         int regnum = obj->fence_reg;
3109         uint32_t val;
3110         uint32_t pitch_val;
3111
3112         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3113             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3114                 printf(
3115 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3116                     obj->gtt_offset, size);
3117                 return -EINVAL;
3118         }
3119
3120         pitch_val = obj->stride / 128;
3121         pitch_val = ffs(pitch_val) - 1;
3122
3123         val = obj->gtt_offset;
3124         if (obj->tiling_mode == I915_TILING_Y)
3125                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3126         val |= I830_FENCE_SIZE_BITS(size);
3127         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3128         val |= I830_FENCE_REG_VALID;
3129
3130         if (pipelined) {
3131                 int ret = intel_ring_begin(pipelined, 4);
3132                 if (ret)
3133                         return ret;
3134
3135                 intel_ring_emit(pipelined, MI_NOOP);
3136                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3137                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3138                 intel_ring_emit(pipelined, val);
3139                 intel_ring_advance(pipelined);
3140         } else
3141                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3142
3143         return 0;
3144 }
3145
3146 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3147 {
3148         return i915_seqno_passed(ring->get_seqno(ring), seqno);
3149 }
3150
3151 static int
3152 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3153     struct intel_ring_buffer *pipelined)
3154 {
3155         int ret;
3156
3157         if (obj->fenced_gpu_access) {
3158                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3159                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3160                             obj->base.write_domain);
3161                         if (ret)
3162                                 return ret;
3163                 }
3164
3165                 obj->fenced_gpu_access = false;
3166         }
3167
3168         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3169                 if (!ring_passed_seqno(obj->last_fenced_ring,
3170                                        obj->last_fenced_seqno)) {
3171                         ret = i915_wait_request(obj->last_fenced_ring,
3172                                                 obj->last_fenced_seqno,
3173                                                 true);
3174                         if (ret)
3175                                 return ret;
3176                 }
3177
3178                 obj->last_fenced_seqno = 0;
3179                 obj->last_fenced_ring = NULL;
3180         }
3181
3182         /* Ensure that all CPU reads are completed before installing a fence
3183          * and all writes before removing the fence.
3184          */
3185         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3186                 mb();
3187
3188         return 0;
3189 }
3190
3191 int
3192 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3193 {
3194         int ret;
3195
3196         if (obj->tiling_mode)
3197                 i915_gem_release_mmap(obj);
3198
3199         ret = i915_gem_object_flush_fence(obj, NULL);
3200         if (ret)
3201                 return ret;
3202
3203         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3204                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3205
3206                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3207                         printf("%s: pin_count %d\n", __func__,
3208                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3209                 i915_gem_clear_fence_reg(obj->base.dev,
3210                                          &dev_priv->fence_regs[obj->fence_reg]);
3211
3212                 obj->fence_reg = I915_FENCE_REG_NONE;
3213         }
3214
3215         return 0;
3216 }
3217
3218 static struct drm_i915_fence_reg *
3219 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3220 {
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222         struct drm_i915_fence_reg *reg, *first, *avail;
3223         int i;
3224
3225         /* First try to find a free reg */
3226         avail = NULL;
3227         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3228                 reg = &dev_priv->fence_regs[i];
3229                 if (!reg->obj)
3230                         return reg;
3231
3232                 if (!reg->pin_count)
3233                         avail = reg;
3234         }
3235
3236         if (avail == NULL)
3237                 return NULL;
3238
3239         /* None available, try to steal one or wait for a user to finish */
3240         avail = first = NULL;
3241         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3242                 if (reg->pin_count)
3243                         continue;
3244
3245                 if (first == NULL)
3246                         first = reg;
3247
3248                 if (!pipelined ||
3249                     !reg->obj->last_fenced_ring ||
3250                     reg->obj->last_fenced_ring == pipelined) {
3251                         avail = reg;
3252                         break;
3253                 }
3254         }
3255
3256         if (avail == NULL)
3257                 avail = first;
3258
3259         return avail;
3260 }
3261
3262 int
3263 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3264     struct intel_ring_buffer *pipelined)
3265 {
3266         struct drm_device *dev = obj->base.dev;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct drm_i915_fence_reg *reg;
3269         int ret;
3270
3271         pipelined = NULL;
3272         ret = 0;
3273
3274         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3275                 reg = &dev_priv->fence_regs[obj->fence_reg];
3276                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3277
3278                 if (obj->tiling_changed) {
3279                         ret = i915_gem_object_flush_fence(obj, pipelined);
3280                         if (ret)
3281                                 return ret;
3282
3283                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3284                                 pipelined = NULL;
3285
3286                         if (pipelined) {
3287                                 reg->setup_seqno =
3288                                         i915_gem_next_request_seqno(pipelined);
3289                                 obj->last_fenced_seqno = reg->setup_seqno;
3290                                 obj->last_fenced_ring = pipelined;
3291                         }
3292
3293                         goto update;
3294                 }
3295
3296                 if (!pipelined) {
3297                         if (reg->setup_seqno) {
3298                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3299                                     reg->setup_seqno)) {
3300                                         ret = i915_wait_request(
3301                                             obj->last_fenced_ring,
3302                                             reg->setup_seqno,
3303                                             true);
3304                                         if (ret)
3305                                                 return ret;
3306                                 }
3307
3308                                 reg->setup_seqno = 0;
3309                         }
3310                 } else if (obj->last_fenced_ring &&
3311                            obj->last_fenced_ring != pipelined) {
3312                         ret = i915_gem_object_flush_fence(obj, pipelined);
3313                         if (ret)
3314                                 return ret;
3315                 }
3316
3317                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3318                         pipelined = NULL;
3319                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3320
3321                 if (obj->tiling_changed) {
3322                         if (pipelined) {
3323                                 reg->setup_seqno =
3324                                         i915_gem_next_request_seqno(pipelined);
3325                                 obj->last_fenced_seqno = reg->setup_seqno;
3326                                 obj->last_fenced_ring = pipelined;
3327                         }
3328                         goto update;
3329                 }
3330
3331                 return 0;
3332         }
3333
3334         reg = i915_find_fence_reg(dev, pipelined);
3335         if (reg == NULL)
3336                 return -EDEADLK;
3337
3338         ret = i915_gem_object_flush_fence(obj, pipelined);
3339         if (ret)
3340                 return ret;
3341
3342         if (reg->obj) {
3343                 struct drm_i915_gem_object *old = reg->obj;
3344
3345                 drm_gem_object_reference(&old->base);
3346
3347                 if (old->tiling_mode)
3348                         i915_gem_release_mmap(old);
3349
3350                 ret = i915_gem_object_flush_fence(old, pipelined);
3351                 if (ret) {
3352                         drm_gem_object_unreference(&old->base);
3353                         return ret;
3354                 }
3355
3356                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3357                         pipelined = NULL;
3358
3359                 old->fence_reg = I915_FENCE_REG_NONE;
3360                 old->last_fenced_ring = pipelined;
3361                 old->last_fenced_seqno =
3362                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3363
3364                 drm_gem_object_unreference(&old->base);
3365         } else if (obj->last_fenced_seqno == 0)
3366                 pipelined = NULL;
3367
3368         reg->obj = obj;
3369         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3370         obj->fence_reg = reg - dev_priv->fence_regs;
3371         obj->last_fenced_ring = pipelined;
3372
3373         reg->setup_seqno =
3374                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3375         obj->last_fenced_seqno = reg->setup_seqno;
3376
3377 update:
3378         obj->tiling_changed = false;
3379         switch (INTEL_INFO(dev)->gen) {
3380         case 7:
3381         case 6:
3382                 ret = sandybridge_write_fence_reg(obj, pipelined);
3383                 break;
3384         case 5:
3385         case 4:
3386                 ret = i965_write_fence_reg(obj, pipelined);
3387                 break;
3388         case 3:
3389                 ret = i915_write_fence_reg(obj, pipelined);
3390                 break;
3391         case 2:
3392                 ret = i830_write_fence_reg(obj, pipelined);
3393                 break;
3394         }
3395
3396         return ret;
3397 }
3398
3399 static void
3400 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3401 {
3402         drm_i915_private_t *dev_priv = dev->dev_private;
3403         uint32_t fence_reg = reg - dev_priv->fence_regs;
3404
3405         switch (INTEL_INFO(dev)->gen) {
3406         case 7:
3407         case 6:
3408                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3409                 break;
3410         case 5:
3411         case 4:
3412                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3413                 break;
3414         case 3:
3415                 if (fence_reg >= 8)
3416                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3417                 else
3418         case 2:
3419                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3420
3421                 I915_WRITE(fence_reg, 0);
3422                 break;
3423         }
3424
3425         list_del_init(&reg->lru_list);
3426         reg->obj = NULL;
3427         reg->setup_seqno = 0;
3428         reg->pin_count = 0;
3429 }
3430
3431 int
3432 i915_gem_init_object(struct drm_gem_object *obj)
3433 {
3434
3435         printf("i915_gem_init_object called\n");
3436         return (0);
3437 }
3438
3439 static bool
3440 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3441 {
3442
3443         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3444 }
3445
3446 static void
3447 i915_gem_retire_task_handler(void *arg, int pending)
3448 {
3449         drm_i915_private_t *dev_priv;
3450         struct drm_device *dev;
3451         bool idle;
3452         int i;
3453
3454         dev_priv = arg;
3455         dev = dev_priv->dev;
3456
3457         /* Come back later if the device is busy... */
3458         if (!sx_try_xlock(&dev->dev_struct_lock)) {
3459                 taskqueue_enqueue_timeout(dev_priv->tq,
3460                     &dev_priv->mm.retire_task, hz);
3461                 return;
3462         }
3463
3464         CTR0(KTR_DRM, "retire_task");
3465
3466         i915_gem_retire_requests(dev);
3467
3468         /* Send a periodic flush down the ring so we don't hold onto GEM
3469          * objects indefinitely.
3470          */
3471         idle = true;
3472         for (i = 0; i < I915_NUM_RINGS; i++) {
3473                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3474
3475                 if (!list_empty(&ring->gpu_write_list)) {
3476                         struct drm_i915_gem_request *request;
3477                         int ret;
3478
3479                         ret = i915_gem_flush_ring(ring,
3480                                                   0, I915_GEM_GPU_DOMAINS);
3481                         request = malloc(sizeof(*request), DRM_I915_GEM,
3482                             M_WAITOK | M_ZERO);
3483                         if (ret || request == NULL ||
3484                             i915_add_request(ring, NULL, request))
3485                                 free(request, DRM_I915_GEM);
3486                 }
3487
3488                 idle &= list_empty(&ring->request_list);
3489         }
3490
3491         if (!dev_priv->mm.suspended && !idle)
3492                 taskqueue_enqueue_timeout(dev_priv->tq,
3493                     &dev_priv->mm.retire_task, hz);
3494
3495         DRM_UNLOCK(dev);
3496 }
3497
3498 void
3499 i915_gem_lastclose(struct drm_device *dev)
3500 {
3501         int ret;
3502
3503         if (drm_core_check_feature(dev, DRIVER_MODESET))
3504                 return;
3505
3506         ret = i915_gem_idle(dev);
3507         if (ret != 0)
3508                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3509 }
3510
3511 static int
3512 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3513 {
3514         drm_i915_private_t *dev_priv;
3515         struct drm_i915_gem_phys_object *phys_obj;
3516         int ret;
3517
3518         dev_priv = dev->dev_private;
3519         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3520                 return (0);
3521
3522         phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3523             M_WAITOK | M_ZERO);
3524
3525         phys_obj->id = id;
3526
3527         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3528         if (phys_obj->handle == NULL) {
3529                 ret = -ENOMEM;
3530                 goto free_obj;
3531         }
3532         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3533             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3534
3535         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3536
3537         return (0);
3538
3539 free_obj:
3540         free(phys_obj, DRM_I915_GEM);
3541         return (ret);
3542 }
3543
3544 static void
3545 i915_gem_free_phys_object(struct drm_device *dev, int id)
3546 {
3547         drm_i915_private_t *dev_priv;
3548         struct drm_i915_gem_phys_object *phys_obj;
3549
3550         dev_priv = dev->dev_private;
3551         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3552                 return;
3553
3554         phys_obj = dev_priv->mm.phys_objs[id - 1];
3555         if (phys_obj->cur_obj != NULL)
3556                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3557
3558         drm_pci_free(dev, phys_obj->handle);
3559         free(phys_obj, DRM_I915_GEM);
3560         dev_priv->mm.phys_objs[id - 1] = NULL;
3561 }
3562
3563 void
3564 i915_gem_free_all_phys_object(struct drm_device *dev)
3565 {
3566         int i;
3567
3568         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3569                 i915_gem_free_phys_object(dev, i);
3570 }
3571
3572 void
3573 i915_gem_detach_phys_object(struct drm_device *dev,
3574     struct drm_i915_gem_object *obj)
3575 {
3576         vm_page_t m;
3577         struct sf_buf *sf;
3578         char *vaddr, *dst;
3579         int i, page_count;
3580
3581         if (obj->phys_obj == NULL)
3582                 return;
3583         vaddr = obj->phys_obj->handle->vaddr;
3584
3585         page_count = obj->base.size / PAGE_SIZE;
3586         VM_OBJECT_LOCK(obj->base.vm_obj);
3587         for (i = 0; i < page_count; i++) {
3588                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3589                 if (m == NULL)
3590                         continue; /* XXX */
3591
3592                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3593                 sf = sf_buf_alloc(m, 0);
3594                 if (sf != NULL) {
3595                         dst = (char *)sf_buf_kva(sf);
3596                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3597                         sf_buf_free(sf);
3598                 }
3599                 drm_clflush_pages(&m, 1);
3600
3601                 VM_OBJECT_LOCK(obj->base.vm_obj);
3602                 vm_page_reference(m);
3603                 vm_page_lock(m);
3604                 vm_page_dirty(m);
3605                 vm_page_unwire(m, 0);
3606                 vm_page_unlock(m);
3607                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3608         }
3609         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3610         intel_gtt_chipset_flush();
3611
3612         obj->phys_obj->cur_obj = NULL;
3613         obj->phys_obj = NULL;
3614 }
3615
3616 int
3617 i915_gem_attach_phys_object(struct drm_device *dev,
3618     struct drm_i915_gem_object *obj, int id, int align)
3619 {
3620         drm_i915_private_t *dev_priv;
3621         vm_page_t m;
3622         struct sf_buf *sf;
3623         char *dst, *src;
3624         int i, page_count, ret;
3625
3626         if (id > I915_MAX_PHYS_OBJECT)
3627                 return (-EINVAL);
3628
3629         if (obj->phys_obj != NULL) {
3630                 if (obj->phys_obj->id == id)
3631                         return (0);
3632                 i915_gem_detach_phys_object(dev, obj);
3633         }
3634
3635         dev_priv = dev->dev_private;
3636         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3637                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3638                 if (ret != 0) {
3639                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3640                                   id, obj->base.size);
3641                         return (ret);
3642                 }
3643         }
3644
3645         /* bind to the object */
3646         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3647         obj->phys_obj->cur_obj = obj;
3648
3649         page_count = obj->base.size / PAGE_SIZE;
3650
3651         VM_OBJECT_LOCK(obj->base.vm_obj);
3652         ret = 0;
3653         for (i = 0; i < page_count; i++) {
3654                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3655                 if (m == NULL) {
3656                         ret = -EIO;
3657                         break;
3658                 }
3659                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3660                 sf = sf_buf_alloc(m, 0);
3661                 src = (char *)sf_buf_kva(sf);
3662                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3663                 memcpy(dst, src, PAGE_SIZE);
3664                 sf_buf_free(sf);
3665
3666                 VM_OBJECT_LOCK(obj->base.vm_obj);
3667
3668                 vm_page_reference(m);
3669                 vm_page_lock(m);
3670                 vm_page_unwire(m, 0);
3671                 vm_page_unlock(m);
3672                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3673         }
3674         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3675
3676         return (0);
3677 }
3678
3679 static int
3680 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3681     uint64_t data_ptr, uint64_t offset, uint64_t size,
3682     struct drm_file *file_priv)
3683 {
3684         char *user_data, *vaddr;
3685         int ret;
3686
3687         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3688         user_data = (char *)(uintptr_t)data_ptr;
3689
3690         if (copyin_nofault(user_data, vaddr, size) != 0) {
3691                 /* The physical object once assigned is fixed for the lifetime
3692                  * of the obj, so we can safely drop the lock and continue
3693                  * to access vaddr.
3694                  */
3695                 DRM_UNLOCK(dev);
3696                 ret = -copyin(user_data, vaddr, size);
3697                 DRM_LOCK(dev);
3698                 if (ret != 0)
3699                         return (ret);
3700         }
3701
3702         intel_gtt_chipset_flush();
3703         return (0);
3704 }
3705
3706 static int
3707 i915_gpu_is_active(struct drm_device *dev)
3708 {
3709         drm_i915_private_t *dev_priv;
3710
3711         dev_priv = dev->dev_private;
3712         return (!list_empty(&dev_priv->mm.flushing_list) ||
3713             !list_empty(&dev_priv->mm.active_list));
3714 }
3715
3716 static void
3717 i915_gem_lowmem(void *arg)
3718 {
3719         struct drm_device *dev;
3720         struct drm_i915_private *dev_priv;
3721         struct drm_i915_gem_object *obj, *next;
3722         int cnt, cnt_fail, cnt_total;
3723
3724         dev = arg;
3725         dev_priv = dev->dev_private;
3726
3727         if (!sx_try_xlock(&dev->dev_struct_lock))
3728                 return;
3729
3730         CTR0(KTR_DRM, "gem_lowmem");
3731
3732 rescan:
3733         /* first scan for clean buffers */
3734         i915_gem_retire_requests(dev);
3735
3736         cnt_total = cnt_fail = cnt = 0;
3737
3738         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3739             mm_list) {
3740                 if (i915_gem_object_is_purgeable(obj)) {
3741                         if (i915_gem_object_unbind(obj) != 0)
3742                                 cnt_total++;
3743                 } else
3744                         cnt_total++;
3745         }
3746
3747         /* second pass, evict/count anything still on the inactive list */
3748         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3749             mm_list) {
3750                 if (i915_gem_object_unbind(obj) == 0)
3751                         cnt++;
3752                 else
3753                         cnt_fail++;
3754         }
3755
3756         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3757                 /*
3758                  * We are desperate for pages, so as a last resort, wait
3759                  * for the GPU to finish and discard whatever we can.
3760                  * This has a dramatic impact to reduce the number of
3761                  * OOM-killer events whilst running the GPU aggressively.
3762                  */
3763                 if (i915_gpu_idle(dev, true) == 0)
3764                         goto rescan;
3765         }
3766         DRM_UNLOCK(dev);
3767 }
3768
3769 void
3770 i915_gem_unload(struct drm_device *dev)
3771 {
3772         struct drm_i915_private *dev_priv;
3773
3774         dev_priv = dev->dev_private;
3775         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3776 }