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32 ******************************************************************************/
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value);
67 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
68 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
69 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
70 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
71 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
72 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
73 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
74 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
76 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
77 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
80 * e1000_init_phy_params_82543 - Init PHY func ptrs.
81 * @hw: pointer to the HW structure
83 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
85 struct e1000_phy_info *phy = &hw->phy;
86 s32 ret_val = E1000_SUCCESS;
88 DEBUGFUNC("e1000_init_phy_params_82543");
90 if (hw->phy.media_type != e1000_media_type_copper) {
91 phy->type = e1000_phy_none;
94 phy->ops.power_up = e1000_power_up_phy_copper;
95 phy->ops.power_down = e1000_power_down_phy_copper;
99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
100 phy->reset_delay_us = 10000;
101 phy->type = e1000_phy_m88;
103 /* Function Pointers */
104 phy->ops.check_polarity = e1000_check_polarity_m88;
105 phy->ops.commit = e1000_phy_sw_reset_generic;
106 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
107 phy->ops.get_cable_length = e1000_get_cable_length_m88;
108 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
109 phy->ops.read_reg = (hw->mac.type == e1000_82543)
110 ? e1000_read_phy_reg_82543
111 : e1000_read_phy_reg_m88;
112 phy->ops.reset = (hw->mac.type == e1000_82543)
113 ? e1000_phy_hw_reset_82543
114 : e1000_phy_hw_reset_generic;
115 phy->ops.write_reg = (hw->mac.type == e1000_82543)
116 ? e1000_write_phy_reg_82543
117 : e1000_write_phy_reg_m88;
118 phy->ops.get_info = e1000_get_phy_info_m88;
121 * The external PHY of the 82543 can be in a funky state.
122 * Resetting helps us read the PHY registers for acquiring
125 if (!e1000_init_phy_disabled_82543(hw)) {
126 ret_val = phy->ops.reset(hw);
128 DEBUGOUT("Resetting PHY during init failed.\n");
134 ret_val = e1000_get_phy_id(hw);
139 switch (hw->mac.type) {
141 if (phy->id != M88E1000_E_PHY_ID) {
142 ret_val = -E1000_ERR_PHY;
147 if (phy->id != M88E1000_I_PHY_ID) {
148 ret_val = -E1000_ERR_PHY;
153 ret_val = -E1000_ERR_PHY;
163 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
164 * @hw: pointer to the HW structure
166 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
168 struct e1000_nvm_info *nvm = &hw->nvm;
170 DEBUGFUNC("e1000_init_nvm_params_82543");
172 nvm->type = e1000_nvm_eeprom_microwire;
174 nvm->delay_usec = 50;
175 nvm->address_bits = 6;
176 nvm->opcode_bits = 3;
178 /* Function Pointers */
179 nvm->ops.read = e1000_read_nvm_microwire;
180 nvm->ops.update = e1000_update_nvm_checksum_generic;
181 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
182 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
183 nvm->ops.write = e1000_write_nvm_microwire;
185 return E1000_SUCCESS;
189 * e1000_init_mac_params_82543 - Init MAC func ptrs.
190 * @hw: pointer to the HW structure
192 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
194 struct e1000_mac_info *mac = &hw->mac;
196 DEBUGFUNC("e1000_init_mac_params_82543");
199 switch (hw->device_id) {
200 case E1000_DEV_ID_82543GC_FIBER:
201 case E1000_DEV_ID_82544EI_FIBER:
202 hw->phy.media_type = e1000_media_type_fiber;
205 hw->phy.media_type = e1000_media_type_copper;
209 /* Set mta register count */
210 mac->mta_reg_count = 128;
211 /* Set rar entry count */
212 mac->rar_entry_count = E1000_RAR_ENTRIES;
214 /* Function pointers */
216 /* bus type/speed/width */
217 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
219 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
221 mac->ops.reset_hw = e1000_reset_hw_82543;
222 /* hw initialization */
223 mac->ops.init_hw = e1000_init_hw_82543;
225 mac->ops.setup_link = e1000_setup_link_82543;
226 /* physical interface setup */
227 mac->ops.setup_physical_interface =
228 (hw->phy.media_type == e1000_media_type_copper)
229 ? e1000_setup_copper_link_82543
230 : e1000_setup_fiber_link_82543;
232 mac->ops.check_for_link =
233 (hw->phy.media_type == e1000_media_type_copper)
234 ? e1000_check_for_copper_link_82543
235 : e1000_check_for_fiber_link_82543;
237 mac->ops.get_link_up_info =
238 (hw->phy.media_type == e1000_media_type_copper)
239 ? e1000_get_speed_and_duplex_copper_generic
240 : e1000_get_speed_and_duplex_fiber_serdes_generic;
241 /* multicast address update */
242 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
244 mac->ops.write_vfta = e1000_write_vfta_82543;
246 mac->ops.clear_vfta = e1000_clear_vfta_generic;
248 mac->ops.mta_set = e1000_mta_set_82543;
249 /* turn on/off LED */
250 mac->ops.led_on = e1000_led_on_82543;
251 mac->ops.led_off = e1000_led_off_82543;
252 /* clear hardware counters */
253 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
255 /* Set tbi compatibility */
256 if ((hw->mac.type != e1000_82543) ||
257 (hw->phy.media_type == e1000_media_type_fiber))
258 e1000_set_tbi_compatibility_82543(hw, FALSE);
260 return E1000_SUCCESS;
264 * e1000_init_function_pointers_82543 - Init func ptrs.
265 * @hw: pointer to the HW structure
267 * Called to initialize all function pointers and parameters.
269 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
271 DEBUGFUNC("e1000_init_function_pointers_82543");
273 hw->mac.ops.init_params = e1000_init_mac_params_82543;
274 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
275 hw->phy.ops.init_params = e1000_init_phy_params_82543;
279 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
280 * @hw: pointer to the HW structure
282 * Returns the current status of 10-bit Interface (TBI) compatibility
283 * (enabled/disabled).
285 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
287 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
290 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
292 if (hw->mac.type != e1000_82543) {
293 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
297 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
305 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
306 * @hw: pointer to the HW structure
307 * @state: enable/disable TBI compatibility
309 * Enables or disabled 10-bit Interface (TBI) compatibility.
311 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
313 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
315 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
317 if (hw->mac.type != e1000_82543) {
318 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
323 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
325 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
332 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
333 * @hw: pointer to the HW structure
335 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
336 * (enabled/disabled).
338 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
340 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
343 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
345 if (hw->mac.type != e1000_82543) {
346 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
350 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
358 * e1000_set_tbi_sbp_82543 - Set TBI SBP
359 * @hw: pointer to the HW structure
360 * @state: enable/disable TBI store bad packet
362 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
364 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
366 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
368 DEBUGFUNC("e1000_set_tbi_sbp_82543");
370 if (state && e1000_tbi_compatibility_enabled_82543(hw))
371 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
373 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
379 * e1000_init_phy_disabled_82543 - Returns init PHY status
380 * @hw: pointer to the HW structure
382 * Returns the current status of whether PHY initialization is disabled.
383 * True if PHY initialization is disabled else FALSE.
385 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
387 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
390 DEBUGFUNC("e1000_init_phy_disabled_82543");
392 if (hw->mac.type != e1000_82543) {
397 ret_val = dev_spec->init_phy_disabled;
404 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
405 * @hw: pointer to the HW structure
406 * @stats: Struct containing statistic register values
407 * @frame_len: The length of the frame in question
408 * @mac_addr: The Ethernet destination address of the frame in question
409 * @max_frame_size: The maximum frame size
411 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
413 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
414 struct e1000_hw_stats *stats, u32 frame_len,
415 u8 *mac_addr, u32 max_frame_size)
417 if (!(e1000_tbi_sbp_enabled_82543(hw)))
420 /* First adjust the frame length. */
423 * We need to adjust the statistics counters, since the hardware
424 * counters overcount this packet as a CRC error and undercount
425 * the packet as a good packet
427 /* This packet should not be counted as a CRC error. */
429 /* This packet does count as a Good Packet Received. */
432 /* Adjust the Good Octets received counters */
433 stats->gorc += frame_len;
436 * Is this a broadcast or multicast? Check broadcast first,
437 * since the test for a multicast frame will test positive on
440 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
441 /* Broadcast packet */
443 else if (*mac_addr & 0x01)
444 /* Multicast packet */
448 * In this case, the hardware has overcounted the number of
451 if ((frame_len == max_frame_size) && (stats->roc > 0))
455 * Adjust the bin counters when the extra byte put the frame in the
456 * wrong bin. Remember that the frame_len was adjusted above.
458 if (frame_len == 64) {
461 } else if (frame_len == 127) {
464 } else if (frame_len == 255) {
467 } else if (frame_len == 511) {
470 } else if (frame_len == 1023) {
473 } else if (frame_len == 1522) {
482 * e1000_read_phy_reg_82543 - Read PHY register
483 * @hw: pointer to the HW structure
484 * @offset: register offset to be read
485 * @data: pointer to the read data
487 * Reads the PHY at offset and stores the information read to data.
489 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
492 s32 ret_val = E1000_SUCCESS;
494 DEBUGFUNC("e1000_read_phy_reg_82543");
496 if (offset > MAX_PHY_REG_ADDRESS) {
497 DEBUGOUT1("PHY Address %d is out of range\n", offset);
498 ret_val = -E1000_ERR_PARAM;
503 * We must first send a preamble through the MDIO pin to signal the
504 * beginning of an MII instruction. This is done by sending 32
505 * consecutive "1" bits.
507 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
510 * Now combine the next few fields that are required for a read
511 * operation. We use this method instead of calling the
512 * e1000_shift_out_mdi_bits routine five different times. The format
513 * of an MII read instruction consists of a shift out of 14 bits and
514 * is defined as follows:
515 * <Preamble><SOF><Op Code><Phy Addr><Offset>
516 * followed by a shift in of 18 bits. This first two bits shifted in
517 * are TurnAround bits used to avoid contention on the MDIO pin when a
518 * READ operation is performed. These two bits are thrown away
519 * followed by a shift in of 16 bits which contains the desired data.
521 mdic = (offset | (hw->phy.addr << 5) |
522 (PHY_OP_READ << 10) | (PHY_SOF << 12));
524 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
527 * Now that we've shifted out the read command to the MII, we need to
528 * "shift in" the 16-bit value (18 total bits) of the requested PHY
531 *data = e1000_shift_in_mdi_bits_82543(hw);
538 * e1000_write_phy_reg_82543 - Write PHY register
539 * @hw: pointer to the HW structure
540 * @offset: register offset to be written
541 * @data: pointer to the data to be written at offset
543 * Writes data to the PHY at offset.
545 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
548 s32 ret_val = E1000_SUCCESS;
550 DEBUGFUNC("e1000_write_phy_reg_82543");
552 if (offset > MAX_PHY_REG_ADDRESS) {
553 DEBUGOUT1("PHY Address %d is out of range\n", offset);
554 ret_val = -E1000_ERR_PARAM;
559 * We'll need to use the SW defined pins to shift the write command
560 * out to the PHY. We first send a preamble to the PHY to signal the
561 * beginning of the MII instruction. This is done by sending 32
562 * consecutive "1" bits.
564 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
567 * Now combine the remaining required fields that will indicate a
568 * write operation. We use this method instead of calling the
569 * e1000_shift_out_mdi_bits routine for each field in the command. The
570 * format of a MII write instruction is as follows:
571 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
573 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
574 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
578 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
585 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
586 * @hw: pointer to the HW structure
587 * @ctrl: pointer to the control register
589 * Raise the management data input clock by setting the MDC bit in the control
592 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
595 * Raise the clock input to the Management Data Clock (by setting the
596 * MDC bit), and then delay a sufficient amount of time.
598 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
599 E1000_WRITE_FLUSH(hw);
604 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
605 * @hw: pointer to the HW structure
606 * @ctrl: pointer to the control register
608 * Lower the management data input clock by clearing the MDC bit in the
611 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
614 * Lower the clock input to the Management Data Clock (by clearing the
615 * MDC bit), and then delay a sufficient amount of time.
617 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
618 E1000_WRITE_FLUSH(hw);
623 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
624 * @hw: pointer to the HW structure
625 * @data: data to send to the PHY
626 * @count: number of bits to shift out
628 * We need to shift 'count' bits out to the PHY. So, the value in the
629 * "data" parameter will be shifted out to the PHY one bit at a time.
630 * In order to do this, "data" must be broken down into bits.
632 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
638 * We need to shift "count" number of bits out to the PHY. So, the
639 * value in the "data" parameter will be shifted out to the PHY one
640 * bit at a time. In order to do this, "data" must be broken down
646 ctrl = E1000_READ_REG(hw, E1000_CTRL);
648 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
649 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
653 * A "1" is shifted out to the PHY by setting the MDIO bit to
654 * "1" and then raising and lowering the Management Data Clock.
655 * A "0" is shifted out to the PHY by setting the MDIO bit to
656 * "0" and then raising and lowering the clock.
658 if (data & mask) ctrl |= E1000_CTRL_MDIO;
659 else ctrl &= ~E1000_CTRL_MDIO;
661 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
662 E1000_WRITE_FLUSH(hw);
666 e1000_raise_mdi_clk_82543(hw, &ctrl);
667 e1000_lower_mdi_clk_82543(hw, &ctrl);
674 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
675 * @hw: pointer to the HW structure
677 * In order to read a register from the PHY, we need to shift 18 bits
678 * in from the PHY. Bits are "shifted in" by raising the clock input to
679 * the PHY (setting the MDC bit), and then reading the value of the data out
682 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
689 * In order to read a register from the PHY, we need to shift in a
690 * total of 18 bits from the PHY. The first two bit (turnaround)
691 * times are used to avoid contention on the MDIO pin when a read
692 * operation is performed. These two bits are ignored by us and
693 * thrown away. Bits are "shifted in" by raising the input to the
694 * Management Data Clock (setting the MDC bit) and then reading the
695 * value of the MDIO bit.
697 ctrl = E1000_READ_REG(hw, E1000_CTRL);
700 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
703 ctrl &= ~E1000_CTRL_MDIO_DIR;
704 ctrl &= ~E1000_CTRL_MDIO;
706 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
707 E1000_WRITE_FLUSH(hw);
710 * Raise and lower the clock before reading in the data. This accounts
711 * for the turnaround bits. The first clock occurred when we clocked
712 * out the last bit of the Register Address.
714 e1000_raise_mdi_clk_82543(hw, &ctrl);
715 e1000_lower_mdi_clk_82543(hw, &ctrl);
717 for (data = 0, i = 0; i < 16; i++) {
719 e1000_raise_mdi_clk_82543(hw, &ctrl);
720 ctrl = E1000_READ_REG(hw, E1000_CTRL);
721 /* Check to see if we shifted in a "1". */
722 if (ctrl & E1000_CTRL_MDIO)
724 e1000_lower_mdi_clk_82543(hw, &ctrl);
727 e1000_raise_mdi_clk_82543(hw, &ctrl);
728 e1000_lower_mdi_clk_82543(hw, &ctrl);
734 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
735 * @hw: pointer to the HW structure
737 * Calls the function to force speed and duplex for the m88 PHY, and
738 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
739 * then call the function for polarity reversal workaround.
741 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
745 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
747 ret_val = e1000_phy_force_speed_duplex_m88(hw);
751 if (!hw->mac.autoneg &&
752 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
753 ret_val = e1000_polarity_reversal_workaround_82543(hw);
760 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
761 * @hw: pointer to the HW structure
763 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
764 * inadvertently. To workaround the issue, we disable the transmitter on
765 * the PHY until we have established the link partner's link parameters.
767 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
769 s32 ret_val = E1000_SUCCESS;
774 if (!(hw->phy.ops.write_reg))
777 /* Polarity reversal workaround for forced 10F/10H links. */
779 /* Disable the transmitter on the PHY */
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
793 * This loop will early-out if the NO link condition has been met.
794 * In other words, DO NOT use e1000_phy_has_link_generic() here.
796 for (i = PHY_FORCE_TIME; i > 0; i--) {
798 * Read the MII Status Register and wait for Link Status bit
802 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
806 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
810 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
815 /* Recommended delay time after link has been lost */
816 msec_delay_irq(1000);
818 /* Now we will re-enable the transmitter on the PHY */
820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
841 * Read the MII Status Register and wait for Link Status bit
844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
853 * e1000_phy_hw_reset_82543 - PHY hardware reset
854 * @hw: pointer to the HW structure
856 * Sets the PHY_RESET_DIR bit in the extended device control register
857 * to put the PHY into a reset and waits for completion. Once the reset
858 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
861 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
866 DEBUGFUNC("e1000_phy_hw_reset_82543");
869 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
870 * bit to put the PHY into reset...
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
873 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
874 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
880 /* ...then take it out of reset. */
881 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
883 E1000_WRITE_FLUSH(hw);
887 if (!(hw->phy.ops.get_cfg_done))
888 return E1000_SUCCESS;
890 ret_val = hw->phy.ops.get_cfg_done(hw);
896 * e1000_reset_hw_82543 - Reset hardware
897 * @hw: pointer to the HW structure
899 * This resets the hardware into a known state.
901 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
904 s32 ret_val = E1000_SUCCESS;
906 DEBUGFUNC("e1000_reset_hw_82543");
908 DEBUGOUT("Masking off all interrupts\n");
909 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911 E1000_WRITE_REG(hw, E1000_RCTL, 0);
912 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
913 E1000_WRITE_FLUSH(hw);
915 e1000_set_tbi_sbp_82543(hw, FALSE);
918 * Delay to allow any outstanding PCI transactions to complete before
919 * resetting the device
923 ctrl = E1000_READ_REG(hw, E1000_CTRL);
925 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
926 if (hw->mac.type == e1000_82543) {
927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
930 * The 82544 can't ACK the 64-bit write when issuing the
931 * reset, so use IO-mapping as a workaround.
933 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
937 * After MAC reset, force reload of NVM to restore power-on
938 * settings to device.
940 hw->nvm.ops.reload(hw);
943 /* Masking off and clearing any pending interrupts */
944 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
945 icr = E1000_READ_REG(hw, E1000_ICR);
951 * e1000_init_hw_82543 - Initialize hardware
952 * @hw: pointer to the HW structure
954 * This inits the hardware readying it for operation.
956 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
958 struct e1000_mac_info *mac = &hw->mac;
959 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
964 DEBUGFUNC("e1000_init_hw_82543");
966 /* Disabling VLAN filtering */
967 E1000_WRITE_REG(hw, E1000_VET, 0);
968 mac->ops.clear_vfta(hw);
970 /* Setup the receive address. */
971 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
973 /* Zero out the Multicast HASH table */
974 DEBUGOUT("Zeroing the MTA\n");
975 for (i = 0; i < mac->mta_reg_count; i++) {
976 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
977 E1000_WRITE_FLUSH(hw);
981 * Set the PCI priority bit correctly in the CTRL register. This
982 * determines if the adapter gives priority to receives, or if it
983 * gives equal priority to transmits and receives.
985 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
986 ctrl = E1000_READ_REG(hw, E1000_CTRL);
987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
990 e1000_pcix_mmrbc_workaround_generic(hw);
992 /* Setup link and flow control */
993 ret_val = mac->ops.setup_link(hw);
996 * Clear all of the statistics registers (clear on read). It is
997 * important that we do this after we have tried to establish link
998 * because the symbol error count will increment wildly if there
1001 e1000_clear_hw_cntrs_82543(hw);
1007 * e1000_setup_link_82543 - Setup flow control and link settings
1008 * @hw: pointer to the HW structure
1010 * Read the EEPROM to determine the initial polarity value and write the
1011 * extended device control register with the information before calling
1012 * the generic setup link function, which does the following:
1013 * Determines which flow control settings to use, then configures flow
1014 * control. Calls the appropriate media-specific link configuration
1015 * function. Assuming the adapter has a valid link partner, a valid link
1016 * should be established. Assumes the hardware has previously been reset
1017 * and the transmitter and receiver are not enabled.
1019 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1025 DEBUGFUNC("e1000_setup_link_82543");
1028 * Take the 4 bits from NVM word 0xF that determine the initial
1029 * polarity value for the SW controlled pins, and setup the
1030 * Extended Device Control reg with that info.
1031 * This is needed because one of the SW controlled pins is used for
1032 * signal detection. So this should be done before phy setup.
1034 if (hw->mac.type == e1000_82543) {
1035 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1037 DEBUGOUT("NVM Read Error\n");
1038 ret_val = -E1000_ERR_NVM;
1041 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1042 NVM_SWDPIO_EXT_SHIFT);
1043 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1046 ret_val = e1000_setup_link_generic(hw);
1053 * e1000_setup_copper_link_82543 - Configure copper link settings
1054 * @hw: pointer to the HW structure
1056 * Configures the link for auto-neg or forced speed and duplex. Then we check
1057 * for link, once link is established calls to configure collision distance
1058 * and flow control are called.
1060 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1066 DEBUGFUNC("e1000_setup_copper_link_82543");
1068 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1070 * With 82543, we need to force speed and duplex on the MAC
1071 * equal to what the PHY speed and duplex configuration is.
1072 * In addition, we need to perform a hardware reset on the
1073 * PHY to take it out of reset.
1075 if (hw->mac.type == e1000_82543) {
1076 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1078 ret_val = hw->phy.ops.reset(hw);
1081 hw->phy.reset_disable = FALSE;
1083 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1087 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1088 ret_val = e1000_copper_link_setup_m88(hw);
1092 if (hw->mac.autoneg) {
1094 * Setup autoneg and flow control advertisement and perform
1097 ret_val = e1000_copper_link_autoneg(hw);
1102 * PHY will be set to 10H, 10F, 100H or 100F
1103 * depending on user settings.
1105 DEBUGOUT("Forcing Speed and Duplex\n");
1106 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1108 DEBUGOUT("Error Forcing Speed and Duplex\n");
1114 * Check link status. Wait up to 100 microseconds for link to become
1117 ret_val = e1000_phy_has_link_generic(hw,
1118 COPPER_LINK_UP_LIMIT,
1126 DEBUGOUT("Valid link established!!!\n");
1127 /* Config the MAC and PHY after link is up */
1128 if (hw->mac.type == e1000_82544) {
1129 e1000_config_collision_dist_generic(hw);
1131 ret_val = e1000_config_mac_to_phy_82543(hw);
1135 ret_val = e1000_config_fc_after_link_up_generic(hw);
1137 DEBUGOUT("Unable to establish link!!!\n");
1145 * e1000_setup_fiber_link_82543 - Setup link for fiber
1146 * @hw: pointer to the HW structure
1148 * Configures collision distance and flow control for fiber links. Upon
1149 * successful setup, poll for link.
1151 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1156 DEBUGFUNC("e1000_setup_fiber_link_82543");
1158 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1160 /* Take the link out of reset */
1161 ctrl &= ~E1000_CTRL_LRST;
1163 e1000_config_collision_dist_generic(hw);
1165 ret_val = e1000_commit_fc_settings_generic(hw);
1169 DEBUGOUT("Auto-negotiation enabled\n");
1171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1172 E1000_WRITE_FLUSH(hw);
1176 * For these adapters, the SW definable pin 1 is cleared when the
1177 * optics detect a signal. If we have a signal, then poll for a
1178 * "Link-Up" indication.
1180 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1181 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1183 DEBUGOUT("No signal detected\n");
1191 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1192 * @hw: pointer to the HW structure
1194 * Checks the phy for link, if link exists, do the following:
1195 * - check for downshift
1196 * - do polarity workaround (if necessary)
1197 * - configure collision distance
1198 * - configure flow control after link up
1199 * - configure tbi compatibility
1201 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1203 struct e1000_mac_info *mac = &hw->mac;
1209 DEBUGFUNC("e1000_check_for_copper_link_82543");
1211 if (!mac->get_link_status) {
1212 ret_val = E1000_SUCCESS;
1216 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1221 goto out; /* No link detected */
1223 mac->get_link_status = FALSE;
1225 e1000_check_downshift_generic(hw);
1228 * If we are forcing speed/duplex, then we can return since
1229 * we have already determined whether we have link or not.
1231 if (!mac->autoneg) {
1233 * If speed and duplex are forced to 10H or 10F, then we will
1234 * implement the polarity reversal workaround. We disable
1235 * interrupts first, and upon returning, place the devices
1236 * interrupt state to its previous value except for the link
1237 * status change interrupt which will happened due to the
1238 * execution of this workaround.
1240 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1241 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1242 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1243 icr = E1000_READ_REG(hw, E1000_ICR);
1244 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1245 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1248 ret_val = -E1000_ERR_CONFIG;
1253 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1254 * have Si on board that is 82544 or newer, Auto
1255 * Speed Detection takes care of MAC speed/duplex
1256 * configuration. So we only need to configure Collision
1257 * Distance in the MAC. Otherwise, we need to force
1258 * speed/duplex on the MAC to the current PHY speed/duplex
1261 if (mac->type == e1000_82544)
1262 e1000_config_collision_dist_generic(hw);
1264 ret_val = e1000_config_mac_to_phy_82543(hw);
1266 DEBUGOUT("Error configuring MAC to PHY settings\n");
1272 * Configure Flow Control now that Auto-Neg has completed.
1273 * First, we need to restore the desired flow control
1274 * settings because we may have had to re-autoneg with a
1275 * different link partner.
1277 ret_val = e1000_config_fc_after_link_up_generic(hw);
1279 DEBUGOUT("Error configuring flow control\n");
1283 * At this point we know that we are on copper and we have
1284 * auto-negotiated link. These are conditions for checking the link
1285 * partner capability register. We use the link speed to determine if
1286 * TBI compatibility needs to be turned on or off. If the link is not
1287 * at gigabit speed, then TBI compatibility is not needed. If we are
1288 * at gigabit speed, we turn on TBI compatibility.
1290 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1291 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1293 DEBUGOUT("Error getting link speed and duplex\n");
1296 if (speed != SPEED_1000) {
1298 * If link speed is not set to gigabit speed,
1299 * we do not need to enable TBI compatibility.
1301 if (e1000_tbi_sbp_enabled_82543(hw)) {
1303 * If we previously were in the mode,
1306 e1000_set_tbi_sbp_82543(hw, FALSE);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1308 rctl &= ~E1000_RCTL_SBP;
1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313 * If TBI compatibility is was previously off,
1314 * turn it on. For compatibility with a TBI link
1315 * partner, we will store bad packets. Some
1316 * frames have an additional byte on the end and
1317 * will look like CRC errors to to the hardware.
1319 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1320 e1000_set_tbi_sbp_82543(hw, TRUE);
1321 rctl = E1000_READ_REG(hw, E1000_RCTL);
1322 rctl |= E1000_RCTL_SBP;
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1332 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1333 * @hw: pointer to the HW structure
1335 * Checks for link up on the hardware. If link is not up and we have
1336 * a signal, then we need to force link up.
1338 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1340 struct e1000_mac_info *mac = &hw->mac;
1341 u32 rxcw, ctrl, status;
1342 s32 ret_val = E1000_SUCCESS;
1344 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1346 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1347 status = E1000_READ_REG(hw, E1000_STATUS);
1348 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1351 * If we don't have link (auto-negotiation failed or link partner
1352 * cannot auto-negotiate), the cable is plugged in (we have signal),
1353 * and our link partner is not trying to auto-negotiate with us (we
1354 * are receiving idles or data), we need to force link up. We also
1355 * need to give auto-negotiation time to complete, in case the cable
1356 * was just plugged in. The autoneg_failed flag does this.
1358 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1359 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1360 (!(status & E1000_STATUS_LU)) &&
1361 (!(rxcw & E1000_RXCW_C))) {
1362 if (mac->autoneg_failed == 0) {
1363 mac->autoneg_failed = 1;
1367 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1369 /* Disable auto-negotiation in the TXCW register */
1370 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1372 /* Force link-up and also force full-duplex. */
1373 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1374 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1375 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1377 /* Configure Flow Control after forcing link up. */
1378 ret_val = e1000_config_fc_after_link_up_generic(hw);
1380 DEBUGOUT("Error configuring flow control\n");
1383 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1385 * If we are forcing link and we are receiving /C/ ordered
1386 * sets, re-enable auto-negotiation in the TXCW register
1387 * and disable forced link in the Device Control register
1388 * in an attempt to auto-negotiate with our link partner.
1390 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1391 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1392 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1394 mac->serdes_has_link = TRUE;
1402 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1403 * @hw: pointer to the HW structure
1405 * For the 82543 silicon, we need to set the MAC to match the settings
1406 * of the PHY, even if the PHY is auto-negotiating.
1408 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1411 s32 ret_val = E1000_SUCCESS;
1414 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1416 if (!(hw->phy.ops.read_reg))
1419 /* Set the bits to force speed and duplex */
1420 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1421 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1422 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1425 * Set up duplex in the Device Control and Transmit Control
1426 * registers depending on negotiated values.
1428 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1432 ctrl &= ~E1000_CTRL_FD;
1433 if (phy_data & M88E1000_PSSR_DPLX)
1434 ctrl |= E1000_CTRL_FD;
1436 e1000_config_collision_dist_generic(hw);
1439 * Set up speed in the Device Control register depending on
1440 * negotiated values.
1442 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1443 ctrl |= E1000_CTRL_SPD_1000;
1444 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1445 ctrl |= E1000_CTRL_SPD_100;
1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1454 * e1000_write_vfta_82543 - Write value to VLAN filter table
1455 * @hw: pointer to the HW structure
1456 * @offset: the 32-bit offset in which to write the value to.
1457 * @value: the 32-bit value to write at location offset.
1459 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1462 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1466 DEBUGFUNC("e1000_write_vfta_82543");
1468 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1469 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1470 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1471 E1000_WRITE_FLUSH(hw);
1472 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1473 E1000_WRITE_FLUSH(hw);
1475 e1000_write_vfta_generic(hw, offset, value);
1480 * e1000_mta_set_82543 - Set multicast filter table address
1481 * @hw: pointer to the HW structure
1482 * @hash_value: determines the MTA register and bit to set
1484 * The multicast table address is a register array of 32-bit registers.
1485 * The hash_value is used to determine what register the bit is in, the
1486 * current value is read, the new bit is OR'd in and the new value is
1487 * written back into the register.
1489 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value)
1491 u32 hash_bit, hash_reg, mta, temp;
1493 DEBUGFUNC("e1000_mta_set_82543");
1495 hash_reg = (hash_value >> 5);
1498 * If we are on an 82544 and we are trying to write an odd offset
1499 * in the MTA, save off the previous entry before writing and
1500 * restore the old value after writing.
1502 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) {
1503 hash_reg &= (hw->mac.mta_reg_count - 1);
1504 hash_bit = hash_value & 0x1F;
1505 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
1506 mta |= (1 << hash_bit);
1507 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1);
1509 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
1510 E1000_WRITE_FLUSH(hw);
1511 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp);
1512 E1000_WRITE_FLUSH(hw);
1514 e1000_mta_set_generic(hw, hash_value);
1519 * e1000_led_on_82543 - Turn on SW controllable LED
1520 * @hw: pointer to the HW structure
1522 * Turns the SW defined LED on.
1524 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1526 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1528 DEBUGFUNC("e1000_led_on_82543");
1530 if (hw->mac.type == e1000_82544 &&
1531 hw->phy.media_type == e1000_media_type_copper) {
1532 /* Clear SW-definable Pin 0 to turn on the LED */
1533 ctrl &= ~E1000_CTRL_SWDPIN0;
1534 ctrl |= E1000_CTRL_SWDPIO0;
1536 /* Fiber 82544 and all 82543 use this method */
1537 ctrl |= E1000_CTRL_SWDPIN0;
1538 ctrl |= E1000_CTRL_SWDPIO0;
1540 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1542 return E1000_SUCCESS;
1546 * e1000_led_off_82543 - Turn off SW controllable LED
1547 * @hw: pointer to the HW structure
1549 * Turns the SW defined LED off.
1551 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1553 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1555 DEBUGFUNC("e1000_led_off_82543");
1557 if (hw->mac.type == e1000_82544 &&
1558 hw->phy.media_type == e1000_media_type_copper) {
1559 /* Set SW-definable Pin 0 to turn off the LED */
1560 ctrl |= E1000_CTRL_SWDPIN0;
1561 ctrl |= E1000_CTRL_SWDPIO0;
1563 ctrl &= ~E1000_CTRL_SWDPIN0;
1564 ctrl |= E1000_CTRL_SWDPIO0;
1566 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1568 return E1000_SUCCESS;
1572 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1573 * @hw: pointer to the HW structure
1575 * Clears the hardware counters by reading the counter registers.
1577 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1579 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1581 e1000_clear_hw_cntrs_base_generic(hw);
1583 E1000_READ_REG(hw, E1000_PRC64);
1584 E1000_READ_REG(hw, E1000_PRC127);
1585 E1000_READ_REG(hw, E1000_PRC255);
1586 E1000_READ_REG(hw, E1000_PRC511);
1587 E1000_READ_REG(hw, E1000_PRC1023);
1588 E1000_READ_REG(hw, E1000_PRC1522);
1589 E1000_READ_REG(hw, E1000_PTC64);
1590 E1000_READ_REG(hw, E1000_PTC127);
1591 E1000_READ_REG(hw, E1000_PTC255);
1592 E1000_READ_REG(hw, E1000_PTC511);
1593 E1000_READ_REG(hw, E1000_PTC1023);
1594 E1000_READ_REG(hw, E1000_PTC1522);
1596 E1000_READ_REG(hw, E1000_ALGNERRC);
1597 E1000_READ_REG(hw, E1000_RXERRC);
1598 E1000_READ_REG(hw, E1000_TNCRS);
1599 E1000_READ_REG(hw, E1000_CEXTERR);
1600 E1000_READ_REG(hw, E1000_TSCTC);
1601 E1000_READ_REG(hw, E1000_TSCTFC);