1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
40 * e1000_init_mac_ops_generic - Initialize MAC function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
47 struct e1000_mac_info *mac = &hw->mac;
48 DEBUGFUNC("e1000_init_mac_ops_generic");
51 mac->ops.init_params = e1000_null_ops_generic;
52 mac->ops.init_hw = e1000_null_ops_generic;
53 mac->ops.reset_hw = e1000_null_ops_generic;
54 mac->ops.setup_physical_interface = e1000_null_ops_generic;
55 mac->ops.get_bus_info = e1000_null_ops_generic;
56 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
57 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
58 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
59 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
61 mac->ops.cleanup_led = e1000_null_ops_generic;
62 mac->ops.setup_led = e1000_null_ops_generic;
63 mac->ops.blink_led = e1000_null_ops_generic;
64 mac->ops.led_on = e1000_null_ops_generic;
65 mac->ops.led_off = e1000_null_ops_generic;
67 mac->ops.setup_link = e1000_null_ops_generic;
68 mac->ops.get_link_up_info = e1000_null_link_info;
69 mac->ops.check_for_link = e1000_null_ops_generic;
70 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
72 mac->ops.check_mng_mode = e1000_null_mng_mode;
73 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
74 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
75 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
77 mac->ops.update_mc_addr_list = e1000_null_update_mc;
78 mac->ops.clear_vfta = e1000_null_mac_generic;
79 mac->ops.write_vfta = e1000_null_write_vfta;
80 mac->ops.mta_set = e1000_null_mta_set;
81 mac->ops.rar_set = e1000_rar_set_generic;
82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
86 * e1000_null_ops_generic - No-op function, returns 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_ops_generic(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_null_ops_generic");
96 * e1000_null_mac_generic - No-op function, return void
97 * @hw: pointer to the HW structure
99 void e1000_null_mac_generic(struct e1000_hw *hw)
101 DEBUGFUNC("e1000_null_mac_generic");
106 * e1000_null_link_info - No-op function, return 0
107 * @hw: pointer to the HW structure
109 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
116 * e1000_null_mng_mode - No-op function, return FALSE
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw *hw)
121 DEBUGFUNC("e1000_null_mng_mode");
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a, u32 b, u32 c)
131 DEBUGFUNC("e1000_null_update_mc");
136 * e1000_null_write_vfta - No-op function, return void
137 * @hw: pointer to the HW structure
139 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
141 DEBUGFUNC("e1000_null_write_vfta");
146 * e1000_null_set_mta - No-op function, return void
147 * @hw: pointer to the HW structure
149 void e1000_null_mta_set(struct e1000_hw *hw, u32 a)
151 DEBUGFUNC("e1000_null_mta_set");
156 * e1000_null_rar_set - No-op function, return void
157 * @hw: pointer to the HW structure
159 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
161 DEBUGFUNC("e1000_null_rar_set");
166 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
167 * @hw: pointer to the HW structure
169 * Determines and stores the system bus information for a particular
170 * network interface. The following bus information is determined and stored:
171 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
173 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
175 struct e1000_mac_info *mac = &hw->mac;
176 struct e1000_bus_info *bus = &hw->bus;
177 u32 status = E1000_READ_REG(hw, E1000_STATUS);
178 s32 ret_val = E1000_SUCCESS;
180 DEBUGFUNC("e1000_get_bus_info_pci_generic");
183 bus->type = (status & E1000_STATUS_PCIX_MODE)
184 ? e1000_bus_type_pcix
185 : e1000_bus_type_pci;
188 if (bus->type == e1000_bus_type_pci) {
189 bus->speed = (status & E1000_STATUS_PCI66)
191 : e1000_bus_speed_33;
193 switch (status & E1000_STATUS_PCIX_SPEED) {
194 case E1000_STATUS_PCIX_SPEED_66:
195 bus->speed = e1000_bus_speed_66;
197 case E1000_STATUS_PCIX_SPEED_100:
198 bus->speed = e1000_bus_speed_100;
200 case E1000_STATUS_PCIX_SPEED_133:
201 bus->speed = e1000_bus_speed_133;
204 bus->speed = e1000_bus_speed_reserved;
210 bus->width = (status & E1000_STATUS_BUS64)
212 : e1000_bus_width_32;
214 /* Which PCI(-X) function? */
215 mac->ops.set_lan_id(hw);
221 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
222 * @hw: pointer to the HW structure
224 * Determines and stores the system bus information for a particular
225 * network interface. The following bus information is determined and stored:
226 * bus speed, bus width, type (PCIe), and PCIe function.
228 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
230 struct e1000_mac_info *mac = &hw->mac;
231 struct e1000_bus_info *bus = &hw->bus;
234 u16 pcie_link_status;
236 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
238 bus->type = e1000_bus_type_pci_express;
239 bus->speed = e1000_bus_speed_2500;
241 ret_val = e1000_read_pcie_cap_reg(hw,
245 bus->width = e1000_bus_width_unknown;
247 bus->width = (enum e1000_bus_width)((pcie_link_status &
248 PCIE_LINK_WIDTH_MASK) >>
249 PCIE_LINK_WIDTH_SHIFT);
251 mac->ops.set_lan_id(hw);
253 return E1000_SUCCESS;
257 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
259 * @hw: pointer to the HW structure
261 * Determines the LAN function id by reading memory-mapped registers
262 * and swaps the port value if requested.
264 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
266 struct e1000_bus_info *bus = &hw->bus;
269 reg = E1000_READ_REG(hw, E1000_STATUS);
270 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
272 /* check for a port swap */
273 reg = E1000_READ_REG(hw, E1000_FACTPS);
274 if (reg & E1000_FACTPS_LFS)
279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
280 * @hw: pointer to the HW structure
282 * Determines the LAN function id by reading PCI config space.
284 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
286 struct e1000_bus_info *bus = &hw->bus;
290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
292 status = E1000_READ_REG(hw, E1000_STATUS);
293 bus->func = (status & E1000_STATUS_FUNC_MASK)
294 >> E1000_STATUS_FUNC_SHIFT;
301 * e1000_set_lan_id_single_port - Set LAN id for a single port device
302 * @hw: pointer to the HW structure
304 * Sets the LAN function id to zero for a single port device.
306 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
308 struct e1000_bus_info *bus = &hw->bus;
314 * e1000_clear_vfta_generic - Clear VLAN filter table
315 * @hw: pointer to the HW structure
317 * Clears the register array which contains the VLAN filter table by
318 * setting all the values to 0.
320 void e1000_clear_vfta_generic(struct e1000_hw *hw)
324 DEBUGFUNC("e1000_clear_vfta_generic");
326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
328 E1000_WRITE_FLUSH(hw);
333 * e1000_write_vfta_generic - Write value to VLAN filter table
334 * @hw: pointer to the HW structure
335 * @offset: register offset in VLAN filter table
336 * @value: register value written to VLAN filter table
338 * Writes value at the given offset in the register array which stores
339 * the VLAN filter table.
341 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
343 DEBUGFUNC("e1000_write_vfta_generic");
345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
346 E1000_WRITE_FLUSH(hw);
350 * e1000_init_rx_addrs_generic - Initialize receive address's
351 * @hw: pointer to the HW structure
352 * @rar_count: receive address registers
354 * Setups the receive address registers by setting the base receive address
355 * register to the devices MAC address and clearing all the other receive
356 * address registers to 0.
358 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
362 DEBUGFUNC("e1000_init_rx_addrs_generic");
364 /* Setup the receive address */
365 DEBUGOUT("Programming MAC Address into RAR[0]\n");
367 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
369 /* Zero out the other (rar_entry_count - 1) receive addresses */
370 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
371 for (i = 1; i < rar_count; i++) {
372 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
373 E1000_WRITE_FLUSH(hw);
374 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
375 E1000_WRITE_FLUSH(hw);
380 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
381 * @hw: pointer to the HW structure
383 * Checks the nvm for an alternate MAC address. An alternate MAC address
384 * can be setup by pre-boot software and must be treated like a permanent
385 * address and must override the actual permanent MAC address. If an
386 * alternate MAC address is found it is saved in the hw struct and
387 * programmed into RAR0 and the function returns success, otherwise the
388 * function returns an error.
390 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
393 s32 ret_val = E1000_SUCCESS;
394 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
395 u8 alt_mac_addr[ETH_ADDR_LEN];
397 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
399 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
400 &nvm_alt_mac_addr_offset);
402 DEBUGOUT("NVM Read Error\n");
406 if (nvm_alt_mac_addr_offset == 0xFFFF) {
407 ret_val = -(E1000_NOT_IMPLEMENTED);
411 if (hw->bus.func == E1000_FUNC_1)
412 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16);
414 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
415 offset = nvm_alt_mac_addr_offset + (i >> 1);
416 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
418 DEBUGOUT("NVM Read Error\n");
422 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
423 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
426 /* if multicast bit is set, the alternate address will not be used */
427 if (alt_mac_addr[0] & 0x01) {
428 ret_val = -(E1000_NOT_IMPLEMENTED);
432 for (i = 0; i < ETH_ADDR_LEN; i++)
433 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
435 hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0);
442 * e1000_rar_set_generic - Set receive address register
443 * @hw: pointer to the HW structure
444 * @addr: pointer to the receive address
445 * @index: receive address array register
447 * Sets the receive address array register at index to the address passed
450 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
452 u32 rar_low, rar_high;
454 DEBUGFUNC("e1000_rar_set_generic");
457 * HW expects these in little endian so we reverse the byte order
458 * from network order (big endian) to little endian
460 rar_low = ((u32) addr[0] |
461 ((u32) addr[1] << 8) |
462 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
464 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
466 /* If MAC address zero, no need to set the AV bit */
467 if (rar_low || rar_high)
468 rar_high |= E1000_RAH_AV;
470 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
471 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
475 * e1000_mta_set_generic - Set multicast filter table address
476 * @hw: pointer to the HW structure
477 * @hash_value: determines the MTA register and bit to set
479 * The multicast table address is a register array of 32-bit registers.
480 * The hash_value is used to determine what register the bit is in, the
481 * current value is read, the new bit is OR'd in and the new value is
482 * written back into the register.
484 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
486 u32 hash_bit, hash_reg, mta;
488 DEBUGFUNC("e1000_mta_set_generic");
490 * The MTA is a register array of 32-bit registers. It is
491 * treated like an array of (32*mta_reg_count) bits. We want to
492 * set bit BitArray[hash_value]. So we figure out what register
493 * the bit is in, read it, OR in the new bit, then write
494 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
495 * mask to bits 31:5 of the hash value which gives us the
496 * register we're modifying. The hash bit within that register
497 * is determined by the lower 5 bits of the hash value.
499 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
500 hash_bit = hash_value & 0x1F;
502 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
504 mta |= (1 << hash_bit);
506 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
507 E1000_WRITE_FLUSH(hw);
511 * e1000_update_mc_addr_list_generic - Update Multicast addresses
512 * @hw: pointer to the HW structure
513 * @mc_addr_list: array of multicast addresses to program
514 * @mc_addr_count: number of multicast addresses to program
515 * @rar_used_count: the first RAR register free to program
516 * @rar_count: total number of supported Receive Address Registers
518 * Updates the Receive Address Registers and Multicast Table Array.
519 * The caller must have a packed mc_addr_list of multicast addresses.
520 * The parameter rar_count will usually be hw->mac.rar_entry_count
521 * unless there are workarounds that change this.
523 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
524 u8 *mc_addr_list, u32 mc_addr_count,
525 u32 rar_used_count, u32 rar_count)
530 DEBUGFUNC("e1000_update_mc_addr_list_generic");
533 * Load the first set of multicast addresses into the exact
534 * filters (RAR). If there are not enough to fill the RAR
535 * array, clear the filters.
537 for (i = rar_used_count; i < rar_count; i++) {
539 hw->mac.ops.rar_set(hw, mc_addr_list, i);
541 mc_addr_list += ETH_ADDR_LEN;
543 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
544 E1000_WRITE_FLUSH(hw);
545 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
546 E1000_WRITE_FLUSH(hw);
550 /* Clear the old settings from the MTA */
551 DEBUGOUT("Clearing MTA\n");
552 for (i = 0; i < hw->mac.mta_reg_count; i++) {
553 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
554 E1000_WRITE_FLUSH(hw);
557 /* Load any remaining multicast addresses into the hash table. */
558 for (; mc_addr_count > 0; mc_addr_count--) {
559 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
560 DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
561 hw->mac.ops.mta_set(hw, hash_value);
562 mc_addr_list += ETH_ADDR_LEN;
567 * e1000_hash_mc_addr_generic - Generate a multicast hash value
568 * @hw: pointer to the HW structure
569 * @mc_addr: pointer to a multicast address
571 * Generates a multicast address hash value which is used to determine
572 * the multicast filter table array address and new table value. See
573 * e1000_mta_set_generic()
575 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
577 u32 hash_value, hash_mask;
580 DEBUGFUNC("e1000_hash_mc_addr_generic");
582 /* Register count multiplied by bits per register */
583 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
586 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
587 * where 0xFF would still fall within the hash mask.
589 while (hash_mask >> bit_shift != 0xFF)
593 * The portion of the address that is used for the hash table
594 * is determined by the mc_filter_type setting.
595 * The algorithm is such that there is a total of 8 bits of shifting.
596 * The bit_shift for a mc_filter_type of 0 represents the number of
597 * left-shifts where the MSB of mc_addr[5] would still fall within
598 * the hash_mask. Case 0 does this exactly. Since there are a total
599 * of 8 bits of shifting, then mc_addr[4] will shift right the
600 * remaining number of bits. Thus 8 - bit_shift. The rest of the
601 * cases are a variation of this algorithm...essentially raising the
602 * number of bits to shift mc_addr[5] left, while still keeping the
603 * 8-bit shifting total.
605 * For example, given the following Destination MAC Address and an
606 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
607 * we can see that the bit_shift for case 0 is 4. These are the hash
608 * values resulting from each mc_filter_type...
609 * [0] [1] [2] [3] [4] [5]
613 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
614 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
615 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
616 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
618 switch (hw->mac.mc_filter_type) {
633 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
634 (((u16) mc_addr[5]) << bit_shift)));
640 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
641 * @hw: pointer to the HW structure
643 * In certain situations, a system BIOS may report that the PCIx maximum
644 * memory read byte count (MMRBC) value is higher than than the actual
645 * value. We check the PCIx command register with the current PCIx status
648 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
652 u16 pcix_stat_hi_word;
655 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
657 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
658 if (hw->bus.type != e1000_bus_type_pcix)
661 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
662 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
663 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
664 PCIX_COMMAND_MMRBC_SHIFT;
665 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
666 PCIX_STATUS_HI_MMRBC_SHIFT;
667 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
668 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
669 if (cmd_mmrbc > stat_mmrbc) {
670 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
671 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
672 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
677 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
678 * @hw: pointer to the HW structure
680 * Clears the base hardware counters by reading the counter registers.
682 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
684 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
686 E1000_READ_REG(hw, E1000_CRCERRS);
687 E1000_READ_REG(hw, E1000_SYMERRS);
688 E1000_READ_REG(hw, E1000_MPC);
689 E1000_READ_REG(hw, E1000_SCC);
690 E1000_READ_REG(hw, E1000_ECOL);
691 E1000_READ_REG(hw, E1000_MCC);
692 E1000_READ_REG(hw, E1000_LATECOL);
693 E1000_READ_REG(hw, E1000_COLC);
694 E1000_READ_REG(hw, E1000_DC);
695 E1000_READ_REG(hw, E1000_SEC);
696 E1000_READ_REG(hw, E1000_RLEC);
697 E1000_READ_REG(hw, E1000_XONRXC);
698 E1000_READ_REG(hw, E1000_XONTXC);
699 E1000_READ_REG(hw, E1000_XOFFRXC);
700 E1000_READ_REG(hw, E1000_XOFFTXC);
701 E1000_READ_REG(hw, E1000_FCRUC);
702 E1000_READ_REG(hw, E1000_GPRC);
703 E1000_READ_REG(hw, E1000_BPRC);
704 E1000_READ_REG(hw, E1000_MPRC);
705 E1000_READ_REG(hw, E1000_GPTC);
706 E1000_READ_REG(hw, E1000_GORCL);
707 E1000_READ_REG(hw, E1000_GORCH);
708 E1000_READ_REG(hw, E1000_GOTCL);
709 E1000_READ_REG(hw, E1000_GOTCH);
710 E1000_READ_REG(hw, E1000_RNBC);
711 E1000_READ_REG(hw, E1000_RUC);
712 E1000_READ_REG(hw, E1000_RFC);
713 E1000_READ_REG(hw, E1000_ROC);
714 E1000_READ_REG(hw, E1000_RJC);
715 E1000_READ_REG(hw, E1000_TORL);
716 E1000_READ_REG(hw, E1000_TORH);
717 E1000_READ_REG(hw, E1000_TOTL);
718 E1000_READ_REG(hw, E1000_TOTH);
719 E1000_READ_REG(hw, E1000_TPR);
720 E1000_READ_REG(hw, E1000_TPT);
721 E1000_READ_REG(hw, E1000_MPTC);
722 E1000_READ_REG(hw, E1000_BPTC);
726 * e1000_check_for_copper_link_generic - Check for link (Copper)
727 * @hw: pointer to the HW structure
729 * Checks to see of the link status of the hardware has changed. If a
730 * change in link status has been detected, then we read the PHY registers
731 * to get the current speed/duplex if link exists.
733 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
735 struct e1000_mac_info *mac = &hw->mac;
739 DEBUGFUNC("e1000_check_for_copper_link");
742 * We only want to go out to the PHY registers to see if Auto-Neg
743 * has completed and/or if our link status has changed. The
744 * get_link_status flag is set upon receiving a Link Status
745 * Change or Rx Sequence Error interrupt.
747 if (!mac->get_link_status) {
748 ret_val = E1000_SUCCESS;
753 * First we want to see if the MII Status Register reports
754 * link. If so, then we want to get the current speed/duplex
757 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
762 goto out; /* No link detected */
764 mac->get_link_status = FALSE;
767 * Check if there was DownShift, must be checked
768 * immediately after link-up
770 e1000_check_downshift_generic(hw);
773 * If we are forcing speed/duplex, then we simply return since
774 * we have already determined whether we have link or not.
777 ret_val = -E1000_ERR_CONFIG;
782 * Auto-Neg is enabled. Auto Speed Detection takes care
783 * of MAC speed/duplex configuration. So we only need to
784 * configure Collision Distance in the MAC.
786 e1000_config_collision_dist_generic(hw);
789 * Configure Flow Control now that Auto-Neg has completed.
790 * First, we need to restore the desired flow control
791 * settings because we may have had to re-autoneg with a
792 * different link partner.
794 ret_val = e1000_config_fc_after_link_up_generic(hw);
796 DEBUGOUT("Error configuring flow control\n");
803 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
804 * @hw: pointer to the HW structure
806 * Checks for link up on the hardware. If link is not up and we have
807 * a signal, then we need to force link up.
809 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
811 struct e1000_mac_info *mac = &hw->mac;
815 s32 ret_val = E1000_SUCCESS;
817 DEBUGFUNC("e1000_check_for_fiber_link_generic");
819 ctrl = E1000_READ_REG(hw, E1000_CTRL);
820 status = E1000_READ_REG(hw, E1000_STATUS);
821 rxcw = E1000_READ_REG(hw, E1000_RXCW);
824 * If we don't have link (auto-negotiation failed or link partner
825 * cannot auto-negotiate), the cable is plugged in (we have signal),
826 * and our link partner is not trying to auto-negotiate with us (we
827 * are receiving idles or data), we need to force link up. We also
828 * need to give auto-negotiation time to complete, in case the cable
829 * was just plugged in. The autoneg_failed flag does this.
831 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
832 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
833 (!(rxcw & E1000_RXCW_C))) {
834 if (mac->autoneg_failed == 0) {
835 mac->autoneg_failed = 1;
838 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
840 /* Disable auto-negotiation in the TXCW register */
841 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
843 /* Force link-up and also force full-duplex. */
844 ctrl = E1000_READ_REG(hw, E1000_CTRL);
845 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
846 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
848 /* Configure Flow Control after forcing link up. */
849 ret_val = e1000_config_fc_after_link_up_generic(hw);
851 DEBUGOUT("Error configuring flow control\n");
854 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
856 * If we are forcing link and we are receiving /C/ ordered
857 * sets, re-enable auto-negotiation in the TXCW register
858 * and disable forced link in the Device Control register
859 * in an attempt to auto-negotiate with our link partner.
861 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
862 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
863 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
865 mac->serdes_has_link = TRUE;
873 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
874 * @hw: pointer to the HW structure
876 * Checks for link up on the hardware. If link is not up and we have
877 * a signal, then we need to force link up.
879 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
881 struct e1000_mac_info *mac = &hw->mac;
885 s32 ret_val = E1000_SUCCESS;
887 DEBUGFUNC("e1000_check_for_serdes_link_generic");
889 ctrl = E1000_READ_REG(hw, E1000_CTRL);
890 status = E1000_READ_REG(hw, E1000_STATUS);
891 rxcw = E1000_READ_REG(hw, E1000_RXCW);
894 * If we don't have link (auto-negotiation failed or link partner
895 * cannot auto-negotiate), and our link partner is not trying to
896 * auto-negotiate with us (we are receiving idles or data),
897 * we need to force link up. We also need to give auto-negotiation
900 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
901 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
902 if (mac->autoneg_failed == 0) {
903 mac->autoneg_failed = 1;
906 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
908 /* Disable auto-negotiation in the TXCW register */
909 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
911 /* Force link-up and also force full-duplex. */
912 ctrl = E1000_READ_REG(hw, E1000_CTRL);
913 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
914 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
916 /* Configure Flow Control after forcing link up. */
917 ret_val = e1000_config_fc_after_link_up_generic(hw);
919 DEBUGOUT("Error configuring flow control\n");
922 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
924 * If we are forcing link and we are receiving /C/ ordered
925 * sets, re-enable auto-negotiation in the TXCW register
926 * and disable forced link in the Device Control register
927 * in an attempt to auto-negotiate with our link partner.
929 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
930 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
931 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
933 mac->serdes_has_link = TRUE;
934 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
936 * If we force link for non-auto-negotiation switch, check
937 * link status based on MAC synchronization for internal
940 /* SYNCH bit and IV bit are sticky. */
942 rxcw = E1000_READ_REG(hw, E1000_RXCW);
943 if (rxcw & E1000_RXCW_SYNCH) {
944 if (!(rxcw & E1000_RXCW_IV)) {
945 mac->serdes_has_link = TRUE;
946 DEBUGOUT("SERDES: Link up - forced.\n");
949 mac->serdes_has_link = FALSE;
950 DEBUGOUT("SERDES: Link down - force failed.\n");
954 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
955 status = E1000_READ_REG(hw, E1000_STATUS);
956 if (status & E1000_STATUS_LU) {
957 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
959 rxcw = E1000_READ_REG(hw, E1000_RXCW);
960 if (rxcw & E1000_RXCW_SYNCH) {
961 if (!(rxcw & E1000_RXCW_IV)) {
962 mac->serdes_has_link = TRUE;
963 DEBUGOUT("SERDES: Link up - autoneg "
964 "completed sucessfully.\n");
966 mac->serdes_has_link = FALSE;
967 DEBUGOUT("SERDES: Link down - invalid"
968 "codewords detected in autoneg.\n");
971 mac->serdes_has_link = FALSE;
972 DEBUGOUT("SERDES: Link down - no sync.\n");
975 mac->serdes_has_link = FALSE;
976 DEBUGOUT("SERDES: Link down - autoneg failed\n");
985 * e1000_setup_link_generic - Setup flow control and link settings
986 * @hw: pointer to the HW structure
988 * Determines which flow control settings to use, then configures flow
989 * control. Calls the appropriate media-specific link configuration
990 * function. Assuming the adapter has a valid link partner, a valid link
991 * should be established. Assumes the hardware has previously been reset
992 * and the transmitter and receiver are not enabled.
994 s32 e1000_setup_link_generic(struct e1000_hw *hw)
996 s32 ret_val = E1000_SUCCESS;
998 DEBUGFUNC("e1000_setup_link_generic");
1001 * In the case of the phy reset being blocked, we already have a link.
1002 * We do not need to set it up again.
1004 if (hw->phy.ops.check_reset_block)
1005 if (hw->phy.ops.check_reset_block(hw))
1009 * If requested flow control is set to default, set flow control
1010 * based on the EEPROM flow control settings.
1012 if (hw->fc.requested_mode == e1000_fc_default) {
1013 ret_val = e1000_set_default_fc_generic(hw);
1019 * Save off the requested flow control mode for use later. Depending
1020 * on the link partner's capabilities, we may or may not use this mode.
1022 hw->fc.current_mode = hw->fc.requested_mode;
1024 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1025 hw->fc.current_mode);
1027 /* Call the necessary media_type subroutine to configure the link. */
1028 ret_val = hw->mac.ops.setup_physical_interface(hw);
1033 * Initialize the flow control address, type, and PAUSE timer
1034 * registers to their default values. This is done even if flow
1035 * control is disabled, because it does not hurt anything to
1036 * initialize these registers.
1038 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1039 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1040 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1041 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1043 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1045 ret_val = e1000_set_fc_watermarks_generic(hw);
1052 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1053 * @hw: pointer to the HW structure
1055 * Configures collision distance and flow control for fiber and serdes
1056 * links. Upon successful setup, poll for link.
1058 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1061 s32 ret_val = E1000_SUCCESS;
1063 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1065 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1067 /* Take the link out of reset */
1068 ctrl &= ~E1000_CTRL_LRST;
1070 e1000_config_collision_dist_generic(hw);
1072 ret_val = e1000_commit_fc_settings_generic(hw);
1077 * Since auto-negotiation is enabled, take the link out of reset (the
1078 * link will be in reset, because we previously reset the chip). This
1079 * will restart auto-negotiation. If auto-negotiation is successful
1080 * then the link-up status bit will be set and the flow control enable
1081 * bits (RFCE and TFCE) will be set according to their negotiated value.
1083 DEBUGOUT("Auto-negotiation enabled\n");
1085 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1086 E1000_WRITE_FLUSH(hw);
1090 * For these adapters, the SW definable pin 1 is set when the optics
1091 * detect a signal. If we have a signal, then poll for a "Link-Up"
1094 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1095 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1096 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1098 DEBUGOUT("No signal detected\n");
1106 * e1000_config_collision_dist_generic - Configure collision distance
1107 * @hw: pointer to the HW structure
1109 * Configures the collision distance to the default value and is used
1110 * during link setup. Currently no func pointer exists and all
1111 * implementations are handled in the generic version of this function.
1113 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1117 DEBUGFUNC("e1000_config_collision_dist_generic");
1119 tctl = E1000_READ_REG(hw, E1000_TCTL);
1121 tctl &= ~E1000_TCTL_COLD;
1122 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1124 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1125 E1000_WRITE_FLUSH(hw);
1129 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1130 * @hw: pointer to the HW structure
1132 * Polls for link up by reading the status register, if link fails to come
1133 * up with auto-negotiation, then the link is forced if a signal is detected.
1135 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1137 struct e1000_mac_info *mac = &hw->mac;
1139 s32 ret_val = E1000_SUCCESS;
1141 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1144 * If we have a signal (the cable is plugged in, or assumed TRUE for
1145 * serdes media) then poll for a "Link-Up" indication in the Device
1146 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1147 * seconds (Auto-negotiation should complete in less than 500
1148 * milliseconds even if the other end is doing it in SW).
1150 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1152 status = E1000_READ_REG(hw, E1000_STATUS);
1153 if (status & E1000_STATUS_LU)
1156 if (i == FIBER_LINK_UP_LIMIT) {
1157 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1158 mac->autoneg_failed = 1;
1160 * AutoNeg failed to achieve a link, so we'll call
1161 * mac->check_for_link. This routine will force the
1162 * link up if we detect a signal. This will allow us to
1163 * communicate with non-autonegotiating link partners.
1165 ret_val = hw->mac.ops.check_for_link(hw);
1167 DEBUGOUT("Error while checking for link\n");
1170 mac->autoneg_failed = 0;
1172 mac->autoneg_failed = 0;
1173 DEBUGOUT("Valid Link Found\n");
1181 * e1000_commit_fc_settings_generic - Configure flow control
1182 * @hw: pointer to the HW structure
1184 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1185 * base on the flow control settings in e1000_mac_info.
1187 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1189 struct e1000_mac_info *mac = &hw->mac;
1191 s32 ret_val = E1000_SUCCESS;
1193 DEBUGFUNC("e1000_commit_fc_settings_generic");
1196 * Check for a software override of the flow control settings, and
1197 * setup the device accordingly. If auto-negotiation is enabled, then
1198 * software will have to set the "PAUSE" bits to the correct value in
1199 * the Transmit Config Word Register (TXCW) and re-start auto-
1200 * negotiation. However, if auto-negotiation is disabled, then
1201 * software will have to manually configure the two flow control enable
1202 * bits in the CTRL register.
1204 * The possible values of the "fc" parameter are:
1205 * 0: Flow control is completely disabled
1206 * 1: Rx flow control is enabled (we can receive pause frames,
1207 * but not send pause frames).
1208 * 2: Tx flow control is enabled (we can send pause frames but we
1209 * do not support receiving pause frames).
1210 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1212 switch (hw->fc.current_mode) {
1214 /* Flow control completely disabled by a software over-ride. */
1215 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1217 case e1000_fc_rx_pause:
1219 * Rx Flow control is enabled and Tx Flow control is disabled
1220 * by a software over-ride. Since there really isn't a way to
1221 * advertise that we are capable of Rx Pause ONLY, we will
1222 * advertise that we support both symmetric and asymmetric RX
1223 * PAUSE. Later, we will disable the adapter's ability to send
1226 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1228 case e1000_fc_tx_pause:
1230 * Tx Flow control is enabled, and Rx Flow control is disabled,
1231 * by a software over-ride.
1233 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1237 * Flow control (both Rx and Tx) is enabled by a software
1240 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1243 DEBUGOUT("Flow control param set incorrectly\n");
1244 ret_val = -E1000_ERR_CONFIG;
1249 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1257 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1258 * @hw: pointer to the HW structure
1260 * Sets the flow control high/low threshold (watermark) registers. If
1261 * flow control XON frame transmission is enabled, then set XON frame
1262 * transmission as well.
1264 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1266 s32 ret_val = E1000_SUCCESS;
1267 u32 fcrtl = 0, fcrth = 0;
1269 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1272 * Set the flow control receive threshold registers. Normally,
1273 * these registers will be set to a default threshold that may be
1274 * adjusted later by the driver's runtime code. However, if the
1275 * ability to transmit pause frames is not enabled, then these
1276 * registers will be set to 0.
1278 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1280 * We need to set up the Receive Threshold high and low water
1281 * marks as well as (optionally) enabling the transmission of
1284 fcrtl = hw->fc.low_water;
1285 if (hw->fc.send_xon)
1286 fcrtl |= E1000_FCRTL_XONE;
1288 fcrth = hw->fc.high_water;
1290 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1291 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1297 * e1000_set_default_fc_generic - Set flow control default values
1298 * @hw: pointer to the HW structure
1300 * Read the EEPROM for the default values for flow control and store the
1303 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1305 s32 ret_val = E1000_SUCCESS;
1308 DEBUGFUNC("e1000_set_default_fc_generic");
1311 * Read and store word 0x0F of the EEPROM. This word contains bits
1312 * that determine the hardware's default PAUSE (flow control) mode,
1313 * a bit that determines whether the HW defaults to enabling or
1314 * disabling auto-negotiation, and the direction of the
1315 * SW defined pins. If there is no SW over-ride of the flow
1316 * control setting, then the variable hw->fc will
1317 * be initialized based on a value in the EEPROM.
1319 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1322 DEBUGOUT("NVM Read Error\n");
1326 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1327 hw->fc.requested_mode = e1000_fc_none;
1328 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1330 hw->fc.requested_mode = e1000_fc_tx_pause;
1332 hw->fc.requested_mode = e1000_fc_full;
1339 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1340 * @hw: pointer to the HW structure
1342 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1343 * device control register to reflect the adapter settings. TFCE and RFCE
1344 * need to be explicitly set by software when a copper PHY is used because
1345 * autonegotiation is managed by the PHY rather than the MAC. Software must
1346 * also configure these bits when link is forced on a fiber connection.
1348 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1351 s32 ret_val = E1000_SUCCESS;
1353 DEBUGFUNC("e1000_force_mac_fc_generic");
1355 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1358 * Because we didn't get link via the internal auto-negotiation
1359 * mechanism (we either forced link or we got link via PHY
1360 * auto-neg), we have to manually enable/disable transmit an
1361 * receive flow control.
1363 * The "Case" statement below enables/disable flow control
1364 * according to the "hw->fc.current_mode" parameter.
1366 * The possible values of the "fc" parameter are:
1367 * 0: Flow control is completely disabled
1368 * 1: Rx flow control is enabled (we can receive pause
1369 * frames but not send pause frames).
1370 * 2: Tx flow control is enabled (we can send pause frames
1371 * frames but we do not receive pause frames).
1372 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1373 * other: No other values should be possible at this point.
1375 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1377 switch (hw->fc.current_mode) {
1379 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1381 case e1000_fc_rx_pause:
1382 ctrl &= (~E1000_CTRL_TFCE);
1383 ctrl |= E1000_CTRL_RFCE;
1385 case e1000_fc_tx_pause:
1386 ctrl &= (~E1000_CTRL_RFCE);
1387 ctrl |= E1000_CTRL_TFCE;
1390 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1393 DEBUGOUT("Flow control param set incorrectly\n");
1394 ret_val = -E1000_ERR_CONFIG;
1398 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1405 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1406 * @hw: pointer to the HW structure
1408 * Checks the status of auto-negotiation after link up to ensure that the
1409 * speed and duplex were not forced. If the link needed to be forced, then
1410 * flow control needs to be forced also. If auto-negotiation is enabled
1411 * and did not fail, then we configure flow control based on our link
1414 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1416 struct e1000_mac_info *mac = &hw->mac;
1417 s32 ret_val = E1000_SUCCESS;
1418 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1421 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1424 * Check for the case where we have fiber media and auto-neg failed
1425 * so we had to force link. In this case, we need to force the
1426 * configuration of the MAC to match the "fc" parameter.
1428 if (mac->autoneg_failed) {
1429 if (hw->phy.media_type == e1000_media_type_fiber ||
1430 hw->phy.media_type == e1000_media_type_internal_serdes)
1431 ret_val = e1000_force_mac_fc_generic(hw);
1433 if (hw->phy.media_type == e1000_media_type_copper)
1434 ret_val = e1000_force_mac_fc_generic(hw);
1438 DEBUGOUT("Error forcing flow control settings\n");
1443 * Check for the case where we have copper media and auto-neg is
1444 * enabled. In this case, we need to check and see if Auto-Neg
1445 * has completed, and if so, how the PHY and link partner has
1446 * flow control configured.
1448 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1450 * Read the MII Status Register and check to see if AutoNeg
1451 * has completed. We read this twice because this reg has
1452 * some "sticky" (latched) bits.
1454 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1457 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1461 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1462 DEBUGOUT("Copper PHY and Auto Neg "
1463 "has not completed.\n");
1468 * The AutoNeg process has completed, so we now need to
1469 * read both the Auto Negotiation Advertisement
1470 * Register (Address 4) and the Auto_Negotiation Base
1471 * Page Ability Register (Address 5) to determine how
1472 * flow control was negotiated.
1474 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1478 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1479 &mii_nway_lp_ability_reg);
1484 * Two bits in the Auto Negotiation Advertisement Register
1485 * (Address 4) and two bits in the Auto Negotiation Base
1486 * Page Ability Register (Address 5) determine flow control
1487 * for both the PHY and the link partner. The following
1488 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1489 * 1999, describes these PAUSE resolution bits and how flow
1490 * control is determined based upon these settings.
1491 * NOTE: DC = Don't Care
1493 * LOCAL DEVICE | LINK PARTNER
1494 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1495 *-------|---------|-------|---------|--------------------
1496 * 0 | 0 | DC | DC | e1000_fc_none
1497 * 0 | 1 | 0 | DC | e1000_fc_none
1498 * 0 | 1 | 1 | 0 | e1000_fc_none
1499 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1500 * 1 | 0 | 0 | DC | e1000_fc_none
1501 * 1 | DC | 1 | DC | e1000_fc_full
1502 * 1 | 1 | 0 | 0 | e1000_fc_none
1503 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1505 * Are both PAUSE bits set to 1? If so, this implies
1506 * Symmetric Flow Control is enabled at both ends. The
1507 * ASM_DIR bits are irrelevant per the spec.
1509 * For Symmetric Flow Control:
1511 * LOCAL DEVICE | LINK PARTNER
1512 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1513 *-------|---------|-------|---------|--------------------
1514 * 1 | DC | 1 | DC | E1000_fc_full
1517 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1518 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1520 * Now we need to check if the user selected Rx ONLY
1521 * of pause frames. In this case, we had to advertise
1522 * FULL flow control because we could not advertise RX
1523 * ONLY. Hence, we must now check to see if we need to
1524 * turn OFF the TRANSMISSION of PAUSE frames.
1526 if (hw->fc.requested_mode == e1000_fc_full) {
1527 hw->fc.current_mode = e1000_fc_full;
1528 DEBUGOUT("Flow Control = FULL.\r\n");
1530 hw->fc.current_mode = e1000_fc_rx_pause;
1531 DEBUGOUT("Flow Control = "
1532 "RX PAUSE frames only.\r\n");
1536 * For receiving PAUSE frames ONLY.
1538 * LOCAL DEVICE | LINK PARTNER
1539 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1540 *-------|---------|-------|---------|--------------------
1541 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1543 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1544 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1545 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1546 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1547 hw->fc.current_mode = e1000_fc_tx_pause;
1548 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1551 * For transmitting PAUSE frames ONLY.
1553 * LOCAL DEVICE | LINK PARTNER
1554 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1555 *-------|---------|-------|---------|--------------------
1556 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1558 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1559 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1560 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1561 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1562 hw->fc.current_mode = e1000_fc_rx_pause;
1563 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1566 * Per the IEEE spec, at this point flow control
1567 * should be disabled.
1569 hw->fc.current_mode = e1000_fc_none;
1570 DEBUGOUT("Flow Control = NONE.\r\n");
1574 * Now we need to do one last check... If we auto-
1575 * negotiated to HALF DUPLEX, flow control should not be
1576 * enabled per IEEE 802.3 spec.
1578 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1580 DEBUGOUT("Error getting link speed and duplex\n");
1584 if (duplex == HALF_DUPLEX)
1585 hw->fc.current_mode = e1000_fc_none;
1588 * Now we call a subroutine to actually force the MAC
1589 * controller to use the correct flow control settings.
1591 ret_val = e1000_force_mac_fc_generic(hw);
1593 DEBUGOUT("Error forcing flow control settings\n");
1603 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1604 * @hw: pointer to the HW structure
1605 * @speed: stores the current speed
1606 * @duplex: stores the current duplex
1608 * Read the status register for the current speed/duplex and store the current
1609 * speed and duplex for copper connections.
1611 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1616 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1618 status = E1000_READ_REG(hw, E1000_STATUS);
1619 if (status & E1000_STATUS_SPEED_1000) {
1620 *speed = SPEED_1000;
1621 DEBUGOUT("1000 Mbs, ");
1622 } else if (status & E1000_STATUS_SPEED_100) {
1624 DEBUGOUT("100 Mbs, ");
1627 DEBUGOUT("10 Mbs, ");
1630 if (status & E1000_STATUS_FD) {
1631 *duplex = FULL_DUPLEX;
1632 DEBUGOUT("Full Duplex\n");
1634 *duplex = HALF_DUPLEX;
1635 DEBUGOUT("Half Duplex\n");
1638 return E1000_SUCCESS;
1642 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1643 * @hw: pointer to the HW structure
1644 * @speed: stores the current speed
1645 * @duplex: stores the current duplex
1647 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1648 * for fiber/serdes links.
1650 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1651 u16 *speed, u16 *duplex)
1653 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1655 *speed = SPEED_1000;
1656 *duplex = FULL_DUPLEX;
1658 return E1000_SUCCESS;
1662 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1663 * @hw: pointer to the HW structure
1665 * Acquire the HW semaphore to access the PHY or NVM
1667 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1670 s32 ret_val = E1000_SUCCESS;
1671 s32 timeout = hw->nvm.word_size + 1;
1674 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1676 /* Get the SW semaphore */
1677 while (i < timeout) {
1678 swsm = E1000_READ_REG(hw, E1000_SWSM);
1679 if (!(swsm & E1000_SWSM_SMBI))
1687 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1688 ret_val = -E1000_ERR_NVM;
1692 /* Get the FW semaphore. */
1693 for (i = 0; i < timeout; i++) {
1694 swsm = E1000_READ_REG(hw, E1000_SWSM);
1695 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1697 /* Semaphore acquired if bit latched */
1698 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1705 /* Release semaphores */
1706 e1000_put_hw_semaphore_generic(hw);
1707 DEBUGOUT("Driver can't access the NVM\n");
1708 ret_val = -E1000_ERR_NVM;
1717 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1718 * @hw: pointer to the HW structure
1720 * Release hardware semaphore used to access the PHY or NVM
1722 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1726 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1728 swsm = E1000_READ_REG(hw, E1000_SWSM);
1730 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1732 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1736 * e1000_get_auto_rd_done_generic - Check for auto read completion
1737 * @hw: pointer to the HW structure
1739 * Check EEPROM for Auto Read done bit.
1741 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1744 s32 ret_val = E1000_SUCCESS;
1746 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1748 while (i < AUTO_READ_DONE_TIMEOUT) {
1749 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1755 if (i == AUTO_READ_DONE_TIMEOUT) {
1756 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1757 ret_val = -E1000_ERR_RESET;
1766 * e1000_valid_led_default_generic - Verify a valid default LED config
1767 * @hw: pointer to the HW structure
1768 * @data: pointer to the NVM (EEPROM)
1770 * Read the EEPROM for the current default LED configuration. If the
1771 * LED configuration is not valid, set to a valid LED configuration.
1773 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1777 DEBUGFUNC("e1000_valid_led_default_generic");
1779 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1781 DEBUGOUT("NVM Read Error\n");
1785 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1786 *data = ID_LED_DEFAULT;
1793 * e1000_id_led_init_generic -
1794 * @hw: pointer to the HW structure
1797 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1799 struct e1000_mac_info *mac = &hw->mac;
1801 const u32 ledctl_mask = 0x000000FF;
1802 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1803 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1805 const u16 led_mask = 0x0F;
1807 DEBUGFUNC("e1000_id_led_init_generic");
1809 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1813 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1814 mac->ledctl_mode1 = mac->ledctl_default;
1815 mac->ledctl_mode2 = mac->ledctl_default;
1817 for (i = 0; i < 4; i++) {
1818 temp = (data >> (i << 2)) & led_mask;
1820 case ID_LED_ON1_DEF2:
1821 case ID_LED_ON1_ON2:
1822 case ID_LED_ON1_OFF2:
1823 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1824 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1826 case ID_LED_OFF1_DEF2:
1827 case ID_LED_OFF1_ON2:
1828 case ID_LED_OFF1_OFF2:
1829 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1830 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1837 case ID_LED_DEF1_ON2:
1838 case ID_LED_ON1_ON2:
1839 case ID_LED_OFF1_ON2:
1840 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1841 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1843 case ID_LED_DEF1_OFF2:
1844 case ID_LED_ON1_OFF2:
1845 case ID_LED_OFF1_OFF2:
1846 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1847 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1860 * e1000_setup_led_generic - Configures SW controllable LED
1861 * @hw: pointer to the HW structure
1863 * This prepares the SW controllable LED for use and saves the current state
1864 * of the LED so it can be later restored.
1866 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1869 s32 ret_val = E1000_SUCCESS;
1871 DEBUGFUNC("e1000_setup_led_generic");
1873 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1874 ret_val = -E1000_ERR_CONFIG;
1878 if (hw->phy.media_type == e1000_media_type_fiber) {
1879 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1880 hw->mac.ledctl_default = ledctl;
1882 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1883 E1000_LEDCTL_LED0_BLINK |
1884 E1000_LEDCTL_LED0_MODE_MASK);
1885 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1886 E1000_LEDCTL_LED0_MODE_SHIFT);
1887 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1888 } else if (hw->phy.media_type == e1000_media_type_copper) {
1889 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1897 * e1000_cleanup_led_generic - Set LED config to default operation
1898 * @hw: pointer to the HW structure
1900 * Remove the current LED configuration and set the LED configuration
1901 * to the default value, saved from the EEPROM.
1903 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1905 s32 ret_val = E1000_SUCCESS;
1907 DEBUGFUNC("e1000_cleanup_led_generic");
1909 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
1910 ret_val = -E1000_ERR_CONFIG;
1914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1921 * e1000_blink_led_generic - Blink LED
1922 * @hw: pointer to the HW structure
1924 * Blink the LEDs which are set to be on.
1926 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1928 u32 ledctl_blink = 0;
1931 DEBUGFUNC("e1000_blink_led_generic");
1933 if (hw->phy.media_type == e1000_media_type_fiber) {
1934 /* always blink LED0 for PCI-E fiber */
1935 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1936 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1939 * set the blink bit for each LED that's "on" (0x0E)
1942 ledctl_blink = hw->mac.ledctl_mode2;
1943 for (i = 0; i < 4; i++)
1944 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1945 E1000_LEDCTL_MODE_LED_ON)
1946 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1950 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1952 return E1000_SUCCESS;
1956 * e1000_led_on_generic - Turn LED on
1957 * @hw: pointer to the HW structure
1961 s32 e1000_led_on_generic(struct e1000_hw *hw)
1965 DEBUGFUNC("e1000_led_on_generic");
1967 switch (hw->phy.media_type) {
1968 case e1000_media_type_fiber:
1969 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1970 ctrl &= ~E1000_CTRL_SWDPIN0;
1971 ctrl |= E1000_CTRL_SWDPIO0;
1972 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1974 case e1000_media_type_copper:
1975 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1981 return E1000_SUCCESS;
1985 * e1000_led_off_generic - Turn LED off
1986 * @hw: pointer to the HW structure
1990 s32 e1000_led_off_generic(struct e1000_hw *hw)
1994 DEBUGFUNC("e1000_led_off_generic");
1996 switch (hw->phy.media_type) {
1997 case e1000_media_type_fiber:
1998 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1999 ctrl |= E1000_CTRL_SWDPIN0;
2000 ctrl |= E1000_CTRL_SWDPIO0;
2001 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2003 case e1000_media_type_copper:
2004 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2010 return E1000_SUCCESS;
2014 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2015 * @hw: pointer to the HW structure
2016 * @no_snoop: bitmap of snoop events
2018 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2020 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2024 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2026 if (hw->bus.type != e1000_bus_type_pci_express)
2030 gcr = E1000_READ_REG(hw, E1000_GCR);
2031 gcr &= ~(PCIE_NO_SNOOP_ALL);
2033 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2040 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2041 * @hw: pointer to the HW structure
2043 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
2044 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2045 * the master requests to be disabled.
2047 * Disables PCI-Express master access and verifies there are no pending
2050 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2053 s32 timeout = MASTER_DISABLE_TIMEOUT;
2054 s32 ret_val = E1000_SUCCESS;
2056 DEBUGFUNC("e1000_disable_pcie_master_generic");
2058 if (hw->bus.type != e1000_bus_type_pci_express)
2061 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2062 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2063 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2066 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2067 E1000_STATUS_GIO_MASTER_ENABLE))
2074 DEBUGOUT("Master requests are pending.\n");
2075 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2084 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2085 * @hw: pointer to the HW structure
2087 * Reset the Adaptive Interframe Spacing throttle to default values.
2089 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2091 struct e1000_mac_info *mac = &hw->mac;
2093 DEBUGFUNC("e1000_reset_adaptive_generic");
2095 if (!mac->adaptive_ifs) {
2096 DEBUGOUT("Not in Adaptive IFS mode!\n");
2100 mac->current_ifs_val = 0;
2101 mac->ifs_min_val = IFS_MIN;
2102 mac->ifs_max_val = IFS_MAX;
2103 mac->ifs_step_size = IFS_STEP;
2104 mac->ifs_ratio = IFS_RATIO;
2106 mac->in_ifs_mode = FALSE;
2107 E1000_WRITE_REG(hw, E1000_AIT, 0);
2113 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2114 * @hw: pointer to the HW structure
2116 * Update the Adaptive Interframe Spacing Throttle value based on the
2117 * time between transmitted packets and time between collisions.
2119 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2121 struct e1000_mac_info *mac = &hw->mac;
2123 DEBUGFUNC("e1000_update_adaptive_generic");
2125 if (!mac->adaptive_ifs) {
2126 DEBUGOUT("Not in Adaptive IFS mode!\n");
2130 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2131 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2132 mac->in_ifs_mode = TRUE;
2133 if (mac->current_ifs_val < mac->ifs_max_val) {
2134 if (!mac->current_ifs_val)
2135 mac->current_ifs_val = mac->ifs_min_val;
2137 mac->current_ifs_val +=
2139 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2143 if (mac->in_ifs_mode &&
2144 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2145 mac->current_ifs_val = 0;
2146 mac->in_ifs_mode = FALSE;
2147 E1000_WRITE_REG(hw, E1000_AIT, 0);
2155 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2156 * @hw: pointer to the HW structure
2158 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2159 * set, which is forced to MDI mode only.
2161 s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2163 s32 ret_val = E1000_SUCCESS;
2165 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2167 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2168 DEBUGOUT("Invalid MDI setting detected\n");
2170 ret_val = -E1000_ERR_CONFIG;
2179 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2180 * @hw: pointer to the HW structure
2181 * @reg: 32bit register offset such as E1000_SCTL
2182 * @offset: register offset to write to
2183 * @data: data to write at register offset
2185 * Writes an address/data control type register. There are several of these
2186 * and they all have the format address << 8 | data and bit 31 is polled for
2189 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2190 u32 offset, u8 data)
2192 u32 i, regvalue = 0;
2193 s32 ret_val = E1000_SUCCESS;
2195 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2197 /* Set up the address and data */
2198 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2199 E1000_WRITE_REG(hw, reg, regvalue);
2201 /* Poll the ready bit to see if the MDI read completed */
2202 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2204 regvalue = E1000_READ_REG(hw, reg);
2205 if (regvalue & E1000_GEN_CTL_READY)
2208 if (!(regvalue & E1000_GEN_CTL_READY)) {
2209 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2210 ret_val = -E1000_ERR_PHY;