1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
38 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
39 * @hw: pointer to the HW structure
41 * Setups up the function pointers to no-op functions
43 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
45 struct e1000_nvm_info *nvm = &hw->nvm;
46 DEBUGFUNC("e1000_init_nvm_ops_generic");
48 /* Initialize function pointers */
49 nvm->ops.init_params = e1000_null_ops_generic;
50 nvm->ops.acquire = e1000_null_ops_generic;
51 nvm->ops.read = e1000_null_read_nvm;
52 nvm->ops.release = e1000_null_nvm_generic;
53 nvm->ops.reload = e1000_reload_nvm_generic;
54 nvm->ops.update = e1000_null_ops_generic;
55 nvm->ops.valid_led_default = e1000_null_led_default;
56 nvm->ops.validate = e1000_null_ops_generic;
57 nvm->ops.write = e1000_null_write_nvm;
61 * e1000_null_nvm_read - No-op function, return 0
62 * @hw: pointer to the HW structure
64 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
66 DEBUGFUNC("e1000_null_read_nvm");
71 * e1000_null_nvm_generic - No-op function, return void
72 * @hw: pointer to the HW structure
74 void e1000_null_nvm_generic(struct e1000_hw *hw)
76 DEBUGFUNC("e1000_null_nvm_generic");
81 * e1000_null_led_default - No-op function, return 0
82 * @hw: pointer to the HW structure
84 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
86 DEBUGFUNC("e1000_null_led_default");
91 * e1000_null_write_nvm - No-op function, return 0
92 * @hw: pointer to the HW structure
94 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
96 DEBUGFUNC("e1000_null_write_nvm");
101 * e1000_raise_eec_clk - Raise EEPROM clock
102 * @hw: pointer to the HW structure
103 * @eecd: pointer to the EEPROM
105 * Enable/Raise the EEPROM clock bit.
107 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
109 *eecd = *eecd | E1000_EECD_SK;
110 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
111 E1000_WRITE_FLUSH(hw);
112 usec_delay(hw->nvm.delay_usec);
116 * e1000_lower_eec_clk - Lower EEPROM clock
117 * @hw: pointer to the HW structure
118 * @eecd: pointer to the EEPROM
120 * Clear/Lower the EEPROM clock bit.
122 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
124 *eecd = *eecd & ~E1000_EECD_SK;
125 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
126 E1000_WRITE_FLUSH(hw);
127 usec_delay(hw->nvm.delay_usec);
131 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
132 * @hw: pointer to the HW structure
133 * @data: data to send to the EEPROM
134 * @count: number of bits to shift out
136 * We need to shift 'count' bits out to the EEPROM. So, the value in the
137 * "data" parameter will be shifted out to the EEPROM one bit at a time.
138 * In order to do this, "data" must be broken down into bits.
140 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
146 DEBUGFUNC("e1000_shift_out_eec_bits");
148 mask = 0x01 << (count - 1);
149 if (nvm->type == e1000_nvm_eeprom_microwire)
150 eecd &= ~E1000_EECD_DO;
152 if (nvm->type == e1000_nvm_eeprom_spi)
153 eecd |= E1000_EECD_DO;
156 eecd &= ~E1000_EECD_DI;
159 eecd |= E1000_EECD_DI;
161 E1000_WRITE_REG(hw, E1000_EECD, eecd);
162 E1000_WRITE_FLUSH(hw);
164 usec_delay(nvm->delay_usec);
166 e1000_raise_eec_clk(hw, &eecd);
167 e1000_lower_eec_clk(hw, &eecd);
172 eecd &= ~E1000_EECD_DI;
173 E1000_WRITE_REG(hw, E1000_EECD, eecd);
177 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
178 * @hw: pointer to the HW structure
179 * @count: number of bits to shift in
181 * In order to read a register from the EEPROM, we need to shift 'count' bits
182 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
183 * the EEPROM (setting the SK bit), and then reading the value of the data out
184 * "DO" bit. During this "shifting in" process the data in "DI" bit should
187 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
193 DEBUGFUNC("e1000_shift_in_eec_bits");
195 eecd = E1000_READ_REG(hw, E1000_EECD);
197 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
200 for (i = 0; i < count; i++) {
202 e1000_raise_eec_clk(hw, &eecd);
204 eecd = E1000_READ_REG(hw, E1000_EECD);
206 eecd &= ~E1000_EECD_DI;
207 if (eecd & E1000_EECD_DO)
210 e1000_lower_eec_clk(hw, &eecd);
217 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
218 * @hw: pointer to the HW structure
219 * @ee_reg: EEPROM flag for polling
221 * Polls the EEPROM status bit for either read or write completion based
222 * upon the value of 'ee_reg'.
224 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
226 u32 attempts = 100000;
228 s32 ret_val = -E1000_ERR_NVM;
230 DEBUGFUNC("e1000_poll_eerd_eewr_done");
232 for (i = 0; i < attempts; i++) {
233 if (ee_reg == E1000_NVM_POLL_READ)
234 reg = E1000_READ_REG(hw, E1000_EERD);
236 reg = E1000_READ_REG(hw, E1000_EEWR);
238 if (reg & E1000_NVM_RW_REG_DONE) {
239 ret_val = E1000_SUCCESS;
250 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
251 * @hw: pointer to the HW structure
253 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
254 * Return successful if access grant bit set, else clear the request for
255 * EEPROM access and return -E1000_ERR_NVM (-1).
257 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
259 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
260 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
261 s32 ret_val = E1000_SUCCESS;
263 DEBUGFUNC("e1000_acquire_nvm_generic");
265 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
266 eecd = E1000_READ_REG(hw, E1000_EECD);
269 if (eecd & E1000_EECD_GNT)
272 eecd = E1000_READ_REG(hw, E1000_EECD);
277 eecd &= ~E1000_EECD_REQ;
278 E1000_WRITE_REG(hw, E1000_EECD, eecd);
279 DEBUGOUT("Could not acquire NVM grant\n");
280 ret_val = -E1000_ERR_NVM;
287 * e1000_standby_nvm - Return EEPROM to standby state
288 * @hw: pointer to the HW structure
290 * Return the EEPROM to a standby state.
292 static void e1000_standby_nvm(struct e1000_hw *hw)
294 struct e1000_nvm_info *nvm = &hw->nvm;
295 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
297 DEBUGFUNC("e1000_standby_nvm");
299 if (nvm->type == e1000_nvm_eeprom_microwire) {
300 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
301 E1000_WRITE_REG(hw, E1000_EECD, eecd);
302 E1000_WRITE_FLUSH(hw);
303 usec_delay(nvm->delay_usec);
305 e1000_raise_eec_clk(hw, &eecd);
308 eecd |= E1000_EECD_CS;
309 E1000_WRITE_REG(hw, E1000_EECD, eecd);
310 E1000_WRITE_FLUSH(hw);
311 usec_delay(nvm->delay_usec);
313 e1000_lower_eec_clk(hw, &eecd);
315 if (nvm->type == e1000_nvm_eeprom_spi) {
316 /* Toggle CS to flush commands */
317 eecd |= E1000_EECD_CS;
318 E1000_WRITE_REG(hw, E1000_EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 usec_delay(nvm->delay_usec);
321 eecd &= ~E1000_EECD_CS;
322 E1000_WRITE_REG(hw, E1000_EECD, eecd);
323 E1000_WRITE_FLUSH(hw);
324 usec_delay(nvm->delay_usec);
329 * e1000_stop_nvm - Terminate EEPROM command
330 * @hw: pointer to the HW structure
332 * Terminates the current command by inverting the EEPROM's chip select pin.
334 void e1000_stop_nvm(struct e1000_hw *hw)
338 DEBUGFUNC("e1000_stop_nvm");
340 eecd = E1000_READ_REG(hw, E1000_EECD);
341 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
343 eecd |= E1000_EECD_CS;
344 e1000_lower_eec_clk(hw, &eecd);
345 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
346 /* CS on Microwire is active-high */
347 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
348 E1000_WRITE_REG(hw, E1000_EECD, eecd);
349 e1000_raise_eec_clk(hw, &eecd);
350 e1000_lower_eec_clk(hw, &eecd);
355 * e1000_release_nvm_generic - Release exclusive access to EEPROM
356 * @hw: pointer to the HW structure
358 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
360 void e1000_release_nvm_generic(struct e1000_hw *hw)
364 DEBUGFUNC("e1000_release_nvm_generic");
368 eecd = E1000_READ_REG(hw, E1000_EECD);
369 eecd &= ~E1000_EECD_REQ;
370 E1000_WRITE_REG(hw, E1000_EECD, eecd);
374 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
375 * @hw: pointer to the HW structure
377 * Setups the EEPROM for reading and writing.
379 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
381 struct e1000_nvm_info *nvm = &hw->nvm;
382 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
383 s32 ret_val = E1000_SUCCESS;
387 DEBUGFUNC("e1000_ready_nvm_eeprom");
389 if (nvm->type == e1000_nvm_eeprom_microwire) {
390 /* Clear SK and DI */
391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 eecd |= E1000_EECD_CS;
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 if (nvm->type == e1000_nvm_eeprom_spi) {
398 /* Clear SK and CS */
399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
400 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 timeout = NVM_MAX_RETRY_SPI;
405 * Read "Status Register" repeatedly until the LSB is cleared.
406 * The EEPROM will signal that the command has been completed
407 * by clearing bit 0 of the internal status register. If it's
408 * not cleared within 'timeout', then error out.
411 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
412 hw->nvm.opcode_bits);
413 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
414 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
418 e1000_standby_nvm(hw);
423 DEBUGOUT("SPI NVM Status error\n");
424 ret_val = -E1000_ERR_NVM;
434 * e1000_read_nvm_spi - Read EEPROM's using SPI
435 * @hw: pointer to the HW structure
436 * @offset: offset of word in the EEPROM to read
437 * @words: number of words to read
438 * @data: word read from the EEPROM
440 * Reads a 16 bit word from the EEPROM.
442 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
444 struct e1000_nvm_info *nvm = &hw->nvm;
448 u8 read_opcode = NVM_READ_OPCODE_SPI;
450 DEBUGFUNC("e1000_read_nvm_spi");
453 * A check for invalid values: offset too large, too many words,
454 * and not enough words.
456 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
458 DEBUGOUT("nvm parameter(s) out of bounds\n");
459 ret_val = -E1000_ERR_NVM;
463 ret_val = nvm->ops.acquire(hw);
467 ret_val = e1000_ready_nvm_eeprom(hw);
471 e1000_standby_nvm(hw);
473 if ((nvm->address_bits == 8) && (offset >= 128))
474 read_opcode |= NVM_A8_OPCODE_SPI;
476 /* Send the READ command (opcode + addr) */
477 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
478 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
481 * Read the data. SPI NVMs increment the address with each byte
482 * read and will roll over if reading beyond the end. This allows
483 * us to read the whole NVM from any offset
485 for (i = 0; i < words; i++) {
486 word_in = e1000_shift_in_eec_bits(hw, 16);
487 data[i] = (word_in >> 8) | (word_in << 8);
491 nvm->ops.release(hw);
498 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
499 * @hw: pointer to the HW structure
500 * @offset: offset of word in the EEPROM to read
501 * @words: number of words to read
502 * @data: word read from the EEPROM
504 * Reads a 16 bit word from the EEPROM.
506 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
509 struct e1000_nvm_info *nvm = &hw->nvm;
512 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
514 DEBUGFUNC("e1000_read_nvm_microwire");
517 * A check for invalid values: offset too large, too many words,
518 * and not enough words.
520 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
522 DEBUGOUT("nvm parameter(s) out of bounds\n");
523 ret_val = -E1000_ERR_NVM;
527 ret_val = nvm->ops.acquire(hw);
531 ret_val = e1000_ready_nvm_eeprom(hw);
535 for (i = 0; i < words; i++) {
536 /* Send the READ command (opcode + addr) */
537 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
538 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
542 * Read the data. For microwire, each word requires the
543 * overhead of setup and tear-down.
545 data[i] = e1000_shift_in_eec_bits(hw, 16);
546 e1000_standby_nvm(hw);
550 nvm->ops.release(hw);
557 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
558 * @hw: pointer to the HW structure
559 * @offset: offset of word in the EEPROM to read
560 * @words: number of words to read
561 * @data: word read from the EEPROM
563 * Reads a 16 bit word from the EEPROM using the EERD register.
565 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
567 struct e1000_nvm_info *nvm = &hw->nvm;
569 s32 ret_val = E1000_SUCCESS;
571 DEBUGFUNC("e1000_read_nvm_eerd");
574 * A check for invalid values: offset too large, too many words,
575 * too many words for the offset, and not enough words.
577 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
579 DEBUGOUT("nvm parameter(s) out of bounds\n");
580 ret_val = -E1000_ERR_NVM;
584 for (i = 0; i < words; i++) {
585 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
586 E1000_NVM_RW_REG_START;
588 E1000_WRITE_REG(hw, E1000_EERD, eerd);
589 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
593 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
594 E1000_NVM_RW_REG_DATA);
602 * e1000_write_nvm_spi - Write to EEPROM using SPI
603 * @hw: pointer to the HW structure
604 * @offset: offset within the EEPROM to be written to
605 * @words: number of words to write
606 * @data: 16 bit word(s) to be written to the EEPROM
608 * Writes data to EEPROM at offset using SPI interface.
610 * If e1000_update_nvm_checksum is not called after this function , the
611 * EEPROM will most likely contain an invalid checksum.
613 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
615 struct e1000_nvm_info *nvm = &hw->nvm;
619 DEBUGFUNC("e1000_write_nvm_spi");
622 * A check for invalid values: offset too large, too many words,
623 * and not enough words.
625 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
627 DEBUGOUT("nvm parameter(s) out of bounds\n");
628 ret_val = -E1000_ERR_NVM;
632 ret_val = nvm->ops.acquire(hw);
636 while (widx < words) {
637 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
639 ret_val = e1000_ready_nvm_eeprom(hw);
643 e1000_standby_nvm(hw);
645 /* Send the WRITE ENABLE command (8 bit opcode) */
646 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
649 e1000_standby_nvm(hw);
652 * Some SPI eeproms use the 8th address bit embedded in the
655 if ((nvm->address_bits == 8) && (offset >= 128))
656 write_opcode |= NVM_A8_OPCODE_SPI;
658 /* Send the Write command (8-bit opcode + addr) */
659 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
660 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
663 /* Loop to allow for up to whole page write of eeprom */
664 while (widx < words) {
665 u16 word_out = data[widx];
666 word_out = (word_out >> 8) | (word_out << 8);
667 e1000_shift_out_eec_bits(hw, word_out, 16);
670 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
671 e1000_standby_nvm(hw);
679 nvm->ops.release(hw);
686 * e1000_write_nvm_microwire - Writes EEPROM using microwire
687 * @hw: pointer to the HW structure
688 * @offset: offset within the EEPROM to be written to
689 * @words: number of words to write
690 * @data: 16 bit word(s) to be written to the EEPROM
692 * Writes data to EEPROM at offset using microwire interface.
694 * If e1000_update_nvm_checksum is not called after this function , the
695 * EEPROM will most likely contain an invalid checksum.
697 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
700 struct e1000_nvm_info *nvm = &hw->nvm;
703 u16 words_written = 0;
706 DEBUGFUNC("e1000_write_nvm_microwire");
709 * A check for invalid values: offset too large, too many words,
710 * and not enough words.
712 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
714 DEBUGOUT("nvm parameter(s) out of bounds\n");
715 ret_val = -E1000_ERR_NVM;
719 ret_val = nvm->ops.acquire(hw);
723 ret_val = e1000_ready_nvm_eeprom(hw);
727 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
728 (u16)(nvm->opcode_bits + 2));
730 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
732 e1000_standby_nvm(hw);
734 while (words_written < words) {
735 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
738 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
741 e1000_shift_out_eec_bits(hw, data[words_written], 16);
743 e1000_standby_nvm(hw);
745 for (widx = 0; widx < 200; widx++) {
746 eecd = E1000_READ_REG(hw, E1000_EECD);
747 if (eecd & E1000_EECD_DO)
753 DEBUGOUT("NVM Write did not complete\n");
754 ret_val = -E1000_ERR_NVM;
758 e1000_standby_nvm(hw);
763 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
764 (u16)(nvm->opcode_bits + 2));
766 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
769 nvm->ops.release(hw);
776 * e1000_read_pba_num_generic - Read device part number
777 * @hw: pointer to the HW structure
778 * @pba_num: pointer to device part number
780 * Reads the product board assembly (PBA) number from the EEPROM and stores
781 * the value in pba_num.
783 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
788 DEBUGFUNC("e1000_read_pba_num_generic");
790 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
792 DEBUGOUT("NVM Read Error\n");
795 *pba_num = (u32)(nvm_data << 16);
797 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
799 DEBUGOUT("NVM Read Error\n");
802 *pba_num |= nvm_data;
809 * e1000_read_mac_addr_generic - Read device MAC address
810 * @hw: pointer to the HW structure
812 * Reads the device MAC address from the EEPROM and stores the value.
813 * Since devices with two ports use the same EEPROM, we increment the
814 * last bit in the MAC address for the second port.
816 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
818 s32 ret_val = E1000_SUCCESS;
819 u16 offset, nvm_data, i;
821 DEBUGFUNC("e1000_read_mac_addr");
823 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
825 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
827 DEBUGOUT("NVM Read Error\n");
830 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
831 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
834 /* Flip last bit of mac address if we're on second port */
835 if (hw->bus.func == E1000_FUNC_1)
836 hw->mac.perm_addr[5] ^= 1;
838 for (i = 0; i < ETH_ADDR_LEN; i++)
839 hw->mac.addr[i] = hw->mac.perm_addr[i];
846 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
847 * @hw: pointer to the HW structure
849 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
850 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
852 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
854 s32 ret_val = E1000_SUCCESS;
858 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
860 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
861 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
863 DEBUGOUT("NVM Read Error\n");
866 checksum += nvm_data;
869 if (checksum != (u16) NVM_SUM) {
870 DEBUGOUT("NVM Checksum Invalid\n");
871 ret_val = -E1000_ERR_NVM;
880 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
881 * @hw: pointer to the HW structure
883 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
884 * up to the checksum. Then calculates the EEPROM checksum and writes the
885 * value to the EEPROM.
887 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
893 DEBUGFUNC("e1000_update_nvm_checksum");
895 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
896 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
898 DEBUGOUT("NVM Read Error while updating checksum.\n");
901 checksum += nvm_data;
903 checksum = (u16) NVM_SUM - checksum;
904 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
906 DEBUGOUT("NVM Write Error while updating checksum.\n");
913 * e1000_reload_nvm_generic - Reloads EEPROM
914 * @hw: pointer to the HW structure
916 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
917 * extended control register.
919 void e1000_reload_nvm_generic(struct e1000_hw *hw)
923 DEBUGFUNC("e1000_reload_nvm_generic");
926 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
927 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
928 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
929 E1000_WRITE_FLUSH(hw);