2 * Copyright (c) 2011-2012 Stefan Bethke.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/param.h>
31 #include <sys/errno.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/socket.h>
35 #include <sys/sockio.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
40 #include <net/if_arp.h>
41 #include <net/ethernet.h>
42 #include <net/if_dl.h>
43 #include <net/if_media.h>
44 #include <net/if_types.h>
46 #include <machine/bus.h>
47 #include <dev/iicbus/iic.h>
48 #include <dev/iicbus/iiconf.h>
49 #include <dev/iicbus/iicbus.h>
50 #include <dev/mii/mii.h>
51 #include <dev/mii/miivar.h>
53 #include <dev/etherswitch/etherswitch.h>
54 #include <dev/etherswitch/rtl8366/rtl8366rbvar.h>
56 #include "iicbus_if.h"
57 #include "miibus_if.h"
58 #include "etherswitch_if.h"
61 struct rtl8366rb_softc {
62 struct mtx sc_mtx; /* serialize access to softc */
63 int smi_acquired; /* serialize access to SMI/I2C bus */
64 struct mtx callout_mtx; /* serialize callout */
66 int vid[RTL8366RB_NUM_VLANS];
67 char *ifname[RTL8366RB_NUM_PHYS];
68 device_t miibus[RTL8366RB_NUM_PHYS];
69 struct ifnet *ifp[RTL8366RB_NUM_PHYS];
70 struct callout callout_tick;
73 static etherswitch_info_t etherswitch_info = {
74 .es_nports = RTL8366RB_NUM_PORTS,
75 .es_nvlangroups = RTL8366RB_NUM_VLANS,
76 .es_name = "Realtek RTL8366RB"
79 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
80 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
81 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what))
82 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx)
87 #define RTL_SMI_ACQUIRED 1
88 #define RTL_SMI_ACQUIRED_ASSERT(_sc) \
89 KASSERT((_sc)->smi_acquired == RTL_SMI_ACQUIRED, ("smi must be acquired @%s", __FUNCTION__))
92 #define DPRINTF(dev, args...) device_printf(dev, args)
93 #define DEVERR(dev, err, fmt, args...) do { \
94 if (err != 0) device_printf(dev, fmt, err, args); \
96 #define DEBUG_INCRVAR(var) do { \
100 static int callout_blocked = 0;
101 static int iic_select_retries = 0;
102 static int phy_access_retries = 0;
103 static SYSCTL_NODE(_debug, OID_AUTO, rtl8366rb, CTLFLAG_RD, 0, "rtl8366rb");
104 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, callout_blocked, CTLFLAG_RW, &callout_blocked, 0,
105 "number of times the callout couldn't acquire the bus");
106 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, iic_select_retries, CTLFLAG_RW, &iic_select_retries, 0,
107 "number of times the I2C bus selection had to be retried");
108 SYSCTL_INT(_debug_rtl8366rb, OID_AUTO, phy_access_retries, CTLFLAG_RW, &phy_access_retries, 0,
109 "number of times PHY register access had to be retried");
111 #define DPRINTF(dev, args...)
112 #define DEVERR(dev, err, fmt, args...)
113 #define DEBUG_INCRVAR(var)
116 static int smi_probe(device_t dev);
117 static int smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep);
118 static int smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep);
119 static int smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep);
120 static void rtl8366rb_tick(void *arg);
121 static int rtl8366rb_ifmedia_upd(struct ifnet *);
122 static void rtl8366rb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125 rtl8366rb_identify(driver_t *driver, device_t parent)
128 struct iicbus_ivar *devi;
130 if (device_find_child(parent, "rtl8366rb", -1) == NULL) {
131 child = BUS_ADD_CHILD(parent, 0, "rtl8366rb", -1);
132 devi = IICBUS_IVAR(child);
133 devi->addr = RTL8366RB_IIC_ADDR;
138 rtl8366rb_probe(device_t dev)
140 if (smi_probe(dev) != 0)
142 device_set_desc(dev, "RTL8366RB Ethernet Switch Controller");
143 return (BUS_PROBE_DEFAULT);
147 rtl8366rb_init(device_t dev)
149 /* Initialisation for TL-WR1043ND */
150 smi_rmw(dev, RTL8366RB_RCR,
151 RTL8366RB_RCR_HARD_RESET,
152 RTL8366RB_RCR_HARD_RESET, RTL_WAITOK);
154 /* Enable 16 VLAN mode */
155 smi_rmw(dev, RTL8366RB_SGCR,
156 RTL8366RB_SGCR_EN_VLAN | RTL8366RB_SGCR_EN_VLAN_4KTB,
157 RTL8366RB_SGCR_EN_VLAN, RTL_WAITOK);
158 /* remove port 0 form VLAN 0 */
159 smi_rmw(dev, RTL8366RB_VMCR(RTL8366RB_VMCR_MU_REG, 0),
160 (1 << 0), 0, RTL_WAITOK);
161 /* add port 0 untagged and port 5 tagged to VLAN 1 */
162 smi_rmw(dev, RTL8366RB_VMCR(RTL8366RB_VMCR_MU_REG, 1),
163 ((1 << 5 | 1 << 0) << RTL8366RB_VMCR_MU_MEMBER_SHIFT)
164 | ((1 << 5 | 1 << 0) << RTL8366RB_VMCR_MU_UNTAG_SHIFT),
165 ((1 << 5 | 1 << 0) << RTL8366RB_VMCR_MU_MEMBER_SHIFT
166 | ((1 << 0) << RTL8366RB_VMCR_MU_UNTAG_SHIFT)),
168 /* set PVLAN 1 for port 0 */
169 smi_rmw(dev, RTL8366RB_PVCR_REG(0),
170 RTL8366RB_PVCR_VAL(0, RTL8366RB_PVCR_PORT_MASK),
171 RTL8366RB_PVCR_VAL(0, 1), RTL_WAITOK);
175 rtl8366rb_attach(device_t dev)
178 struct rtl8366rb_softc *sc;
183 sc = device_get_softc(dev);
184 bzero(sc, sizeof(*sc));
186 mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF);
187 sc->smi_acquired = 0;
188 mtx_init(&sc->callout_mtx, "rtl8366rbcallout", NULL, MTX_DEF);
191 smi_read(dev, RTL8366RB_CVCR, &rev, RTL_WAITOK);
192 device_printf(dev, "rev. %d\n", rev & 0x000f);
194 /* attach miibus and phys */
195 /* PHYs need an interface, so we generate a dummy one */
196 for (i = 0; i < RTL8366RB_NUM_PHYS; i++) {
197 sc->ifp[i] = if_alloc(IFT_ETHER);
198 sc->ifp[i]->if_softc = sc;
199 sc->ifp[i]->if_flags |= IFF_UP | IFF_BROADCAST | IFF_DRV_RUNNING
201 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(dev));
202 sc->ifname[i] = malloc(strlen(name)+1, M_DEVBUF, M_WAITOK);
203 bcopy(name, sc->ifname[i], strlen(name)+1);
204 if_initname(sc->ifp[i], sc->ifname[i], i);
205 err = mii_attach(dev, &sc->miibus[i], sc->ifp[i], rtl8366rb_ifmedia_upd, \
206 rtl8366rb_ifmedia_sts, BMSR_DEFCAPMASK, \
207 i, MII_OFFSET_ANY, 0);
209 device_printf(dev, "attaching PHY %d failed\n", i);
214 bus_generic_probe(dev);
215 bus_enumerate_hinted_children(dev);
216 err = bus_generic_attach(dev);
220 callout_init_mtx(&sc->callout_tick, &sc->callout_mtx, 0);
227 rtl8366rb_detach(device_t dev)
229 struct rtl8366rb_softc *sc = device_get_softc(dev);
232 for (i=0; i < RTL8366RB_NUM_PHYS; i++) {
234 device_delete_child(dev, sc->miibus[i]);
235 if (sc->ifp[i] != NULL)
237 free(sc->ifname[i], M_DEVBUF);
239 bus_generic_detach(dev);
240 callout_drain(&sc->callout_tick);
241 mtx_destroy(&sc->callout_mtx);
242 mtx_destroy(&sc->sc_mtx);
248 rtl8366rb_update_ifmedia(int portstatus, u_int *media_status, u_int *media_active)
250 *media_active = IFM_ETHER;
251 *media_status = IFM_AVALID;
252 if ((portstatus & RTL8366RB_PLSR_LINK) != 0)
253 *media_status |= IFM_ACTIVE;
255 *media_active |= IFM_NONE;
258 switch (portstatus & RTL8366RB_PLSR_SPEED_MASK) {
259 case RTL8366RB_PLSR_SPEED_10:
260 *media_active |= IFM_10_T;
262 case RTL8366RB_PLSR_SPEED_100:
263 *media_active |= IFM_100_TX;
265 case RTL8366RB_PLSR_SPEED_1000:
266 *media_active |= IFM_1000_T;
269 if ((portstatus & RTL8366RB_PLSR_FULLDUPLEX) == 0)
270 *media_active |= IFM_FDX;
272 *media_active |= IFM_HDX;
273 if ((portstatus & RTL8366RB_PLSR_TXPAUSE) != 0)
274 *media_active |= IFM_ETH_TXPAUSE;
275 if ((portstatus & RTL8366RB_PLSR_RXPAUSE) != 0)
276 *media_active |= IFM_ETH_RXPAUSE;
280 rtl833rb_miipollstat(struct rtl8366rb_softc *sc)
283 struct mii_data *mii;
284 struct mii_softc *miisc;
288 for (i = 0; i < RTL8366RB_NUM_PHYS; i++) {
289 mii = device_get_softc(sc->miibus[i]);
291 if (smi_read(sc->dev, RTL8366RB_PLSR_BASE + i/2, &value, RTL_NOWAIT) != 0) {
292 DEBUG_INCRVAR(callout_blocked);
295 portstatus = value & 0xff;
297 portstatus = (value >> 8) & 0xff;
299 rtl8366rb_update_ifmedia(portstatus, &mii->mii_media_status, &mii->mii_media_active);
300 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
301 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) != miisc->mii_inst)
303 mii_phy_update(miisc, MII_POLLSTAT);
309 rtl8366rb_tick(void *arg)
311 struct rtl8366rb_softc *sc = arg;
313 rtl833rb_miipollstat(sc);
314 callout_reset(&sc->callout_tick, hz, rtl8366rb_tick, sc);
318 smi_probe(device_t dev)
320 device_t iicbus, iicha;
326 bytes[0] = RTL8366RB_CIR & 0xff;
327 bytes[1] = (RTL8366RB_CIR >> 8) & 0xff;
328 iicbus = device_get_parent(dev);
329 iicha = device_get_parent(iicbus);
330 iicbus_reset(iicbus, IIC_FASTEST, RTL8366RB_IIC_ADDR, NULL);
334 * we go directly to the host adapter because iicbus.c
335 * only issues a stop on a bus that was successfully started.
338 err = iicbus_request_bus(iicbus, dev, IIC_WAIT);
341 err = iicbus_start(iicbus, RTL8366RB_IIC_ADDR | RTL_IICBUS_READ, RTL_IICBUS_TIMEOUT);
344 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT);
347 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0);
350 chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
351 DPRINTF(dev, "chip id 0x%04x\n", chipid);
352 if (chipid != RTL8366RB_CIR_ID8366RB)
356 iicbus_release_bus(iicbus, dev);
357 return (err == 0 ? 0 : ENXIO);
361 smi_acquire(struct rtl8366rb_softc *sc, int sleep)
364 if (sleep == RTL_WAITOK)
367 if (RTL_TRYLOCK(sc) == 0)
368 return (EWOULDBLOCK);
369 if (sc->smi_acquired == RTL_SMI_ACQUIRED)
372 r = iicbus_request_bus(device_get_parent(sc->dev), sc->dev, \
373 sleep == RTL_WAITOK ? IIC_WAIT : IIC_DONTWAIT);
375 sc->smi_acquired = RTL_SMI_ACQUIRED;
382 smi_release(struct rtl8366rb_softc *sc, int sleep)
384 if (sleep == RTL_WAITOK)
387 if (RTL_TRYLOCK(sc) == 0)
388 return (EWOULDBLOCK);
389 RTL_SMI_ACQUIRED_ASSERT(sc);
390 iicbus_release_bus(device_get_parent(sc->dev), sc->dev);
391 sc->smi_acquired = 0;
397 smi_select(device_t dev, int op, int sleep)
400 device_t iicbus = device_get_parent(dev);
401 struct iicbus_ivar *devi = IICBUS_IVAR(dev);
402 int slave = devi->addr;
404 RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev));
406 * The chip does not use clock stretching when it is busy,
407 * instead ignoring the command. Retry a few times.
409 for (i = RTL_IICBUS_RETRIES; i--; ) {
410 err = iicbus_start(iicbus, slave | op, RTL_IICBUS_TIMEOUT);
411 if (err != IIC_ENOACK)
413 if (sleep == RTL_WAITOK) {
414 DEBUG_INCRVAR(iic_select_retries);
415 pause("smi_select", RTL_IICBUS_RETRY_SLEEP);
423 smi_read_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t *data, int sleep)
426 device_t iicbus = device_get_parent(sc->dev);
430 RTL_SMI_ACQUIRED_ASSERT(sc);
431 bytes[0] = addr & 0xff;
432 bytes[1] = (addr >> 8) & 0xff;
433 err = smi_select(sc->dev, RTL_IICBUS_READ, sleep);
436 err = iicbus_write(iicbus, bytes, 2, &xferd, RTL_IICBUS_TIMEOUT);
439 err = iicbus_read(iicbus, bytes, 2, &xferd, IIC_LAST_READ, 0);
442 *data = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
450 smi_write_locked(struct rtl8366rb_softc *sc, uint16_t addr, uint16_t data, int sleep)
453 device_t iicbus = device_get_parent(sc->dev);
457 RTL_SMI_ACQUIRED_ASSERT(sc);
458 bytes[0] = addr & 0xff;
459 bytes[1] = (addr >> 8) & 0xff;
460 bytes[2] = data & 0xff;
461 bytes[3] = (data >> 8) & 0xff;
463 err = smi_select(sc->dev, RTL_IICBUS_WRITE, sleep);
465 err = iicbus_write(iicbus, bytes, 4, &xferd, RTL_IICBUS_TIMEOUT);
472 smi_read(device_t dev, uint16_t addr, uint16_t *data, int sleep)
474 struct rtl8366rb_softc *sc = device_get_softc(dev);
477 err = smi_acquire(sc, sleep);
480 err = smi_read_locked(sc, addr, data, sleep);
481 smi_release(sc, sleep);
482 DEVERR(dev, err, "smi_read()=%d: addr=%04x\n", addr);
483 return (err == 0 ? 0 : EIO);
487 smi_write(device_t dev, uint16_t addr, uint16_t data, int sleep)
489 struct rtl8366rb_softc *sc = device_get_softc(dev);
492 err = smi_acquire(sc, sleep);
495 err = smi_write_locked(sc, addr, data, sleep);
496 smi_release(sc, sleep);
497 DEVERR(dev, err, "smi_write()=%d: addr=%04x\n", addr);
498 return (err == 0 ? 0 : EIO);
502 smi_rmw(device_t dev, uint16_t addr, uint16_t mask, uint16_t data, int sleep)
504 struct rtl8366rb_softc *sc = device_get_softc(dev);
508 err = smi_acquire(sc, sleep);
512 err = smi_read_locked(sc, addr, &oldv, sleep);
517 err = smi_write_locked(sc, addr, newv, sleep);
520 smi_release(sc, sleep);
521 DEVERR(dev, err, "smi_rmw()=%d: addr=%04x\n", addr);
522 return (err == 0 ? 0 : EIO);
525 static etherswitch_info_t *
526 rtl_getinfo(device_t dev)
528 return (ðerswitch_info);
532 rtl_readreg(device_t dev, int reg)
536 smi_read(dev, reg, &data, RTL_WAITOK);
541 rtl_writereg(device_t dev, int reg, int value)
543 return (smi_write(dev, reg, value, RTL_WAITOK));
547 rtl_getport(device_t dev, etherswitch_port_t *p)
549 struct rtl8366rb_softc *sc;
551 struct mii_data *mii;
552 struct ifmediareq *ifmr = &p->es_ifmr;
556 if (p->es_port < 0 || p->es_port >= RTL8366RB_NUM_PORTS)
558 sc = device_get_softc(dev);
559 vlangroup = RTL8366RB_PVCR_GET(p->es_port,
560 rtl_readreg(dev, RTL8366RB_PVCR_REG(p->es_port)));
561 p->es_pvid = sc->vid[vlangroup];
563 if (p->es_port < RTL8366RB_NUM_PHYS) {
564 mii = device_get_softc(sc->miibus[p->es_port]);
565 ifm = &mii->mii_media;
566 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCGIFMEDIA);
570 /* fill in fixed values for CPU port */
572 smi_read(dev, RTL8366RB_PLSR_BASE + (RTL8366RB_NUM_PHYS)/2, &v, RTL_WAITOK);
573 v = v >> (8 * ((RTL8366RB_NUM_PHYS) % 2));
574 rtl8366rb_update_ifmedia(v, &ifmr->ifm_status, &ifmr->ifm_active);
575 ifmr->ifm_current = ifmr->ifm_active;
577 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
583 rtl_setport(device_t dev, etherswitch_port_t *p)
585 int i, err, vlangroup;
586 struct rtl8366rb_softc *sc;
588 struct mii_data *mii;
590 if (p->es_port < 0 || p->es_port >= RTL8366RB_NUM_PHYS)
592 sc = device_get_softc(dev);
594 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
595 if (sc->vid[i] == p->es_pvid) {
602 err = smi_rmw(dev, RTL8366RB_PVCR_REG(p->es_port),
603 RTL8366RB_PVCR_VAL(p->es_port, RTL8366RB_PVCR_PORT_MASK),
604 RTL8366RB_PVCR_VAL(p->es_port, vlangroup), RTL_WAITOK);
607 mii = device_get_softc(sc->miibus[p->es_port]);
608 ifm = &mii->mii_media;
609 err = ifmedia_ioctl(sc->ifp[p->es_port], &p->es_ifr, ifm, SIOCSIFMEDIA);
614 rtl_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
620 vmcr[i] = rtl_readreg(dev, RTL8366RB_VMCR(i, vg->es_vlangroup));
622 vg->es_vid = RTL8366RB_VMCR_VID(vmcr) | ETHERSWITCH_VID_VALID;
623 vg->es_member_ports = RTL8366RB_VMCR_MEMBER(vmcr);
624 vg->es_untagged_ports = RTL8366RB_VMCR_UNTAG(vmcr);
625 vg->es_fid = RTL8366RB_VMCR_FID(vmcr);
630 rtl_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
632 struct rtl8366rb_softc *sc;
633 int g = vg->es_vlangroup;
635 sc = device_get_softc(dev);
636 sc->vid[g] = vg->es_vid;
637 rtl_writereg(dev, RTL8366RB_VMCR(RTL8366RB_VMCR_DOT1Q_REG, g),
638 (vg->es_vid << RTL8366RB_VMCR_DOT1Q_VID_SHIFT) & RTL8366RB_VMCR_DOT1Q_VID_MASK);
639 rtl_writereg(dev, RTL8366RB_VMCR(RTL8366RB_VMCR_MU_REG, g),
640 ((vg->es_member_ports << RTL8366RB_VMCR_MU_MEMBER_SHIFT) & RTL8366RB_VMCR_MU_MEMBER_MASK) |
641 ((vg->es_untagged_ports << RTL8366RB_VMCR_MU_UNTAG_SHIFT) & RTL8366RB_VMCR_MU_UNTAG_MASK));
642 rtl_writereg(dev, RTL8366RB_VMCR(RTL8366RB_VMCR_FID_REG, g),
648 rtl_readphy(device_t dev, int phy, int reg)
650 struct rtl8366rb_softc *sc = device_get_softc(dev);
654 if (phy < 0 || phy >= RTL8366RB_NUM_PHYS)
656 if (reg < 0 || reg >= RTL8366RB_NUM_PHY_REG)
659 err = smi_acquire(sc, sleep);
662 for (i = RTL_IICBUS_RETRIES; i--; ) {
663 err = smi_write_locked(sc, RTL8366RB_PACR, RTL8366RB_PACR_READ, sleep);
665 err = smi_write_locked(sc, RTL8366RB_PHYREG(phy, 0, reg), 0, sleep);
667 err = smi_read_locked(sc, RTL8366RB_PADR, &data, sleep);
670 DEBUG_INCRVAR(phy_access_retries);
671 DPRINTF(dev, "rtl_readphy(): chip not responsive, retrying %d more times\n", i);
672 pause("rtl_readphy", RTL_IICBUS_RETRY_SLEEP);
674 smi_release(sc, sleep);
675 DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg);
680 rtl_writephy(device_t dev, int phy, int reg, int data)
682 struct rtl8366rb_softc *sc = device_get_softc(dev);
685 if (phy < 0 || phy >= RTL8366RB_NUM_PHYS)
687 if (reg < 0 || reg >= RTL8366RB_NUM_PHY_REG)
690 err = smi_acquire(sc, sleep);
693 for (i = RTL_IICBUS_RETRIES; i--; ) {
694 err = smi_write_locked(sc, RTL8366RB_PACR, RTL8366RB_PACR_WRITE, sleep);
696 err = smi_write_locked(sc, RTL8366RB_PHYREG(phy, 0, reg), data, sleep);
700 DEBUG_INCRVAR(phy_access_retries);
701 DPRINTF(dev, "rtl_writephy(): chip not responsive, retrying %d more tiems\n", i);
702 pause("rtl_writephy", RTL_IICBUS_RETRY_SLEEP);
704 smi_release(sc, sleep);
705 DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg);
706 return (err == 0 ? 0 : EIO);
710 rtl8366rb_ifmedia_upd(struct ifnet *ifp)
712 struct rtl8366rb_softc *sc = ifp->if_softc;
713 struct mii_data *mii = device_get_softc(sc->miibus[ifp->if_dunit]);
720 rtl8366rb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
722 struct rtl8366rb_softc *sc = ifp->if_softc;
723 struct mii_data *mii = device_get_softc(sc->miibus[ifp->if_dunit]);
726 ifmr->ifm_active = mii->mii_media_active;
727 ifmr->ifm_status = mii->mii_media_status;
731 static device_method_t rtl8366rb_methods[] = {
732 /* Device interface */
733 DEVMETHOD(device_identify, rtl8366rb_identify),
734 DEVMETHOD(device_probe, rtl8366rb_probe),
735 DEVMETHOD(device_attach, rtl8366rb_attach),
736 DEVMETHOD(device_detach, rtl8366rb_detach),
739 DEVMETHOD(bus_add_child, device_add_child_ordered),
742 DEVMETHOD(miibus_readreg, rtl_readphy),
743 DEVMETHOD(miibus_writereg, rtl_writephy),
745 /* etherswitch interface */
746 DEVMETHOD(etherswitch_getinfo, rtl_getinfo),
747 DEVMETHOD(etherswitch_readreg, rtl_readreg),
748 DEVMETHOD(etherswitch_writereg, rtl_writereg),
749 DEVMETHOD(etherswitch_readphyreg, rtl_readphy),
750 DEVMETHOD(etherswitch_writephyreg, rtl_writephy),
751 DEVMETHOD(etherswitch_getport, rtl_getport),
752 DEVMETHOD(etherswitch_setport, rtl_setport),
753 DEVMETHOD(etherswitch_getvgroup, rtl_getvgroup),
754 DEVMETHOD(etherswitch_setvgroup, rtl_setvgroup),
759 DEFINE_CLASS_0(rtl8366rb, rtl8366rb_driver, rtl8366rb_methods,
760 sizeof(struct rtl8366rb_softc));
761 static devclass_t rtl8366rb_devclass;
763 DRIVER_MODULE(rtl8366rb, iicbus, rtl8366rb_driver, rtl8366rb_devclass, 0, 0);
764 DRIVER_MODULE(miibus, rtl8366rb, miibus_driver, miibus_devclass, 0, 0);
765 DRIVER_MODULE(etherswitch, rtl8366rb, etherswitch_driver, etherswitch_devclass, 0, 0);
766 MODULE_VERSION(rtl8366rb, 1);
767 MODULE_DEPEND(rtl8366rb, iicbus, 1, 1, 1); /* XXX which versions? */
768 MODULE_DEPEND(rtl8366rb, miibus, 1, 1, 1); /* XXX which versions? */
769 MODULE_DEPEND(rtl8366rb, etherswitch, 1, 1, 1); /* XXX which versions? */