2 * Copyright (c) 1996, Javier MartÃn Rueda (jmrueda@diatel.upm.es)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * MAINTAINER: Matthew N. Dodd <winter@jurai.net>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Intel EtherExpress Pro/10, Pro/10+ Ethernet driver
40 * dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver.
41 * 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/sockio.h>
49 #include <sys/socket.h>
51 #include <sys/module.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/ethernet.h>
66 #include <netinet/in.h>
67 #include <netinet/if_ether.h>
70 #include <isa/isavar.h>
71 #include <isa/pnpvar.h>
73 #include <dev/ex/if_exreg.h>
74 #include <dev/ex/if_exvar.h>
81 static int debug_mask = 0;
82 # define DODEBUG(level, action) if (level & debug_mask) action
84 # define DODEBUG(level, action)
87 devclass_t ex_devclass;
90 { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 };
92 { 9, 3, 5, 10, 11, 0, 0, 0 };
94 char plus_irq2eemap[] =
95 { -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 };
96 u_char plus_ee2irqmap[] =
97 { 3, 4, 5, 7, 9, 10, 11, 12 };
99 /* Network Interface Functions */
100 static void ex_init(void *);
101 static void ex_start(struct ifnet *);
102 static int ex_ioctl(struct ifnet *, u_long, caddr_t);
103 static void ex_watchdog(struct ifnet *);
105 /* ifmedia Functions */
106 static int ex_ifmedia_upd(struct ifnet *);
107 static void ex_ifmedia_sts(struct ifnet *, struct ifmediareq *);
109 static int ex_get_media(struct ex_softc *);
111 static void ex_reset(struct ex_softc *);
112 static void ex_setmulti(struct ex_softc *);
114 static void ex_tx_intr(struct ex_softc *);
115 static void ex_rx_intr(struct ex_softc *);
118 ex_get_address(struct ex_softc *sc, u_char *enaddr)
122 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo);
123 enaddr[5] = eaddr_tmp & 0xff;
124 enaddr[4] = eaddr_tmp >> 8;
125 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid);
126 enaddr[3] = eaddr_tmp & 0xff;
127 enaddr[2] = eaddr_tmp >> 8;
128 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi);
129 enaddr[1] = eaddr_tmp & 0xff;
130 enaddr[0] = eaddr_tmp >> 8;
136 ex_card_type(u_char *enaddr)
138 if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9))
139 return (CARD_TYPE_EX_10_PLUS);
141 return (CARD_TYPE_EX_10);
145 * Caller is responsible for eventually calling
146 * ex_release_resources() on failure.
149 ex_alloc_resources(device_t dev)
151 struct ex_softc * sc = device_get_softc(dev);
154 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
155 &sc->ioport_rid, RF_ACTIVE);
157 device_printf(dev, "No I/O space?!\n");
161 sc->bst = rman_get_bustag(sc->ioport);
162 sc->bsh = rman_get_bushandle(sc->ioport);
164 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
168 device_printf(dev, "No IRQ?!\n");
178 ex_release_resources(device_t dev)
180 struct ex_softc * sc = device_get_softc(dev);
183 bus_teardown_intr(dev, sc->irq, sc->ih);
188 bus_release_resource(dev, SYS_RES_IOPORT,
189 sc->ioport_rid, sc->ioport);
194 bus_release_resource(dev, SYS_RES_IRQ,
195 sc->irq_rid, sc->irq);
206 ex_attach(device_t dev)
208 struct ex_softc * sc = device_get_softc(dev);
210 struct ifmedia * ifm;
213 ifp = sc->ifp = if_alloc(IFT_ETHER);
215 device_printf(dev, "can not if_alloc()\n");
218 /* work out which set of irq <-> internal tables to use */
219 if (ex_card_type(sc->enaddr) == CARD_TYPE_EX_10_PLUS) {
220 sc->irq2ee = plus_irq2eemap;
221 sc->ee2irq = plus_ee2irqmap;
223 sc->irq2ee = irq2eemap;
224 sc->ee2irq = ee2irqmap;
227 sc->mem_size = CARD_RAM_SIZE; /* XXX This should be read from the card itself. */
230 * Initialize the ifnet structure.
233 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
234 ifp->if_mtu = ETHERMTU;
235 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST |
237 ifp->if_start = ex_start;
238 ifp->if_ioctl = ex_ioctl;
239 ifp->if_watchdog = ex_watchdog;
240 ifp->if_init = ex_init;
241 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
243 ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts);
245 temp = ex_eeprom_read(sc, EE_W5);
246 if (temp & EE_W5_PORT_TPE)
247 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
248 if (temp & EE_W5_PORT_BNC)
249 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
250 if (temp & EE_W5_PORT_AUI)
251 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
253 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
254 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL);
255 ifmedia_set(&sc->ifmedia, ex_get_media(sc));
258 ifm->ifm_media = ifm->ifm_cur->ifm_media;
262 * Attach the interface.
264 ether_ifattach(ifp, sc->enaddr);
270 ex_detach(device_t dev)
275 sc = device_get_softc(dev);
280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
283 ex_release_resources(dev);
291 struct ex_softc * sc = (struct ex_softc *) xsc;
292 struct ifnet * ifp = sc->ifp;
295 unsigned short temp_reg;
297 DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname););
303 * Load the ethernet address into the card.
305 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
306 temp_reg = CSR_READ_1(sc, EEPROM_REG);
307 if (temp_reg & Trnoff_Enable) {
308 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
310 for (i = 0; i < ETHER_ADDR_LEN; i++) {
311 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
314 * - Setup transmit chaining and discard bad received frames.
317 * - Set receiving mode.
320 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
321 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
322 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
323 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
324 CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | sc->irq2ee[sc->irq_no]);
327 * Divide the available memory in the card into rcv and xmt buffers.
328 * By default, I use the first 3/4 of the memory for the rcv buffer,
329 * and the remaining 1/4 of the memory for the xmt buffer.
331 sc->rx_mem_size = sc->mem_size * 3 / 4;
332 sc->tx_mem_size = sc->mem_size - sc->rx_mem_size;
333 sc->rx_lower_limit = 0x0000;
334 sc->rx_upper_limit = sc->rx_mem_size - 2;
335 sc->tx_lower_limit = sc->rx_mem_size;
336 sc->tx_upper_limit = sc->mem_size - 2;
337 CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
338 CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);
339 CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);
340 CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);
343 * Enable receive and transmit interrupts, and clear any pending int.
345 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
346 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
347 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
348 CSR_WRITE_1(sc, STATUS_REG, All_Int);
351 * Initialize receive and transmit ring buffers.
353 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
354 sc->rx_head = sc->rx_lower_limit;
355 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
356 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
357 sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
359 ifp->if_drv_flags |= IFF_DRV_RUNNING;
360 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
361 DODEBUG(Status, printf("OIDLE init\n"););
366 * Final reset of the board, and enable operation.
368 CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);
370 CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);
375 DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname););
380 ex_start(struct ifnet *ifp)
382 struct ex_softc * sc = ifp->if_softc;
383 int i, s, len, data_len, avail, dest, next;
384 unsigned char tmp16[2];
388 DODEBUG(Start_End, printf("ex_start%d: start\n", unit););
393 * Main loop: send outgoing packets to network card until there are no
394 * more packets left, or the card cannot accept any more yet.
396 while (((opkt = ifp->if_snd.ifq_head) != NULL) &&
397 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
400 * Ensure there is enough free transmit buffer space for
401 * this packet, including its header. Note: the header
402 * cannot wrap around the end of the transmit buffer and
403 * must be kept together, so we allow space for twice the
404 * length of the header, just in case.
407 for (len = 0, m = opkt; m != NULL; m = m->m_next) {
413 DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len););
416 len += XMT_HEADER_LEN + 1;
418 len += XMT_HEADER_LEN;
421 if ((i = sc->tx_tail - sc->tx_head) >= 0) {
422 avail = sc->tx_mem_size - i;
427 DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail););
429 if (avail >= len + XMT_HEADER_LEN) {
430 IF_DEQUEUE(&ifp->if_snd, opkt);
434 * Disable rx and tx interrupts, to avoid corruption
435 * of the host address register by interrupt service
437 * XXX Is this necessary with splimp() enabled?
439 CSR_WRITE_1(sc, MASK_REG, All_Int);
443 * Compute the start and end addresses of this
444 * frame in the tx buffer.
449 if (next > sc->tx_upper_limit) {
450 if ((sc->tx_upper_limit + 2 - sc->tx_tail) <=
452 dest = sc->tx_lower_limit;
455 next = sc->tx_lower_limit +
456 next - sc->tx_upper_limit - 2;
461 * Build the packet frame in the card's ring buffer.
463 DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next););
465 CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
466 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
467 CSR_WRITE_2(sc, IO_PORT_REG, 0);
468 CSR_WRITE_2(sc, IO_PORT_REG, next);
469 CSR_WRITE_2(sc, IO_PORT_REG, data_len);
472 * Output the packet data to the card. Ensure all
473 * transfers are 16-bit wide, even if individual
474 * mbufs have odd length.
476 for (m = opkt, i = 0; m != NULL; m = m->m_next) {
477 DODEBUG(Sent_Pkts, printf("[%d]", m->m_len););
479 tmp16[1] = *(mtod(m, caddr_t));
480 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
481 (uint16_t *) tmp16, 1);
483 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
484 (uint16_t *) (mtod(m, caddr_t) + i),
486 if ((i = (m->m_len - i) & 1) != 0) {
487 tmp16[0] = *(mtod(m, caddr_t) +
492 CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
493 (uint16_t *) tmp16, 1);
495 * If there were other frames chained, update the
496 * chain in the last one.
498 if (sc->tx_head != sc->tx_tail) {
499 if (sc->tx_tail != dest) {
500 CSR_WRITE_2(sc, HOST_ADDR_REG,
501 sc->tx_last + XMT_Chain_Point);
502 CSR_WRITE_2(sc, IO_PORT_REG, dest);
504 CSR_WRITE_2(sc, HOST_ADDR_REG,
505 sc->tx_last + XMT_Byte_Count);
506 i = CSR_READ_2(sc, IO_PORT_REG);
507 CSR_WRITE_2(sc, HOST_ADDR_REG,
508 sc->tx_last + XMT_Byte_Count);
509 CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);
513 * Resume normal operation of the card:
514 * - Make a dummy read to flush the DRAM write
516 * - Enable receive and transmit interrupts.
517 * - Send Transmit or Resume_XMT command, as
520 CSR_READ_2(sc, IO_PORT_REG);
522 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
524 if (sc->tx_head == sc->tx_tail) {
525 CSR_WRITE_2(sc, XMT_BAR, dest);
526 CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);
528 DODEBUG(Sent_Pkts, printf("Transmit\n"););
530 CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);
531 DODEBUG(Sent_Pkts, printf("Resume\n"););
543 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
544 DODEBUG(Status, printf("OACTIVE start\n"););
550 DODEBUG(Start_End, printf("ex_start%d: finish\n", unit););
554 ex_stop(struct ex_softc *sc)
557 DODEBUG(Start_End, printf("ex_stop%d: start\n", unit););
560 * Disable card operation:
561 * - Disable the interrupt line.
562 * - Flush transmission and disable reception.
563 * - Mask and clear all interrupts.
566 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
567 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
568 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
569 CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);
570 sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
571 sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */
572 CSR_WRITE_1(sc, MASK_REG, All_Int);
573 CSR_WRITE_1(sc, STATUS_REG, All_Int);
574 CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
577 DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit););
585 struct ex_softc *sc = (struct ex_softc *)arg;
586 struct ifnet *ifp = sc->ifp;
587 int int_status, send_pkts;
590 DODEBUG(Start_End, printf("ex_intr%d: start\n", unit););
593 while (loops-- > 0 &&
594 (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
595 /* don't loop forever */
596 if (int_status == 0xff)
598 if (int_status & Rx_Int) {
599 CSR_WRITE_1(sc, STATUS_REG, Rx_Int);
601 } else if (int_status & Tx_Int) {
602 CSR_WRITE_1(sc, STATUS_REG, Tx_Int);
608 printf("100 loops are not enough\n");
611 * If any packet has been transmitted, and there are queued packets to
612 * be sent, attempt to send more packets to the network card.
614 if (send_pkts && (ifp->if_snd.ifq_head != NULL))
617 DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit););
623 ex_tx_intr(struct ex_softc *sc)
625 struct ifnet * ifp = sc->ifp;
628 DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit););
631 * - Cancel the watchdog.
632 * For all packets transmitted since last transmit interrupt:
633 * - Advance chain pointer to next queued packet.
634 * - Update statistics.
639 while (sc->tx_head != sc->tx_tail) {
640 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);
642 if (! CSR_READ_2(sc, IO_PORT_REG) & Done_bit)
645 tx_status = CSR_READ_2(sc, IO_PORT_REG);
646 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
648 if (tx_status & TX_OK_bit) {
654 ifp->if_collisions += tx_status & No_Collisions_bits;
658 * The card should be ready to accept more packets now.
661 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
663 DODEBUG(Status, printf("OIDLE tx_intr\n"););
664 DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit););
670 ex_rx_intr(struct ex_softc *sc)
672 struct ifnet * ifp = sc->ifp;
678 struct ether_header * eh;
680 DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit););
683 * For all packets received since last receive interrupt:
684 * - If packet ok, read it into a new mbuf and queue it to interface,
685 * updating statistics.
686 * - If packet bad, just discard it, and update statistics.
687 * Finally, advance receive stop limit in card's memory to new location.
690 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
692 while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
694 rx_status = CSR_READ_2(sc, IO_PORT_REG);
695 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
696 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
698 if (rx_status & RCV_OK_bit) {
699 MGETHDR(m, M_DONTWAIT, MT_DATA);
704 ipkt->m_pkthdr.rcvif = ifp;
705 ipkt->m_pkthdr.len = pkt_len;
708 while (pkt_len > 0) {
709 if (pkt_len >= MINCLSIZE) {
710 MCLGET(m, M_DONTWAIT);
711 if (m->m_flags & M_EXT) {
719 m->m_len = min(m->m_len, pkt_len);
722 * NOTE: I'm assuming that all mbufs allocated are of even length,
723 * except for the last one in an odd-length packet.
726 CSR_READ_MULTI_2(sc, IO_PORT_REG,
727 mtod(m, uint16_t *), m->m_len / 2);
730 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
735 MGET(m->m_next, M_DONTWAIT, MT_DATA);
736 if (m->m_next == NULL) {
745 eh = mtod(ipkt, struct ether_header *);
747 if (debug_mask & Rcvd_Pkts) {
748 if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) {
749 printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":");
750 printf("%6D\n", eh->ether_dhost, ":");
754 (*ifp->if_input)(ifp, ipkt);
760 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
764 if (sc->rx_head < sc->rx_lower_limit + 2)
765 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);
767 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);
769 DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit););
776 ex_ioctl(register struct ifnet *ifp, u_long cmd, caddr_t data)
778 struct ex_softc * sc = ifp->if_softc;
779 struct ifreq * ifr = (struct ifreq *)data;
783 DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname););
791 error = ether_ioctl(ifp, cmd, data);
795 DODEBUG(Start_End, printf("SIOCSIFFLAGS"););
796 if ((ifp->if_flags & IFF_UP) == 0 &&
797 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
799 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
812 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
815 DODEBUG(Start_End, printf("unknown"););
821 DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname););
827 ex_setmulti(struct ex_softc *sc)
830 struct ifmultiaddr *maddr;
839 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
840 if (maddr->ifma_addr->sa_family != AF_LINK)
846 if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)
848 /* Interface is in promiscuous mode or there are too many
849 * multicast addresses for the card to handle */
850 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
851 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
852 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
853 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
855 else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) {
856 /* Program multicast addresses plus our MAC address
858 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
859 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
860 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
861 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
863 /* Borrow space from TX buffer; this should be safe
864 * as this is only called from ex_init */
866 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);
867 CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);
868 CSR_WRITE_2(sc, IO_PORT_REG, 0);
869 CSR_WRITE_2(sc, IO_PORT_REG, 0);
870 CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);
873 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
874 if (maddr->ifma_addr->sa_family != AF_LINK)
877 addr = (uint16_t*)LLADDR((struct sockaddr_dl *)
879 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
880 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
881 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
885 /* Program our MAC address as well */
886 /* XXX: Is this necessary? The Linux driver does this
887 * but the NetBSD driver does not */
888 addr = (uint16_t*)IF_LLADDR(sc->ifp);
889 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
890 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
891 CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
893 CSR_READ_2(sc, IO_PORT_REG);
894 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
895 CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);
897 sc->tx_head = sc->tx_lower_limit;
898 sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6;
900 for (timeout=0; timeout<100; timeout++) {
902 if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
905 status = CSR_READ_1(sc, CMD_REG);
906 CSR_WRITE_1(sc, STATUS_REG, Exec_Int);
910 sc->tx_head = sc->tx_tail;
914 /* No multicast or promiscuous mode */
915 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
916 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
917 /* ~(Multi_IA | Promisc_Mode) */
918 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
919 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
924 ex_reset(struct ex_softc *sc)
928 DODEBUG(Start_End, printf("ex_reset%d: start\n", unit););
937 DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit););
943 ex_watchdog(struct ifnet *ifp)
945 struct ex_softc * sc = ifp->if_softc;
947 DODEBUG(Start_End, printf("%s: ex_watchdog: start\n", ifp->if_xname););
949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
951 DODEBUG(Status, printf("OIDLE watchdog\n"););
957 DODEBUG(Start_End, printf("%s: ex_watchdog: finish\n", ifp->if_xname););
963 ex_get_media(struct ex_softc *sc)
968 media = ex_eeprom_read(sc, EE_W5);
970 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
971 current = CSR_READ_1(sc, REG3);
972 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
974 if ((current & TPE_bit) && (media & EE_W5_PORT_TPE))
975 return(IFM_ETHER|IFM_10_T);
976 if ((current & BNC_bit) && (media & EE_W5_PORT_BNC))
977 return(IFM_ETHER|IFM_10_2);
979 if (media & EE_W5_PORT_AUI)
980 return (IFM_ETHER|IFM_10_5);
982 return (IFM_ETHER|IFM_AUTO);
989 struct ex_softc * sc = ifp->if_softc;
991 if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
998 ex_ifmedia_sts(ifp, ifmr)
1000 struct ifmediareq * ifmr;
1002 struct ex_softc * sc = ifp->if_softc;
1004 ifmr->ifm_active = ex_get_media(sc);
1005 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1011 ex_eeprom_read(struct ex_softc *sc, int location)
1015 int read_cmd = location | EE_READ_CMD;
1016 short ctrl_val = EECS;
1018 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
1019 CSR_WRITE_1(sc, EEPROM_REG, EECS);
1020 for (i = 8; i >= 0; i--) {
1021 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
1022 CSR_WRITE_1(sc, EEPROM_REG, outval);
1023 CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);
1025 CSR_WRITE_1(sc, EEPROM_REG, outval);
1028 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1030 for (i = 16; i > 0; i--) {
1031 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1033 data = (data << 1) |
1034 ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
1035 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1040 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
1042 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
1044 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);