2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
90 #include <vm/vm.h> /* for vtophys */
91 #include <vm/pmap.h> /* for vtophys */
92 #include <machine/bus.h>
93 #include <machine/resource.h>
97 #include <dev/mii/mii.h>
98 #include <dev/mii/miivar.h>
100 #include <dev/pci/pcireg.h>
101 #include <dev/pci/pcivar.h>
103 #define LGE_USEIOSPACE
105 #include <dev/lge/if_lgereg.h>
107 /* "device miibus" required. See GENERIC if you get errors here. */
108 #include "miibus_if.h"
111 * Various supported device vendors/types and their names.
113 static const struct lge_type lge_devs[] = {
114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
118 static int lge_probe(device_t);
119 static int lge_attach(device_t);
120 static int lge_detach(device_t);
122 static int lge_alloc_jumbo_mem(struct lge_softc *);
123 static void lge_free_jumbo_mem(struct lge_softc *);
124 static void *lge_jalloc(struct lge_softc *);
125 static void lge_jfree(void *, void *);
127 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
128 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
129 static void lge_rxeof(struct lge_softc *, int);
130 static void lge_rxeoc(struct lge_softc *);
131 static void lge_txeof(struct lge_softc *);
132 static void lge_intr(void *);
133 static void lge_tick(void *);
134 static void lge_start(struct ifnet *);
135 static void lge_start_locked(struct ifnet *);
136 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
137 static void lge_init(void *);
138 static void lge_init_locked(struct lge_softc *);
139 static void lge_stop(struct lge_softc *);
140 static void lge_watchdog(struct lge_softc *);
141 static int lge_shutdown(device_t);
142 static int lge_ifmedia_upd(struct ifnet *);
143 static void lge_ifmedia_upd_locked(struct ifnet *);
144 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
146 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
147 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149 static int lge_miibus_readreg(device_t, int, int);
150 static int lge_miibus_writereg(device_t, int, int, int);
151 static void lge_miibus_statchg(device_t);
153 static void lge_setmulti(struct lge_softc *);
154 static void lge_reset(struct lge_softc *);
155 static int lge_list_rx_init(struct lge_softc *);
156 static int lge_list_tx_init(struct lge_softc *);
158 #ifdef LGE_USEIOSPACE
159 #define LGE_RES SYS_RES_IOPORT
160 #define LGE_RID LGE_PCI_LOIO
162 #define LGE_RES SYS_RES_MEMORY
163 #define LGE_RID LGE_PCI_LOMEM
166 static device_method_t lge_methods[] = {
167 /* Device interface */
168 DEVMETHOD(device_probe, lge_probe),
169 DEVMETHOD(device_attach, lge_attach),
170 DEVMETHOD(device_detach, lge_detach),
171 DEVMETHOD(device_shutdown, lge_shutdown),
174 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
175 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
176 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
181 static driver_t lge_driver = {
184 sizeof(struct lge_softc)
187 static devclass_t lge_devclass;
189 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
190 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
191 MODULE_DEPEND(lge, pci, 1, 1, 1);
192 MODULE_DEPEND(lge, ether, 1, 1, 1);
193 MODULE_DEPEND(lge, miibus, 1, 1, 1);
195 #define LGE_SETBIT(sc, reg, x) \
196 CSR_WRITE_4(sc, reg, \
197 CSR_READ_4(sc, reg) | (x))
199 #define LGE_CLRBIT(sc, reg, x) \
200 CSR_WRITE_4(sc, reg, \
201 CSR_READ_4(sc, reg) & ~(x))
204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
210 * Read a word of data stored in the EEPROM at address 'addr.'
213 lge_eeprom_getword(sc, addr, dest)
214 struct lge_softc *sc;
221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
222 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
224 for (i = 0; i < LGE_TIMEOUT; i++)
225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
228 if (i == LGE_TIMEOUT) {
229 device_printf(sc->lge_dev, "EEPROM read timed out\n");
233 val = CSR_READ_4(sc, LGE_EEDATA);
236 *dest = (val >> 16) & 0xFFFF;
238 *dest = val & 0xFFFF;
244 * Read a sequence of words from the EEPROM.
247 lge_read_eeprom(sc, dest, off, cnt, swap)
248 struct lge_softc *sc;
255 u_int16_t word = 0, *ptr;
257 for (i = 0; i < cnt; i++) {
258 lge_eeprom_getword(sc, off + i, &word);
259 ptr = (u_int16_t *)(dest + (i * 2));
270 lge_miibus_readreg(dev, phy, reg)
274 struct lge_softc *sc;
277 sc = device_get_softc(dev);
280 * If we have a non-PCS PHY, pretend that the internal
281 * autoneg stuff at PHY address 0 isn't there so that
282 * the miibus code will find only the GMII PHY.
284 if (sc->lge_pcs == 0 && phy == 0)
287 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
289 for (i = 0; i < LGE_TIMEOUT; i++)
290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
293 if (i == LGE_TIMEOUT) {
294 device_printf(sc->lge_dev, "PHY read timed out\n");
298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
302 lge_miibus_writereg(dev, phy, reg, data)
306 struct lge_softc *sc;
309 sc = device_get_softc(dev);
311 CSR_WRITE_4(sc, LGE_GMIICTL,
312 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
314 for (i = 0; i < LGE_TIMEOUT; i++)
315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
318 if (i == LGE_TIMEOUT) {
319 device_printf(sc->lge_dev, "PHY write timed out\n");
327 lge_miibus_statchg(dev)
330 struct lge_softc *sc;
331 struct mii_data *mii;
333 sc = device_get_softc(dev);
334 mii = device_get_softc(sc->lge_miibus);
336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
337 switch (IFM_SUBTYPE(mii->mii_media_active)) {
340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
350 * Choose something, even if it's wrong. Clearing
351 * all the bits will hose autoneg on the internal
354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
358 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
359 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
361 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
369 struct lge_softc *sc;
372 struct ifmultiaddr *ifma;
373 u_int32_t h = 0, hashes[2] = { 0, 0 };
378 /* Make sure multicast hash table is enabled. */
379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
381 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
382 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
383 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
387 /* first, zot all the existing hash bits */
388 CSR_WRITE_4(sc, LGE_MAR0, 0);
389 CSR_WRITE_4(sc, LGE_MAR1, 0);
391 /* now program new ones */
393 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
394 if (ifma->ifma_addr->sa_family != AF_LINK)
396 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
397 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
399 hashes[0] |= (1 << h);
401 hashes[1] |= (1 << (h - 32));
403 if_maddr_runlock(ifp);
405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
413 struct lge_softc *sc;
417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
419 for (i = 0; i < LGE_TIMEOUT; i++) {
420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
424 if (i == LGE_TIMEOUT)
425 device_printf(sc->lge_dev, "reset never completed\n");
427 /* Wait a little while for the chip to get its brains in order. */
434 * Probe for a Level 1 chip. Check the PCI vendor and device
435 * IDs against our list and return a device name if we find a match.
441 const struct lge_type *t;
445 while(t->lge_name != NULL) {
446 if ((pci_get_vendor(dev) == t->lge_vid) &&
447 (pci_get_device(dev) == t->lge_did)) {
448 device_set_desc(dev, t->lge_name);
449 return(BUS_PROBE_DEFAULT);
458 * Attach the interface. Allocate softc structures, do ifmedia
459 * setup and ethernet/BPF attach.
465 u_char eaddr[ETHER_ADDR_LEN];
466 struct lge_softc *sc;
467 struct ifnet *ifp = NULL;
470 sc = device_get_softc(dev);
473 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
475 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
478 * Map control/status registers.
480 pci_enable_busmaster(dev);
483 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
485 if (sc->lge_res == NULL) {
486 device_printf(dev, "couldn't map ports/memory\n");
491 sc->lge_btag = rman_get_bustag(sc->lge_res);
492 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
494 /* Allocate interrupt */
496 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
497 RF_SHAREABLE | RF_ACTIVE);
499 if (sc->lge_irq == NULL) {
500 device_printf(dev, "couldn't map interrupt\n");
505 /* Reset the adapter. */
509 * Get station address from the EEPROM.
511 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
512 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
513 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
515 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
516 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
518 if (sc->lge_ldata == NULL) {
519 device_printf(dev, "no memory for list buffers!\n");
524 /* Try to allocate memory for jumbo buffers. */
525 if (lge_alloc_jumbo_mem(sc)) {
526 device_printf(dev, "jumbo buffer allocation failed\n");
531 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
533 device_printf(dev, "can not if_alloc()\n");
538 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
539 ifp->if_mtu = ETHERMTU;
540 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
541 ifp->if_ioctl = lge_ioctl;
542 ifp->if_start = lge_start;
543 ifp->if_init = lge_init;
544 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
545 ifp->if_capabilities = IFCAP_RXCSUM;
546 ifp->if_capenable = ifp->if_capabilities;
548 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
556 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
557 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
559 device_printf(dev, "attaching PHYs failed\n");
564 * Call MI attach routine.
566 ether_ifattach(ifp, eaddr);
568 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
569 NULL, lge_intr, sc, &sc->lge_intrhand);
573 device_printf(dev, "couldn't set up irq\n");
579 lge_free_jumbo_mem(sc);
581 contigfree(sc->lge_ldata,
582 sizeof(struct lge_list_data), M_DEVBUF);
586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 mtx_destroy(&sc->lge_mtx);
597 struct lge_softc *sc;
600 sc = device_get_softc(dev);
607 callout_drain(&sc->lge_stat_callout);
610 bus_generic_detach(dev);
611 device_delete_child(dev, sc->lge_miibus);
613 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
614 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
615 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
617 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
619 lge_free_jumbo_mem(sc);
620 mtx_destroy(&sc->lge_mtx);
626 * Initialize the transmit descriptors.
630 struct lge_softc *sc;
632 struct lge_list_data *ld;
633 struct lge_ring_data *cd;
638 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
639 ld->lge_tx_list[i].lge_mbuf = NULL;
640 ld->lge_tx_list[i].lge_ctl = 0;
643 cd->lge_tx_prod = cd->lge_tx_cons = 0;
650 * Initialize the RX descriptors and allocate mbufs for them. Note that
651 * we arralge the descriptors in a closed ring, so that the last descriptor
652 * points back to the first.
656 struct lge_softc *sc;
658 struct lge_list_data *ld;
659 struct lge_ring_data *cd;
665 cd->lge_rx_prod = cd->lge_rx_cons = 0;
667 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
669 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
670 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
672 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
676 /* Clear possible 'rx command queue empty' interrupt. */
677 CSR_READ_4(sc, LGE_ISR);
683 * Initialize an RX descriptor and attach an MBUF cluster.
687 struct lge_softc *sc;
688 struct lge_rx_desc *c;
691 struct mbuf *m_new = NULL;
695 MGETHDR(m_new, M_NOWAIT, MT_DATA);
697 device_printf(sc->lge_dev, "no memory for rx list "
698 "-- packet dropped!\n");
702 /* Allocate the jumbo buffer */
703 buf = lge_jalloc(sc);
706 device_printf(sc->lge_dev, "jumbo allocation failed "
707 "-- packet dropped!\n");
712 /* Attach the buffer to the mbuf */
713 m_new->m_data = (void *)buf;
714 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
715 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
716 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV);
719 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
720 m_new->m_data = m_new->m_ext.ext_buf;
724 * Adjust alignment so packet payload begins on a
725 * longword boundary. Mandatory for Alpha, useful on
728 m_adj(m_new, ETHER_ALIGN);
731 c->lge_fragptr_hi = 0;
732 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
733 c->lge_fraglen = m_new->m_len;
734 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
738 * Put this buffer in the RX command FIFO. To do this,
739 * we just write the physical address of the descriptor
740 * into the RX descriptor address registers. Note that
741 * there are two registers, one high DWORD and one low
742 * DWORD, which lets us specify a 64-bit address if
743 * desired. We only use a 32-bit address for now.
744 * Writing to the low DWORD register is what actually
745 * causes the command to be issued, so we do that
748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
749 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
755 lge_alloc_jumbo_mem(sc)
756 struct lge_softc *sc;
760 struct lge_jpool_entry *entry;
762 /* Grab a big chunk o' storage. */
763 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
764 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
766 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
767 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
771 SLIST_INIT(&sc->lge_jfree_listhead);
772 SLIST_INIT(&sc->lge_jinuse_listhead);
775 * Now divide it up into 9K pieces and save the addresses
778 ptr = sc->lge_cdata.lge_jumbo_buf;
779 for (i = 0; i < LGE_JSLOTS; i++) {
780 sc->lge_cdata.lge_jslots[i] = ptr;
782 entry = malloc(sizeof(struct lge_jpool_entry),
785 device_printf(sc->lge_dev, "no memory for jumbo "
790 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
791 entry, jpool_entries);
798 lge_free_jumbo_mem(sc)
799 struct lge_softc *sc;
801 struct lge_jpool_entry *entry;
803 if (sc->lge_cdata.lge_jumbo_buf == NULL)
806 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
807 device_printf(sc->lge_dev,
808 "asked to free buffer that is in use!\n");
809 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
810 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
813 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
814 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
815 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
816 free(entry, M_DEVBUF);
819 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
825 * Allocate a jumbo buffer.
829 struct lge_softc *sc;
831 struct lge_jpool_entry *entry;
833 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
837 device_printf(sc->lge_dev, "no free jumbo buffers\n");
842 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
843 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
844 return(sc->lge_cdata.lge_jslots[entry->slot]);
848 * Release a jumbo buffer.
855 struct lge_softc *sc;
857 struct lge_jpool_entry *entry;
859 /* Extract the softc struct pointer. */
863 panic("lge_jfree: can't find softc pointer!");
865 /* calculate the slot this buffer belongs to */
866 i = ((vm_offset_t)buf
867 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
869 if ((i < 0) || (i >= LGE_JSLOTS))
870 panic("lge_jfree: asked to free buffer that we don't manage!");
872 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
874 panic("lge_jfree: buffer not in use!");
876 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
877 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
883 * A frame has been uploaded: pass the resulting mbuf chain up to
884 * the higher level protocols.
888 struct lge_softc *sc;
893 struct lge_rx_desc *cur_rx;
894 int c, i, total_len = 0;
895 u_int32_t rxsts, rxctl;
899 /* Find out how many frames were processed. */
901 i = sc->lge_cdata.lge_rx_cons;
905 struct mbuf *m0 = NULL;
907 cur_rx = &sc->lge_ldata->lge_rx_list[i];
908 rxctl = cur_rx->lge_ctl;
909 rxsts = cur_rx->lge_sts;
910 m = cur_rx->lge_mbuf;
911 cur_rx->lge_mbuf = NULL;
912 total_len = LGE_RXBYTES(cur_rx);
913 LGE_INC(i, LGE_RX_LIST_CNT);
917 * If an error occurs, update stats, clear the
918 * status word and leave the mbuf cluster in place:
919 * it should simply get re-used next time this descriptor
920 * comes up in the ring.
922 if (rxctl & LGE_RXCTL_ERRMASK) {
924 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
928 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
931 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
933 device_printf(sc->lge_dev, "no receive buffers "
934 "available -- packet dropped!\n");
940 m->m_pkthdr.rcvif = ifp;
941 m->m_pkthdr.len = m->m_len = total_len;
946 /* Do IP checksum checking. */
947 if (rxsts & LGE_RXSTS_ISIP)
948 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
949 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
950 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
951 if ((rxsts & LGE_RXSTS_ISTCP &&
952 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
953 (rxsts & LGE_RXSTS_ISUDP &&
954 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
955 m->m_pkthdr.csum_flags |=
956 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
957 m->m_pkthdr.csum_data = 0xffff;
961 (*ifp->if_input)(ifp, m);
965 sc->lge_cdata.lge_rx_cons = i;
972 struct lge_softc *sc;
977 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
983 * A frame was downloaded to the chip. It's safe for us to clean up
989 struct lge_softc *sc;
991 struct lge_tx_desc *cur_tx = NULL;
993 u_int32_t idx, txdone;
997 /* Clear the timeout timer. */
1001 * Go through our tx list and free mbufs for those
1002 * frames that have been transmitted.
1004 idx = sc->lge_cdata.lge_tx_cons;
1005 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1007 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1008 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1011 if (cur_tx->lge_mbuf != NULL) {
1012 m_freem(cur_tx->lge_mbuf);
1013 cur_tx->lge_mbuf = NULL;
1015 cur_tx->lge_ctl = 0;
1018 LGE_INC(idx, LGE_TX_LIST_CNT);
1022 sc->lge_cdata.lge_tx_cons = idx;
1025 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1034 struct lge_softc *sc;
1035 struct mii_data *mii;
1040 LGE_LOCK_ASSERT(sc);
1042 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1043 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1044 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1045 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1047 if (!sc->lge_link) {
1048 mii = device_get_softc(sc->lge_miibus);
1050 if (mii->mii_media_status & IFM_ACTIVE &&
1051 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1054 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1055 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1056 device_printf(sc->lge_dev, "gigabit link up\n");
1057 if (ifp->if_snd.ifq_head != NULL)
1058 lge_start_locked(ifp);
1062 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1064 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1073 struct lge_softc *sc;
1081 /* Supress unwanted interrupts */
1082 if (!(ifp->if_flags & IFF_UP)) {
1090 * Reading the ISR register clears all interrupts, and
1091 * clears the 'interrupts enabled' bit in the IMR
1094 status = CSR_READ_4(sc, LGE_ISR);
1096 if ((status & LGE_INTRS) == 0)
1099 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1102 if (status & LGE_ISR_RXDMA_DONE)
1103 lge_rxeof(sc, LGE_RX_DMACNT(status));
1105 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1108 if (status & LGE_ISR_PHY_INTR) {
1110 callout_stop(&sc->lge_stat_callout);
1115 /* Re-enable interrupts. */
1116 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1118 if (ifp->if_snd.ifq_head != NULL)
1119 lge_start_locked(ifp);
1126 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1127 * pointers to the fragment pointers.
1130 lge_encap(sc, m_head, txidx)
1131 struct lge_softc *sc;
1132 struct mbuf *m_head;
1135 struct lge_frag *f = NULL;
1136 struct lge_tx_desc *cur_tx;
1138 int frag = 0, tot_len = 0;
1141 * Start packing the mbufs in this chain into
1142 * the fragment pointers. Stop when we run out
1143 * of fragments or hit the end of the mbuf chain.
1146 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1149 for (m = m_head; m != NULL; m = m->m_next) {
1150 if (m->m_len != 0) {
1151 tot_len += m->m_len;
1152 f = &cur_tx->lge_frags[frag];
1153 f->lge_fraglen = m->m_len;
1154 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1155 f->lge_fragptr_hi = 0;
1163 cur_tx->lge_mbuf = m_head;
1164 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1165 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1167 /* Queue for transmit */
1168 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1174 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1175 * to the mbuf data regions directly in the transmit lists. We also save a
1176 * copy of the pointers since the transmit list fragment pointers are
1177 * physical addresses.
1184 struct lge_softc *sc;
1188 lge_start_locked(ifp);
1193 lge_start_locked(ifp)
1196 struct lge_softc *sc;
1197 struct mbuf *m_head = NULL;
1205 idx = sc->lge_cdata.lge_tx_prod;
1207 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1210 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1211 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1214 IF_DEQUEUE(&ifp->if_snd, m_head);
1218 if (lge_encap(sc, m_head, &idx)) {
1219 IF_PREPEND(&ifp->if_snd, m_head);
1220 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1225 * If there's a BPF listener, bounce a copy of this frame
1228 BPF_MTAP(ifp, m_head);
1231 sc->lge_cdata.lge_tx_prod = idx;
1234 * Set a timeout in case the chip goes out to lunch.
1245 struct lge_softc *sc = xsc;
1248 lge_init_locked(sc);
1254 struct lge_softc *sc;
1256 struct ifnet *ifp = sc->lge_ifp;
1258 LGE_LOCK_ASSERT(sc);
1259 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1263 * Cancel pending I/O and free all RX/TX buffers.
1268 /* Set MAC address */
1269 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1270 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1272 /* Init circular RX list. */
1273 if (lge_list_rx_init(sc) == ENOBUFS) {
1274 device_printf(sc->lge_dev, "initialization failed: no "
1275 "memory for rx buffers\n");
1281 * Init tx descriptors.
1283 lge_list_tx_init(sc);
1285 /* Set initial value for MODE1 register. */
1286 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1287 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1288 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1289 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1291 /* If we want promiscuous mode, set the allframes bit. */
1292 if (ifp->if_flags & IFF_PROMISC) {
1293 CSR_WRITE_4(sc, LGE_MODE1,
1294 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1296 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1300 * Set the capture broadcast bit to capture broadcast frames.
1302 if (ifp->if_flags & IFF_BROADCAST) {
1303 CSR_WRITE_4(sc, LGE_MODE1,
1304 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1309 /* Packet padding workaround? */
1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1312 /* No error frames */
1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1315 /* Receive large frames */
1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1318 /* Workaround: disable RX/TX flow control */
1319 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1322 /* Make sure to strip CRC from received frames */
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1325 /* Turn off magic packet mode */
1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1328 /* Turn off all VLAN stuff */
1329 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1330 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1332 /* Workarond: FIFO overflow */
1333 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1334 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1337 * Load the multicast filter.
1342 * Enable hardware checksum validation for all received IPv4
1343 * packets, do not reject packets with bad checksums.
1345 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1346 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1347 LGE_MODE2_RX_ERRCSUM);
1350 * Enable the delivery of PHY interrupts based on
1351 * link/speed/duplex status chalges.
1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1355 /* Enable receiver and transmitter. */
1356 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1359 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1363 * Enable interrupts.
1365 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1366 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1368 lge_ifmedia_upd_locked(ifp);
1370 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1371 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1373 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1379 * Set media options.
1382 lge_ifmedia_upd(ifp)
1385 struct lge_softc *sc;
1389 lge_ifmedia_upd_locked(ifp);
1396 lge_ifmedia_upd_locked(ifp)
1399 struct lge_softc *sc;
1400 struct mii_data *mii;
1401 struct mii_softc *miisc;
1405 LGE_LOCK_ASSERT(sc);
1406 mii = device_get_softc(sc->lge_miibus);
1408 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1414 * Report current media status.
1417 lge_ifmedia_sts(ifp, ifmr)
1419 struct ifmediareq *ifmr;
1421 struct lge_softc *sc;
1422 struct mii_data *mii;
1427 mii = device_get_softc(sc->lge_miibus);
1429 ifmr->ifm_active = mii->mii_media_active;
1430 ifmr->ifm_status = mii->mii_media_status;
1437 lge_ioctl(ifp, command, data)
1442 struct lge_softc *sc = ifp->if_softc;
1443 struct ifreq *ifr = (struct ifreq *) data;
1444 struct mii_data *mii;
1450 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1453 ifp->if_mtu = ifr->ifr_mtu;
1458 if (ifp->if_flags & IFF_UP) {
1459 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1460 ifp->if_flags & IFF_PROMISC &&
1461 !(sc->lge_if_flags & IFF_PROMISC)) {
1462 CSR_WRITE_4(sc, LGE_MODE1,
1463 LGE_MODE1_SETRST_CTL1|
1464 LGE_MODE1_RX_PROMISC);
1465 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1466 !(ifp->if_flags & IFF_PROMISC) &&
1467 sc->lge_if_flags & IFF_PROMISC) {
1468 CSR_WRITE_4(sc, LGE_MODE1,
1469 LGE_MODE1_RX_PROMISC);
1471 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1472 lge_init_locked(sc);
1475 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1478 sc->lge_if_flags = ifp->if_flags;
1491 mii = device_get_softc(sc->lge_miibus);
1492 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1495 error = ether_ioctl(ifp, command, data);
1504 struct lge_softc *sc;
1508 LGE_LOCK_ASSERT(sc);
1512 if_printf(ifp, "watchdog timeout\n");
1516 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1517 lge_init_locked(sc);
1519 if (ifp->if_snd.ifq_head != NULL)
1520 lge_start_locked(ifp);
1524 * Stop the adapter and free any mbufs allocated to the
1529 struct lge_softc *sc;
1534 LGE_LOCK_ASSERT(sc);
1537 callout_stop(&sc->lge_stat_callout);
1538 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1540 /* Disable receiver and transmitter. */
1541 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1545 * Free data in the RX lists.
1547 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1548 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1549 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1550 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1553 bzero((char *)&sc->lge_ldata->lge_rx_list,
1554 sizeof(sc->lge_ldata->lge_rx_list));
1557 * Free the TX list buffers.
1559 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1560 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1561 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1562 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1566 bzero((char *)&sc->lge_ldata->lge_tx_list,
1567 sizeof(sc->lge_ldata->lge_tx_list));
1569 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1575 * Stop all chip I/O so that the kernel's probe routines don't
1576 * get confused by errant DMAs when rebooting.
1582 struct lge_softc *sc;
1584 sc = device_get_softc(dev);