2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/driver.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
34 #if (__FreeBSD_version >= 1100000)
39 #include <net/rss_config.h>
40 #include <netinet/in_rss.h>
44 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
45 MLX5_EQE_OWNER_INIT_VAL = 0x1,
49 MLX5_NUM_SPARE_EQE = 0x80,
50 MLX5_NUM_ASYNC_EQE = 0x100,
51 MLX5_NUM_CMD_EQE = 32,
55 MLX5_EQ_DOORBEL_OFFSET = 0x40,
58 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
59 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
60 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
61 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
64 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
65 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
67 (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE) | \
68 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
69 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
70 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
83 /*Function prototype*/
84 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
85 struct mlx5_eqe *eqe);
87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
89 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)];
90 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)];
92 memset(in, 0, sizeof(in));
94 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
95 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
97 memset(out, 0, sizeof(out));
98 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
102 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
104 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
107 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
109 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
111 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
114 static const char *eqe_type_str(u8 type)
117 case MLX5_EVENT_TYPE_COMP:
118 return "MLX5_EVENT_TYPE_COMP";
119 case MLX5_EVENT_TYPE_PATH_MIG:
120 return "MLX5_EVENT_TYPE_PATH_MIG";
121 case MLX5_EVENT_TYPE_COMM_EST:
122 return "MLX5_EVENT_TYPE_COMM_EST";
123 case MLX5_EVENT_TYPE_SQ_DRAINED:
124 return "MLX5_EVENT_TYPE_SQ_DRAINED";
125 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
126 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
127 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
128 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
129 case MLX5_EVENT_TYPE_CQ_ERROR:
130 return "MLX5_EVENT_TYPE_CQ_ERROR";
131 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
132 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
133 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
134 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
135 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
136 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
137 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
138 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
139 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
140 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
141 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
142 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
143 case MLX5_EVENT_TYPE_PORT_CHANGE:
144 return "MLX5_EVENT_TYPE_PORT_CHANGE";
145 case MLX5_EVENT_TYPE_GPIO_EVENT:
146 return "MLX5_EVENT_TYPE_GPIO_EVENT";
147 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
148 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
149 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
150 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
151 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
152 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
153 case MLX5_EVENT_TYPE_STALL_EVENT:
154 return "MLX5_EVENT_TYPE_STALL_EVENT";
155 case MLX5_EVENT_TYPE_CMD:
156 return "MLX5_EVENT_TYPE_CMD";
157 case MLX5_EVENT_TYPE_PAGE_REQUEST:
158 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
159 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
160 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
162 return "Unrecognized event";
166 static enum mlx5_dev_event port_subtype_event(u8 subtype)
169 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
170 return MLX5_DEV_EVENT_PORT_DOWN;
171 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
172 return MLX5_DEV_EVENT_PORT_UP;
173 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
174 return MLX5_DEV_EVENT_PORT_INITIALIZED;
175 case MLX5_PORT_CHANGE_SUBTYPE_LID:
176 return MLX5_DEV_EVENT_LID_CHANGE;
177 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
178 return MLX5_DEV_EVENT_PKEY_CHANGE;
179 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
180 return MLX5_DEV_EVENT_GUID_CHANGE;
181 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
182 return MLX5_DEV_EVENT_CLIENT_REREG;
187 static void eq_update_ci(struct mlx5_eq *eq, int arm)
189 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
190 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
191 __raw_writel((__force u32) cpu_to_be32(val), addr);
192 /* We still want ordering, just not swabbing, so add a barrier */
196 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
198 struct mlx5_eqe *eqe;
205 while ((eqe = next_eqe_sw(eq))) {
207 * Make sure we read EQ entry contents after we've
208 * checked the ownership bit.
212 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
213 eq->eqn, eqe_type_str(eqe->type));
215 case MLX5_EVENT_TYPE_COMP:
216 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
217 mlx5_cq_completion(dev, cqn);
220 case MLX5_EVENT_TYPE_PATH_MIG:
221 case MLX5_EVENT_TYPE_COMM_EST:
222 case MLX5_EVENT_TYPE_SQ_DRAINED:
223 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
224 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
225 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
226 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
229 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
230 eqe_type_str(eqe->type), eqe->type, rsn);
231 mlx5_rsc_event(dev, rsn, eqe->type);
234 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
235 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
236 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
237 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
238 eqe_type_str(eqe->type), eqe->type, rsn);
239 mlx5_srq_event(dev, rsn, eqe->type);
242 case MLX5_EVENT_TYPE_CMD:
243 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
246 case MLX5_EVENT_TYPE_PORT_CHANGE:
247 port = (eqe->data.port.port >> 4) & 0xf;
248 switch (eqe->sub_type) {
249 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
250 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
251 case MLX5_PORT_CHANGE_SUBTYPE_LID:
252 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
253 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
254 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
255 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
257 dev->event(dev, port_subtype_event(eqe->sub_type),
258 (unsigned long)port);
261 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
262 port, eqe->sub_type);
265 case MLX5_EVENT_TYPE_CQ_ERROR:
266 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
267 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
268 cqn, eqe->data.cq_err.syndrome);
269 mlx5_cq_event(dev, cqn, eqe->type);
272 case MLX5_EVENT_TYPE_PAGE_REQUEST:
274 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
275 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
277 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
279 mlx5_core_req_pages_handler(dev, func_id, npages);
283 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
284 mlx5_port_module_event(dev, eqe);
287 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
289 struct mlx5_eqe_vport_change *vc_eqe =
290 &eqe->data.vport_change;
291 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
295 MLX5_DEV_EVENT_VPORT_CHANGE,
296 (unsigned long)vport_num);
301 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
310 /* The HCA will think the queue has overflowed if we
311 * don't tell it we've been processing events. We
312 * create our EQs with MLX5_NUM_SPARE_EQE extra
313 * entries, so we must update our consumer index at
316 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
327 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
329 struct mlx5_eq *eq = eq_ptr;
330 struct mlx5_core_dev *dev = eq->dev;
332 mlx5_eq_int(dev, eq);
334 /* MSI-X vectors always belong to us */
338 static void init_eq_buf(struct mlx5_eq *eq)
340 struct mlx5_eqe *eqe;
343 for (i = 0; i < eq->nent; i++) {
344 eqe = get_eqe(eq, i);
345 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
349 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
350 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
352 struct mlx5_priv *priv = &dev->priv;
353 struct mlx5_create_eq_mbox_in *in;
354 struct mlx5_create_eq_mbox_out out;
358 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
359 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
366 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
367 in = mlx5_vzalloc(inlen);
372 memset(&out, 0, sizeof(out));
374 mlx5_fill_page_array(&eq->buf, in->pas);
376 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
377 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
378 in->ctx.intr = vecidx;
379 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
380 in->events_mask = cpu_to_be64(mask);
382 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
386 if (out.hdr.status) {
387 err = mlx5_cmd_status_to_err(&out.hdr);
391 eq->eqn = out.eq_number;
394 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
395 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
396 name, pci_name(dev->pdev));
397 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
398 priv->irq_info[vecidx].name, eq);
402 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
403 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
404 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
405 rss_getcpu(bucket % rss_getnumbuckets()));
415 /* EQs are created in ARMED state
423 free_irq(priv->msix_arr[vecidx].vector, eq);
426 mlx5_cmd_destroy_eq(dev, eq->eqn);
432 mlx5_buf_free(dev, &eq->buf);
435 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
437 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
441 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
442 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
444 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
446 mlx5_buf_free(dev, &eq->buf);
450 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
452 int mlx5_eq_init(struct mlx5_core_dev *dev)
456 spin_lock_init(&dev->priv.eq_table.lock);
464 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
468 int mlx5_start_eqs(struct mlx5_core_dev *dev)
470 struct mlx5_eq_table *table = &dev->priv.eq_table;
471 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
474 if (MLX5_CAP_GEN(dev, port_module_event))
475 async_event_mask |= (1ull <<
476 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
478 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
479 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
480 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
482 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
486 mlx5_cmd_use_events(dev);
488 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
489 MLX5_NUM_ASYNC_EQE, async_event_mask,
490 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
492 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
496 err = mlx5_create_map_eq(dev, &table->pages_eq,
498 /* TODO: sriov max_vf + */ 1,
499 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
500 &dev->priv.uuari.uars[0]);
502 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
509 mlx5_destroy_unmap_eq(dev, &table->async_eq);
512 mlx5_cmd_use_polling(dev);
513 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
517 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
519 struct mlx5_eq_table *table = &dev->priv.eq_table;
522 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
526 mlx5_destroy_unmap_eq(dev, &table->async_eq);
527 mlx5_cmd_use_polling(dev);
529 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
531 mlx5_cmd_use_events(dev);
536 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
537 struct mlx5_query_eq_mbox_out *out, int outlen)
539 struct mlx5_query_eq_mbox_in in;
542 memset(&in, 0, sizeof(in));
543 memset(out, 0, outlen);
544 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
546 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
551 err = mlx5_cmd_status_to_err(&out->hdr);
556 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
558 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
560 switch (error_type) {
561 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
562 return "Power Budget Exceeded";
563 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
564 return "Long Range for non MLNX cable/module";
565 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
566 return "Bus stuck(I2C or data shorted)";
567 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
568 return "No EEPROM/retry timeout";
569 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
570 return "Enforce part number list";
571 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER:
572 return "Unknown identifier";
573 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
574 return "High Temperature";
577 return "Unknown error type";
581 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
582 struct mlx5_eqe *eqe)
584 unsigned int module_num;
585 unsigned int module_status;
586 unsigned int error_type;
587 struct mlx5_eqe_port_module_event *module_event_eqe;
588 struct pci_dev *pdev = dev->pdev;
590 module_event_eqe = &eqe->data.port_module_event;
592 module_num = (unsigned int)module_event_eqe->module;
593 module_status = (unsigned int)module_event_eqe->module_status &
594 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
595 error_type = (unsigned int)module_event_eqe->error_type &
596 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
598 switch (module_status) {
599 case MLX5_MODULE_STATUS_PLUGGED:
600 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num);
603 case MLX5_MODULE_STATUS_UNPLUGGED:
604 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num);
607 case MLX5_MODULE_STATUS_ERROR:
608 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type));
612 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num);