sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 /*
 310  * This function reads the physical port counters from the firmware
 311  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 312  * macros. The output is converted from big-endian 64-bit values into
 313  * host endian ones and stored in the "priv->stats.pport" structure.
 314  */
 315 static void
 316 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 317 {
 318         struct mlx5_core_dev *mdev = priv->mdev;
 319         struct mlx5e_pport_stats *s = &priv->stats.pport;
 320         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 321         u32 *in;
 322         u32 *out;
 323         const u64 *ptr;
 324         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 325         unsigned x;
 326         unsigned y;
 327
 328         /* allocate firmware request structures */
 329         in = mlx5_vzalloc(sz);
 330         out = mlx5_vzalloc(sz);
 331         if (in == NULL || out == NULL)
 332                 goto free_out;
 333
 334         /*
 335          * Get pointer to the 64-bit counter set which is located at a
 336          * fixed offset in the output firmware request structure:
 337          */
 338         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 339
 340         MLX5_SET(ppcnt_reg, in, local_port, 1);
 341
 342         /* read IEEE802_3 counter group using predefined counter layout */
 343         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 344         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 345         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 346                 s->arg[y] = be64toh(ptr[x]);
 347
 348         /* read RFC2819 counter group using predefined counter layout */
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 352                 s->arg[y] = be64toh(ptr[x]);
 353         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 354             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 355                 s_debug->arg[y] = be64toh(ptr[x]);
 356
 357         /* read RFC2863 counter group using predefined counter layout */
 358         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 359         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 360         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 361                 s_debug->arg[y] = be64toh(ptr[x]);
 362
 363         /* read physical layer stats counter group using predefined counter layout */
 364         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 365         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 366         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 367                 s_debug->arg[y] = be64toh(ptr[x]);
 368 free_out:
 369         /* free firmware request structures */
 370         kvfree(in);
 371         kvfree(out);
 372 }
 373
 374 /*
 375  * This function is called regularly to collect all statistics
 376  * counters from the firmware. The values can be viewed through the
 377  * sysctl interface. Execution is serialized using the priv's global
 378  * configuration lock.
 379  */
 380 static void
 381 mlx5e_update_stats_work(struct work_struct *work)
 382 {
 383         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 384             update_stats_work);
 385         struct mlx5_core_dev *mdev = priv->mdev;
 386         struct mlx5e_vport_stats *s = &priv->stats.vport;
 387         struct mlx5e_rq_stats *rq_stats;
 388         struct mlx5e_sq_stats *sq_stats;
 389         struct buf_ring *sq_br;
 390 #if (__FreeBSD_version < 1100000)
 391         struct ifnet *ifp = priv->ifp;
 392 #endif
 393
 394         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 395         u32 *out;
 396         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 397         u64 tso_packets = 0;
 398         u64 tso_bytes = 0;
 399         u64 tx_queue_dropped = 0;
 400         u64 tx_defragged = 0;
 401         u64 tx_offload_none = 0;
 402         u64 lro_packets = 0;
 403         u64 lro_bytes = 0;
 404         u64 sw_lro_queued = 0;
 405         u64 sw_lro_flushed = 0;
 406         u64 rx_csum_none = 0;
 407         u64 rx_wqe_err = 0;
 408         u32 rx_out_of_buffer = 0;
 409         int i;
 410         int j;
 411
 412         PRIV_LOCK(priv);
 413         out = mlx5_vzalloc(outlen);
 414         if (out == NULL)
 415                 goto free_out;
 416         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 417                 goto free_out;
 418
 419         /* Collect firts the SW counters and then HW for consistency */
 420         for (i = 0; i < priv->params.num_channels; i++) {
 421                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 422
 423                 rq_stats = &priv->channel[i]->rq.stats;
 424
 425                 /* collect stats from LRO */
 426                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 427                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 428                 sw_lro_queued += rq_stats->sw_lro_queued;
 429                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 430                 lro_packets += rq_stats->lro_packets;
 431                 lro_bytes += rq_stats->lro_bytes;
 432                 rx_csum_none += rq_stats->csum_none;
 433                 rx_wqe_err += rq_stats->wqe_err;
 434
 435                 for (j = 0; j < priv->num_tc; j++) {
 436                         sq_stats = &priv->channel[i]->sq[j].stats;
 437                         sq_br = priv->channel[i]->sq[j].br;
 438
 439                         tso_packets += sq_stats->tso_packets;
 440                         tso_bytes += sq_stats->tso_bytes;
 441                         tx_queue_dropped += sq_stats->dropped;
 442                         if (sq_br != NULL)
 443                                 tx_queue_dropped += sq_br->br_drops;
 444                         tx_defragged += sq_stats->defragged;
 445                         tx_offload_none += sq_stats->csum_offload_none;
 446                 }
 447         }
 448
 449         /* update counters */
 450         s->tso_packets = tso_packets;
 451         s->tso_bytes = tso_bytes;
 452         s->tx_queue_dropped = tx_queue_dropped;
 453         s->tx_defragged = tx_defragged;
 454         s->lro_packets = lro_packets;
 455         s->lro_bytes = lro_bytes;
 456         s->sw_lro_queued = sw_lro_queued;
 457         s->sw_lro_flushed = sw_lro_flushed;
 458         s->rx_csum_none = rx_csum_none;
 459         s->rx_wqe_err = rx_wqe_err;
 460
 461         /* HW counters */
 462         memset(in, 0, sizeof(in));
 463
 464         MLX5_SET(query_vport_counter_in, in, opcode,
 465             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 466         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 467         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 468
 469         memset(out, 0, outlen);
 470
 471         /* get number of out-of-buffer drops first */
 472         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 473             &rx_out_of_buffer))
 474                 goto free_out;
 475
 476         /* accumulate difference into a 64-bit counter */
 477         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 478         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 479
 480         /* get port statistics */
 481         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 482                 goto free_out;
 483
 484 #define MLX5_GET_CTR(out, x) \
 485         MLX5_GET64(query_vport_counter_out, out, x)
 486
 487         s->rx_error_packets =
 488             MLX5_GET_CTR(out, received_errors.packets);
 489         s->rx_error_bytes =
 490             MLX5_GET_CTR(out, received_errors.octets);
 491         s->tx_error_packets =
 492             MLX5_GET_CTR(out, transmit_errors.packets);
 493         s->tx_error_bytes =
 494             MLX5_GET_CTR(out, transmit_errors.octets);
 495
 496         s->rx_unicast_packets =
 497             MLX5_GET_CTR(out, received_eth_unicast.packets);
 498         s->rx_unicast_bytes =
 499             MLX5_GET_CTR(out, received_eth_unicast.octets);
 500         s->tx_unicast_packets =
 501             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 502         s->tx_unicast_bytes =
 503             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 504
 505         s->rx_multicast_packets =
 506             MLX5_GET_CTR(out, received_eth_multicast.packets);
 507         s->rx_multicast_bytes =
 508             MLX5_GET_CTR(out, received_eth_multicast.octets);
 509         s->tx_multicast_packets =
 510             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 511         s->tx_multicast_bytes =
 512             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 513
 514         s->rx_broadcast_packets =
 515             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 516         s->rx_broadcast_bytes =
 517             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 518         s->tx_broadcast_packets =
 519             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 520         s->tx_broadcast_bytes =
 521             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 522
 523         s->rx_packets =
 524             s->rx_unicast_packets +
 525             s->rx_multicast_packets +
 526             s->rx_broadcast_packets -
 527             s->rx_out_of_buffer;
 528         s->rx_bytes =
 529             s->rx_unicast_bytes +
 530             s->rx_multicast_bytes +
 531             s->rx_broadcast_bytes;
 532         s->tx_packets =
 533             s->tx_unicast_packets +
 534             s->tx_multicast_packets +
 535             s->tx_broadcast_packets;
 536         s->tx_bytes =
 537             s->tx_unicast_bytes +
 538             s->tx_multicast_bytes +
 539             s->tx_broadcast_bytes;
 540
 541         /* Update calculated offload counters */
 542         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 543         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 544
 545         /* Get physical port counters */
 546         mlx5e_update_pport_counters(priv);
 547
 548 #if (__FreeBSD_version < 1100000)
 549         /* no get_counters interface in fbsd 10 */
 550         ifp->if_ipackets = s->rx_packets;
 551         ifp->if_ierrors = s->rx_error_packets +
 552             priv->stats.pport.alignment_err +
 553             priv->stats.pport.check_seq_err +
 554             priv->stats.pport.crc_align_errors +
 555             priv->stats.pport.drop_events +
 556             priv->stats.pport.in_range_len_errors +
 557             priv->stats.pport.jabbers +
 558             priv->stats.pport.out_of_range_len +
 559             priv->stats.pport.oversize_pkts +
 560             priv->stats.pport.symbol_err +
 561             priv->stats.pport.too_long_errors +
 562             priv->stats.pport.undersize_pkts +
 563             priv->stats.pport.unsupported_op_rx;
 564         ifp->if_iqdrops = s->rx_out_of_buffer;
 565         ifp->if_opackets = s->tx_packets;
 566         ifp->if_oerrors = s->tx_error_packets;
 567         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 568         ifp->if_ibytes = s->rx_bytes;
 569         ifp->if_obytes = s->tx_bytes;
 570         ifp->if_collisions =
 571             priv->stats.pport.collisions;
 572 #endif
 573
 574 free_out:
 575         kvfree(out);
 576         PRIV_UNLOCK(priv);
 577 }
 578
 579 static void
 580 mlx5e_update_stats(void *arg)
 581 {
 582         struct mlx5e_priv *priv = arg;
 583
 584         schedule_work(&priv->update_stats_work);
 585
 586         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 587 }
 588
 589 static void
 590 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 591     enum mlx5_dev_event event)
 592 {
 593         switch (event) {
 594         case MLX5_DEV_EVENT_PORT_UP:
 595         case MLX5_DEV_EVENT_PORT_DOWN:
 596                 schedule_work(&priv->update_carrier_work);
 597                 break;
 598
 599         default:
 600                 break;
 601         }
 602 }
 603
 604 static void
 605 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 606     enum mlx5_dev_event event, unsigned long param)
 607 {
 608         struct mlx5e_priv *priv = vpriv;
 609
 610         mtx_lock(&priv->async_events_mtx);
 611         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 612                 mlx5e_async_event_sub(priv, event);
 613         mtx_unlock(&priv->async_events_mtx);
 614 }
 615
 616 static void
 617 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 618 {
 619         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 620 }
 621
 622 static void
 623 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 624 {
 625         mtx_lock(&priv->async_events_mtx);
 626         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 627         mtx_unlock(&priv->async_events_mtx);
 628 }
 629
 630 static const char *mlx5e_rq_stats_desc[] = {
 631         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 632 };
 633
 634 static int
 635 mlx5e_create_rq(struct mlx5e_channel *c,
 636     struct mlx5e_rq_param *param,
 637     struct mlx5e_rq *rq)
 638 {
 639         struct mlx5e_priv *priv = c->priv;
 640         struct mlx5_core_dev *mdev = priv->mdev;
 641         char buffer[16];
 642         void *rqc = param->rqc;
 643         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 644         int wq_sz;
 645         int err;
 646         int i;
 647
 648         /* Create DMA descriptor TAG */
 649         if ((err = -bus_dma_tag_create(
 650             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 651             1,                          /* any alignment */
 652             0,                          /* no boundary */
 653             BUS_SPACE_MAXADDR,          /* lowaddr */
 654             BUS_SPACE_MAXADDR,          /* highaddr */
 655             NULL, NULL,                 /* filter, filterarg */
 656             MJUM16BYTES,                /* maxsize */
 657             1,                          /* nsegments */
 658             MJUM16BYTES,                /* maxsegsize */
 659             0,                          /* flags */
 660             NULL, NULL,                 /* lockfunc, lockfuncarg */
 661             &rq->dma_tag)))
 662                 goto done;
 663
 664         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 665             &rq->wq_ctrl);
 666         if (err)
 667                 goto err_free_dma_tag;
 668
 669         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 670
 671         if (priv->params.hw_lro_en) {
 672                 rq->wqe_sz = priv->params.lro_wqe_sz;
 673         } else {
 674                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 675         }
 676         if (rq->wqe_sz > MJUM16BYTES) {
 677                 err = -ENOMEM;
 678                 goto err_rq_wq_destroy;
 679         } else if (rq->wqe_sz > MJUM9BYTES) {
 680                 rq->wqe_sz = MJUM16BYTES;
 681         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 682                 rq->wqe_sz = MJUM9BYTES;
 683         } else if (rq->wqe_sz > MCLBYTES) {
 684                 rq->wqe_sz = MJUMPAGESIZE;
 685         } else {
 686                 rq->wqe_sz = MCLBYTES;
 687         }
 688
 689         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 690         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 691         for (i = 0; i != wq_sz; i++) {
 692                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 693                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 694
 695                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 696                 if (err != 0) {
 697                         while (i--)
 698                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 699                         goto err_rq_mbuf_free;
 700                 }
 701                 wqe->data.lkey = c->mkey_be;
 702                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 703         }
 704
 705         rq->ifp = c->ifp;
 706         rq->channel = c;
 707         rq->ix = c->ix;
 708
 709         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 710         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 711             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 712             rq->stats.arg);
 713
 714 #ifdef HAVE_TURBO_LRO
 715         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 716                 rq->lro.mbuf = NULL;
 717 #else
 718         if (tcp_lro_init(&rq->lro))
 719                 rq->lro.lro_cnt = 0;
 720         else
 721                 rq->lro.ifp = c->ifp;
 722 #endif
 723         return (0);
 724
 725 err_rq_mbuf_free:
 726         free(rq->mbuf, M_MLX5EN);
 727 err_rq_wq_destroy:
 728         mlx5_wq_destroy(&rq->wq_ctrl);
 729 err_free_dma_tag:
 730         bus_dma_tag_destroy(rq->dma_tag);
 731 done:
 732         return (err);
 733 }
 734
 735 static void
 736 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 737 {
 738         int wq_sz;
 739         int i;
 740
 741         /* destroy all sysctl nodes */
 742         sysctl_ctx_free(&rq->stats.ctx);
 743
 744         /* free leftover LRO packets, if any */
 745 #ifdef HAVE_TURBO_LRO
 746         tcp_tlro_free(&rq->lro);
 747 #else
 748         tcp_lro_free(&rq->lro);
 749 #endif
 750         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 751         for (i = 0; i != wq_sz; i++) {
 752                 if (rq->mbuf[i].mbuf != NULL) {
 753                         bus_dmamap_unload(rq->dma_tag,
 754                             rq->mbuf[i].dma_map);
 755                         m_freem(rq->mbuf[i].mbuf);
 756                 }
 757                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 758         }
 759         free(rq->mbuf, M_MLX5EN);
 760         mlx5_wq_destroy(&rq->wq_ctrl);
 761 }
 762
 763 static int
 764 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 765 {
 766         struct mlx5e_channel *c = rq->channel;
 767         struct mlx5e_priv *priv = c->priv;
 768         struct mlx5_core_dev *mdev = priv->mdev;
 769
 770         void *in;
 771         void *rqc;
 772         void *wq;
 773         int inlen;
 774         int err;
 775
 776         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 777             sizeof(u64) * rq->wq_ctrl.buf.npages;
 778         in = mlx5_vzalloc(inlen);
 779         if (in == NULL)
 780                 return (-ENOMEM);
 781
 782         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 783         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 784
 785         memcpy(rqc, param->rqc, sizeof(param->rqc));
 786
 787         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 788         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 789         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 790         if (priv->counter_set_id >= 0)
 791                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 792         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 793             PAGE_SHIFT);
 794         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 795
 796         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 797             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 798
 799         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 800
 801         kvfree(in);
 802
 803         return (err);
 804 }
 805
 806 static int
 807 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 808 {
 809         struct mlx5e_channel *c = rq->channel;
 810         struct mlx5e_priv *priv = c->priv;
 811         struct mlx5_core_dev *mdev = priv->mdev;
 812
 813         void *in;
 814         void *rqc;
 815         int inlen;
 816         int err;
 817
 818         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 819         in = mlx5_vzalloc(inlen);
 820         if (in == NULL)
 821                 return (-ENOMEM);
 822
 823         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 824
 825         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 826         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 827         MLX5_SET(rqc, rqc, state, next_state);
 828
 829         err = mlx5_core_modify_rq(mdev, in, inlen);
 830
 831         kvfree(in);
 832
 833         return (err);
 834 }
 835
 836 static void
 837 mlx5e_disable_rq(struct mlx5e_rq *rq)
 838 {
 839         struct mlx5e_channel *c = rq->channel;
 840         struct mlx5e_priv *priv = c->priv;
 841         struct mlx5_core_dev *mdev = priv->mdev;
 842
 843         mlx5_core_destroy_rq(mdev, rq->rqn);
 844 }
 845
 846 static int
 847 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 848 {
 849         struct mlx5e_channel *c = rq->channel;
 850         struct mlx5e_priv *priv = c->priv;
 851         struct mlx5_wq_ll *wq = &rq->wq;
 852         int i;
 853
 854         for (i = 0; i < 1000; i++) {
 855                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 856                         return (0);
 857
 858                 msleep(4);
 859         }
 860         return (-ETIMEDOUT);
 861 }
 862
 863 static int
 864 mlx5e_open_rq(struct mlx5e_channel *c,
 865     struct mlx5e_rq_param *param,
 866     struct mlx5e_rq *rq)
 867 {
 868         int err;
 869
 870         err = mlx5e_create_rq(c, param, rq);
 871         if (err)
 872                 return (err);
 873
 874         err = mlx5e_enable_rq(rq, param);
 875         if (err)
 876                 goto err_destroy_rq;
 877
 878         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 879         if (err)
 880                 goto err_disable_rq;
 881
 882         c->rq.enabled = 1;
 883
 884         return (0);
 885
 886 err_disable_rq:
 887         mlx5e_disable_rq(rq);
 888 err_destroy_rq:
 889         mlx5e_destroy_rq(rq);
 890
 891         return (err);
 892 }
 893
 894 static void
 895 mlx5e_close_rq(struct mlx5e_rq *rq)
 896 {
 897         mtx_lock(&rq->mtx);
 898         rq->enabled = 0;
 899         callout_stop(&rq->watchdog);
 900         mtx_unlock(&rq->mtx);
 901
 902         callout_drain(&rq->watchdog);
 903
 904         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 905 }
 906
 907 static void
 908 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 909 {
 910         /* wait till RQ is empty */
 911         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 912                 msleep(4);
 913                 rq->cq.mcq.comp(&rq->cq.mcq);
 914         }
 915
 916         mlx5e_disable_rq(rq);
 917         mlx5e_destroy_rq(rq);
 918 }
 919
 920 void
 921 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 922 {
 923         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 924         int x;
 925
 926         for (x = 0; x != wq_sz; x++)
 927                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 928         free(sq->mbuf, M_MLX5EN);
 929 }
 930
 931 int
 932 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 933 {
 934         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 935         int err;
 936         int x;
 937
 938         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 939
 940         /* Create DMA descriptor MAPs */
 941         for (x = 0; x != wq_sz; x++) {
 942                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 943                 if (err != 0) {
 944                         while (x--)
 945                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 946                         free(sq->mbuf, M_MLX5EN);
 947                         return (err);
 948                 }
 949         }
 950         return (0);
 951 }
 952
 953 static const char *mlx5e_sq_stats_desc[] = {
 954         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 955 };
 956
 957 static int
 958 mlx5e_create_sq(struct mlx5e_channel *c,
 959     int tc,
 960     struct mlx5e_sq_param *param,
 961     struct mlx5e_sq *sq)
 962 {
 963         struct mlx5e_priv *priv = c->priv;
 964         struct mlx5_core_dev *mdev = priv->mdev;
 965         char buffer[16];
 966
 967         void *sqc = param->sqc;
 968         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 969 #ifdef RSS
 970         cpuset_t cpu_mask;
 971         int cpu_id;
 972 #endif
 973         int err;
 974
 975         /* Create DMA descriptor TAG */
 976         if ((err = -bus_dma_tag_create(
 977             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 978             1,                          /* any alignment */
 979             0,                          /* no boundary */
 980             BUS_SPACE_MAXADDR,          /* lowaddr */
 981             BUS_SPACE_MAXADDR,          /* highaddr */
 982             NULL, NULL,                 /* filter, filterarg */
 983             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 984             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 985             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 986             0,                          /* flags */
 987             NULL, NULL,                 /* lockfunc, lockfuncarg */
 988             &sq->dma_tag)))
 989                 goto done;
 990
 991         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 992         if (err)
 993                 goto err_free_dma_tag;
 994
 995         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 996             &sq->wq_ctrl);
 997         if (err)
 998                 goto err_unmap_free_uar;
 999
1000         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1001         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1002
1003         err = mlx5e_alloc_sq_db(sq);
1004         if (err)
1005                 goto err_sq_wq_destroy;
1006
1007         sq->mkey_be = c->mkey_be;
1008         sq->ifp = priv->ifp;
1009         sq->priv = priv;
1010         sq->tc = tc;
1011
1012         /* check if we should allocate a second packet buffer */
1013         if (priv->params_ethtool.tx_bufring_disable == 0) {
1014                 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1015                     M_WAITOK, &sq->lock);
1016                 if (sq->br == NULL) {
1017                         if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1018                             __func__);
1019                         err = -ENOMEM;
1020                         goto err_free_sq_db;
1021                 }
1022
1023                 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1024                     taskqueue_thread_enqueue, &sq->sq_tq);
1025                 if (sq->sq_tq == NULL) {
1026                         if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1027                             __func__);
1028                         err = -ENOMEM;
1029                         goto err_free_drbr;
1030                 }
1031
1032                 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1033 #ifdef RSS
1034                 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1035                 CPU_SETOF(cpu_id, &cpu_mask);
1036                 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1037                     "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1038 #else
1039                 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1040                     "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1041 #endif
1042         }
1043         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1044         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1045             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1046             sq->stats.arg);
1047
1048         return (0);
1049
1050 err_free_drbr:
1051         buf_ring_free(sq->br, M_MLX5EN);
1052 err_free_sq_db:
1053         mlx5e_free_sq_db(sq);
1054 err_sq_wq_destroy:
1055         mlx5_wq_destroy(&sq->wq_ctrl);
1056
1057 err_unmap_free_uar:
1058         mlx5_unmap_free_uar(mdev, &sq->uar);
1059
1060 err_free_dma_tag:
1061         bus_dma_tag_destroy(sq->dma_tag);
1062 done:
1063         return (err);
1064 }
1065
1066 static void
1067 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1068 {
1069         /* destroy all sysctl nodes */
1070         sysctl_ctx_free(&sq->stats.ctx);
1071
1072         mlx5e_free_sq_db(sq);
1073         mlx5_wq_destroy(&sq->wq_ctrl);
1074         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1075         if (sq->sq_tq != NULL) {
1076                 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1077                 taskqueue_free(sq->sq_tq);
1078         }
1079         if (sq->br != NULL)
1080                 buf_ring_free(sq->br, M_MLX5EN);
1081 }
1082
1083 int
1084 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1085     int tis_num)
1086 {
1087         void *in;
1088         void *sqc;
1089         void *wq;
1090         int inlen;
1091         int err;
1092
1093         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1094             sizeof(u64) * sq->wq_ctrl.buf.npages;
1095         in = mlx5_vzalloc(inlen);
1096         if (in == NULL)
1097                 return (-ENOMEM);
1098
1099         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1100         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1101
1102         memcpy(sqc, param->sqc, sizeof(param->sqc));
1103
1104         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1105         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1106         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1107         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1108         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1109
1110         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1111         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1112         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1113             PAGE_SHIFT);
1114         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1115
1116         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1117             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1118
1119         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1120
1121         kvfree(in);
1122
1123         return (err);
1124 }
1125
1126 int
1127 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1128 {
1129         void *in;
1130         void *sqc;
1131         int inlen;
1132         int err;
1133
1134         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1135         in = mlx5_vzalloc(inlen);
1136         if (in == NULL)
1137                 return (-ENOMEM);
1138
1139         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1140
1141         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1142         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1143         MLX5_SET(sqc, sqc, state, next_state);
1144
1145         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1146
1147         kvfree(in);
1148
1149         return (err);
1150 }
1151
1152 void
1153 mlx5e_disable_sq(struct mlx5e_sq *sq)
1154 {
1155
1156         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1157 }
1158
1159 static int
1160 mlx5e_open_sq(struct mlx5e_channel *c,
1161     int tc,
1162     struct mlx5e_sq_param *param,
1163     struct mlx5e_sq *sq)
1164 {
1165         int err;
1166
1167         err = mlx5e_create_sq(c, tc, param, sq);
1168         if (err)
1169                 return (err);
1170
1171         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1172         if (err)
1173                 goto err_destroy_sq;
1174
1175         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1176         if (err)
1177                 goto err_disable_sq;
1178
1179         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1180
1181         return (0);
1182
1183 err_disable_sq:
1184         mlx5e_disable_sq(sq);
1185 err_destroy_sq:
1186         mlx5e_destroy_sq(sq);
1187
1188         return (err);
1189 }
1190
1191 static void
1192 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1193 {
1194         /* fill up remainder with NOPs */
1195         while (sq->cev_counter != 0) {
1196                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1197                         if (can_sleep != 0) {
1198                                 mtx_unlock(&sq->lock);
1199                                 msleep(4);
1200                                 mtx_lock(&sq->lock);
1201                         } else {
1202                                 goto done;
1203                         }
1204                 }
1205                 /* send a single NOP */
1206                 mlx5e_send_nop(sq, 1);
1207                 wmb();
1208         }
1209 done:
1210         /* Check if we need to write the doorbell */
1211         if (likely(sq->doorbell.d64 != 0)) {
1212                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1213                 sq->doorbell.d64 = 0;
1214         }
1215         return;
1216 }
1217
1218 void
1219 mlx5e_sq_cev_timeout(void *arg)
1220 {
1221         struct mlx5e_sq *sq = arg;
1222
1223         mtx_assert(&sq->lock, MA_OWNED);
1224
1225         /* check next state */
1226         switch (sq->cev_next_state) {
1227         case MLX5E_CEV_STATE_SEND_NOPS:
1228                 /* fill TX ring with NOPs, if any */
1229                 mlx5e_sq_send_nops_locked(sq, 0);
1230
1231                 /* check if completed */
1232                 if (sq->cev_counter == 0) {
1233                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1234                         return;
1235                 }
1236                 break;
1237         default:
1238                 /* send NOPs on next timeout */
1239                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1240                 break;
1241         }
1242
1243         /* restart timer */
1244         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1245 }
1246
1247 void
1248 mlx5e_drain_sq(struct mlx5e_sq *sq)
1249 {
1250         int error;
1251
1252         /*
1253          * Check if already stopped.
1254          *
1255          * NOTE: The "stopped" variable is only written when both the
1256          * priv's configuration lock and the SQ's lock is locked. It
1257          * can therefore safely be read when only one of the two locks
1258          * is locked. This function is always called when the priv's
1259          * configuration lock is locked.
1260          */
1261         if (sq->stopped != 0)
1262                 return;
1263
1264         mtx_lock(&sq->lock);
1265
1266         /* don't put more packets into the SQ */
1267         sq->stopped = 1;
1268
1269         /* teardown event factor timer, if any */
1270         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1271         callout_stop(&sq->cev_callout);
1272
1273         /* send dummy NOPs in order to flush the transmit ring */
1274         mlx5e_sq_send_nops_locked(sq, 1);
1275         mtx_unlock(&sq->lock);
1276
1277         /* make sure it is safe to free the callout */
1278         callout_drain(&sq->cev_callout);
1279
1280         /* wait till SQ is empty or link is down */
1281         mtx_lock(&sq->lock);
1282         while (sq->cc != sq->pc &&
1283             (sq->priv->media_status_last & IFM_ACTIVE) != 0) {
1284                 mtx_unlock(&sq->lock);
1285                 msleep(1);
1286                 sq->cq.mcq.comp(&sq->cq.mcq);
1287                 mtx_lock(&sq->lock);
1288         }
1289         mtx_unlock(&sq->lock);
1290
1291         /* error out remaining requests */
1292         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1293         if (error != 0) {
1294                 if_printf(sq->ifp,
1295                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1296         }
1297
1298         /* wait till SQ is empty */
1299         mtx_lock(&sq->lock);
1300         while (sq->cc != sq->pc) {
1301                 mtx_unlock(&sq->lock);
1302                 msleep(1);
1303                 sq->cq.mcq.comp(&sq->cq.mcq);
1304                 mtx_lock(&sq->lock);
1305         }
1306         mtx_unlock(&sq->lock);
1307 }
1308
1309 static void
1310 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1311 {
1312
1313         mlx5e_drain_sq(sq);
1314         mlx5e_disable_sq(sq);
1315         mlx5e_destroy_sq(sq);
1316 }
1317
1318 static int
1319 mlx5e_create_cq(struct mlx5e_priv *priv,
1320     struct mlx5e_cq_param *param,
1321     struct mlx5e_cq *cq,
1322     mlx5e_cq_comp_t *comp,
1323     int eq_ix)
1324 {
1325         struct mlx5_core_dev *mdev = priv->mdev;
1326         struct mlx5_core_cq *mcq = &cq->mcq;
1327         int eqn_not_used;
1328         int irqn;
1329         int err;
1330         u32 i;
1331
1332         param->wq.buf_numa_node = 0;
1333         param->wq.db_numa_node = 0;
1334
1335         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1336             &cq->wq_ctrl);
1337         if (err)
1338                 return (err);
1339
1340         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1341
1342         mcq->cqe_sz = 64;
1343         mcq->set_ci_db = cq->wq_ctrl.db.db;
1344         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1345         *mcq->set_ci_db = 0;
1346         *mcq->arm_db = 0;
1347         mcq->vector = eq_ix;
1348         mcq->comp = comp;
1349         mcq->event = mlx5e_cq_error_event;
1350         mcq->irqn = irqn;
1351         mcq->uar = &priv->cq_uar;
1352
1353         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1354                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1355
1356                 cqe->op_own = 0xf1;
1357         }
1358
1359         cq->priv = priv;
1360
1361         return (0);
1362 }
1363
1364 static void
1365 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1366 {
1367         mlx5_wq_destroy(&cq->wq_ctrl);
1368 }
1369
1370 static int
1371 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1372 {
1373         struct mlx5_core_cq *mcq = &cq->mcq;
1374         void *in;
1375         void *cqc;
1376         int inlen;
1377         int irqn_not_used;
1378         int eqn;
1379         int err;
1380
1381         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1382             sizeof(u64) * cq->wq_ctrl.buf.npages;
1383         in = mlx5_vzalloc(inlen);
1384         if (in == NULL)
1385                 return (-ENOMEM);
1386
1387         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1388
1389         memcpy(cqc, param->cqc, sizeof(param->cqc));
1390
1391         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1392             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1393
1394         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1395
1396         MLX5_SET(cqc, cqc, c_eqn, eqn);
1397         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1398         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1399             PAGE_SHIFT);
1400         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1401
1402         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1403
1404         kvfree(in);
1405
1406         if (err)
1407                 return (err);
1408
1409         mlx5e_cq_arm(cq);
1410
1411         return (0);
1412 }
1413
1414 static void
1415 mlx5e_disable_cq(struct mlx5e_cq *cq)
1416 {
1417
1418         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1419 }
1420
1421 int
1422 mlx5e_open_cq(struct mlx5e_priv *priv,
1423     struct mlx5e_cq_param *param,
1424     struct mlx5e_cq *cq,
1425     mlx5e_cq_comp_t *comp,
1426     int eq_ix)
1427 {
1428         int err;
1429
1430         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1431         if (err)
1432                 return (err);
1433
1434         err = mlx5e_enable_cq(cq, param, eq_ix);
1435         if (err)
1436                 goto err_destroy_cq;
1437
1438         return (0);
1439
1440 err_destroy_cq:
1441         mlx5e_destroy_cq(cq);
1442
1443         return (err);
1444 }
1445
1446 void
1447 mlx5e_close_cq(struct mlx5e_cq *cq)
1448 {
1449         mlx5e_disable_cq(cq);
1450         mlx5e_destroy_cq(cq);
1451 }
1452
1453 static int
1454 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1455     struct mlx5e_channel_param *cparam)
1456 {
1457         int err;
1458         int tc;
1459
1460         for (tc = 0; tc < c->num_tc; tc++) {
1461                 /* open completion queue */
1462                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1463                     &mlx5e_tx_cq_comp, c->ix);
1464                 if (err)
1465                         goto err_close_tx_cqs;
1466         }
1467         return (0);
1468
1469 err_close_tx_cqs:
1470         for (tc--; tc >= 0; tc--)
1471                 mlx5e_close_cq(&c->sq[tc].cq);
1472
1473         return (err);
1474 }
1475
1476 static void
1477 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1478 {
1479         int tc;
1480
1481         for (tc = 0; tc < c->num_tc; tc++)
1482                 mlx5e_close_cq(&c->sq[tc].cq);
1483 }
1484
1485 static int
1486 mlx5e_open_sqs(struct mlx5e_channel *c,
1487     struct mlx5e_channel_param *cparam)
1488 {
1489         int err;
1490         int tc;
1491
1492         for (tc = 0; tc < c->num_tc; tc++) {
1493                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1494                 if (err)
1495                         goto err_close_sqs;
1496         }
1497
1498         return (0);
1499
1500 err_close_sqs:
1501         for (tc--; tc >= 0; tc--)
1502                 mlx5e_close_sq_wait(&c->sq[tc]);
1503
1504         return (err);
1505 }
1506
1507 static void
1508 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1509 {
1510         int tc;
1511
1512         for (tc = 0; tc < c->num_tc; tc++)
1513                 mlx5e_close_sq_wait(&c->sq[tc]);
1514 }
1515
1516 static void
1517 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1518 {
1519         int tc;
1520
1521         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1522
1523         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1524
1525         for (tc = 0; tc < c->num_tc; tc++) {
1526                 struct mlx5e_sq *sq = c->sq + tc;
1527
1528                 mtx_init(&sq->lock, "mlx5tx",
1529                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1530                 mtx_init(&sq->comp_lock, "mlx5comp",
1531                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1532
1533                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1534
1535                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1536
1537                 /* ensure the TX completion event factor is not zero */
1538                 if (sq->cev_factor == 0)
1539                         sq->cev_factor = 1;
1540         }
1541 }
1542
1543 static void
1544 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1545 {
1546         int tc;
1547
1548         mtx_destroy(&c->rq.mtx);
1549
1550         for (tc = 0; tc < c->num_tc; tc++) {
1551                 mtx_destroy(&c->sq[tc].lock);
1552                 mtx_destroy(&c->sq[tc].comp_lock);
1553         }
1554 }
1555
1556 static int
1557 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1558     struct mlx5e_channel_param *cparam,
1559     struct mlx5e_channel *volatile *cp)
1560 {
1561         struct mlx5e_channel *c;
1562         int err;
1563
1564         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1565         c->priv = priv;
1566         c->ix = ix;
1567         c->cpu = 0;
1568         c->ifp = priv->ifp;
1569         c->mkey_be = cpu_to_be32(priv->mr.key);
1570         c->num_tc = priv->num_tc;
1571
1572         /* init mutexes */
1573         mlx5e_chan_mtx_init(c);
1574
1575         /* open transmit completion queue */
1576         err = mlx5e_open_tx_cqs(c, cparam);
1577         if (err)
1578                 goto err_free;
1579
1580         /* open receive completion queue */
1581         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1582             &mlx5e_rx_cq_comp, c->ix);
1583         if (err)
1584                 goto err_close_tx_cqs;
1585
1586         err = mlx5e_open_sqs(c, cparam);
1587         if (err)
1588                 goto err_close_rx_cq;
1589
1590         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1591         if (err)
1592                 goto err_close_sqs;
1593
1594         /* store channel pointer */
1595         *cp = c;
1596
1597         /* poll receive queue initially */
1598         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1599
1600         return (0);
1601
1602 err_close_sqs:
1603         mlx5e_close_sqs_wait(c);
1604
1605 err_close_rx_cq:
1606         mlx5e_close_cq(&c->rq.cq);
1607
1608 err_close_tx_cqs:
1609         mlx5e_close_tx_cqs(c);
1610
1611 err_free:
1612         /* destroy mutexes */
1613         mlx5e_chan_mtx_destroy(c);
1614         free(c, M_MLX5EN);
1615         return (err);
1616 }
1617
1618 static void
1619 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1620 {
1621         struct mlx5e_channel *c = *pp;
1622
1623         /* check if channel is already closed */
1624         if (c == NULL)
1625                 return;
1626         mlx5e_close_rq(&c->rq);
1627 }
1628
1629 static void
1630 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1631 {
1632         struct mlx5e_channel *c = *pp;
1633
1634         /* check if channel is already closed */
1635         if (c == NULL)
1636                 return;
1637         /* ensure channel pointer is no longer used */
1638         *pp = NULL;
1639
1640         mlx5e_close_rq_wait(&c->rq);
1641         mlx5e_close_sqs_wait(c);
1642         mlx5e_close_cq(&c->rq.cq);
1643         mlx5e_close_tx_cqs(c);
1644         /* destroy mutexes */
1645         mlx5e_chan_mtx_destroy(c);
1646         free(c, M_MLX5EN);
1647 }
1648
1649 static void
1650 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1651     struct mlx5e_rq_param *param)
1652 {
1653         void *rqc = param->rqc;
1654         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1655
1656         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1657         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1658         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1659         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1660         MLX5_SET(wq, wq, pd, priv->pdn);
1661
1662         param->wq.buf_numa_node = 0;
1663         param->wq.db_numa_node = 0;
1664         param->wq.linear = 1;
1665 }
1666
1667 static void
1668 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1669     struct mlx5e_sq_param *param)
1670 {
1671         void *sqc = param->sqc;
1672         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1673
1674         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1675         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1676         MLX5_SET(wq, wq, pd, priv->pdn);
1677
1678         param->wq.buf_numa_node = 0;
1679         param->wq.db_numa_node = 0;
1680         param->wq.linear = 1;
1681 }
1682
1683 static void
1684 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1685     struct mlx5e_cq_param *param)
1686 {
1687         void *cqc = param->cqc;
1688
1689         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1690 }
1691
1692 static void
1693 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1694     struct mlx5e_cq_param *param)
1695 {
1696         void *cqc = param->cqc;
1697
1698
1699         /*
1700          * TODO The sysctl to control on/off is a bool value for now, which means
1701          * we only support CSUM, once HASH is implemnted we'll need to address that.
1702          */
1703         if (priv->params.cqe_zipping_en) {
1704                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1705                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1706         }
1707
1708         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1709         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1710         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1711
1712         switch (priv->params.rx_cq_moderation_mode) {
1713         case 0:
1714                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1715                 break;
1716         default:
1717                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1718                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1719                 else
1720                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1721                 break;
1722         }
1723
1724         mlx5e_build_common_cq_param(priv, param);
1725 }
1726
1727 static void
1728 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1729     struct mlx5e_cq_param *param)
1730 {
1731         void *cqc = param->cqc;
1732
1733         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1734         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1735         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1736
1737         switch (priv->params.tx_cq_moderation_mode) {
1738         case 0:
1739                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1740                 break;
1741         default:
1742                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1743                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1744                 else
1745                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1746                 break;
1747         }
1748
1749         mlx5e_build_common_cq_param(priv, param);
1750 }
1751
1752 static void
1753 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1754     struct mlx5e_channel_param *cparam)
1755 {
1756         memset(cparam, 0, sizeof(*cparam));
1757
1758         mlx5e_build_rq_param(priv, &cparam->rq);
1759         mlx5e_build_sq_param(priv, &cparam->sq);
1760         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1761         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1762 }
1763
1764 static int
1765 mlx5e_open_channels(struct mlx5e_priv *priv)
1766 {
1767         struct mlx5e_channel_param cparam;
1768         void *ptr;
1769         int err;
1770         int i;
1771         int j;
1772
1773         priv->channel = malloc(priv->params.num_channels *
1774             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1775
1776         mlx5e_build_channel_param(priv, &cparam);
1777         for (i = 0; i < priv->params.num_channels; i++) {
1778                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1779                 if (err)
1780                         goto err_close_channels;
1781         }
1782
1783         for (j = 0; j < priv->params.num_channels; j++) {
1784                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1785                 if (err)
1786                         goto err_close_channels;
1787         }
1788
1789         return (0);
1790
1791 err_close_channels:
1792         for (i--; i >= 0; i--) {
1793                 mlx5e_close_channel(&priv->channel[i]);
1794                 mlx5e_close_channel_wait(&priv->channel[i]);
1795         }
1796
1797         /* remove "volatile" attribute from "channel" pointer */
1798         ptr = __DECONST(void *, priv->channel);
1799         priv->channel = NULL;
1800
1801         free(ptr, M_MLX5EN);
1802
1803         return (err);
1804 }
1805
1806 static void
1807 mlx5e_close_channels(struct mlx5e_priv *priv)
1808 {
1809         void *ptr;
1810         int i;
1811
1812         if (priv->channel == NULL)
1813                 return;
1814
1815         for (i = 0; i < priv->params.num_channels; i++)
1816                 mlx5e_close_channel(&priv->channel[i]);
1817         for (i = 0; i < priv->params.num_channels; i++)
1818                 mlx5e_close_channel_wait(&priv->channel[i]);
1819
1820         /* remove "volatile" attribute from "channel" pointer */
1821         ptr = __DECONST(void *, priv->channel);
1822         priv->channel = NULL;
1823
1824         free(ptr, M_MLX5EN);
1825 }
1826
1827 static int
1828 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1829 {
1830
1831         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1832                 uint8_t cq_mode;
1833
1834                 switch (priv->params.tx_cq_moderation_mode) {
1835                 case 0:
1836                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1837                         break;
1838                 default:
1839                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1840                         break;
1841                 }
1842
1843                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1844                     priv->params.tx_cq_moderation_usec,
1845                     priv->params.tx_cq_moderation_pkts,
1846                     cq_mode));
1847         }
1848
1849         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1850             priv->params.tx_cq_moderation_usec,
1851             priv->params.tx_cq_moderation_pkts));
1852 }
1853
1854 static int
1855 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1856 {
1857
1858         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1859                 uint8_t cq_mode;
1860                 int retval;
1861
1862                 switch (priv->params.rx_cq_moderation_mode) {
1863                 case 0:
1864                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1865                         break;
1866                 default:
1867                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1868                         break;
1869                 }
1870
1871                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1872                     priv->params.rx_cq_moderation_usec,
1873                     priv->params.rx_cq_moderation_pkts,
1874                     cq_mode);
1875
1876                 return (retval);
1877         }
1878
1879         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1880             priv->params.rx_cq_moderation_usec,
1881             priv->params.rx_cq_moderation_pkts));
1882 }
1883
1884 static int
1885 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1886 {
1887         int err;
1888         int i;
1889
1890         if (c == NULL)
1891                 return (EINVAL);
1892
1893         err = mlx5e_refresh_rq_params(priv, &c->rq);
1894         if (err)
1895                 goto done;
1896
1897         for (i = 0; i != c->num_tc; i++) {
1898                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1899                 if (err)
1900                         goto done;
1901         }
1902 done:
1903         return (err);
1904 }
1905
1906 int
1907 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1908 {
1909         int i;
1910
1911         if (priv->channel == NULL)
1912                 return (EINVAL);
1913
1914         for (i = 0; i < priv->params.num_channels; i++) {
1915                 int err;
1916
1917                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1918                 if (err)
1919                         return (err);
1920         }
1921         return (0);
1922 }
1923
1924 static int
1925 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1926 {
1927         struct mlx5_core_dev *mdev = priv->mdev;
1928         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1929         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1930
1931         memset(in, 0, sizeof(in));
1932
1933         MLX5_SET(tisc, tisc, prio, tc);
1934         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1935
1936         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1937 }
1938
1939 static void
1940 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1941 {
1942         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1943 }
1944
1945 static int
1946 mlx5e_open_tises(struct mlx5e_priv *priv)
1947 {
1948         int num_tc = priv->num_tc;
1949         int err;
1950         int tc;
1951
1952         for (tc = 0; tc < num_tc; tc++) {
1953                 err = mlx5e_open_tis(priv, tc);
1954                 if (err)
1955                         goto err_close_tises;
1956         }
1957
1958         return (0);
1959
1960 err_close_tises:
1961         for (tc--; tc >= 0; tc--)
1962                 mlx5e_close_tis(priv, tc);
1963
1964         return (err);
1965 }
1966
1967 static void
1968 mlx5e_close_tises(struct mlx5e_priv *priv)
1969 {
1970         int num_tc = priv->num_tc;
1971         int tc;
1972
1973         for (tc = 0; tc < num_tc; tc++)
1974                 mlx5e_close_tis(priv, tc);
1975 }
1976
1977 static int
1978 mlx5e_open_rqt(struct mlx5e_priv *priv)
1979 {
1980         struct mlx5_core_dev *mdev = priv->mdev;
1981         u32 *in;
1982         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1983         void *rqtc;
1984         int inlen;
1985         int err;
1986         int sz;
1987         int i;
1988
1989         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1990
1991         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1992         in = mlx5_vzalloc(inlen);
1993         if (in == NULL)
1994                 return (-ENOMEM);
1995         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1996
1997         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1998         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1999
2000         for (i = 0; i < sz; i++) {
2001                 int ix;
2002 #ifdef RSS
2003                 ix = rss_get_indirection_to_bucket(i);
2004 #else
2005                 ix = i;
2006 #endif
2007                 /* ensure we don't overflow */
2008                 ix %= priv->params.num_channels;
2009                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2010         }
2011
2012         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2013
2014         memset(out, 0, sizeof(out));
2015         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
2016         if (!err)
2017                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2018
2019         kvfree(in);
2020
2021         return (err);
2022 }
2023
2024 static void
2025 mlx5e_close_rqt(struct mlx5e_priv *priv)
2026 {
2027         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
2028         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
2029
2030         memset(in, 0, sizeof(in));
2031
2032         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2033         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2034
2035         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
2036             sizeof(out));
2037 }
2038
2039 static void
2040 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2041 {
2042         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2043         __be32 *hkey;
2044
2045         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2046
2047 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2048
2049 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2050                           MLX5_HASH_FIELD_SEL_DST_IP)
2051
2052 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2053                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2054                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2055                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2056
2057 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2058                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2059                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2060
2061         if (priv->params.hw_lro_en) {
2062                 MLX5_SET(tirc, tirc, lro_enable_mask,
2063                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2064                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2065                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2066                     (priv->params.lro_wqe_sz -
2067                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2068                 /* TODO: add the option to choose timer value dynamically */
2069                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2070                     MLX5_CAP_ETH(priv->mdev,
2071                     lro_timer_supported_periods[2]));
2072         }
2073
2074         /* setup parameters for hashing TIR type, if any */
2075         switch (tt) {
2076         case MLX5E_TT_ANY:
2077                 MLX5_SET(tirc, tirc, disp_type,
2078                     MLX5_TIRC_DISP_TYPE_DIRECT);
2079                 MLX5_SET(tirc, tirc, inline_rqn,
2080                     priv->channel[0]->rq.rqn);
2081                 break;
2082         default:
2083                 MLX5_SET(tirc, tirc, disp_type,
2084                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2085                 MLX5_SET(tirc, tirc, indirect_table,
2086                     priv->rqtn);
2087                 MLX5_SET(tirc, tirc, rx_hash_fn,
2088                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2089                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2090 #ifdef RSS
2091                 /*
2092                  * The FreeBSD RSS implementation does currently not
2093                  * support symmetric Toeplitz hashes:
2094                  */
2095                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2096                 rss_getkey((uint8_t *)hkey);
2097 #else
2098                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2099                 hkey[0] = cpu_to_be32(0xD181C62C);
2100                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2101                 hkey[2] = cpu_to_be32(0x1983A2FC);
2102                 hkey[3] = cpu_to_be32(0x943E1ADB);
2103                 hkey[4] = cpu_to_be32(0xD9389E6B);
2104                 hkey[5] = cpu_to_be32(0xD1039C2C);
2105                 hkey[6] = cpu_to_be32(0xA74499AD);
2106                 hkey[7] = cpu_to_be32(0x593D56D9);
2107                 hkey[8] = cpu_to_be32(0xF3253C06);
2108                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2109 #endif
2110                 break;
2111         }
2112
2113         switch (tt) {
2114         case MLX5E_TT_IPV4_TCP:
2115                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2116                     MLX5_L3_PROT_TYPE_IPV4);
2117                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2118                     MLX5_L4_PROT_TYPE_TCP);
2119 #ifdef RSS
2120                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2121                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2122                             MLX5_HASH_IP);
2123                 } else
2124 #endif
2125                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2126                     MLX5_HASH_ALL);
2127                 break;
2128
2129         case MLX5E_TT_IPV6_TCP:
2130                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2131                     MLX5_L3_PROT_TYPE_IPV6);
2132                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2133                     MLX5_L4_PROT_TYPE_TCP);
2134 #ifdef RSS
2135                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2136                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2137                             MLX5_HASH_IP);
2138                 } else
2139 #endif
2140                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2141                     MLX5_HASH_ALL);
2142                 break;
2143
2144         case MLX5E_TT_IPV4_UDP:
2145                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2146                     MLX5_L3_PROT_TYPE_IPV4);
2147                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2148                     MLX5_L4_PROT_TYPE_UDP);
2149 #ifdef RSS
2150                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2151                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2152                             MLX5_HASH_IP);
2153                 } else
2154 #endif
2155                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2156                     MLX5_HASH_ALL);
2157                 break;
2158
2159         case MLX5E_TT_IPV6_UDP:
2160                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2161                     MLX5_L3_PROT_TYPE_IPV6);
2162                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2163                     MLX5_L4_PROT_TYPE_UDP);
2164 #ifdef RSS
2165                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2166                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2167                             MLX5_HASH_IP);
2168                 } else
2169 #endif
2170                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2171                     MLX5_HASH_ALL);
2172                 break;
2173
2174         case MLX5E_TT_IPV4_IPSEC_AH:
2175                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2176                     MLX5_L3_PROT_TYPE_IPV4);
2177                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2178                     MLX5_HASH_IP_IPSEC_SPI);
2179                 break;
2180
2181         case MLX5E_TT_IPV6_IPSEC_AH:
2182                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2183                     MLX5_L3_PROT_TYPE_IPV6);
2184                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2185                     MLX5_HASH_IP_IPSEC_SPI);
2186                 break;
2187
2188         case MLX5E_TT_IPV4_IPSEC_ESP:
2189                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2190                     MLX5_L3_PROT_TYPE_IPV4);
2191                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2192                     MLX5_HASH_IP_IPSEC_SPI);
2193                 break;
2194
2195         case MLX5E_TT_IPV6_IPSEC_ESP:
2196                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2197                     MLX5_L3_PROT_TYPE_IPV6);
2198                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2199                     MLX5_HASH_IP_IPSEC_SPI);
2200                 break;
2201
2202         case MLX5E_TT_IPV4:
2203                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2204                     MLX5_L3_PROT_TYPE_IPV4);
2205                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2206                     MLX5_HASH_IP);
2207                 break;
2208
2209         case MLX5E_TT_IPV6:
2210                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2211                     MLX5_L3_PROT_TYPE_IPV6);
2212                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2213                     MLX5_HASH_IP);
2214                 break;
2215
2216         default:
2217                 break;
2218         }
2219 }
2220
2221 static int
2222 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2223 {
2224         struct mlx5_core_dev *mdev = priv->mdev;
2225         u32 *in;
2226         void *tirc;
2227         int inlen;
2228         int err;
2229
2230         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2231         in = mlx5_vzalloc(inlen);
2232         if (in == NULL)
2233                 return (-ENOMEM);
2234         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2235
2236         mlx5e_build_tir_ctx(priv, tirc, tt);
2237
2238         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2239
2240         kvfree(in);
2241
2242         return (err);
2243 }
2244
2245 static void
2246 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2247 {
2248         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2249 }
2250
2251 static int
2252 mlx5e_open_tirs(struct mlx5e_priv *priv)
2253 {
2254         int err;
2255         int i;
2256
2257         for (i = 0; i < MLX5E_NUM_TT; i++) {
2258                 err = mlx5e_open_tir(priv, i);
2259                 if (err)
2260                         goto err_close_tirs;
2261         }
2262
2263         return (0);
2264
2265 err_close_tirs:
2266         for (i--; i >= 0; i--)
2267                 mlx5e_close_tir(priv, i);
2268
2269         return (err);
2270 }
2271
2272 static void
2273 mlx5e_close_tirs(struct mlx5e_priv *priv)
2274 {
2275         int i;
2276
2277         for (i = 0; i < MLX5E_NUM_TT; i++)
2278                 mlx5e_close_tir(priv, i);
2279 }
2280
2281 /*
2282  * SW MTU does not include headers,
2283  * HW MTU includes all headers and checksums.
2284  */
2285 static int
2286 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2287 {
2288         struct mlx5e_priv *priv = ifp->if_softc;
2289         struct mlx5_core_dev *mdev = priv->mdev;
2290         int hw_mtu;
2291         int err;
2292
2293         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2294         if (err) {
2295                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2296                     __func__, sw_mtu, err);
2297                 return (err);
2298         }
2299         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2300         if (err) {
2301                 if_printf(ifp, "Query port MTU, after setting new "
2302                     "MTU value, failed\n");
2303         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2304                 err = -E2BIG,
2305                 if_printf(ifp, "Port MTU %d is smaller than "
2306                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2307         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2308                 err = -EINVAL;
2309                 if_printf(ifp, "Port MTU %d is bigger than "
2310                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2311         }
2312         ifp->if_mtu = sw_mtu;
2313         return (err);
2314 }
2315
2316 int
2317 mlx5e_open_locked(struct ifnet *ifp)
2318 {
2319         struct mlx5e_priv *priv = ifp->if_softc;
2320         int err;
2321         u16 set_id;
2322
2323         /* check if already opened */
2324         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2325                 return (0);
2326
2327 #ifdef RSS
2328         if (rss_getnumbuckets() > priv->params.num_channels) {
2329                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2330                     "channels(%u) available\n", rss_getnumbuckets(),
2331                     priv->params.num_channels);
2332         }
2333 #endif
2334         err = mlx5e_open_tises(priv);
2335         if (err) {
2336                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2337                     __func__, err);
2338                 return (err);
2339         }
2340         err = mlx5_vport_alloc_q_counter(priv->mdev,
2341             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2342         if (err) {
2343                 if_printf(priv->ifp,
2344                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2345                     __func__, err);
2346                 goto err_close_tises;
2347         }
2348         /* store counter set ID */
2349         priv->counter_set_id = set_id;
2350
2351         err = mlx5e_open_channels(priv);
2352         if (err) {
2353                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2354                     __func__, err);
2355                 goto err_dalloc_q_counter;
2356         }
2357         err = mlx5e_open_rqt(priv);
2358         if (err) {
2359                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2360                     __func__, err);
2361                 goto err_close_channels;
2362         }
2363         err = mlx5e_open_tirs(priv);
2364         if (err) {
2365                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2366                     __func__, err);
2367                 goto err_close_rqls;
2368         }
2369         err = mlx5e_open_flow_table(priv);
2370         if (err) {
2371                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2372                     __func__, err);
2373                 goto err_close_tirs;
2374         }
2375         err = mlx5e_add_all_vlan_rules(priv);
2376         if (err) {
2377                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2378                     __func__, err);
2379                 goto err_close_flow_table;
2380         }
2381         set_bit(MLX5E_STATE_OPENED, &priv->state);
2382
2383         mlx5e_update_carrier(priv);
2384         mlx5e_set_rx_mode_core(priv);
2385
2386         return (0);
2387
2388 err_close_flow_table:
2389         mlx5e_close_flow_table(priv);
2390
2391 err_close_tirs:
2392         mlx5e_close_tirs(priv);
2393
2394 err_close_rqls:
2395         mlx5e_close_rqt(priv);
2396
2397 err_close_channels:
2398         mlx5e_close_channels(priv);
2399
2400 err_dalloc_q_counter:
2401         mlx5_vport_dealloc_q_counter(priv->mdev,
2402             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2403
2404 err_close_tises:
2405         mlx5e_close_tises(priv);
2406
2407         return (err);
2408 }
2409
2410 static void
2411 mlx5e_open(void *arg)
2412 {
2413         struct mlx5e_priv *priv = arg;
2414
2415         PRIV_LOCK(priv);
2416         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2417                 if_printf(priv->ifp,
2418                     "%s: Setting port status to up failed\n",
2419                     __func__);
2420
2421         mlx5e_open_locked(priv->ifp);
2422         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2423         PRIV_UNLOCK(priv);
2424 }
2425
2426 int
2427 mlx5e_close_locked(struct ifnet *ifp)
2428 {
2429         struct mlx5e_priv *priv = ifp->if_softc;
2430
2431         /* check if already closed */
2432         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2433                 return (0);
2434
2435         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2436
2437         mlx5e_set_rx_mode_core(priv);
2438         mlx5e_del_all_vlan_rules(priv);
2439         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2440         mlx5e_close_flow_table(priv);
2441         mlx5e_close_tirs(priv);
2442         mlx5e_close_rqt(priv);
2443         mlx5e_close_channels(priv);
2444         mlx5_vport_dealloc_q_counter(priv->mdev,
2445             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2446         mlx5e_close_tises(priv);
2447
2448         return (0);
2449 }
2450
2451 #if (__FreeBSD_version >= 1100000)
2452 static uint64_t
2453 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2454 {
2455         struct mlx5e_priv *priv = ifp->if_softc;
2456         u64 retval;
2457
2458         /* PRIV_LOCK(priv); XXX not allowed */
2459         switch (cnt) {
2460         case IFCOUNTER_IPACKETS:
2461                 retval = priv->stats.vport.rx_packets;
2462                 break;
2463         case IFCOUNTER_IERRORS:
2464                 retval = priv->stats.vport.rx_error_packets +
2465                     priv->stats.pport.alignment_err +
2466                     priv->stats.pport.check_seq_err +
2467                     priv->stats.pport.crc_align_errors +
2468                     priv->stats.pport.drop_events +
2469                     priv->stats.pport.in_range_len_errors +
2470                     priv->stats.pport.jabbers +
2471                     priv->stats.pport.out_of_range_len +
2472                     priv->stats.pport.oversize_pkts +
2473                     priv->stats.pport.symbol_err +
2474                     priv->stats.pport.too_long_errors +
2475                     priv->stats.pport.undersize_pkts +
2476                     priv->stats.pport.unsupported_op_rx;
2477                 break;
2478         case IFCOUNTER_IQDROPS:
2479                 retval = priv->stats.vport.rx_out_of_buffer;
2480                 break;
2481         case IFCOUNTER_OPACKETS:
2482                 retval = priv->stats.vport.tx_packets;
2483                 break;
2484         case IFCOUNTER_OERRORS:
2485                 retval = priv->stats.vport.tx_error_packets;
2486                 break;
2487         case IFCOUNTER_IBYTES:
2488                 retval = priv->stats.vport.rx_bytes;
2489                 break;
2490         case IFCOUNTER_OBYTES:
2491                 retval = priv->stats.vport.tx_bytes;
2492                 break;
2493         case IFCOUNTER_IMCASTS:
2494                 retval = priv->stats.vport.rx_multicast_packets;
2495                 break;
2496         case IFCOUNTER_OMCASTS:
2497                 retval = priv->stats.vport.tx_multicast_packets;
2498                 break;
2499         case IFCOUNTER_OQDROPS:
2500                 retval = priv->stats.vport.tx_queue_dropped;
2501                 break;
2502         case IFCOUNTER_COLLISIONS:
2503                 retval = priv->stats.pport.collisions;
2504                 break;
2505         default:
2506                 retval = if_get_counter_default(ifp, cnt);
2507                 break;
2508         }
2509         /* PRIV_UNLOCK(priv); XXX not allowed */
2510         return (retval);
2511 }
2512 #endif
2513
2514 static void
2515 mlx5e_set_rx_mode(struct ifnet *ifp)
2516 {
2517         struct mlx5e_priv *priv = ifp->if_softc;
2518
2519         schedule_work(&priv->set_rx_mode_work);
2520 }
2521
2522 static int
2523 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2524 {
2525         struct mlx5e_priv *priv;
2526         struct ifreq *ifr;
2527         struct ifi2creq i2c;
2528         int error = 0;
2529         int mask = 0;
2530         int size_read = 0;
2531         int module_num;
2532         int max_mtu;
2533         uint8_t read_addr;
2534
2535         priv = ifp->if_softc;
2536
2537         /* check if detaching */
2538         if (priv == NULL || priv->gone != 0)
2539                 return (ENXIO);
2540
2541         switch (command) {
2542         case SIOCSIFMTU:
2543                 ifr = (struct ifreq *)data;
2544
2545                 PRIV_LOCK(priv);
2546                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2547
2548                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2549                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2550                         int was_opened;
2551
2552                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2553                         if (was_opened)
2554                                 mlx5e_close_locked(ifp);
2555
2556                         /* set new MTU */
2557                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2558
2559                         if (was_opened)
2560                                 mlx5e_open_locked(ifp);
2561                 } else {
2562                         error = EINVAL;
2563                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2564                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2565                 }
2566                 PRIV_UNLOCK(priv);
2567                 break;
2568         case SIOCSIFFLAGS:
2569                 if ((ifp->if_flags & IFF_UP) &&
2570                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2571                         mlx5e_set_rx_mode(ifp);
2572                         break;
2573                 }
2574                 PRIV_LOCK(priv);
2575                 if (ifp->if_flags & IFF_UP) {
2576                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2577                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2578                                         mlx5e_open_locked(ifp);
2579                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2580                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2581                         }
2582                 } else {
2583                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2584                                 mlx5_set_port_status(priv->mdev,
2585                                     MLX5_PORT_DOWN);
2586                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2587                                         mlx5e_close_locked(ifp);
2588                                 mlx5e_update_carrier(priv);
2589                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2590                         }
2591                 }
2592                 PRIV_UNLOCK(priv);
2593                 break;
2594         case SIOCADDMULTI:
2595         case SIOCDELMULTI:
2596                 mlx5e_set_rx_mode(ifp);
2597                 break;
2598         case SIOCSIFMEDIA:
2599         case SIOCGIFMEDIA:
2600         case SIOCGIFXMEDIA:
2601                 ifr = (struct ifreq *)data;
2602                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2603                 break;
2604         case SIOCSIFCAP:
2605                 ifr = (struct ifreq *)data;
2606                 PRIV_LOCK(priv);
2607                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2608
2609                 if (mask & IFCAP_TXCSUM) {
2610                         ifp->if_capenable ^= IFCAP_TXCSUM;
2611                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2612
2613                         if (IFCAP_TSO4 & ifp->if_capenable &&
2614                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2615                                 ifp->if_capenable &= ~IFCAP_TSO4;
2616                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2617                                 if_printf(ifp,
2618                                     "tso4 disabled due to -txcsum.\n");
2619                         }
2620                 }
2621                 if (mask & IFCAP_TXCSUM_IPV6) {
2622                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2623                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2624
2625                         if (IFCAP_TSO6 & ifp->if_capenable &&
2626                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2627                                 ifp->if_capenable &= ~IFCAP_TSO6;
2628                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2629                                 if_printf(ifp,
2630                                     "tso6 disabled due to -txcsum6.\n");
2631                         }
2632                 }
2633                 if (mask & IFCAP_RXCSUM)
2634                         ifp->if_capenable ^= IFCAP_RXCSUM;
2635                 if (mask & IFCAP_RXCSUM_IPV6)
2636                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2637                 if (mask & IFCAP_TSO4) {
2638                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2639                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2640                                 if_printf(ifp, "enable txcsum first.\n");
2641                                 error = EAGAIN;
2642                                 goto out;
2643                         }
2644                         ifp->if_capenable ^= IFCAP_TSO4;
2645                         ifp->if_hwassist ^= CSUM_IP_TSO;
2646                 }
2647                 if (mask & IFCAP_TSO6) {
2648                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2649                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2650                                 if_printf(ifp, "enable txcsum6 first.\n");
2651                                 error = EAGAIN;
2652                                 goto out;
2653                         }
2654                         ifp->if_capenable ^= IFCAP_TSO6;
2655                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2656                 }
2657                 if (mask & IFCAP_VLAN_HWFILTER) {
2658                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2659                                 mlx5e_disable_vlan_filter(priv);
2660                         else
2661                                 mlx5e_enable_vlan_filter(priv);
2662
2663                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2664                 }
2665                 if (mask & IFCAP_VLAN_HWTAGGING)
2666                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2667                 if (mask & IFCAP_WOL_MAGIC)
2668                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2669
2670                 VLAN_CAPABILITIES(ifp);
2671                 /* turn off LRO means also turn of HW LRO - if it's on */
2672                 if (mask & IFCAP_LRO) {
2673                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2674                         bool need_restart = false;
2675
2676                         ifp->if_capenable ^= IFCAP_LRO;
2677                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2678                                 if (priv->params.hw_lro_en) {
2679                                         priv->params.hw_lro_en = false;
2680                                         need_restart = true;
2681                                         /* Not sure this is the correct way */
2682                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2683                                 }
2684                         }
2685                         if (was_opened && need_restart) {
2686                                 mlx5e_close_locked(ifp);
2687                                 mlx5e_open_locked(ifp);
2688                         }
2689                 }
2690 out:
2691                 PRIV_UNLOCK(priv);
2692                 break;
2693
2694         case SIOCGI2C:
2695                 ifr = (struct ifreq *)data;
2696
2697                 /*
2698                  * Copy from the user-space address ifr_data to the
2699                  * kernel-space address i2c
2700                  */
2701                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2702                 if (error)
2703                         break;
2704
2705                 if (i2c.len > sizeof(i2c.data)) {
2706                         error = EINVAL;
2707                         break;
2708                 }
2709
2710                 PRIV_LOCK(priv);
2711                 /* Get module_num which is required for the query_eeprom */
2712                 error = mlx5_query_module_num(priv->mdev, &module_num);
2713                 if (error) {
2714                         if_printf(ifp, "Query module num failed, eeprom "
2715                             "reading is not supported\n");
2716                         error = EINVAL;
2717                         goto err_i2c;
2718                 }
2719                 /* Check if module is present before doing an access */
2720                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2721                     MLX5_MODULE_STATUS_PLUGGED) {
2722                         error = EINVAL;
2723                         goto err_i2c;
2724                 }
2725                 /*
2726                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2727                  * The internal conversion is as follows:
2728                  */
2729                 if (i2c.dev_addr == 0xA0)
2730                         read_addr = MLX5E_I2C_ADDR_LOW;
2731                 else if (i2c.dev_addr == 0xA2)
2732                         read_addr = MLX5E_I2C_ADDR_HIGH;
2733                 else {
2734                         if_printf(ifp, "Query eeprom failed, "
2735                             "Invalid Address: %X\n", i2c.dev_addr);
2736                         error = EINVAL;
2737                         goto err_i2c;
2738                 }
2739                 error = mlx5_query_eeprom(priv->mdev,
2740                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2741                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2742                     (uint32_t *)i2c.data, &size_read);
2743                 if (error) {
2744                         if_printf(ifp, "Query eeprom failed, eeprom "
2745                             "reading is not supported\n");
2746                         error = EINVAL;
2747                         goto err_i2c;
2748                 }
2749
2750                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2751                         error = mlx5_query_eeprom(priv->mdev,
2752                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2753                             (uint32_t)(i2c.offset + size_read),
2754                             (uint32_t)(i2c.len - size_read), module_num,
2755                             (uint32_t *)(i2c.data + size_read), &size_read);
2756                 }
2757                 if (error) {
2758                         if_printf(ifp, "Query eeprom failed, eeprom "
2759                             "reading is not supported\n");
2760                         error = EINVAL;
2761                         goto err_i2c;
2762                 }
2763
2764                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2765 err_i2c:
2766                 PRIV_UNLOCK(priv);
2767                 break;
2768
2769         default:
2770                 error = ether_ioctl(ifp, command, data);
2771                 break;
2772         }
2773         return (error);
2774 }
2775
2776 static int
2777 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2778 {
2779         /*
2780          * TODO: uncoment once FW really sets all these bits if
2781          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2782          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2783          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2784          * -ENOTSUPP;
2785          */
2786
2787         /* TODO: add more must-to-have features */
2788
2789         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2790                 return (-ENODEV);
2791
2792         return (0);
2793 }
2794
2795 static void
2796 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2797     struct mlx5e_priv *priv,
2798     int num_comp_vectors)
2799 {
2800         /*
2801          * TODO: Consider link speed for setting "log_sq_size",
2802          * "log_rq_size" and "cq_moderation_xxx":
2803          */
2804         priv->params.log_sq_size =
2805             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2806         priv->params.log_rq_size =
2807             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2808         priv->params.rx_cq_moderation_usec =
2809             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2810             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2811             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2812         priv->params.rx_cq_moderation_mode =
2813             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2814         priv->params.rx_cq_moderation_pkts =
2815             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2816         priv->params.tx_cq_moderation_usec =
2817             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2818         priv->params.tx_cq_moderation_pkts =
2819             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2820         priv->params.min_rx_wqes =
2821             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2822         priv->params.rx_hash_log_tbl_sz =
2823             (order_base_2(num_comp_vectors) >
2824             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2825             order_base_2(num_comp_vectors) :
2826             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2827         priv->params.num_tc = 1;
2828         priv->params.default_vlan_prio = 0;
2829         priv->counter_set_id = -1;
2830
2831         /*
2832          * hw lro is currently defaulted to off. when it won't anymore we
2833          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2834          */
2835         priv->params.hw_lro_en = false;
2836         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2837
2838         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2839
2840         priv->mdev = mdev;
2841         priv->params.num_channels = num_comp_vectors;
2842         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2843         priv->queue_mapping_channel_mask =
2844             roundup_pow_of_two(num_comp_vectors) - 1;
2845         priv->num_tc = priv->params.num_tc;
2846         priv->default_vlan_prio = priv->params.default_vlan_prio;
2847
2848         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2849         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2850         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2851 }
2852
2853 static int
2854 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2855     struct mlx5_core_mr *mr)
2856 {
2857         struct ifnet *ifp = priv->ifp;
2858         struct mlx5_core_dev *mdev = priv->mdev;
2859         struct mlx5_create_mkey_mbox_in *in;
2860         int err;
2861
2862         in = mlx5_vzalloc(sizeof(*in));
2863         if (in == NULL) {
2864                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2865                 return (-ENOMEM);
2866         }
2867         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2868             MLX5_PERM_LOCAL_READ |
2869             MLX5_ACCESS_MODE_PA;
2870         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2871         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2872
2873         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2874             NULL);
2875         if (err)
2876                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2877                     __func__, err);
2878
2879         kvfree(in);
2880
2881         return (err);
2882 }
2883
2884 static const char *mlx5e_vport_stats_desc[] = {
2885         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2886 };
2887
2888 static const char *mlx5e_pport_stats_desc[] = {
2889         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2890 };
2891
2892 static void
2893 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2894 {
2895         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2896         sx_init(&priv->state_lock, "mlx5state");
2897         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2898         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2899 }
2900
2901 static void
2902 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2903 {
2904         mtx_destroy(&priv->async_events_mtx);
2905         sx_destroy(&priv->state_lock);
2906 }
2907
2908 static int
2909 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2910 {
2911         /*
2912          * %d.%d%.d the string format.
2913          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2914          * We need at most 5 chars to store that.
2915          * It also has: two "." and NULL at the end, which means we need 18
2916          * (5*3 + 3) chars at most.
2917          */
2918         char fw[18];
2919         struct mlx5e_priv *priv = arg1;
2920         int error;
2921
2922         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2923             fw_rev_sub(priv->mdev));
2924         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2925         return (error);
2926 }
2927
2928 static void
2929 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2930 {
2931         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2932             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2933             sysctl_firmware, "A", "HCA firmware version");
2934
2935         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2936             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2937             "Board ID");
2938 }
2939
2940 static void
2941 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2942 {
2943 #if (__FreeBSD_version < 1100000)
2944         char path[64];
2945
2946 #endif
2947         /* Only receiving pauseframes is enabled by default */
2948         priv->params.tx_pauseframe_control = 0;
2949         priv->params.rx_pauseframe_control = 1;
2950
2951 #if (__FreeBSD_version < 1100000)
2952         /* compute path for sysctl */
2953         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2954             device_get_unit(priv->mdev->pdev->dev.bsddev));
2955
2956         /* try to fetch tunable, if any */
2957         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2958
2959         /* compute path for sysctl */
2960         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2961             device_get_unit(priv->mdev->pdev->dev.bsddev));
2962
2963         /* try to fetch tunable, if any */
2964         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2965 #endif
2966
2967         /* register pausframe SYSCTLs */
2968         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2969             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2970             &priv->params.tx_pauseframe_control, 0,
2971             "Set to enable TX pause frames. Clear to disable.");
2972
2973         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2974             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2975             &priv->params.rx_pauseframe_control, 0,
2976             "Set to enable RX pause frames. Clear to disable.");
2977
2978         /* range check */
2979         priv->params.tx_pauseframe_control =
2980             priv->params.tx_pauseframe_control ? 1 : 0;
2981         priv->params.rx_pauseframe_control =
2982             priv->params.rx_pauseframe_control ? 1 : 0;
2983
2984         /* update firmware */
2985         mlx5_set_port_pause(priv->mdev, 1,
2986             priv->params.rx_pauseframe_control,
2987             priv->params.tx_pauseframe_control);
2988 }
2989
2990 static void *
2991 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2992 {
2993         static volatile int mlx5_en_unit;
2994         struct ifnet *ifp;
2995         struct mlx5e_priv *priv;
2996         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2997         struct sysctl_oid_list *child;
2998         int ncv = mdev->priv.eq_table.num_comp_vectors;
2999         char unit[16];
3000         int err;
3001         int i;
3002         u32 eth_proto_cap;
3003
3004         if (mlx5e_check_required_hca_cap(mdev)) {
3005                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3006                 return (NULL);
3007         }
3008         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3009         mlx5e_priv_mtx_init(priv);
3010
3011         ifp = priv->ifp = if_alloc(IFT_ETHER);
3012         if (ifp == NULL) {
3013                 mlx5_core_err(mdev, "if_alloc() failed\n");
3014                 goto err_free_priv;
3015         }
3016         ifp->if_softc = priv;
3017         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
3018         ifp->if_mtu = ETHERMTU;
3019         ifp->if_init = mlx5e_open;
3020         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3021         ifp->if_ioctl = mlx5e_ioctl;
3022         ifp->if_transmit = mlx5e_xmit;
3023         ifp->if_qflush = if_qflush;
3024 #if (__FreeBSD_version >= 1100000)
3025         ifp->if_get_counter = mlx5e_get_counter;
3026 #endif
3027         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3028         /*
3029          * Set driver features
3030          */
3031         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3032         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3033         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3034         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3035         ifp->if_capabilities |= IFCAP_LRO;
3036         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3037         ifp->if_capabilities |= IFCAP_HWSTATS;
3038
3039         /* set TSO limits so that we don't have to drop TX packets */
3040         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3041         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3042         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3043
3044         ifp->if_capenable = ifp->if_capabilities;
3045         ifp->if_hwassist = 0;
3046         if (ifp->if_capenable & IFCAP_TSO)
3047                 ifp->if_hwassist |= CSUM_TSO;
3048         if (ifp->if_capenable & IFCAP_TXCSUM)
3049                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3050         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3051                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3052
3053         /* ifnet sysctl tree */
3054         sysctl_ctx_init(&priv->sysctl_ctx);
3055         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3056             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3057         if (priv->sysctl_ifnet == NULL) {
3058                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3059                 goto err_free_sysctl;
3060         }
3061         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3062         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3063             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3064         if (priv->sysctl_ifnet == NULL) {
3065                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3066                 goto err_free_sysctl;
3067         }
3068
3069         /* HW sysctl tree */
3070         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3071         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3072             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3073         if (priv->sysctl_hw == NULL) {
3074                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3075                 goto err_free_sysctl;
3076         }
3077         mlx5e_build_ifp_priv(mdev, priv, ncv);
3078         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3079         if (err) {
3080                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3081                     __func__, err);
3082                 goto err_free_sysctl;
3083         }
3084         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3085         if (err) {
3086                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3087                     __func__, err);
3088                 goto err_unmap_free_uar;
3089         }
3090         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3091         if (err) {
3092                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3093                     __func__, err);
3094                 goto err_dealloc_pd;
3095         }
3096         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3097         if (err) {
3098                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3099                     __func__, err);
3100                 goto err_dealloc_transport_domain;
3101         }
3102         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3103
3104         /* check if we should generate a random MAC address */
3105         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3106             is_zero_ether_addr(dev_addr)) {
3107                 random_ether_addr(dev_addr);
3108                 if_printf(ifp, "Assigned random MAC address\n");
3109         }
3110
3111         /* set default MTU */
3112         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3113
3114         /* Set desc */
3115         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3116
3117         /* Set default media status */
3118         priv->media_status_last = IFM_AVALID;
3119         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3120             IFM_ETH_RXPAUSE | IFM_FDX;
3121
3122         /* setup default pauseframes configuration */
3123         mlx5e_setup_pauseframes(priv);
3124
3125         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3126         if (err) {
3127                 eth_proto_cap = 0;
3128                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3129                     __func__, err);
3130         }
3131
3132         /* Setup supported medias */
3133         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3134             mlx5e_media_change, mlx5e_media_status);
3135
3136         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3137                 if (mlx5e_mode_table[i].baudrate == 0)
3138                         continue;
3139                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3140                         ifmedia_add(&priv->media,
3141                             mlx5e_mode_table[i].subtype |
3142                             IFM_ETHER, 0, NULL);
3143                         ifmedia_add(&priv->media,
3144                             mlx5e_mode_table[i].subtype |
3145                             IFM_ETHER | IFM_FDX |
3146                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3147                 }
3148         }
3149
3150         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3151         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3152             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3153
3154         /* Set autoselect by default */
3155         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3156             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3157         ether_ifattach(ifp, dev_addr);
3158
3159         /* Register for VLAN events */
3160         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3161             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3162         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3163             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3164
3165         /* Link is down by default */
3166         if_link_state_change(ifp, LINK_STATE_DOWN);
3167
3168         mlx5e_enable_async_events(priv);
3169
3170         mlx5e_add_hw_stats(priv);
3171
3172         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3173             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3174             priv->stats.vport.arg);
3175
3176         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3177             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3178             priv->stats.pport.arg);
3179
3180         mlx5e_create_ethtool(priv);
3181
3182         mtx_lock(&priv->async_events_mtx);
3183         mlx5e_update_stats(priv);
3184         mtx_unlock(&priv->async_events_mtx);
3185
3186         return (priv);
3187
3188 err_dealloc_transport_domain:
3189         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3190
3191 err_dealloc_pd:
3192         mlx5_core_dealloc_pd(mdev, priv->pdn);
3193
3194 err_unmap_free_uar:
3195         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3196
3197 err_free_sysctl:
3198         sysctl_ctx_free(&priv->sysctl_ctx);
3199
3200         if_free(ifp);
3201
3202 err_free_priv:
3203         mlx5e_priv_mtx_destroy(priv);
3204         free(priv, M_MLX5EN);
3205         return (NULL);
3206 }
3207
3208 static void
3209 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3210 {
3211         struct mlx5e_priv *priv = vpriv;
3212         struct ifnet *ifp = priv->ifp;
3213
3214         /* don't allow more IOCTLs */
3215         priv->gone = 1;
3216
3217         /*
3218          * Clear the device description to avoid use after free,
3219          * because the bsddev is not destroyed when this module is
3220          * unloaded:
3221          */
3222         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3223
3224         /* XXX wait a bit to allow IOCTL handlers to complete */
3225         pause("W", hz);
3226
3227         /* stop watchdog timer */
3228         callout_drain(&priv->watchdog);
3229
3230         if (priv->vlan_attach != NULL)
3231                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3232         if (priv->vlan_detach != NULL)
3233                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3234
3235         /* make sure device gets closed */
3236         PRIV_LOCK(priv);
3237         mlx5e_close_locked(ifp);
3238         PRIV_UNLOCK(priv);
3239
3240         /* unregister device */
3241         ifmedia_removeall(&priv->media);
3242         ether_ifdetach(ifp);
3243         if_free(ifp);
3244
3245         /* destroy all remaining sysctl nodes */
3246         if (priv->sysctl_debug)
3247                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3248         sysctl_ctx_free(&priv->stats.vport.ctx);
3249         sysctl_ctx_free(&priv->stats.pport.ctx);
3250         sysctl_ctx_free(&priv->sysctl_ctx);
3251
3252         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3253         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3254         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3255         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3256         mlx5e_disable_async_events(priv);
3257         flush_scheduled_work();
3258         mlx5e_priv_mtx_destroy(priv);
3259         free(priv, M_MLX5EN);
3260 }
3261
3262 static void *
3263 mlx5e_get_ifp(void *vpriv)
3264 {
3265         struct mlx5e_priv *priv = vpriv;
3266
3267         return (priv->ifp);
3268 }
3269
3270 static struct mlx5_interface mlx5e_interface = {
3271         .add = mlx5e_create_ifp,
3272         .remove = mlx5e_destroy_ifp,
3273         .event = mlx5e_async_event,
3274         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3275         .get_dev = mlx5e_get_ifp,
3276 };
3277
3278 void
3279 mlx5e_init(void)
3280 {
3281         mlx5_register_interface(&mlx5e_interface);
3282 }
3283
3284 void
3285 mlx5e_cleanup(void)
3286 {
3287         mlx5_unregister_interface(&mlx5e_interface);
3288 }
3289
3290 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3291 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3292
3293 #if (__FreeBSD_version >= 1100000)
3294 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3295 #endif
3296 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3297 MODULE_VERSION(mlx5en, 1);