sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 /*
 310  * This function reads the physical port counters from the firmware
 311  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 312  * macros. The output is converted from big-endian 64-bit values into
 313  * host endian ones and stored in the "priv->stats.pport" structure.
 314  */
 315 static void
 316 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 317 {
 318         struct mlx5_core_dev *mdev = priv->mdev;
 319         struct mlx5e_pport_stats *s = &priv->stats.pport;
 320         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 321         u32 *in;
 322         u32 *out;
 323         const u64 *ptr;
 324         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 325         unsigned x;
 326         unsigned y;
 327
 328         /* allocate firmware request structures */
 329         in = mlx5_vzalloc(sz);
 330         out = mlx5_vzalloc(sz);
 331         if (in == NULL || out == NULL)
 332                 goto free_out;
 333
 334         /*
 335          * Get pointer to the 64-bit counter set which is located at a
 336          * fixed offset in the output firmware request structure:
 337          */
 338         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 339
 340         MLX5_SET(ppcnt_reg, in, local_port, 1);
 341
 342         /* read IEEE802_3 counter group using predefined counter layout */
 343         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 344         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 345         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 346                 s->arg[y] = be64toh(ptr[x]);
 347
 348         /* read RFC2819 counter group using predefined counter layout */
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 352                 s->arg[y] = be64toh(ptr[x]);
 353         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 354             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 355                 s_debug->arg[y] = be64toh(ptr[x]);
 356
 357         /* read RFC2863 counter group using predefined counter layout */
 358         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 359         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 360         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 361                 s_debug->arg[y] = be64toh(ptr[x]);
 362
 363         /* read physical layer stats counter group using predefined counter layout */
 364         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 365         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 366         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 367                 s_debug->arg[y] = be64toh(ptr[x]);
 368 free_out:
 369         /* free firmware request structures */
 370         kvfree(in);
 371         kvfree(out);
 372 }
 373
 374 /*
 375  * This function is called regularly to collect all statistics
 376  * counters from the firmware. The values can be viewed through the
 377  * sysctl interface. Execution is serialized using the priv's global
 378  * configuration lock.
 379  */
 380 static void
 381 mlx5e_update_stats_work(struct work_struct *work)
 382 {
 383         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 384             update_stats_work);
 385         struct mlx5_core_dev *mdev = priv->mdev;
 386         struct mlx5e_vport_stats *s = &priv->stats.vport;
 387         struct mlx5e_rq_stats *rq_stats;
 388         struct mlx5e_sq_stats *sq_stats;
 389         struct buf_ring *sq_br;
 390 #if (__FreeBSD_version < 1100000)
 391         struct ifnet *ifp = priv->ifp;
 392 #endif
 393
 394         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 395         u32 *out;
 396         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 397         u64 tso_packets = 0;
 398         u64 tso_bytes = 0;
 399         u64 tx_queue_dropped = 0;
 400         u64 tx_defragged = 0;
 401         u64 tx_offload_none = 0;
 402         u64 lro_packets = 0;
 403         u64 lro_bytes = 0;
 404         u64 sw_lro_queued = 0;
 405         u64 sw_lro_flushed = 0;
 406         u64 rx_csum_none = 0;
 407         u64 rx_wqe_err = 0;
 408         u32 rx_out_of_buffer = 0;
 409         int i;
 410         int j;
 411
 412         PRIV_LOCK(priv);
 413         out = mlx5_vzalloc(outlen);
 414         if (out == NULL)
 415                 goto free_out;
 416         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 417                 goto free_out;
 418
 419         /* Collect firts the SW counters and then HW for consistency */
 420         for (i = 0; i < priv->params.num_channels; i++) {
 421                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 422
 423                 rq_stats = &priv->channel[i]->rq.stats;
 424
 425                 /* collect stats from LRO */
 426                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 427                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 428                 sw_lro_queued += rq_stats->sw_lro_queued;
 429                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 430                 lro_packets += rq_stats->lro_packets;
 431                 lro_bytes += rq_stats->lro_bytes;
 432                 rx_csum_none += rq_stats->csum_none;
 433                 rx_wqe_err += rq_stats->wqe_err;
 434
 435                 for (j = 0; j < priv->num_tc; j++) {
 436                         sq_stats = &priv->channel[i]->sq[j].stats;
 437                         sq_br = priv->channel[i]->sq[j].br;
 438
 439                         tso_packets += sq_stats->tso_packets;
 440                         tso_bytes += sq_stats->tso_bytes;
 441                         tx_queue_dropped += sq_stats->dropped;
 442                         if (sq_br != NULL)
 443                                 tx_queue_dropped += sq_br->br_drops;
 444                         tx_defragged += sq_stats->defragged;
 445                         tx_offload_none += sq_stats->csum_offload_none;
 446                 }
 447         }
 448
 449         /* update counters */
 450         s->tso_packets = tso_packets;
 451         s->tso_bytes = tso_bytes;
 452         s->tx_queue_dropped = tx_queue_dropped;
 453         s->tx_defragged = tx_defragged;
 454         s->lro_packets = lro_packets;
 455         s->lro_bytes = lro_bytes;
 456         s->sw_lro_queued = sw_lro_queued;
 457         s->sw_lro_flushed = sw_lro_flushed;
 458         s->rx_csum_none = rx_csum_none;
 459         s->rx_wqe_err = rx_wqe_err;
 460
 461         /* HW counters */
 462         memset(in, 0, sizeof(in));
 463
 464         MLX5_SET(query_vport_counter_in, in, opcode,
 465             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 466         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 467         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 468
 469         memset(out, 0, outlen);
 470
 471         /* get number of out-of-buffer drops first */
 472         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 473             &rx_out_of_buffer))
 474                 goto free_out;
 475
 476         /* accumulate difference into a 64-bit counter */
 477         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 478         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 479
 480         /* get port statistics */
 481         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 482                 goto free_out;
 483
 484 #define MLX5_GET_CTR(out, x) \
 485         MLX5_GET64(query_vport_counter_out, out, x)
 486
 487         s->rx_error_packets =
 488             MLX5_GET_CTR(out, received_errors.packets);
 489         s->rx_error_bytes =
 490             MLX5_GET_CTR(out, received_errors.octets);
 491         s->tx_error_packets =
 492             MLX5_GET_CTR(out, transmit_errors.packets);
 493         s->tx_error_bytes =
 494             MLX5_GET_CTR(out, transmit_errors.octets);
 495
 496         s->rx_unicast_packets =
 497             MLX5_GET_CTR(out, received_eth_unicast.packets);
 498         s->rx_unicast_bytes =
 499             MLX5_GET_CTR(out, received_eth_unicast.octets);
 500         s->tx_unicast_packets =
 501             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 502         s->tx_unicast_bytes =
 503             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 504
 505         s->rx_multicast_packets =
 506             MLX5_GET_CTR(out, received_eth_multicast.packets);
 507         s->rx_multicast_bytes =
 508             MLX5_GET_CTR(out, received_eth_multicast.octets);
 509         s->tx_multicast_packets =
 510             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 511         s->tx_multicast_bytes =
 512             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 513
 514         s->rx_broadcast_packets =
 515             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 516         s->rx_broadcast_bytes =
 517             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 518         s->tx_broadcast_packets =
 519             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 520         s->tx_broadcast_bytes =
 521             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 522
 523         s->rx_packets =
 524             s->rx_unicast_packets +
 525             s->rx_multicast_packets +
 526             s->rx_broadcast_packets -
 527             s->rx_out_of_buffer;
 528         s->rx_bytes =
 529             s->rx_unicast_bytes +
 530             s->rx_multicast_bytes +
 531             s->rx_broadcast_bytes;
 532         s->tx_packets =
 533             s->tx_unicast_packets +
 534             s->tx_multicast_packets +
 535             s->tx_broadcast_packets;
 536         s->tx_bytes =
 537             s->tx_unicast_bytes +
 538             s->tx_multicast_bytes +
 539             s->tx_broadcast_bytes;
 540
 541         /* Update calculated offload counters */
 542         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 543         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 544
 545         /* Get physical port counters */
 546         mlx5e_update_pport_counters(priv);
 547
 548 #if (__FreeBSD_version < 1100000)
 549         /* no get_counters interface in fbsd 10 */
 550         ifp->if_ipackets = s->rx_packets;
 551         ifp->if_ierrors = s->rx_error_packets +
 552             priv->stats.pport.alignment_err +
 553             priv->stats.pport.check_seq_err +
 554             priv->stats.pport.crc_align_errors +
 555             priv->stats.pport.in_range_len_errors +
 556             priv->stats.pport.jabbers +
 557             priv->stats.pport.out_of_range_len +
 558             priv->stats.pport.oversize_pkts +
 559             priv->stats.pport.symbol_err +
 560             priv->stats.pport.too_long_errors +
 561             priv->stats.pport.undersize_pkts +
 562             priv->stats.pport.unsupported_op_rx;
 563         ifp->if_iqdrops = s->rx_out_of_buffer +
 564             priv->stats.pport.drop_events;
 565         ifp->if_opackets = s->tx_packets;
 566         ifp->if_oerrors = s->tx_error_packets;
 567         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 568         ifp->if_ibytes = s->rx_bytes;
 569         ifp->if_obytes = s->tx_bytes;
 570         ifp->if_collisions =
 571             priv->stats.pport.collisions;
 572 #endif
 573
 574 free_out:
 575         kvfree(out);
 576
 577         /* Update diagnostics, if any */
 578         if (priv->params_ethtool.diag_pci_enable ||
 579             priv->params_ethtool.diag_general_enable) {
 580                 int error = mlx5_core_get_diagnostics_full(mdev,
 581                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 582                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 583                 if (error != 0)
 584                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 585         }
 586         PRIV_UNLOCK(priv);
 587 }
 588
 589 static void
 590 mlx5e_update_stats(void *arg)
 591 {
 592         struct mlx5e_priv *priv = arg;
 593
 594         schedule_work(&priv->update_stats_work);
 595
 596         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 597 }
 598
 599 static void
 600 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 601     enum mlx5_dev_event event)
 602 {
 603         switch (event) {
 604         case MLX5_DEV_EVENT_PORT_UP:
 605         case MLX5_DEV_EVENT_PORT_DOWN:
 606                 schedule_work(&priv->update_carrier_work);
 607                 break;
 608
 609         default:
 610                 break;
 611         }
 612 }
 613
 614 static void
 615 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 616     enum mlx5_dev_event event, unsigned long param)
 617 {
 618         struct mlx5e_priv *priv = vpriv;
 619
 620         mtx_lock(&priv->async_events_mtx);
 621         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 622                 mlx5e_async_event_sub(priv, event);
 623         mtx_unlock(&priv->async_events_mtx);
 624 }
 625
 626 static void
 627 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 628 {
 629         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 630 }
 631
 632 static void
 633 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 634 {
 635         mtx_lock(&priv->async_events_mtx);
 636         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 637         mtx_unlock(&priv->async_events_mtx);
 638 }
 639
 640 static const char *mlx5e_rq_stats_desc[] = {
 641         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 642 };
 643
 644 static int
 645 mlx5e_create_rq(struct mlx5e_channel *c,
 646     struct mlx5e_rq_param *param,
 647     struct mlx5e_rq *rq)
 648 {
 649         struct mlx5e_priv *priv = c->priv;
 650         struct mlx5_core_dev *mdev = priv->mdev;
 651         char buffer[16];
 652         void *rqc = param->rqc;
 653         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 654         int wq_sz;
 655         int err;
 656         int i;
 657
 658         /* Create DMA descriptor TAG */
 659         if ((err = -bus_dma_tag_create(
 660             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 661             1,                          /* any alignment */
 662             0,                          /* no boundary */
 663             BUS_SPACE_MAXADDR,          /* lowaddr */
 664             BUS_SPACE_MAXADDR,          /* highaddr */
 665             NULL, NULL,                 /* filter, filterarg */
 666             MJUM16BYTES,                /* maxsize */
 667             1,                          /* nsegments */
 668             MJUM16BYTES,                /* maxsegsize */
 669             0,                          /* flags */
 670             NULL, NULL,                 /* lockfunc, lockfuncarg */
 671             &rq->dma_tag)))
 672                 goto done;
 673
 674         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 675             &rq->wq_ctrl);
 676         if (err)
 677                 goto err_free_dma_tag;
 678
 679         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 680
 681         if (priv->params.hw_lro_en) {
 682                 rq->wqe_sz = priv->params.lro_wqe_sz;
 683         } else {
 684                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 685         }
 686         if (rq->wqe_sz > MJUM16BYTES) {
 687                 err = -ENOMEM;
 688                 goto err_rq_wq_destroy;
 689         } else if (rq->wqe_sz > MJUM9BYTES) {
 690                 rq->wqe_sz = MJUM16BYTES;
 691         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 692                 rq->wqe_sz = MJUM9BYTES;
 693         } else if (rq->wqe_sz > MCLBYTES) {
 694                 rq->wqe_sz = MJUMPAGESIZE;
 695         } else {
 696                 rq->wqe_sz = MCLBYTES;
 697         }
 698
 699         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 700         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 701         for (i = 0; i != wq_sz; i++) {
 702                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 703                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 704
 705                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 706                 if (err != 0) {
 707                         while (i--)
 708                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 709                         goto err_rq_mbuf_free;
 710                 }
 711                 wqe->data.lkey = c->mkey_be;
 712                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 713         }
 714
 715         rq->ifp = c->ifp;
 716         rq->channel = c;
 717         rq->ix = c->ix;
 718
 719         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 720         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 721             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 722             rq->stats.arg);
 723
 724 #ifdef HAVE_TURBO_LRO
 725         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 726                 rq->lro.mbuf = NULL;
 727 #else
 728         if (tcp_lro_init(&rq->lro))
 729                 rq->lro.lro_cnt = 0;
 730         else
 731                 rq->lro.ifp = c->ifp;
 732 #endif
 733         return (0);
 734
 735 err_rq_mbuf_free:
 736         free(rq->mbuf, M_MLX5EN);
 737 err_rq_wq_destroy:
 738         mlx5_wq_destroy(&rq->wq_ctrl);
 739 err_free_dma_tag:
 740         bus_dma_tag_destroy(rq->dma_tag);
 741 done:
 742         return (err);
 743 }
 744
 745 static void
 746 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 747 {
 748         int wq_sz;
 749         int i;
 750
 751         /* destroy all sysctl nodes */
 752         sysctl_ctx_free(&rq->stats.ctx);
 753
 754         /* free leftover LRO packets, if any */
 755 #ifdef HAVE_TURBO_LRO
 756         tcp_tlro_free(&rq->lro);
 757 #else
 758         tcp_lro_free(&rq->lro);
 759 #endif
 760         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 761         for (i = 0; i != wq_sz; i++) {
 762                 if (rq->mbuf[i].mbuf != NULL) {
 763                         bus_dmamap_unload(rq->dma_tag,
 764                             rq->mbuf[i].dma_map);
 765                         m_freem(rq->mbuf[i].mbuf);
 766                 }
 767                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 768         }
 769         free(rq->mbuf, M_MLX5EN);
 770         mlx5_wq_destroy(&rq->wq_ctrl);
 771 }
 772
 773 static int
 774 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 775 {
 776         struct mlx5e_channel *c = rq->channel;
 777         struct mlx5e_priv *priv = c->priv;
 778         struct mlx5_core_dev *mdev = priv->mdev;
 779
 780         void *in;
 781         void *rqc;
 782         void *wq;
 783         int inlen;
 784         int err;
 785
 786         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 787             sizeof(u64) * rq->wq_ctrl.buf.npages;
 788         in = mlx5_vzalloc(inlen);
 789         if (in == NULL)
 790                 return (-ENOMEM);
 791
 792         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 793         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 794
 795         memcpy(rqc, param->rqc, sizeof(param->rqc));
 796
 797         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 798         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 799         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 800         if (priv->counter_set_id >= 0)
 801                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 802         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 803             PAGE_SHIFT);
 804         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 805
 806         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 807             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 808
 809         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 810
 811         kvfree(in);
 812
 813         return (err);
 814 }
 815
 816 static int
 817 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 818 {
 819         struct mlx5e_channel *c = rq->channel;
 820         struct mlx5e_priv *priv = c->priv;
 821         struct mlx5_core_dev *mdev = priv->mdev;
 822
 823         void *in;
 824         void *rqc;
 825         int inlen;
 826         int err;
 827
 828         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 829         in = mlx5_vzalloc(inlen);
 830         if (in == NULL)
 831                 return (-ENOMEM);
 832
 833         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 834
 835         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 836         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 837         MLX5_SET(rqc, rqc, state, next_state);
 838
 839         err = mlx5_core_modify_rq(mdev, in, inlen);
 840
 841         kvfree(in);
 842
 843         return (err);
 844 }
 845
 846 static void
 847 mlx5e_disable_rq(struct mlx5e_rq *rq)
 848 {
 849         struct mlx5e_channel *c = rq->channel;
 850         struct mlx5e_priv *priv = c->priv;
 851         struct mlx5_core_dev *mdev = priv->mdev;
 852
 853         mlx5_core_destroy_rq(mdev, rq->rqn);
 854 }
 855
 856 static int
 857 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 858 {
 859         struct mlx5e_channel *c = rq->channel;
 860         struct mlx5e_priv *priv = c->priv;
 861         struct mlx5_wq_ll *wq = &rq->wq;
 862         int i;
 863
 864         for (i = 0; i < 1000; i++) {
 865                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 866                         return (0);
 867
 868                 msleep(4);
 869         }
 870         return (-ETIMEDOUT);
 871 }
 872
 873 static int
 874 mlx5e_open_rq(struct mlx5e_channel *c,
 875     struct mlx5e_rq_param *param,
 876     struct mlx5e_rq *rq)
 877 {
 878         int err;
 879
 880         err = mlx5e_create_rq(c, param, rq);
 881         if (err)
 882                 return (err);
 883
 884         err = mlx5e_enable_rq(rq, param);
 885         if (err)
 886                 goto err_destroy_rq;
 887
 888         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 889         if (err)
 890                 goto err_disable_rq;
 891
 892         c->rq.enabled = 1;
 893
 894         return (0);
 895
 896 err_disable_rq:
 897         mlx5e_disable_rq(rq);
 898 err_destroy_rq:
 899         mlx5e_destroy_rq(rq);
 900
 901         return (err);
 902 }
 903
 904 static void
 905 mlx5e_close_rq(struct mlx5e_rq *rq)
 906 {
 907         mtx_lock(&rq->mtx);
 908         rq->enabled = 0;
 909         callout_stop(&rq->watchdog);
 910         mtx_unlock(&rq->mtx);
 911
 912         callout_drain(&rq->watchdog);
 913
 914         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 915 }
 916
 917 static void
 918 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 919 {
 920         /* wait till RQ is empty */
 921         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 922                 msleep(4);
 923                 rq->cq.mcq.comp(&rq->cq.mcq);
 924         }
 925
 926         mlx5e_disable_rq(rq);
 927         mlx5e_destroy_rq(rq);
 928 }
 929
 930 void
 931 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 932 {
 933         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 934         int x;
 935
 936         for (x = 0; x != wq_sz; x++)
 937                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 938         free(sq->mbuf, M_MLX5EN);
 939 }
 940
 941 int
 942 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 943 {
 944         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 945         int err;
 946         int x;
 947
 948         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 949
 950         /* Create DMA descriptor MAPs */
 951         for (x = 0; x != wq_sz; x++) {
 952                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 953                 if (err != 0) {
 954                         while (x--)
 955                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 956                         free(sq->mbuf, M_MLX5EN);
 957                         return (err);
 958                 }
 959         }
 960         return (0);
 961 }
 962
 963 static const char *mlx5e_sq_stats_desc[] = {
 964         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 965 };
 966
 967 static int
 968 mlx5e_create_sq(struct mlx5e_channel *c,
 969     int tc,
 970     struct mlx5e_sq_param *param,
 971     struct mlx5e_sq *sq)
 972 {
 973         struct mlx5e_priv *priv = c->priv;
 974         struct mlx5_core_dev *mdev = priv->mdev;
 975         char buffer[16];
 976
 977         void *sqc = param->sqc;
 978         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 979 #ifdef RSS
 980         cpuset_t cpu_mask;
 981         int cpu_id;
 982 #endif
 983         int err;
 984
 985         /* Create DMA descriptor TAG */
 986         if ((err = -bus_dma_tag_create(
 987             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 988             1,                          /* any alignment */
 989             0,                          /* no boundary */
 990             BUS_SPACE_MAXADDR,          /* lowaddr */
 991             BUS_SPACE_MAXADDR,          /* highaddr */
 992             NULL, NULL,                 /* filter, filterarg */
 993             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 994             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 995             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 996             0,                          /* flags */
 997             NULL, NULL,                 /* lockfunc, lockfuncarg */
 998             &sq->dma_tag)))
 999                 goto done;
1000
1001         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1002         if (err)
1003                 goto err_free_dma_tag;
1004
1005         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1006             &sq->wq_ctrl);
1007         if (err)
1008                 goto err_unmap_free_uar;
1009
1010         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1011         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1012
1013         err = mlx5e_alloc_sq_db(sq);
1014         if (err)
1015                 goto err_sq_wq_destroy;
1016
1017         sq->mkey_be = c->mkey_be;
1018         sq->ifp = priv->ifp;
1019         sq->priv = priv;
1020         sq->tc = tc;
1021
1022         /* check if we should allocate a second packet buffer */
1023         if (priv->params_ethtool.tx_bufring_disable == 0) {
1024                 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1025                     M_WAITOK, &sq->lock);
1026                 if (sq->br == NULL) {
1027                         if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1028                             __func__);
1029                         err = -ENOMEM;
1030                         goto err_free_sq_db;
1031                 }
1032
1033                 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1034                     taskqueue_thread_enqueue, &sq->sq_tq);
1035                 if (sq->sq_tq == NULL) {
1036                         if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1037                             __func__);
1038                         err = -ENOMEM;
1039                         goto err_free_drbr;
1040                 }
1041
1042                 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1043 #ifdef RSS
1044                 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1045                 CPU_SETOF(cpu_id, &cpu_mask);
1046                 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1047                     "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1048 #else
1049                 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1050                     "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1051 #endif
1052         }
1053         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1054         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1055             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1056             sq->stats.arg);
1057
1058         return (0);
1059
1060 err_free_drbr:
1061         buf_ring_free(sq->br, M_MLX5EN);
1062 err_free_sq_db:
1063         mlx5e_free_sq_db(sq);
1064 err_sq_wq_destroy:
1065         mlx5_wq_destroy(&sq->wq_ctrl);
1066
1067 err_unmap_free_uar:
1068         mlx5_unmap_free_uar(mdev, &sq->uar);
1069
1070 err_free_dma_tag:
1071         bus_dma_tag_destroy(sq->dma_tag);
1072 done:
1073         return (err);
1074 }
1075
1076 static void
1077 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1078 {
1079         /* destroy all sysctl nodes */
1080         sysctl_ctx_free(&sq->stats.ctx);
1081
1082         mlx5e_free_sq_db(sq);
1083         mlx5_wq_destroy(&sq->wq_ctrl);
1084         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1085         if (sq->sq_tq != NULL) {
1086                 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1087                 taskqueue_free(sq->sq_tq);
1088         }
1089         if (sq->br != NULL)
1090                 buf_ring_free(sq->br, M_MLX5EN);
1091 }
1092
1093 int
1094 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1095     int tis_num)
1096 {
1097         void *in;
1098         void *sqc;
1099         void *wq;
1100         int inlen;
1101         int err;
1102
1103         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1104             sizeof(u64) * sq->wq_ctrl.buf.npages;
1105         in = mlx5_vzalloc(inlen);
1106         if (in == NULL)
1107                 return (-ENOMEM);
1108
1109         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1110         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1111
1112         memcpy(sqc, param->sqc, sizeof(param->sqc));
1113
1114         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1115         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1116         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1117         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1118         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1119
1120         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1121         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1122         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1123             PAGE_SHIFT);
1124         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1125
1126         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1127             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1128
1129         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1130
1131         kvfree(in);
1132
1133         return (err);
1134 }
1135
1136 int
1137 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1138 {
1139         void *in;
1140         void *sqc;
1141         int inlen;
1142         int err;
1143
1144         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1145         in = mlx5_vzalloc(inlen);
1146         if (in == NULL)
1147                 return (-ENOMEM);
1148
1149         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1150
1151         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1152         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1153         MLX5_SET(sqc, sqc, state, next_state);
1154
1155         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1156
1157         kvfree(in);
1158
1159         return (err);
1160 }
1161
1162 void
1163 mlx5e_disable_sq(struct mlx5e_sq *sq)
1164 {
1165
1166         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1167 }
1168
1169 static int
1170 mlx5e_open_sq(struct mlx5e_channel *c,
1171     int tc,
1172     struct mlx5e_sq_param *param,
1173     struct mlx5e_sq *sq)
1174 {
1175         int err;
1176
1177         err = mlx5e_create_sq(c, tc, param, sq);
1178         if (err)
1179                 return (err);
1180
1181         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1182         if (err)
1183                 goto err_destroy_sq;
1184
1185         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1186         if (err)
1187                 goto err_disable_sq;
1188
1189         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1190
1191         return (0);
1192
1193 err_disable_sq:
1194         mlx5e_disable_sq(sq);
1195 err_destroy_sq:
1196         mlx5e_destroy_sq(sq);
1197
1198         return (err);
1199 }
1200
1201 static void
1202 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1203 {
1204         /* fill up remainder with NOPs */
1205         while (sq->cev_counter != 0) {
1206                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1207                         if (can_sleep != 0) {
1208                                 mtx_unlock(&sq->lock);
1209                                 msleep(4);
1210                                 mtx_lock(&sq->lock);
1211                         } else {
1212                                 goto done;
1213                         }
1214                 }
1215                 /* send a single NOP */
1216                 mlx5e_send_nop(sq, 1);
1217                 wmb();
1218         }
1219 done:
1220         /* Check if we need to write the doorbell */
1221         if (likely(sq->doorbell.d64 != 0)) {
1222                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1223                 sq->doorbell.d64 = 0;
1224         }
1225 }
1226
1227 void
1228 mlx5e_sq_cev_timeout(void *arg)
1229 {
1230         struct mlx5e_sq *sq = arg;
1231
1232         mtx_assert(&sq->lock, MA_OWNED);
1233
1234         /* check next state */
1235         switch (sq->cev_next_state) {
1236         case MLX5E_CEV_STATE_SEND_NOPS:
1237                 /* fill TX ring with NOPs, if any */
1238                 mlx5e_sq_send_nops_locked(sq, 0);
1239
1240                 /* check if completed */
1241                 if (sq->cev_counter == 0) {
1242                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1243                         return;
1244                 }
1245                 break;
1246         default:
1247                 /* send NOPs on next timeout */
1248                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1249                 break;
1250         }
1251
1252         /* restart timer */
1253         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1254 }
1255
1256 void
1257 mlx5e_drain_sq(struct mlx5e_sq *sq)
1258 {
1259         int error;
1260
1261         /*
1262          * Check if already stopped.
1263          *
1264          * NOTE: The "stopped" variable is only written when both the
1265          * priv's configuration lock and the SQ's lock is locked. It
1266          * can therefore safely be read when only one of the two locks
1267          * is locked. This function is always called when the priv's
1268          * configuration lock is locked.
1269          */
1270         if (sq->stopped != 0)
1271                 return;
1272
1273         mtx_lock(&sq->lock);
1274
1275         /* don't put more packets into the SQ */
1276         sq->stopped = 1;
1277
1278         /* teardown event factor timer, if any */
1279         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1280         callout_stop(&sq->cev_callout);
1281
1282         /* send dummy NOPs in order to flush the transmit ring */
1283         mlx5e_sq_send_nops_locked(sq, 1);
1284         mtx_unlock(&sq->lock);
1285
1286         /* make sure it is safe to free the callout */
1287         callout_drain(&sq->cev_callout);
1288
1289         /* wait till SQ is empty or link is down */
1290         mtx_lock(&sq->lock);
1291         while (sq->cc != sq->pc &&
1292             (sq->priv->media_status_last & IFM_ACTIVE) != 0) {
1293                 mtx_unlock(&sq->lock);
1294                 msleep(1);
1295                 sq->cq.mcq.comp(&sq->cq.mcq);
1296                 mtx_lock(&sq->lock);
1297         }
1298         mtx_unlock(&sq->lock);
1299
1300         /* error out remaining requests */
1301         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1302         if (error != 0) {
1303                 if_printf(sq->ifp,
1304                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1305         }
1306
1307         /* wait till SQ is empty */
1308         mtx_lock(&sq->lock);
1309         while (sq->cc != sq->pc) {
1310                 mtx_unlock(&sq->lock);
1311                 msleep(1);
1312                 sq->cq.mcq.comp(&sq->cq.mcq);
1313                 mtx_lock(&sq->lock);
1314         }
1315         mtx_unlock(&sq->lock);
1316 }
1317
1318 static void
1319 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1320 {
1321
1322         mlx5e_drain_sq(sq);
1323         mlx5e_disable_sq(sq);
1324         mlx5e_destroy_sq(sq);
1325 }
1326
1327 static int
1328 mlx5e_create_cq(struct mlx5e_priv *priv,
1329     struct mlx5e_cq_param *param,
1330     struct mlx5e_cq *cq,
1331     mlx5e_cq_comp_t *comp,
1332     int eq_ix)
1333 {
1334         struct mlx5_core_dev *mdev = priv->mdev;
1335         struct mlx5_core_cq *mcq = &cq->mcq;
1336         int eqn_not_used;
1337         int irqn;
1338         int err;
1339         u32 i;
1340
1341         param->wq.buf_numa_node = 0;
1342         param->wq.db_numa_node = 0;
1343
1344         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1345             &cq->wq_ctrl);
1346         if (err)
1347                 return (err);
1348
1349         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1350
1351         mcq->cqe_sz = 64;
1352         mcq->set_ci_db = cq->wq_ctrl.db.db;
1353         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1354         *mcq->set_ci_db = 0;
1355         *mcq->arm_db = 0;
1356         mcq->vector = eq_ix;
1357         mcq->comp = comp;
1358         mcq->event = mlx5e_cq_error_event;
1359         mcq->irqn = irqn;
1360         mcq->uar = &priv->cq_uar;
1361
1362         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1363                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1364
1365                 cqe->op_own = 0xf1;
1366         }
1367
1368         cq->priv = priv;
1369
1370         return (0);
1371 }
1372
1373 static void
1374 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1375 {
1376         mlx5_wq_destroy(&cq->wq_ctrl);
1377 }
1378
1379 static int
1380 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1381 {
1382         struct mlx5_core_cq *mcq = &cq->mcq;
1383         void *in;
1384         void *cqc;
1385         int inlen;
1386         int irqn_not_used;
1387         int eqn;
1388         int err;
1389
1390         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1391             sizeof(u64) * cq->wq_ctrl.buf.npages;
1392         in = mlx5_vzalloc(inlen);
1393         if (in == NULL)
1394                 return (-ENOMEM);
1395
1396         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1397
1398         memcpy(cqc, param->cqc, sizeof(param->cqc));
1399
1400         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1401             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1402
1403         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1404
1405         MLX5_SET(cqc, cqc, c_eqn, eqn);
1406         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1407         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1408             PAGE_SHIFT);
1409         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1410
1411         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1412
1413         kvfree(in);
1414
1415         if (err)
1416                 return (err);
1417
1418         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1419
1420         return (0);
1421 }
1422
1423 static void
1424 mlx5e_disable_cq(struct mlx5e_cq *cq)
1425 {
1426
1427         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1428 }
1429
1430 int
1431 mlx5e_open_cq(struct mlx5e_priv *priv,
1432     struct mlx5e_cq_param *param,
1433     struct mlx5e_cq *cq,
1434     mlx5e_cq_comp_t *comp,
1435     int eq_ix)
1436 {
1437         int err;
1438
1439         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1440         if (err)
1441                 return (err);
1442
1443         err = mlx5e_enable_cq(cq, param, eq_ix);
1444         if (err)
1445                 goto err_destroy_cq;
1446
1447         return (0);
1448
1449 err_destroy_cq:
1450         mlx5e_destroy_cq(cq);
1451
1452         return (err);
1453 }
1454
1455 void
1456 mlx5e_close_cq(struct mlx5e_cq *cq)
1457 {
1458         mlx5e_disable_cq(cq);
1459         mlx5e_destroy_cq(cq);
1460 }
1461
1462 static int
1463 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1464     struct mlx5e_channel_param *cparam)
1465 {
1466         int err;
1467         int tc;
1468
1469         for (tc = 0; tc < c->num_tc; tc++) {
1470                 /* open completion queue */
1471                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1472                     &mlx5e_tx_cq_comp, c->ix);
1473                 if (err)
1474                         goto err_close_tx_cqs;
1475         }
1476         return (0);
1477
1478 err_close_tx_cqs:
1479         for (tc--; tc >= 0; tc--)
1480                 mlx5e_close_cq(&c->sq[tc].cq);
1481
1482         return (err);
1483 }
1484
1485 static void
1486 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1487 {
1488         int tc;
1489
1490         for (tc = 0; tc < c->num_tc; tc++)
1491                 mlx5e_close_cq(&c->sq[tc].cq);
1492 }
1493
1494 static int
1495 mlx5e_open_sqs(struct mlx5e_channel *c,
1496     struct mlx5e_channel_param *cparam)
1497 {
1498         int err;
1499         int tc;
1500
1501         for (tc = 0; tc < c->num_tc; tc++) {
1502                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1503                 if (err)
1504                         goto err_close_sqs;
1505         }
1506
1507         return (0);
1508
1509 err_close_sqs:
1510         for (tc--; tc >= 0; tc--)
1511                 mlx5e_close_sq_wait(&c->sq[tc]);
1512
1513         return (err);
1514 }
1515
1516 static void
1517 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1518 {
1519         int tc;
1520
1521         for (tc = 0; tc < c->num_tc; tc++)
1522                 mlx5e_close_sq_wait(&c->sq[tc]);
1523 }
1524
1525 static void
1526 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1527 {
1528         int tc;
1529
1530         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1531
1532         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1533
1534         for (tc = 0; tc < c->num_tc; tc++) {
1535                 struct mlx5e_sq *sq = c->sq + tc;
1536
1537                 mtx_init(&sq->lock, "mlx5tx",
1538                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1539                 mtx_init(&sq->comp_lock, "mlx5comp",
1540                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1541
1542                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1543
1544                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1545
1546                 /* ensure the TX completion event factor is not zero */
1547                 if (sq->cev_factor == 0)
1548                         sq->cev_factor = 1;
1549         }
1550 }
1551
1552 static void
1553 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1554 {
1555         int tc;
1556
1557         mtx_destroy(&c->rq.mtx);
1558
1559         for (tc = 0; tc < c->num_tc; tc++) {
1560                 mtx_destroy(&c->sq[tc].lock);
1561                 mtx_destroy(&c->sq[tc].comp_lock);
1562         }
1563 }
1564
1565 static int
1566 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1567     struct mlx5e_channel_param *cparam,
1568     struct mlx5e_channel *volatile *cp)
1569 {
1570         struct mlx5e_channel *c;
1571         int err;
1572
1573         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1574         c->priv = priv;
1575         c->ix = ix;
1576         c->cpu = 0;
1577         c->ifp = priv->ifp;
1578         c->mkey_be = cpu_to_be32(priv->mr.key);
1579         c->num_tc = priv->num_tc;
1580
1581         /* init mutexes */
1582         mlx5e_chan_mtx_init(c);
1583
1584         /* open transmit completion queue */
1585         err = mlx5e_open_tx_cqs(c, cparam);
1586         if (err)
1587                 goto err_free;
1588
1589         /* open receive completion queue */
1590         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1591             &mlx5e_rx_cq_comp, c->ix);
1592         if (err)
1593                 goto err_close_tx_cqs;
1594
1595         err = mlx5e_open_sqs(c, cparam);
1596         if (err)
1597                 goto err_close_rx_cq;
1598
1599         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1600         if (err)
1601                 goto err_close_sqs;
1602
1603         /* store channel pointer */
1604         *cp = c;
1605
1606         /* poll receive queue initially */
1607         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1608
1609         return (0);
1610
1611 err_close_sqs:
1612         mlx5e_close_sqs_wait(c);
1613
1614 err_close_rx_cq:
1615         mlx5e_close_cq(&c->rq.cq);
1616
1617 err_close_tx_cqs:
1618         mlx5e_close_tx_cqs(c);
1619
1620 err_free:
1621         /* destroy mutexes */
1622         mlx5e_chan_mtx_destroy(c);
1623         free(c, M_MLX5EN);
1624         return (err);
1625 }
1626
1627 static void
1628 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1629 {
1630         struct mlx5e_channel *c = *pp;
1631
1632         /* check if channel is already closed */
1633         if (c == NULL)
1634                 return;
1635         mlx5e_close_rq(&c->rq);
1636 }
1637
1638 static void
1639 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1640 {
1641         struct mlx5e_channel *c = *pp;
1642
1643         /* check if channel is already closed */
1644         if (c == NULL)
1645                 return;
1646         /* ensure channel pointer is no longer used */
1647         *pp = NULL;
1648
1649         mlx5e_close_rq_wait(&c->rq);
1650         mlx5e_close_sqs_wait(c);
1651         mlx5e_close_cq(&c->rq.cq);
1652         mlx5e_close_tx_cqs(c);
1653         /* destroy mutexes */
1654         mlx5e_chan_mtx_destroy(c);
1655         free(c, M_MLX5EN);
1656 }
1657
1658 static void
1659 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1660     struct mlx5e_rq_param *param)
1661 {
1662         void *rqc = param->rqc;
1663         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1664
1665         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1666         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1667         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1668         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1669         MLX5_SET(wq, wq, pd, priv->pdn);
1670
1671         param->wq.buf_numa_node = 0;
1672         param->wq.db_numa_node = 0;
1673         param->wq.linear = 1;
1674 }
1675
1676 static void
1677 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1678     struct mlx5e_sq_param *param)
1679 {
1680         void *sqc = param->sqc;
1681         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1682
1683         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1684         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1685         MLX5_SET(wq, wq, pd, priv->pdn);
1686
1687         param->wq.buf_numa_node = 0;
1688         param->wq.db_numa_node = 0;
1689         param->wq.linear = 1;
1690 }
1691
1692 static void
1693 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1694     struct mlx5e_cq_param *param)
1695 {
1696         void *cqc = param->cqc;
1697
1698         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1699 }
1700
1701 static void
1702 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1703     struct mlx5e_cq_param *param)
1704 {
1705         void *cqc = param->cqc;
1706
1707
1708         /*
1709          * TODO The sysctl to control on/off is a bool value for now, which means
1710          * we only support CSUM, once HASH is implemnted we'll need to address that.
1711          */
1712         if (priv->params.cqe_zipping_en) {
1713                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1714                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1715         }
1716
1717         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1718         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1719         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1720
1721         switch (priv->params.rx_cq_moderation_mode) {
1722         case 0:
1723                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1724                 break;
1725         default:
1726                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1727                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1728                 else
1729                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1730                 break;
1731         }
1732
1733         mlx5e_build_common_cq_param(priv, param);
1734 }
1735
1736 static void
1737 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1738     struct mlx5e_cq_param *param)
1739 {
1740         void *cqc = param->cqc;
1741
1742         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1743         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1744         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1745
1746         switch (priv->params.tx_cq_moderation_mode) {
1747         case 0:
1748                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1749                 break;
1750         default:
1751                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1752                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1753                 else
1754                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1755                 break;
1756         }
1757
1758         mlx5e_build_common_cq_param(priv, param);
1759 }
1760
1761 static void
1762 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1763     struct mlx5e_channel_param *cparam)
1764 {
1765         memset(cparam, 0, sizeof(*cparam));
1766
1767         mlx5e_build_rq_param(priv, &cparam->rq);
1768         mlx5e_build_sq_param(priv, &cparam->sq);
1769         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1770         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1771 }
1772
1773 static int
1774 mlx5e_open_channels(struct mlx5e_priv *priv)
1775 {
1776         struct mlx5e_channel_param cparam;
1777         void *ptr;
1778         int err;
1779         int i;
1780         int j;
1781
1782         priv->channel = malloc(priv->params.num_channels *
1783             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1784
1785         mlx5e_build_channel_param(priv, &cparam);
1786         for (i = 0; i < priv->params.num_channels; i++) {
1787                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1788                 if (err)
1789                         goto err_close_channels;
1790         }
1791
1792         for (j = 0; j < priv->params.num_channels; j++) {
1793                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1794                 if (err)
1795                         goto err_close_channels;
1796         }
1797
1798         return (0);
1799
1800 err_close_channels:
1801         for (i--; i >= 0; i--) {
1802                 mlx5e_close_channel(&priv->channel[i]);
1803                 mlx5e_close_channel_wait(&priv->channel[i]);
1804         }
1805
1806         /* remove "volatile" attribute from "channel" pointer */
1807         ptr = __DECONST(void *, priv->channel);
1808         priv->channel = NULL;
1809
1810         free(ptr, M_MLX5EN);
1811
1812         return (err);
1813 }
1814
1815 static void
1816 mlx5e_close_channels(struct mlx5e_priv *priv)
1817 {
1818         void *ptr;
1819         int i;
1820
1821         if (priv->channel == NULL)
1822                 return;
1823
1824         for (i = 0; i < priv->params.num_channels; i++)
1825                 mlx5e_close_channel(&priv->channel[i]);
1826         for (i = 0; i < priv->params.num_channels; i++)
1827                 mlx5e_close_channel_wait(&priv->channel[i]);
1828
1829         /* remove "volatile" attribute from "channel" pointer */
1830         ptr = __DECONST(void *, priv->channel);
1831         priv->channel = NULL;
1832
1833         free(ptr, M_MLX5EN);
1834 }
1835
1836 static int
1837 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1838 {
1839
1840         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1841                 uint8_t cq_mode;
1842
1843                 switch (priv->params.tx_cq_moderation_mode) {
1844                 case 0:
1845                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1846                         break;
1847                 default:
1848                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1849                         break;
1850                 }
1851
1852                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1853                     priv->params.tx_cq_moderation_usec,
1854                     priv->params.tx_cq_moderation_pkts,
1855                     cq_mode));
1856         }
1857
1858         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1859             priv->params.tx_cq_moderation_usec,
1860             priv->params.tx_cq_moderation_pkts));
1861 }
1862
1863 static int
1864 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1865 {
1866
1867         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1868                 uint8_t cq_mode;
1869                 int retval;
1870
1871                 switch (priv->params.rx_cq_moderation_mode) {
1872                 case 0:
1873                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1874                         break;
1875                 default:
1876                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1877                         break;
1878                 }
1879
1880                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1881                     priv->params.rx_cq_moderation_usec,
1882                     priv->params.rx_cq_moderation_pkts,
1883                     cq_mode);
1884
1885                 return (retval);
1886         }
1887
1888         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1889             priv->params.rx_cq_moderation_usec,
1890             priv->params.rx_cq_moderation_pkts));
1891 }
1892
1893 static int
1894 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1895 {
1896         int err;
1897         int i;
1898
1899         if (c == NULL)
1900                 return (EINVAL);
1901
1902         err = mlx5e_refresh_rq_params(priv, &c->rq);
1903         if (err)
1904                 goto done;
1905
1906         for (i = 0; i != c->num_tc; i++) {
1907                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1908                 if (err)
1909                         goto done;
1910         }
1911 done:
1912         return (err);
1913 }
1914
1915 int
1916 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1917 {
1918         int i;
1919
1920         if (priv->channel == NULL)
1921                 return (EINVAL);
1922
1923         for (i = 0; i < priv->params.num_channels; i++) {
1924                 int err;
1925
1926                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1927                 if (err)
1928                         return (err);
1929         }
1930         return (0);
1931 }
1932
1933 static int
1934 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1935 {
1936         struct mlx5_core_dev *mdev = priv->mdev;
1937         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1938         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1939
1940         memset(in, 0, sizeof(in));
1941
1942         MLX5_SET(tisc, tisc, prio, tc);
1943         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1944
1945         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1946 }
1947
1948 static void
1949 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1950 {
1951         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1952 }
1953
1954 static int
1955 mlx5e_open_tises(struct mlx5e_priv *priv)
1956 {
1957         int num_tc = priv->num_tc;
1958         int err;
1959         int tc;
1960
1961         for (tc = 0; tc < num_tc; tc++) {
1962                 err = mlx5e_open_tis(priv, tc);
1963                 if (err)
1964                         goto err_close_tises;
1965         }
1966
1967         return (0);
1968
1969 err_close_tises:
1970         for (tc--; tc >= 0; tc--)
1971                 mlx5e_close_tis(priv, tc);
1972
1973         return (err);
1974 }
1975
1976 static void
1977 mlx5e_close_tises(struct mlx5e_priv *priv)
1978 {
1979         int num_tc = priv->num_tc;
1980         int tc;
1981
1982         for (tc = 0; tc < num_tc; tc++)
1983                 mlx5e_close_tis(priv, tc);
1984 }
1985
1986 static int
1987 mlx5e_open_rqt(struct mlx5e_priv *priv)
1988 {
1989         struct mlx5_core_dev *mdev = priv->mdev;
1990         u32 *in;
1991         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1992         void *rqtc;
1993         int inlen;
1994         int err;
1995         int sz;
1996         int i;
1997
1998         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1999
2000         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2001         in = mlx5_vzalloc(inlen);
2002         if (in == NULL)
2003                 return (-ENOMEM);
2004         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2005
2006         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2007         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2008
2009         for (i = 0; i < sz; i++) {
2010                 int ix;
2011 #ifdef RSS
2012                 ix = rss_get_indirection_to_bucket(i);
2013 #else
2014                 ix = i;
2015 #endif
2016                 /* ensure we don't overflow */
2017                 ix %= priv->params.num_channels;
2018                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2019         }
2020
2021         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2022
2023         memset(out, 0, sizeof(out));
2024         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
2025         if (!err)
2026                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2027
2028         kvfree(in);
2029
2030         return (err);
2031 }
2032
2033 static void
2034 mlx5e_close_rqt(struct mlx5e_priv *priv)
2035 {
2036         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
2037         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
2038
2039         memset(in, 0, sizeof(in));
2040
2041         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2042         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2043
2044         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
2045             sizeof(out));
2046 }
2047
2048 static void
2049 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2050 {
2051         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2052         __be32 *hkey;
2053
2054         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2055
2056 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2057
2058 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2059                           MLX5_HASH_FIELD_SEL_DST_IP)
2060
2061 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2062                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2063                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2064                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2065
2066 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2067                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2068                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2069
2070         if (priv->params.hw_lro_en) {
2071                 MLX5_SET(tirc, tirc, lro_enable_mask,
2072                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2073                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2074                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2075                     (priv->params.lro_wqe_sz -
2076                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2077                 /* TODO: add the option to choose timer value dynamically */
2078                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2079                     MLX5_CAP_ETH(priv->mdev,
2080                     lro_timer_supported_periods[2]));
2081         }
2082
2083         /* setup parameters for hashing TIR type, if any */
2084         switch (tt) {
2085         case MLX5E_TT_ANY:
2086                 MLX5_SET(tirc, tirc, disp_type,
2087                     MLX5_TIRC_DISP_TYPE_DIRECT);
2088                 MLX5_SET(tirc, tirc, inline_rqn,
2089                     priv->channel[0]->rq.rqn);
2090                 break;
2091         default:
2092                 MLX5_SET(tirc, tirc, disp_type,
2093                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2094                 MLX5_SET(tirc, tirc, indirect_table,
2095                     priv->rqtn);
2096                 MLX5_SET(tirc, tirc, rx_hash_fn,
2097                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2098                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2099 #ifdef RSS
2100                 /*
2101                  * The FreeBSD RSS implementation does currently not
2102                  * support symmetric Toeplitz hashes:
2103                  */
2104                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2105                 rss_getkey((uint8_t *)hkey);
2106 #else
2107                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2108                 hkey[0] = cpu_to_be32(0xD181C62C);
2109                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2110                 hkey[2] = cpu_to_be32(0x1983A2FC);
2111                 hkey[3] = cpu_to_be32(0x943E1ADB);
2112                 hkey[4] = cpu_to_be32(0xD9389E6B);
2113                 hkey[5] = cpu_to_be32(0xD1039C2C);
2114                 hkey[6] = cpu_to_be32(0xA74499AD);
2115                 hkey[7] = cpu_to_be32(0x593D56D9);
2116                 hkey[8] = cpu_to_be32(0xF3253C06);
2117                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2118 #endif
2119                 break;
2120         }
2121
2122         switch (tt) {
2123         case MLX5E_TT_IPV4_TCP:
2124                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2125                     MLX5_L3_PROT_TYPE_IPV4);
2126                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2127                     MLX5_L4_PROT_TYPE_TCP);
2128 #ifdef RSS
2129                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2130                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2131                             MLX5_HASH_IP);
2132                 } else
2133 #endif
2134                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2135                     MLX5_HASH_ALL);
2136                 break;
2137
2138         case MLX5E_TT_IPV6_TCP:
2139                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2140                     MLX5_L3_PROT_TYPE_IPV6);
2141                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2142                     MLX5_L4_PROT_TYPE_TCP);
2143 #ifdef RSS
2144                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2145                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2146                             MLX5_HASH_IP);
2147                 } else
2148 #endif
2149                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2150                     MLX5_HASH_ALL);
2151                 break;
2152
2153         case MLX5E_TT_IPV4_UDP:
2154                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2155                     MLX5_L3_PROT_TYPE_IPV4);
2156                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2157                     MLX5_L4_PROT_TYPE_UDP);
2158 #ifdef RSS
2159                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2160                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2161                             MLX5_HASH_IP);
2162                 } else
2163 #endif
2164                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2165                     MLX5_HASH_ALL);
2166                 break;
2167
2168         case MLX5E_TT_IPV6_UDP:
2169                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2170                     MLX5_L3_PROT_TYPE_IPV6);
2171                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2172                     MLX5_L4_PROT_TYPE_UDP);
2173 #ifdef RSS
2174                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2175                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2176                             MLX5_HASH_IP);
2177                 } else
2178 #endif
2179                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2180                     MLX5_HASH_ALL);
2181                 break;
2182
2183         case MLX5E_TT_IPV4_IPSEC_AH:
2184                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2185                     MLX5_L3_PROT_TYPE_IPV4);
2186                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2187                     MLX5_HASH_IP_IPSEC_SPI);
2188                 break;
2189
2190         case MLX5E_TT_IPV6_IPSEC_AH:
2191                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2192                     MLX5_L3_PROT_TYPE_IPV6);
2193                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2194                     MLX5_HASH_IP_IPSEC_SPI);
2195                 break;
2196
2197         case MLX5E_TT_IPV4_IPSEC_ESP:
2198                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2199                     MLX5_L3_PROT_TYPE_IPV4);
2200                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2201                     MLX5_HASH_IP_IPSEC_SPI);
2202                 break;
2203
2204         case MLX5E_TT_IPV6_IPSEC_ESP:
2205                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2206                     MLX5_L3_PROT_TYPE_IPV6);
2207                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2208                     MLX5_HASH_IP_IPSEC_SPI);
2209                 break;
2210
2211         case MLX5E_TT_IPV4:
2212                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2213                     MLX5_L3_PROT_TYPE_IPV4);
2214                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2215                     MLX5_HASH_IP);
2216                 break;
2217
2218         case MLX5E_TT_IPV6:
2219                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2220                     MLX5_L3_PROT_TYPE_IPV6);
2221                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2222                     MLX5_HASH_IP);
2223                 break;
2224
2225         default:
2226                 break;
2227         }
2228 }
2229
2230 static int
2231 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2232 {
2233         struct mlx5_core_dev *mdev = priv->mdev;
2234         u32 *in;
2235         void *tirc;
2236         int inlen;
2237         int err;
2238
2239         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2240         in = mlx5_vzalloc(inlen);
2241         if (in == NULL)
2242                 return (-ENOMEM);
2243         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2244
2245         mlx5e_build_tir_ctx(priv, tirc, tt);
2246
2247         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2248
2249         kvfree(in);
2250
2251         return (err);
2252 }
2253
2254 static void
2255 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2256 {
2257         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2258 }
2259
2260 static int
2261 mlx5e_open_tirs(struct mlx5e_priv *priv)
2262 {
2263         int err;
2264         int i;
2265
2266         for (i = 0; i < MLX5E_NUM_TT; i++) {
2267                 err = mlx5e_open_tir(priv, i);
2268                 if (err)
2269                         goto err_close_tirs;
2270         }
2271
2272         return (0);
2273
2274 err_close_tirs:
2275         for (i--; i >= 0; i--)
2276                 mlx5e_close_tir(priv, i);
2277
2278         return (err);
2279 }
2280
2281 static void
2282 mlx5e_close_tirs(struct mlx5e_priv *priv)
2283 {
2284         int i;
2285
2286         for (i = 0; i < MLX5E_NUM_TT; i++)
2287                 mlx5e_close_tir(priv, i);
2288 }
2289
2290 /*
2291  * SW MTU does not include headers,
2292  * HW MTU includes all headers and checksums.
2293  */
2294 static int
2295 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2296 {
2297         struct mlx5e_priv *priv = ifp->if_softc;
2298         struct mlx5_core_dev *mdev = priv->mdev;
2299         int hw_mtu;
2300         int err;
2301
2302         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2303         if (err) {
2304                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2305                     __func__, sw_mtu, err);
2306                 return (err);
2307         }
2308         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2309         if (err) {
2310                 if_printf(ifp, "Query port MTU, after setting new "
2311                     "MTU value, failed\n");
2312         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2313                 err = -E2BIG,
2314                 if_printf(ifp, "Port MTU %d is smaller than "
2315                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2316         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2317                 err = -EINVAL;
2318                 if_printf(ifp, "Port MTU %d is bigger than "
2319                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2320         }
2321         ifp->if_mtu = sw_mtu;
2322         return (err);
2323 }
2324
2325 int
2326 mlx5e_open_locked(struct ifnet *ifp)
2327 {
2328         struct mlx5e_priv *priv = ifp->if_softc;
2329         int err;
2330         u16 set_id;
2331
2332         /* check if already opened */
2333         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2334                 return (0);
2335
2336 #ifdef RSS
2337         if (rss_getnumbuckets() > priv->params.num_channels) {
2338                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2339                     "channels(%u) available\n", rss_getnumbuckets(),
2340                     priv->params.num_channels);
2341         }
2342 #endif
2343         err = mlx5e_open_tises(priv);
2344         if (err) {
2345                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2346                     __func__, err);
2347                 return (err);
2348         }
2349         err = mlx5_vport_alloc_q_counter(priv->mdev,
2350             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2351         if (err) {
2352                 if_printf(priv->ifp,
2353                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2354                     __func__, err);
2355                 goto err_close_tises;
2356         }
2357         /* store counter set ID */
2358         priv->counter_set_id = set_id;
2359
2360         err = mlx5e_open_channels(priv);
2361         if (err) {
2362                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2363                     __func__, err);
2364                 goto err_dalloc_q_counter;
2365         }
2366         err = mlx5e_open_rqt(priv);
2367         if (err) {
2368                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2369                     __func__, err);
2370                 goto err_close_channels;
2371         }
2372         err = mlx5e_open_tirs(priv);
2373         if (err) {
2374                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2375                     __func__, err);
2376                 goto err_close_rqls;
2377         }
2378         err = mlx5e_open_flow_table(priv);
2379         if (err) {
2380                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2381                     __func__, err);
2382                 goto err_close_tirs;
2383         }
2384         err = mlx5e_add_all_vlan_rules(priv);
2385         if (err) {
2386                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2387                     __func__, err);
2388                 goto err_close_flow_table;
2389         }
2390         set_bit(MLX5E_STATE_OPENED, &priv->state);
2391
2392         mlx5e_update_carrier(priv);
2393         mlx5e_set_rx_mode_core(priv);
2394
2395         return (0);
2396
2397 err_close_flow_table:
2398         mlx5e_close_flow_table(priv);
2399
2400 err_close_tirs:
2401         mlx5e_close_tirs(priv);
2402
2403 err_close_rqls:
2404         mlx5e_close_rqt(priv);
2405
2406 err_close_channels:
2407         mlx5e_close_channels(priv);
2408
2409 err_dalloc_q_counter:
2410         mlx5_vport_dealloc_q_counter(priv->mdev,
2411             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2412
2413 err_close_tises:
2414         mlx5e_close_tises(priv);
2415
2416         return (err);
2417 }
2418
2419 static void
2420 mlx5e_open(void *arg)
2421 {
2422         struct mlx5e_priv *priv = arg;
2423
2424         PRIV_LOCK(priv);
2425         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2426                 if_printf(priv->ifp,
2427                     "%s: Setting port status to up failed\n",
2428                     __func__);
2429
2430         mlx5e_open_locked(priv->ifp);
2431         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2432         PRIV_UNLOCK(priv);
2433 }
2434
2435 int
2436 mlx5e_close_locked(struct ifnet *ifp)
2437 {
2438         struct mlx5e_priv *priv = ifp->if_softc;
2439
2440         /* check if already closed */
2441         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2442                 return (0);
2443
2444         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2445
2446         mlx5e_set_rx_mode_core(priv);
2447         mlx5e_del_all_vlan_rules(priv);
2448         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2449         mlx5e_close_flow_table(priv);
2450         mlx5e_close_tirs(priv);
2451         mlx5e_close_rqt(priv);
2452         mlx5e_close_channels(priv);
2453         mlx5_vport_dealloc_q_counter(priv->mdev,
2454             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2455         mlx5e_close_tises(priv);
2456
2457         return (0);
2458 }
2459
2460 #if (__FreeBSD_version >= 1100000)
2461 static uint64_t
2462 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2463 {
2464         struct mlx5e_priv *priv = ifp->if_softc;
2465         u64 retval;
2466
2467         /* PRIV_LOCK(priv); XXX not allowed */
2468         switch (cnt) {
2469         case IFCOUNTER_IPACKETS:
2470                 retval = priv->stats.vport.rx_packets;
2471                 break;
2472         case IFCOUNTER_IERRORS:
2473                 retval = priv->stats.vport.rx_error_packets +
2474                     priv->stats.pport.alignment_err +
2475                     priv->stats.pport.check_seq_err +
2476                     priv->stats.pport.crc_align_errors +
2477                     priv->stats.pport.in_range_len_errors +
2478                     priv->stats.pport.jabbers +
2479                     priv->stats.pport.out_of_range_len +
2480                     priv->stats.pport.oversize_pkts +
2481                     priv->stats.pport.symbol_err +
2482                     priv->stats.pport.too_long_errors +
2483                     priv->stats.pport.undersize_pkts +
2484                     priv->stats.pport.unsupported_op_rx;
2485                 break;
2486         case IFCOUNTER_IQDROPS:
2487                 retval = priv->stats.vport.rx_out_of_buffer +
2488                     priv->stats.pport.drop_events;
2489                 break;
2490         case IFCOUNTER_OPACKETS:
2491                 retval = priv->stats.vport.tx_packets;
2492                 break;
2493         case IFCOUNTER_OERRORS:
2494                 retval = priv->stats.vport.tx_error_packets;
2495                 break;
2496         case IFCOUNTER_IBYTES:
2497                 retval = priv->stats.vport.rx_bytes;
2498                 break;
2499         case IFCOUNTER_OBYTES:
2500                 retval = priv->stats.vport.tx_bytes;
2501                 break;
2502         case IFCOUNTER_IMCASTS:
2503                 retval = priv->stats.vport.rx_multicast_packets;
2504                 break;
2505         case IFCOUNTER_OMCASTS:
2506                 retval = priv->stats.vport.tx_multicast_packets;
2507                 break;
2508         case IFCOUNTER_OQDROPS:
2509                 retval = priv->stats.vport.tx_queue_dropped;
2510                 break;
2511         case IFCOUNTER_COLLISIONS:
2512                 retval = priv->stats.pport.collisions;
2513                 break;
2514         default:
2515                 retval = if_get_counter_default(ifp, cnt);
2516                 break;
2517         }
2518         /* PRIV_UNLOCK(priv); XXX not allowed */
2519         return (retval);
2520 }
2521 #endif
2522
2523 static void
2524 mlx5e_set_rx_mode(struct ifnet *ifp)
2525 {
2526         struct mlx5e_priv *priv = ifp->if_softc;
2527
2528         schedule_work(&priv->set_rx_mode_work);
2529 }
2530
2531 static int
2532 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2533 {
2534         struct mlx5e_priv *priv;
2535         struct ifreq *ifr;
2536         struct ifi2creq i2c;
2537         int error = 0;
2538         int mask = 0;
2539         int size_read = 0;
2540         int module_num;
2541         int max_mtu;
2542         uint8_t read_addr;
2543
2544         priv = ifp->if_softc;
2545
2546         /* check if detaching */
2547         if (priv == NULL || priv->gone != 0)
2548                 return (ENXIO);
2549
2550         switch (command) {
2551         case SIOCSIFMTU:
2552                 ifr = (struct ifreq *)data;
2553
2554                 PRIV_LOCK(priv);
2555                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2556
2557                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2558                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2559                         int was_opened;
2560
2561                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2562                         if (was_opened)
2563                                 mlx5e_close_locked(ifp);
2564
2565                         /* set new MTU */
2566                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2567
2568                         if (was_opened)
2569                                 mlx5e_open_locked(ifp);
2570                 } else {
2571                         error = EINVAL;
2572                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2573                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2574                 }
2575                 PRIV_UNLOCK(priv);
2576                 break;
2577         case SIOCSIFFLAGS:
2578                 if ((ifp->if_flags & IFF_UP) &&
2579                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2580                         mlx5e_set_rx_mode(ifp);
2581                         break;
2582                 }
2583                 PRIV_LOCK(priv);
2584                 if (ifp->if_flags & IFF_UP) {
2585                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2586                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2587                                         mlx5e_open_locked(ifp);
2588                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2589                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2590                         }
2591                 } else {
2592                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2593                                 mlx5_set_port_status(priv->mdev,
2594                                     MLX5_PORT_DOWN);
2595                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2596                                         mlx5e_close_locked(ifp);
2597                                 mlx5e_update_carrier(priv);
2598                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2599                         }
2600                 }
2601                 PRIV_UNLOCK(priv);
2602                 break;
2603         case SIOCADDMULTI:
2604         case SIOCDELMULTI:
2605                 mlx5e_set_rx_mode(ifp);
2606                 break;
2607         case SIOCSIFMEDIA:
2608         case SIOCGIFMEDIA:
2609         case SIOCGIFXMEDIA:
2610                 ifr = (struct ifreq *)data;
2611                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2612                 break;
2613         case SIOCSIFCAP:
2614                 ifr = (struct ifreq *)data;
2615                 PRIV_LOCK(priv);
2616                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2617
2618                 if (mask & IFCAP_TXCSUM) {
2619                         ifp->if_capenable ^= IFCAP_TXCSUM;
2620                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2621
2622                         if (IFCAP_TSO4 & ifp->if_capenable &&
2623                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2624                                 ifp->if_capenable &= ~IFCAP_TSO4;
2625                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2626                                 if_printf(ifp,
2627                                     "tso4 disabled due to -txcsum.\n");
2628                         }
2629                 }
2630                 if (mask & IFCAP_TXCSUM_IPV6) {
2631                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2632                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2633
2634                         if (IFCAP_TSO6 & ifp->if_capenable &&
2635                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2636                                 ifp->if_capenable &= ~IFCAP_TSO6;
2637                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2638                                 if_printf(ifp,
2639                                     "tso6 disabled due to -txcsum6.\n");
2640                         }
2641                 }
2642                 if (mask & IFCAP_RXCSUM)
2643                         ifp->if_capenable ^= IFCAP_RXCSUM;
2644                 if (mask & IFCAP_RXCSUM_IPV6)
2645                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2646                 if (mask & IFCAP_TSO4) {
2647                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2648                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2649                                 if_printf(ifp, "enable txcsum first.\n");
2650                                 error = EAGAIN;
2651                                 goto out;
2652                         }
2653                         ifp->if_capenable ^= IFCAP_TSO4;
2654                         ifp->if_hwassist ^= CSUM_IP_TSO;
2655                 }
2656                 if (mask & IFCAP_TSO6) {
2657                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2658                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2659                                 if_printf(ifp, "enable txcsum6 first.\n");
2660                                 error = EAGAIN;
2661                                 goto out;
2662                         }
2663                         ifp->if_capenable ^= IFCAP_TSO6;
2664                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2665                 }
2666                 if (mask & IFCAP_VLAN_HWFILTER) {
2667                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2668                                 mlx5e_disable_vlan_filter(priv);
2669                         else
2670                                 mlx5e_enable_vlan_filter(priv);
2671
2672                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2673                 }
2674                 if (mask & IFCAP_VLAN_HWTAGGING)
2675                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2676                 if (mask & IFCAP_WOL_MAGIC)
2677                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2678
2679                 VLAN_CAPABILITIES(ifp);
2680                 /* turn off LRO means also turn of HW LRO - if it's on */
2681                 if (mask & IFCAP_LRO) {
2682                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2683                         bool need_restart = false;
2684
2685                         ifp->if_capenable ^= IFCAP_LRO;
2686                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2687                                 if (priv->params.hw_lro_en) {
2688                                         priv->params.hw_lro_en = false;
2689                                         need_restart = true;
2690                                         /* Not sure this is the correct way */
2691                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2692                                 }
2693                         }
2694                         if (was_opened && need_restart) {
2695                                 mlx5e_close_locked(ifp);
2696                                 mlx5e_open_locked(ifp);
2697                         }
2698                 }
2699 out:
2700                 PRIV_UNLOCK(priv);
2701                 break;
2702
2703         case SIOCGI2C:
2704                 ifr = (struct ifreq *)data;
2705
2706                 /*
2707                  * Copy from the user-space address ifr_data to the
2708                  * kernel-space address i2c
2709                  */
2710                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2711                 if (error)
2712                         break;
2713
2714                 if (i2c.len > sizeof(i2c.data)) {
2715                         error = EINVAL;
2716                         break;
2717                 }
2718
2719                 PRIV_LOCK(priv);
2720                 /* Get module_num which is required for the query_eeprom */
2721                 error = mlx5_query_module_num(priv->mdev, &module_num);
2722                 if (error) {
2723                         if_printf(ifp, "Query module num failed, eeprom "
2724                             "reading is not supported\n");
2725                         error = EINVAL;
2726                         goto err_i2c;
2727                 }
2728                 /* Check if module is present before doing an access */
2729                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2730                     MLX5_MODULE_STATUS_PLUGGED) {
2731                         error = EINVAL;
2732                         goto err_i2c;
2733                 }
2734                 /*
2735                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2736                  * The internal conversion is as follows:
2737                  */
2738                 if (i2c.dev_addr == 0xA0)
2739                         read_addr = MLX5E_I2C_ADDR_LOW;
2740                 else if (i2c.dev_addr == 0xA2)
2741                         read_addr = MLX5E_I2C_ADDR_HIGH;
2742                 else {
2743                         if_printf(ifp, "Query eeprom failed, "
2744                             "Invalid Address: %X\n", i2c.dev_addr);
2745                         error = EINVAL;
2746                         goto err_i2c;
2747                 }
2748                 error = mlx5_query_eeprom(priv->mdev,
2749                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2750                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2751                     (uint32_t *)i2c.data, &size_read);
2752                 if (error) {
2753                         if_printf(ifp, "Query eeprom failed, eeprom "
2754                             "reading is not supported\n");
2755                         error = EINVAL;
2756                         goto err_i2c;
2757                 }
2758
2759                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2760                         error = mlx5_query_eeprom(priv->mdev,
2761                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2762                             (uint32_t)(i2c.offset + size_read),
2763                             (uint32_t)(i2c.len - size_read), module_num,
2764                             (uint32_t *)(i2c.data + size_read), &size_read);
2765                 }
2766                 if (error) {
2767                         if_printf(ifp, "Query eeprom failed, eeprom "
2768                             "reading is not supported\n");
2769                         error = EINVAL;
2770                         goto err_i2c;
2771                 }
2772
2773                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2774 err_i2c:
2775                 PRIV_UNLOCK(priv);
2776                 break;
2777
2778         default:
2779                 error = ether_ioctl(ifp, command, data);
2780                 break;
2781         }
2782         return (error);
2783 }
2784
2785 static int
2786 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2787 {
2788         /*
2789          * TODO: uncoment once FW really sets all these bits if
2790          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2791          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2792          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2793          * -ENOTSUPP;
2794          */
2795
2796         /* TODO: add more must-to-have features */
2797
2798         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2799                 return (-ENODEV);
2800
2801         return (0);
2802 }
2803
2804 static void
2805 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2806     struct mlx5e_priv *priv,
2807     int num_comp_vectors)
2808 {
2809         /*
2810          * TODO: Consider link speed for setting "log_sq_size",
2811          * "log_rq_size" and "cq_moderation_xxx":
2812          */
2813         priv->params.log_sq_size =
2814             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2815         priv->params.log_rq_size =
2816             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2817         priv->params.rx_cq_moderation_usec =
2818             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2819             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2820             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2821         priv->params.rx_cq_moderation_mode =
2822             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2823         priv->params.rx_cq_moderation_pkts =
2824             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2825         priv->params.tx_cq_moderation_usec =
2826             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2827         priv->params.tx_cq_moderation_pkts =
2828             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2829         priv->params.min_rx_wqes =
2830             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2831         priv->params.rx_hash_log_tbl_sz =
2832             (order_base_2(num_comp_vectors) >
2833             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2834             order_base_2(num_comp_vectors) :
2835             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2836         priv->params.num_tc = 1;
2837         priv->params.default_vlan_prio = 0;
2838         priv->counter_set_id = -1;
2839
2840         /*
2841          * hw lro is currently defaulted to off. when it won't anymore we
2842          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2843          */
2844         priv->params.hw_lro_en = false;
2845         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2846
2847         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2848
2849         priv->mdev = mdev;
2850         priv->params.num_channels = num_comp_vectors;
2851         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2852         priv->queue_mapping_channel_mask =
2853             roundup_pow_of_two(num_comp_vectors) - 1;
2854         priv->num_tc = priv->params.num_tc;
2855         priv->default_vlan_prio = priv->params.default_vlan_prio;
2856
2857         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2858         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2859         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2860 }
2861
2862 static int
2863 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2864     struct mlx5_core_mr *mr)
2865 {
2866         struct ifnet *ifp = priv->ifp;
2867         struct mlx5_core_dev *mdev = priv->mdev;
2868         struct mlx5_create_mkey_mbox_in *in;
2869         int err;
2870
2871         in = mlx5_vzalloc(sizeof(*in));
2872         if (in == NULL) {
2873                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2874                 return (-ENOMEM);
2875         }
2876         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2877             MLX5_PERM_LOCAL_READ |
2878             MLX5_ACCESS_MODE_PA;
2879         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2880         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2881
2882         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2883             NULL);
2884         if (err)
2885                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2886                     __func__, err);
2887
2888         kvfree(in);
2889
2890         return (err);
2891 }
2892
2893 static const char *mlx5e_vport_stats_desc[] = {
2894         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2895 };
2896
2897 static const char *mlx5e_pport_stats_desc[] = {
2898         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2899 };
2900
2901 static void
2902 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2903 {
2904         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2905         sx_init(&priv->state_lock, "mlx5state");
2906         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2907         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2908 }
2909
2910 static void
2911 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2912 {
2913         mtx_destroy(&priv->async_events_mtx);
2914         sx_destroy(&priv->state_lock);
2915 }
2916
2917 static int
2918 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2919 {
2920         /*
2921          * %d.%d%.d the string format.
2922          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2923          * We need at most 5 chars to store that.
2924          * It also has: two "." and NULL at the end, which means we need 18
2925          * (5*3 + 3) chars at most.
2926          */
2927         char fw[18];
2928         struct mlx5e_priv *priv = arg1;
2929         int error;
2930
2931         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2932             fw_rev_sub(priv->mdev));
2933         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2934         return (error);
2935 }
2936
2937 static void
2938 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2939 {
2940         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2941             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2942             sysctl_firmware, "A", "HCA firmware version");
2943
2944         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2945             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2946             "Board ID");
2947 }
2948
2949 static void
2950 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2951 {
2952 #if (__FreeBSD_version < 1100000)
2953         char path[64];
2954
2955 #endif
2956         /* Only receiving pauseframes is enabled by default */
2957         priv->params.tx_pauseframe_control = 0;
2958         priv->params.rx_pauseframe_control = 1;
2959
2960 #if (__FreeBSD_version < 1100000)
2961         /* compute path for sysctl */
2962         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2963             device_get_unit(priv->mdev->pdev->dev.bsddev));
2964
2965         /* try to fetch tunable, if any */
2966         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2967
2968         /* compute path for sysctl */
2969         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2970             device_get_unit(priv->mdev->pdev->dev.bsddev));
2971
2972         /* try to fetch tunable, if any */
2973         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2974 #endif
2975
2976         /* register pausframe SYSCTLs */
2977         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2978             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2979             &priv->params.tx_pauseframe_control, 0,
2980             "Set to enable TX pause frames. Clear to disable.");
2981
2982         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2983             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2984             &priv->params.rx_pauseframe_control, 0,
2985             "Set to enable RX pause frames. Clear to disable.");
2986
2987         /* range check */
2988         priv->params.tx_pauseframe_control =
2989             priv->params.tx_pauseframe_control ? 1 : 0;
2990         priv->params.rx_pauseframe_control =
2991             priv->params.rx_pauseframe_control ? 1 : 0;
2992
2993         /* update firmware */
2994         mlx5_set_port_pause(priv->mdev, 1,
2995             priv->params.rx_pauseframe_control,
2996             priv->params.tx_pauseframe_control);
2997 }
2998
2999 static void *
3000 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3001 {
3002         static volatile int mlx5_en_unit;
3003         struct ifnet *ifp;
3004         struct mlx5e_priv *priv;
3005         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3006         struct sysctl_oid_list *child;
3007         int ncv = mdev->priv.eq_table.num_comp_vectors;
3008         char unit[16];
3009         int err;
3010         int i;
3011         u32 eth_proto_cap;
3012
3013         if (mlx5e_check_required_hca_cap(mdev)) {
3014                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3015                 return (NULL);
3016         }
3017         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3018         mlx5e_priv_mtx_init(priv);
3019
3020         ifp = priv->ifp = if_alloc(IFT_ETHER);
3021         if (ifp == NULL) {
3022                 mlx5_core_err(mdev, "if_alloc() failed\n");
3023                 goto err_free_priv;
3024         }
3025         ifp->if_softc = priv;
3026         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
3027         ifp->if_mtu = ETHERMTU;
3028         ifp->if_init = mlx5e_open;
3029         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3030         ifp->if_ioctl = mlx5e_ioctl;
3031         ifp->if_transmit = mlx5e_xmit;
3032         ifp->if_qflush = if_qflush;
3033 #if (__FreeBSD_version >= 1100000)
3034         ifp->if_get_counter = mlx5e_get_counter;
3035 #endif
3036         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3037         /*
3038          * Set driver features
3039          */
3040         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3041         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3042         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3043         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3044         ifp->if_capabilities |= IFCAP_LRO;
3045         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3046         ifp->if_capabilities |= IFCAP_HWSTATS;
3047
3048         /* set TSO limits so that we don't have to drop TX packets */
3049         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3050         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3051         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3052
3053         ifp->if_capenable = ifp->if_capabilities;
3054         ifp->if_hwassist = 0;
3055         if (ifp->if_capenable & IFCAP_TSO)
3056                 ifp->if_hwassist |= CSUM_TSO;
3057         if (ifp->if_capenable & IFCAP_TXCSUM)
3058                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3059         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3060                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3061
3062         /* ifnet sysctl tree */
3063         sysctl_ctx_init(&priv->sysctl_ctx);
3064         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3065             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3066         if (priv->sysctl_ifnet == NULL) {
3067                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3068                 goto err_free_sysctl;
3069         }
3070         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3071         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3072             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3073         if (priv->sysctl_ifnet == NULL) {
3074                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3075                 goto err_free_sysctl;
3076         }
3077
3078         /* HW sysctl tree */
3079         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3080         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3081             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3082         if (priv->sysctl_hw == NULL) {
3083                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3084                 goto err_free_sysctl;
3085         }
3086         mlx5e_build_ifp_priv(mdev, priv, ncv);
3087         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3088         if (err) {
3089                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3090                     __func__, err);
3091                 goto err_free_sysctl;
3092         }
3093         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3094         if (err) {
3095                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3096                     __func__, err);
3097                 goto err_unmap_free_uar;
3098         }
3099         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3100         if (err) {
3101                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3102                     __func__, err);
3103                 goto err_dealloc_pd;
3104         }
3105         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3106         if (err) {
3107                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3108                     __func__, err);
3109                 goto err_dealloc_transport_domain;
3110         }
3111         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3112
3113         /* check if we should generate a random MAC address */
3114         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3115             is_zero_ether_addr(dev_addr)) {
3116                 random_ether_addr(dev_addr);
3117                 if_printf(ifp, "Assigned random MAC address\n");
3118         }
3119
3120         /* set default MTU */
3121         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3122
3123         /* Set desc */
3124         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3125
3126         /* Set default media status */
3127         priv->media_status_last = IFM_AVALID;
3128         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3129             IFM_ETH_RXPAUSE | IFM_FDX;
3130
3131         /* setup default pauseframes configuration */
3132         mlx5e_setup_pauseframes(priv);
3133
3134         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3135         if (err) {
3136                 eth_proto_cap = 0;
3137                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3138                     __func__, err);
3139         }
3140
3141         /* Setup supported medias */
3142         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3143             mlx5e_media_change, mlx5e_media_status);
3144
3145         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3146                 if (mlx5e_mode_table[i].baudrate == 0)
3147                         continue;
3148                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3149                         ifmedia_add(&priv->media,
3150                             mlx5e_mode_table[i].subtype |
3151                             IFM_ETHER, 0, NULL);
3152                         ifmedia_add(&priv->media,
3153                             mlx5e_mode_table[i].subtype |
3154                             IFM_ETHER | IFM_FDX |
3155                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3156                 }
3157         }
3158
3159         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3160         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3161             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3162
3163         /* Set autoselect by default */
3164         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3165             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3166         ether_ifattach(ifp, dev_addr);
3167
3168         /* Register for VLAN events */
3169         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3170             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3171         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3172             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3173
3174         /* Link is down by default */
3175         if_link_state_change(ifp, LINK_STATE_DOWN);
3176
3177         mlx5e_enable_async_events(priv);
3178
3179         mlx5e_add_hw_stats(priv);
3180
3181         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3182             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3183             priv->stats.vport.arg);
3184
3185         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3186             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3187             priv->stats.pport.arg);
3188
3189         mlx5e_create_ethtool(priv);
3190
3191         mtx_lock(&priv->async_events_mtx);
3192         mlx5e_update_stats(priv);
3193         mtx_unlock(&priv->async_events_mtx);
3194
3195         return (priv);
3196
3197 err_dealloc_transport_domain:
3198         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3199
3200 err_dealloc_pd:
3201         mlx5_core_dealloc_pd(mdev, priv->pdn);
3202
3203 err_unmap_free_uar:
3204         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3205
3206 err_free_sysctl:
3207         sysctl_ctx_free(&priv->sysctl_ctx);
3208
3209         if_free(ifp);
3210
3211 err_free_priv:
3212         mlx5e_priv_mtx_destroy(priv);
3213         free(priv, M_MLX5EN);
3214         return (NULL);
3215 }
3216
3217 static void
3218 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3219 {
3220         struct mlx5e_priv *priv = vpriv;
3221         struct ifnet *ifp = priv->ifp;
3222
3223         /* don't allow more IOCTLs */
3224         priv->gone = 1;
3225
3226         /*
3227          * Clear the device description to avoid use after free,
3228          * because the bsddev is not destroyed when this module is
3229          * unloaded:
3230          */
3231         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3232
3233         /* XXX wait a bit to allow IOCTL handlers to complete */
3234         pause("W", hz);
3235
3236         /* stop watchdog timer */
3237         callout_drain(&priv->watchdog);
3238
3239         if (priv->vlan_attach != NULL)
3240                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3241         if (priv->vlan_detach != NULL)
3242                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3243
3244         /* make sure device gets closed */
3245         PRIV_LOCK(priv);
3246         mlx5e_close_locked(ifp);
3247         PRIV_UNLOCK(priv);
3248
3249         /* unregister device */
3250         ifmedia_removeall(&priv->media);
3251         ether_ifdetach(ifp);
3252         if_free(ifp);
3253
3254         /* destroy all remaining sysctl nodes */
3255         if (priv->sysctl_debug)
3256                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3257         sysctl_ctx_free(&priv->stats.vport.ctx);
3258         sysctl_ctx_free(&priv->stats.pport.ctx);
3259         sysctl_ctx_free(&priv->sysctl_ctx);
3260
3261         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3262         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3263         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3264         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3265         mlx5e_disable_async_events(priv);
3266         flush_scheduled_work();
3267         mlx5e_priv_mtx_destroy(priv);
3268         free(priv, M_MLX5EN);
3269 }
3270
3271 static void *
3272 mlx5e_get_ifp(void *vpriv)
3273 {
3274         struct mlx5e_priv *priv = vpriv;
3275
3276         return (priv->ifp);
3277 }
3278
3279 static struct mlx5_interface mlx5e_interface = {
3280         .add = mlx5e_create_ifp,
3281         .remove = mlx5e_destroy_ifp,
3282         .event = mlx5e_async_event,
3283         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3284         .get_dev = mlx5e_get_ifp,
3285 };
3286
3287 void
3288 mlx5e_init(void)
3289 {
3290         mlx5_register_interface(&mlx5e_interface);
3291 }
3292
3293 void
3294 mlx5e_cleanup(void)
3295 {
3296         mlx5_unregister_interface(&mlx5e_interface);
3297 }
3298
3299 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3300 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3301
3302 #if (__FreeBSD_version >= 1100000)
3303 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3304 #endif
3305 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3306 MODULE_VERSION(mlx5en, 1);