2 * Copyright (c) 2013 LSI Corp.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * LSI MPT-Fusion Host Adapter FreeBSD
35 * Copyright (c) 2000-2013 LSI Corporation.
39 * Title: MPI Configuration messages and pages
40 * Creation Date: November 10, 2006
42 * mpi2_cnfg.h Version: 02.00.27
44 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
45 * prefix are for use only on MPI v2.5 products, and must not be used
46 * with MPI v2.0 products. Unless otherwise noted, names beginning with
47 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
52 * Date Version Description
53 * -------- -------- ------------------------------------------------------
54 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
55 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
56 * Added Manufacturing Page 11.
57 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
59 * 06-26-07 02.00.02 Adding generic structure for product-specific
60 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
61 * Rework of BIOS Page 2 configuration page.
62 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
64 * Added configuration pages IOC Page 8 and Driver
65 * Persistent Mapping Page 0.
66 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
67 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
68 * RAID Physical Disk Pages 0 and 1, RAID Configuration
70 * Added new value for AccessStatus field of SAS Device
71 * Page 0 (_SATA_NEEDS_INITIALIZATION).
72 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
73 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
74 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
76 * Modified IOC Page 7 to use masks and added field for
77 * SASBroadcastPrimitiveMasks.
78 * Added MPI2_CONFIG_PAGE_BIOS_4.
79 * Added MPI2_CONFIG_PAGE_LOG_0.
80 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
81 * Added SAS Device IDs.
82 * Updated Integrated RAID configuration pages including
83 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
85 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
86 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
87 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
88 * Added missing MaxNumRoutedSasAddresses field to
89 * MPI2_CONFIG_PAGE_EXPANDER_0.
90 * Added SAS Port Page 0.
91 * Modified structure layout for
92 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
93 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
94 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
95 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
97 * Added two new values for the Physical Disk Coercion Size
98 * bits in the Flags field of Manufacturing Page 4.
99 * Added product-specific Manufacturing pages 16 to 31.
100 * Modified Flags bits for controlling write cache on SATA
101 * drives in IO Unit Page 1.
102 * Added new bit to AdditionalControlFlags of SAS IO Unit
103 * Page 1 to control Invalid Topology Correction.
104 * Added additional defines for RAID Volume Page 0
105 * VolumeStatusFlags field.
106 * Modified meaning of RAID Volume Page 0 VolumeSettings
107 * define for auto-configure of hot-swap drives.
108 * Added SupportedPhysDisks field to RAID Volume Page 1 and
109 * added related defines.
110 * Added PhysDiskAttributes field (and related defines) to
111 * RAID Physical Disk Page 0.
112 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
113 * Added three new DiscoveryStatus bits for SAS IO Unit
114 * Page 0 and SAS Expander Page 0.
115 * Removed multiplexing information from SAS IO Unit pages.
116 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
117 * Removed Zone Address Resolved bit from PhyInfo and from
118 * Expander Page 0 Flags field.
119 * Added two new AccessStatus values to SAS Device Page 0
120 * for indicating routing problems. Added 3 reserved words
122 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
123 * Inserted missing reserved field into structure for IOC
125 * Added more pending task bits to RAID Volume Page 0
126 * VolumeStatusFlags defines.
127 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
128 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
129 * and SAS Expander Page 0 to flag a downstream initiator
130 * when in simplified routing mode.
131 * Removed SATA Init Failure defines for DiscoveryStatus
132 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
133 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
134 * Added PortGroups, DmaGroup, and ControlGroup fields to
136 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
138 * Added expander reduced functionality data to SAS
140 * Added SAS PHY Page 2 and SAS PHY Page 3.
141 * 07-30-09 02.00.12 Added IO Unit Page 7.
142 * Added new device ids.
143 * Added SAS IO Unit Page 5.
144 * Added partial and slumber power management capable flags
145 * to SAS Device Page 0 Flags field.
146 * Added PhyInfo defines for power condition.
147 * Added Ethernet configuration pages.
148 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
149 * Added SAS PHY Page 4 structure and defines.
150 * 02-10-10 02.00.14 Modified the comments for the configuration page
151 * structures that contain an array of data. The host
152 * should use the "count" field in the page data (e.g. the
153 * NumPhys field) to determine the number of valid elements
155 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
156 * Added PowerManagementCapabilities to IO Unit Page 7.
157 * Added PortWidthModGroup field to
158 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
159 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
160 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
161 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
162 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
164 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
165 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
166 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
168 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
169 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
171 * Added BoardTemperature and BoardTemperatureUnits fields
172 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
173 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
174 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
175 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
176 * Added IO Unit Page 8, IO Unit Page 9,
177 * and IO Unit Page 10.
178 * Added SASNotifyPrimitiveMasks field to
179 * MPI2_CONFIG_PAGE_IOC_7.
180 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
181 * 05-25-11 02.00.20 Cleaned up a few comments.
182 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
183 * for PCIe link as obsolete.
184 * Added SpinupFlags field containing a Disable Spin-up bit
185 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
187 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
188 * Added UEFIVersion field to BIOS Page 1 and defined new
190 * Incorporating additions for MPI v2.5.
191 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
192 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
193 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
194 * obsolete for MPI v2.5 and later.
195 * Added some defines for 12G SAS speeds.
196 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
197 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
198 * match the specification.
199 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
201 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
202 * MPI2_CONFIG_PAGE_MAN_7.
203 * Added EnclosureLevel and ConnectorName fields to
204 * MPI2_CONFIG_PAGE_SAS_DEV_0.
205 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
206 * MPI2_CONFIG_PAGE_SAS_DEV_0.
207 * Added EnclosureLevel field to
208 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
209 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
210 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
211 * --------------------------------------------------------------------------
217 /*****************************************************************************
218 * Configuration Page Header and defines
219 *****************************************************************************/
221 /* Config Page Header */
222 typedef struct _MPI2_CONFIG_PAGE_HEADER
224 U8 PageVersion; /* 0x00 */
225 U8 PageLength; /* 0x01 */
226 U8 PageNumber; /* 0x02 */
227 U8 PageType; /* 0x03 */
228 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
229 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
231 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
233 MPI2_CONFIG_PAGE_HEADER Struct;
237 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
238 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
240 /* Extended Config Page Header */
241 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
243 U8 PageVersion; /* 0x00 */
244 U8 Reserved1; /* 0x01 */
245 U8 PageNumber; /* 0x02 */
246 U8 PageType; /* 0x03 */
247 U16 ExtPageLength; /* 0x04 */
248 U8 ExtPageType; /* 0x06 */
249 U8 Reserved2; /* 0x07 */
250 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
251 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
252 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
254 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
256 MPI2_CONFIG_PAGE_HEADER Struct;
257 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
261 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
262 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
265 /* PageType field values */
266 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
267 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
268 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
269 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
271 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
272 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
273 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
274 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
275 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
276 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
277 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
278 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
280 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
283 /* ExtPageType field values */
284 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
285 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
286 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
287 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
288 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
289 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
290 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
291 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
292 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
293 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
294 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
297 /*****************************************************************************
298 * PageAddress defines
299 *****************************************************************************/
301 /* RAID Volume PageAddress format */
302 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
303 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
304 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
306 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
309 /* RAID Physical Disk PageAddress format */
310 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
311 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
312 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
313 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
315 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
316 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
319 /* SAS Expander PageAddress format */
320 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
321 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
322 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
323 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
325 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
326 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
327 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
330 /* SAS Device PageAddress format */
331 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
332 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
333 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
335 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
338 /* SAS PHY PageAddress format */
339 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
340 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
341 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
343 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
344 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
347 /* SAS Port PageAddress format */
348 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
349 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
350 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
352 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
355 /* SAS Enclosure PageAddress format */
356 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
357 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
358 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
360 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
363 /* RAID Configuration PageAddress format */
364 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
365 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
366 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
367 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
369 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
372 /* Driver Persistent Mapping PageAddress format */
373 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
374 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
376 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
377 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
378 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
381 /* Ethernet PageAddress format */
382 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
383 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
385 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
389 /****************************************************************************
390 * Configuration messages
391 ****************************************************************************/
393 /* Configuration Request Message */
394 typedef struct _MPI2_CONFIG_REQUEST
396 U8 Action; /* 0x00 */
397 U8 SGLFlags; /* 0x01 */
398 U8 ChainOffset; /* 0x02 */
399 U8 Function; /* 0x03 */
400 U16 ExtPageLength; /* 0x04 */
401 U8 ExtPageType; /* 0x06 */
402 U8 MsgFlags; /* 0x07 */
405 U16 Reserved1; /* 0x0A */
406 U8 Reserved2; /* 0x0C */
407 U8 ProxyVF_ID; /* 0x0D */
408 U16 Reserved4; /* 0x0E */
409 U32 Reserved3; /* 0x10 */
410 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
411 U32 PageAddress; /* 0x18 */
412 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
413 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
414 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
416 /* values for the Action field */
417 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
418 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
419 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
420 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
421 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
422 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
423 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
424 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
426 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
429 /* Config Reply Message */
430 typedef struct _MPI2_CONFIG_REPLY
432 U8 Action; /* 0x00 */
433 U8 SGLFlags; /* 0x01 */
434 U8 MsgLength; /* 0x02 */
435 U8 Function; /* 0x03 */
436 U16 ExtPageLength; /* 0x04 */
437 U8 ExtPageType; /* 0x06 */
438 U8 MsgFlags; /* 0x07 */
441 U16 Reserved1; /* 0x0A */
442 U16 Reserved2; /* 0x0C */
443 U16 IOCStatus; /* 0x0E */
444 U32 IOCLogInfo; /* 0x10 */
445 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
446 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
447 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
451 /*****************************************************************************
453 * C o n f i g u r a t i o n P a g e s
455 *****************************************************************************/
457 /****************************************************************************
458 * Manufacturing Config pages
459 ****************************************************************************/
461 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
463 /* MPI v2.0 SAS products */
464 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
465 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
466 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
467 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
468 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
469 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
470 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
472 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
474 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
475 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
476 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
477 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
478 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
479 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
480 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
481 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
482 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
484 /* MPI v2.5 SAS products */
485 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
486 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
487 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
488 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
489 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
490 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
495 /* Manufacturing Page 0 */
497 typedef struct _MPI2_CONFIG_PAGE_MAN_0
499 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
500 U8 ChipName[16]; /* 0x04 */
501 U8 ChipRevision[8]; /* 0x14 */
502 U8 BoardName[16]; /* 0x1C */
503 U8 BoardAssembly[16]; /* 0x2C */
504 U8 BoardTracerNumber[16]; /* 0x3C */
505 } MPI2_CONFIG_PAGE_MAN_0,
506 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
507 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
509 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
512 /* Manufacturing Page 1 */
514 typedef struct _MPI2_CONFIG_PAGE_MAN_1
516 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
517 U8 VPD[256]; /* 0x04 */
518 } MPI2_CONFIG_PAGE_MAN_1,
519 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
520 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
522 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
525 typedef struct _MPI2_CHIP_REVISION_ID
527 U16 DeviceID; /* 0x00 */
528 U8 PCIRevisionID; /* 0x02 */
529 U8 Reserved; /* 0x03 */
530 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
531 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
534 /* Manufacturing Page 2 */
537 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
538 * one and check Header.PageLength at runtime.
540 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
541 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
544 typedef struct _MPI2_CONFIG_PAGE_MAN_2
546 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
547 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
548 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
549 } MPI2_CONFIG_PAGE_MAN_2,
550 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
551 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
553 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
556 /* Manufacturing Page 3 */
559 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
560 * one and check Header.PageLength at runtime.
562 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
563 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
566 typedef struct _MPI2_CONFIG_PAGE_MAN_3
568 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
569 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
570 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
571 } MPI2_CONFIG_PAGE_MAN_3,
572 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
573 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
575 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
578 /* Manufacturing Page 4 */
580 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
582 U8 PowerSaveFlags; /* 0x00 */
583 U8 InternalOperationsSleepTime; /* 0x01 */
584 U8 InternalOperationsRunTime; /* 0x02 */
585 U8 HostIdleTime; /* 0x03 */
586 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
587 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
588 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
590 /* defines for the PowerSaveFlags field */
591 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
592 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
593 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
594 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
596 typedef struct _MPI2_CONFIG_PAGE_MAN_4
598 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
599 U32 Reserved1; /* 0x04 */
600 U32 Flags; /* 0x08 */
601 U8 InquirySize; /* 0x0C */
602 U8 Reserved2; /* 0x0D */
603 U16 Reserved3; /* 0x0E */
604 U8 InquiryData[56]; /* 0x10 */
605 U32 RAID0VolumeSettings; /* 0x48 */
606 U32 RAID1EVolumeSettings; /* 0x4C */
607 U32 RAID1VolumeSettings; /* 0x50 */
608 U32 RAID10VolumeSettings; /* 0x54 */
609 U32 Reserved4; /* 0x58 */
610 U32 Reserved5; /* 0x5C */
611 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
612 U8 MaxOCEDisks; /* 0x64 */
613 U8 ResyncRate; /* 0x65 */
614 U16 DataScrubDuration; /* 0x66 */
615 U8 MaxHotSpares; /* 0x68 */
616 U8 MaxPhysDisksPerVol; /* 0x69 */
617 U8 MaxPhysDisks; /* 0x6A */
618 U8 MaxVolumes; /* 0x6B */
619 } MPI2_CONFIG_PAGE_MAN_4,
620 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
621 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
623 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
625 /* Manufacturing Page 4 Flags field */
626 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
627 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
629 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
630 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
631 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
633 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
634 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
635 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
636 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
637 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
639 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
640 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
641 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
642 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
644 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
645 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
646 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
647 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
648 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
649 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
650 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
651 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
654 /* Manufacturing Page 5 */
657 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
658 * one and check the value returned for NumPhys at runtime.
660 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
661 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
664 typedef struct _MPI2_MANUFACTURING5_ENTRY
667 U64 DeviceName; /* 0x08 */
668 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
669 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
671 typedef struct _MPI2_CONFIG_PAGE_MAN_5
673 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
674 U8 NumPhys; /* 0x04 */
675 U8 Reserved1; /* 0x05 */
676 U16 Reserved2; /* 0x06 */
677 U32 Reserved3; /* 0x08 */
678 U32 Reserved4; /* 0x0C */
679 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
680 } MPI2_CONFIG_PAGE_MAN_5,
681 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
682 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
684 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
687 /* Manufacturing Page 6 */
689 typedef struct _MPI2_CONFIG_PAGE_MAN_6
691 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
692 U32 ProductSpecificInfo;/* 0x04 */
693 } MPI2_CONFIG_PAGE_MAN_6,
694 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
695 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
697 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
700 /* Manufacturing Page 7 */
702 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
704 U32 Pinout; /* 0x00 */
705 U8 Connector[16]; /* 0x04 */
706 U8 Location; /* 0x14 */
707 U8 ReceptacleID; /* 0x15 */
709 U32 Reserved2; /* 0x18 */
710 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
711 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
713 /* defines for the Pinout field */
714 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
715 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
717 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
718 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
719 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
720 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
721 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
722 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
723 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
724 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
725 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
726 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
727 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
728 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
729 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
730 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
731 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
733 /* defines for the Location field */
734 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
735 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
736 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
737 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
738 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
739 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
740 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
743 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
744 * one and check the value returned for NumPhys at runtime.
746 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
747 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
750 typedef struct _MPI2_CONFIG_PAGE_MAN_7
752 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
753 U32 Reserved1; /* 0x04 */
754 U32 Reserved2; /* 0x08 */
755 U32 Flags; /* 0x0C */
756 U8 EnclosureName[16]; /* 0x10 */
757 U8 NumPhys; /* 0x20 */
758 U8 Reserved3; /* 0x21 */
759 U16 Reserved4; /* 0x22 */
760 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
761 } MPI2_CONFIG_PAGE_MAN_7,
762 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
763 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
765 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
767 /* defines for the Flags field */
768 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
769 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
770 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
774 * Generic structure to use for product-specific manufacturing pages
775 * (currently Manufacturing Page 8 through Manufacturing Page 31).
778 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
780 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
781 U32 ProductSpecificInfo;/* 0x04 */
782 } MPI2_CONFIG_PAGE_MAN_PS,
783 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
784 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
786 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
787 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
788 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
789 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
790 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
791 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
792 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
793 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
794 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
795 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
796 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
797 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
798 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
799 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
800 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
801 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
802 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
803 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
804 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
805 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
806 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
807 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
808 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
809 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
812 /****************************************************************************
813 * IO Unit Config Pages
814 ****************************************************************************/
818 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
820 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
821 U64 UniqueValue; /* 0x04 */
822 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
823 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
824 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
825 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
827 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
832 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
834 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
835 U32 Flags; /* 0x04 */
836 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
837 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
839 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
841 /* IO Unit Page 1 Flags defines */
842 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
843 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
844 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
845 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
846 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
847 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
848 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
849 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
850 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
851 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
852 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
853 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
854 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
860 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
861 * one and check the value returned for GPIOCount at runtime.
863 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
864 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
867 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
869 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
870 U8 GPIOCount; /* 0x04 */
871 U8 Reserved1; /* 0x05 */
872 U16 Reserved2; /* 0x06 */
873 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
874 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
875 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
877 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
879 /* defines for IO Unit Page 3 GPIOVal field */
880 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
881 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
882 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
883 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
889 * Upper layer code (drivers, utilities, etc.) should leave this define set to
890 * one and check the value returned for NumDmaEngines at runtime.
892 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
893 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
896 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
898 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
899 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
900 U64 RaidAcceleratorBufferSize; /* 0x0C */
901 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
902 U8 RAControlSize; /* 0x1C */
903 U8 NumDmaEngines; /* 0x1D */
904 U8 RAMinControlSize; /* 0x1E */
905 U8 RAMaxControlSize; /* 0x1F */
906 U32 Reserved1; /* 0x20 */
907 U32 Reserved2; /* 0x24 */
908 U32 Reserved3; /* 0x28 */
909 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
910 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
911 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
913 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
915 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
916 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
917 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
919 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
920 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
921 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
922 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
927 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
929 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
930 U16 Flags; /* 0x04 */
931 U8 RAHostControlSize; /* 0x06 */
932 U8 Reserved0; /* 0x07 */
933 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
934 U32 Reserved1; /* 0x10 */
935 U32 Reserved2; /* 0x14 */
936 U32 Reserved3; /* 0x18 */
937 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
938 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
940 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
942 /* defines for IO Unit Page 6 Flags field */
943 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
948 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
950 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
951 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */
952 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */
953 U8 PCIeWidth; /* 0x06 */
954 U8 PCIeSpeed; /* 0x07 */
955 U32 ProcessorState; /* 0x08 */
956 U32 PowerManagementCapabilities; /* 0x0C */
957 U16 IOCTemperature; /* 0x10 */
958 U8 IOCTemperatureUnits; /* 0x12 */
959 U8 IOCSpeed; /* 0x13 */
960 U16 BoardTemperature; /* 0x14 */
961 U8 BoardTemperatureUnits; /* 0x16 */
962 U8 Reserved3; /* 0x17 */
963 U32 Reserved4; /* 0x18 */
964 U32 Reserved5; /* 0x1C */
965 U32 Reserved6; /* 0x20 */
966 U32 Reserved7; /* 0x24 */
967 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
968 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
970 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04)
972 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
973 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
974 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
975 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
976 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
977 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
979 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
980 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
981 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
982 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
983 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
984 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
987 /* defines for IO Unit Page 7 PCIeWidth field */
988 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
989 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
990 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
991 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
993 /* defines for IO Unit Page 7 PCIeSpeed field */
994 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
995 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
996 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
998 /* defines for IO Unit Page 7 ProcessorState field */
999 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
1000 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
1002 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
1003 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
1004 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
1006 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
1007 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
1008 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
1009 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
1010 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
1011 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
1012 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
1013 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
1014 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
1015 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
1016 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
1017 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1018 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1019 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1020 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1021 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1022 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */
1023 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */
1024 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */
1025 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */
1027 /* obsolete names for the PowerManagementCapabilities bits (above) */
1028 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1029 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1030 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1031 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
1032 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
1035 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
1036 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1037 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1038 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1040 /* defines for IO Unit Page 7 IOCSpeed field */
1041 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1042 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1043 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1044 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1046 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
1047 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1048 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1049 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1052 /* IO Unit Page 8 */
1054 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1056 typedef struct _MPI2_IOUNIT8_SENSOR
1058 U16 Flags; /* 0x00 */
1059 U16 Reserved1; /* 0x02 */
1060 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
1061 U32 Reserved2; /* 0x0C */
1062 U32 Reserved3; /* 0x10 */
1063 U32 Reserved4; /* 0x14 */
1064 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
1065 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
1067 /* defines for IO Unit Page 8 Sensor Flags field */
1068 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1069 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1070 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1071 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1074 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1075 * one and check the value returned for NumSensors at runtime.
1077 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1078 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
1081 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8
1083 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1084 U32 Reserved1; /* 0x04 */
1085 U32 Reserved2; /* 0x08 */
1086 U8 NumSensors; /* 0x0C */
1087 U8 PollingInterval; /* 0x0D */
1088 U16 Reserved3; /* 0x0E */
1089 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1090 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1091 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1093 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1096 /* IO Unit Page 9 */
1098 typedef struct _MPI2_IOUNIT9_SENSOR
1100 U16 CurrentTemperature; /* 0x00 */
1101 U16 Reserved1; /* 0x02 */
1102 U8 Flags; /* 0x04 */
1103 U8 Reserved2; /* 0x05 */
1104 U16 Reserved3; /* 0x06 */
1105 U32 Reserved4; /* 0x08 */
1106 U32 Reserved5; /* 0x0C */
1107 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1108 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1110 /* defines for IO Unit Page 9 Sensor Flags field */
1111 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1114 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1115 * one and check the value returned for NumSensors at runtime.
1117 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1118 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1121 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9
1123 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1124 U32 Reserved1; /* 0x04 */
1125 U32 Reserved2; /* 0x08 */
1126 U8 NumSensors; /* 0x0C */
1127 U8 Reserved4; /* 0x0D */
1128 U16 Reserved3; /* 0x0E */
1129 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1130 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1131 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1133 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1136 /* IO Unit Page 10 */
1138 typedef struct _MPI2_IOUNIT10_FUNCTION
1140 U8 CreditPercent; /* 0x00 */
1141 U8 Reserved1; /* 0x01 */
1142 U16 Reserved2; /* 0x02 */
1143 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1144 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1147 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1148 * one and check the value returned for NumFunctions at runtime.
1150 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1151 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1154 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10
1156 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1157 U8 NumFunctions; /* 0x04 */
1158 U8 Reserved1; /* 0x05 */
1159 U16 Reserved2; /* 0x06 */
1160 U32 Reserved3; /* 0x08 */
1161 U32 Reserved4; /* 0x0C */
1162 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */
1163 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1164 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1166 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1170 /****************************************************************************
1172 ****************************************************************************/
1176 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1178 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1179 U32 Reserved1; /* 0x04 */
1180 U32 Reserved2; /* 0x08 */
1181 U16 VendorID; /* 0x0C */
1182 U16 DeviceID; /* 0x0E */
1183 U8 RevisionID; /* 0x10 */
1184 U8 Reserved3; /* 0x11 */
1185 U16 Reserved4; /* 0x12 */
1186 U32 ClassCode; /* 0x14 */
1187 U16 SubsystemVendorID; /* 0x18 */
1188 U16 SubsystemID; /* 0x1A */
1189 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1190 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1192 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1197 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1199 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1200 U32 Flags; /* 0x04 */
1201 U32 CoalescingTimeout; /* 0x08 */
1202 U8 CoalescingDepth; /* 0x0C */
1203 U8 PCISlotNum; /* 0x0D */
1204 U8 PCIBusNum; /* 0x0E */
1205 U8 PCIDomainSegment; /* 0x0F */
1206 U32 Reserved1; /* 0x10 */
1207 U32 Reserved2; /* 0x14 */
1208 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1209 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1211 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1213 /* defines for IOC Page 1 Flags field */
1214 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1216 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1217 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1218 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1222 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1224 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1225 U32 CapabilitiesFlags; /* 0x04 */
1226 U8 MaxDrivesRAID0; /* 0x08 */
1227 U8 MaxDrivesRAID1; /* 0x09 */
1228 U8 MaxDrivesRAID1E; /* 0x0A */
1229 U8 MaxDrivesRAID10; /* 0x0B */
1230 U8 MinDrivesRAID0; /* 0x0C */
1231 U8 MinDrivesRAID1; /* 0x0D */
1232 U8 MinDrivesRAID1E; /* 0x0E */
1233 U8 MinDrivesRAID10; /* 0x0F */
1234 U32 Reserved1; /* 0x10 */
1235 U8 MaxGlobalHotSpares; /* 0x14 */
1236 U8 MaxPhysDisks; /* 0x15 */
1237 U8 MaxVolumes; /* 0x16 */
1238 U8 MaxConfigs; /* 0x17 */
1239 U8 MaxOCEDisks; /* 0x18 */
1240 U8 Reserved2; /* 0x19 */
1241 U16 Reserved3; /* 0x1A */
1242 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1243 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1244 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1245 U32 Reserved4; /* 0x28 */
1246 U32 Reserved5; /* 0x2C */
1247 U16 DefaultMetadataSize; /* 0x30 */
1248 U16 Reserved6; /* 0x32 */
1249 U16 MaxBadBlockTableEntries; /* 0x34 */
1250 U16 Reserved7; /* 0x36 */
1251 U32 IRNvsramVersion; /* 0x38 */
1252 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1253 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1255 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1257 /* defines for IOC Page 6 CapabilitiesFlags */
1258 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1259 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1260 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1261 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1262 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1263 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1268 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1270 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1272 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1273 U32 Reserved1; /* 0x04 */
1274 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1275 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1276 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1277 U32 Reserved3; /* 0x1C */
1278 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1279 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1281 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1286 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1288 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1289 U8 NumDevsPerEnclosure; /* 0x04 */
1290 U8 Reserved1; /* 0x05 */
1291 U16 Reserved2; /* 0x06 */
1292 U16 MaxPersistentEntries; /* 0x08 */
1293 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1294 U16 Flags; /* 0x0C */
1295 U16 Reserved3; /* 0x0E */
1296 U16 IRVolumeMappingFlags; /* 0x10 */
1297 U16 Reserved4; /* 0x12 */
1298 U32 Reserved5; /* 0x14 */
1299 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1300 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1302 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1304 /* defines for IOC Page 8 Flags field */
1305 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1306 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1308 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1309 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1310 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1312 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1313 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1315 /* defines for IOC Page 8 IRVolumeMappingFlags */
1316 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1317 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1318 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1321 /****************************************************************************
1323 ****************************************************************************/
1327 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1329 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1330 U32 BiosOptions; /* 0x04 */
1331 U32 IOCSettings; /* 0x08 */
1332 U32 Reserved1; /* 0x0C */
1333 U32 DeviceSettings; /* 0x10 */
1334 U16 NumberOfDevices; /* 0x14 */
1335 U16 UEFIVersion; /* 0x16 */
1336 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1337 U16 IOTimeoutSequential; /* 0x1A */
1338 U16 IOTimeoutOther; /* 0x1C */
1339 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1340 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1341 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1343 #define MPI2_BIOSPAGE1_PAGEVERSION (0x05)
1345 /* values for BIOS Page 1 BiosOptions field */
1346 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1347 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1349 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1350 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1351 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1352 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1354 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1356 /* values for BIOS Page 1 IOCSettings field */
1357 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1358 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1359 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1361 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1362 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1363 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1364 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1366 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1367 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1368 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1369 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1370 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1372 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1374 /* values for BIOS Page 1 DeviceSettings field */
1375 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1376 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1377 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1378 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1379 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1381 /* defines for BIOS Page 1 UEFIVersion field */
1382 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1383 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1384 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1385 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1391 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1393 U32 Reserved1; /* 0x00 */
1394 U32 Reserved2; /* 0x04 */
1395 U32 Reserved3; /* 0x08 */
1396 U32 Reserved4; /* 0x0C */
1397 U32 Reserved5; /* 0x10 */
1398 U32 Reserved6; /* 0x14 */
1399 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1400 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1401 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1403 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1405 U64 SASAddress; /* 0x00 */
1406 U8 LUN[8]; /* 0x08 */
1407 U32 Reserved1; /* 0x10 */
1408 U32 Reserved2; /* 0x14 */
1409 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1410 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1412 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1414 U64 EnclosureLogicalID; /* 0x00 */
1415 U32 Reserved1; /* 0x08 */
1416 U32 Reserved2; /* 0x0C */
1417 U16 SlotNumber; /* 0x10 */
1418 U16 Reserved3; /* 0x12 */
1419 U32 Reserved4; /* 0x14 */
1420 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1421 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1422 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1424 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1426 U64 DeviceName; /* 0x00 */
1427 U8 LUN[8]; /* 0x08 */
1428 U32 Reserved1; /* 0x10 */
1429 U32 Reserved2; /* 0x14 */
1430 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1431 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1433 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1435 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1436 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1437 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1438 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1439 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1440 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1442 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1444 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1445 U32 Reserved1; /* 0x04 */
1446 U32 Reserved2; /* 0x08 */
1447 U32 Reserved3; /* 0x0C */
1448 U32 Reserved4; /* 0x10 */
1449 U32 Reserved5; /* 0x14 */
1450 U32 Reserved6; /* 0x18 */
1451 U8 ReqBootDeviceForm; /* 0x1C */
1452 U8 Reserved7; /* 0x1D */
1453 U16 Reserved8; /* 0x1E */
1454 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1455 U8 ReqAltBootDeviceForm; /* 0x38 */
1456 U8 Reserved9; /* 0x39 */
1457 U16 Reserved10; /* 0x3A */
1458 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1459 U8 CurrentBootDeviceForm; /* 0x58 */
1460 U8 Reserved11; /* 0x59 */
1461 U16 Reserved12; /* 0x5A */
1462 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1463 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1464 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1466 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1468 /* values for BIOS Page 2 BootDeviceForm fields */
1469 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1470 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1471 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1472 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1473 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1478 typedef struct _MPI2_ADAPTER_INFO
1480 U8 PciBusNumber; /* 0x00 */
1481 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1482 U16 AdapterFlags; /* 0x02 */
1483 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1484 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1486 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1487 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1489 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1491 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1492 U32 GlobalFlags; /* 0x04 */
1493 U32 BiosVersion; /* 0x08 */
1494 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1495 U32 Reserved1; /* 0x1C */
1496 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1497 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1499 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1501 /* values for BIOS Page 3 GlobalFlags */
1502 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1503 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1504 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1506 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1507 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1508 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1509 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1515 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1516 * one and check the value returned for NumPhys at runtime.
1518 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1519 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1522 typedef struct _MPI2_BIOS4_ENTRY
1524 U64 ReassignmentWWID; /* 0x00 */
1525 U64 ReassignmentDeviceName; /* 0x08 */
1526 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1527 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1529 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1531 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1532 U8 NumPhys; /* 0x04 */
1533 U8 Reserved1; /* 0x05 */
1534 U16 Reserved2; /* 0x06 */
1535 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1536 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1537 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1539 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1542 /****************************************************************************
1543 * RAID Volume Config Pages
1544 ****************************************************************************/
1546 /* RAID Volume Page 0 */
1548 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1550 U8 RAIDSetNum; /* 0x00 */
1551 U8 PhysDiskMap; /* 0x01 */
1552 U8 PhysDiskNum; /* 0x02 */
1553 U8 Reserved; /* 0x03 */
1554 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1555 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1557 /* defines for the PhysDiskMap field */
1558 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1559 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1561 typedef struct _MPI2_RAIDVOL0_SETTINGS
1563 U16 Settings; /* 0x00 */
1564 U8 HotSparePool; /* 0x01 */
1565 U8 Reserved; /* 0x02 */
1566 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1567 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1569 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1570 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1571 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1572 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1573 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1574 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1575 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1576 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1577 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1579 /* RAID Volume Page 0 VolumeSettings defines */
1580 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1581 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1583 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1584 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1585 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1586 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1589 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1590 * one and check the value returned for NumPhysDisks at runtime.
1592 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1593 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1596 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1598 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1599 U16 DevHandle; /* 0x04 */
1600 U8 VolumeState; /* 0x06 */
1601 U8 VolumeType; /* 0x07 */
1602 U32 VolumeStatusFlags; /* 0x08 */
1603 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1604 U64 MaxLBA; /* 0x10 */
1605 U32 StripeSize; /* 0x18 */
1606 U16 BlockSize; /* 0x1C */
1607 U16 Reserved1; /* 0x1E */
1608 U8 SupportedPhysDisks; /* 0x20 */
1609 U8 ResyncRate; /* 0x21 */
1610 U16 DataScrubDuration; /* 0x22 */
1611 U8 NumPhysDisks; /* 0x24 */
1612 U8 Reserved2; /* 0x25 */
1613 U8 Reserved3; /* 0x26 */
1614 U8 InactiveStatus; /* 0x27 */
1615 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1616 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1617 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1619 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1621 /* values for RAID VolumeState */
1622 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1623 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1624 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1625 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1626 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1627 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1629 /* values for RAID VolumeType */
1630 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1631 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1632 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1633 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1634 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1636 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1637 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1638 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1639 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1640 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1641 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1642 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1643 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1644 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1645 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1646 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1647 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1648 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1649 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1650 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1651 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1652 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1653 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1654 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1655 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1657 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1658 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1659 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1660 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1661 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1663 /* values for RAID Volume Page 0 InactiveStatus field */
1664 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1665 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1666 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1667 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1668 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1669 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1670 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1673 /* RAID Volume Page 1 */
1675 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1677 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1678 U16 DevHandle; /* 0x04 */
1679 U16 Reserved0; /* 0x06 */
1680 U8 GUID[24]; /* 0x08 */
1681 U8 Name[16]; /* 0x20 */
1682 U64 WWID; /* 0x30 */
1683 U32 Reserved1; /* 0x38 */
1684 U32 Reserved2; /* 0x3C */
1685 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1686 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1688 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1691 /****************************************************************************
1692 * RAID Physical Disk Config Pages
1693 ****************************************************************************/
1695 /* RAID Physical Disk Page 0 */
1697 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1699 U16 Reserved1; /* 0x00 */
1700 U8 HotSparePool; /* 0x02 */
1701 U8 Reserved2; /* 0x03 */
1702 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1703 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1705 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1707 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1709 U8 VendorID[8]; /* 0x00 */
1710 U8 ProductID[16]; /* 0x08 */
1711 U8 ProductRevLevel[4]; /* 0x18 */
1712 U8 SerialNum[32]; /* 0x1C */
1713 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1714 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1715 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1717 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1719 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1720 U16 DevHandle; /* 0x04 */
1721 U8 Reserved1; /* 0x06 */
1722 U8 PhysDiskNum; /* 0x07 */
1723 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1724 U32 Reserved2; /* 0x0C */
1725 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1726 U32 Reserved3; /* 0x4C */
1727 U8 PhysDiskState; /* 0x50 */
1728 U8 OfflineReason; /* 0x51 */
1729 U8 IncompatibleReason; /* 0x52 */
1730 U8 PhysDiskAttributes; /* 0x53 */
1731 U32 PhysDiskStatusFlags; /* 0x54 */
1732 U64 DeviceMaxLBA; /* 0x58 */
1733 U64 HostMaxLBA; /* 0x60 */
1734 U64 CoercedMaxLBA; /* 0x68 */
1735 U16 BlockSize; /* 0x70 */
1736 U16 Reserved5; /* 0x72 */
1737 U32 Reserved6; /* 0x74 */
1738 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1739 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1740 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1742 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1744 /* PhysDiskState defines */
1745 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1746 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1747 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1748 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1749 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1750 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1751 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1752 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1754 /* OfflineReason defines */
1755 #define MPI2_PHYSDISK0_ONLINE (0x00)
1756 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1757 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1758 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1759 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1760 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1761 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1763 /* IncompatibleReason defines */
1764 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1765 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1766 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1767 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1768 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1769 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1770 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1771 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1773 /* PhysDiskAttributes defines */
1774 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1775 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1776 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1778 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1779 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1780 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1782 /* PhysDiskStatusFlags defines */
1783 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1784 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1785 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1786 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1787 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1788 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1789 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1790 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1793 /* RAID Physical Disk Page 1 */
1796 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1797 * one and check the value returned for NumPhysDiskPaths at runtime.
1799 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1800 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1803 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1805 U16 DevHandle; /* 0x00 */
1806 U16 Reserved1; /* 0x02 */
1807 U64 WWID; /* 0x04 */
1808 U64 OwnerWWID; /* 0x0C */
1809 U8 OwnerIdentifier; /* 0x14 */
1810 U8 Reserved2; /* 0x15 */
1811 U16 Flags; /* 0x16 */
1812 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1813 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1815 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1816 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1817 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1818 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1820 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1822 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1823 U8 NumPhysDiskPaths; /* 0x04 */
1824 U8 PhysDiskNum; /* 0x05 */
1825 U16 Reserved1; /* 0x06 */
1826 U32 Reserved2; /* 0x08 */
1827 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1828 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1829 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1830 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1832 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1835 /****************************************************************************
1836 * values for fields used by several types of SAS Config Pages
1837 ****************************************************************************/
1839 /* values for NegotiatedLinkRates fields */
1840 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1841 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1842 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1843 /* link rates used for Negotiated Physical and Logical Link Rate */
1844 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1845 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1846 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1847 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1848 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1849 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1850 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1851 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1852 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1853 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1854 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1857 /* values for AttachedPhyInfo fields */
1858 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1859 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1860 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1862 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1863 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1864 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1865 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1866 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1867 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1868 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1869 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1870 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1871 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1874 /* values for PhyInfo fields */
1875 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1877 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1878 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1879 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1880 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1881 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1883 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1884 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1885 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1886 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1887 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1888 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1890 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1891 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1892 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1893 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1894 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1895 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1896 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1897 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1898 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1899 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1901 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1902 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1903 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1904 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1906 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1907 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1909 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1910 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1911 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1912 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1915 /* values for SAS ProgrammedLinkRate fields */
1916 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1917 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1918 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1919 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1920 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1921 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
1922 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1923 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1924 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1925 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1926 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1927 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1930 /* values for SAS HwLinkRate fields */
1931 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1932 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1933 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1934 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1935 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
1936 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1937 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1938 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1939 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1940 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1944 /****************************************************************************
1945 * SAS IO Unit Config Pages
1946 ****************************************************************************/
1948 /* SAS IO Unit Page 0 */
1950 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1953 U8 PortFlags; /* 0x01 */
1954 U8 PhyFlags; /* 0x02 */
1955 U8 NegotiatedLinkRate; /* 0x03 */
1956 U32 ControllerPhyDeviceInfo;/* 0x04 */
1957 U16 AttachedDevHandle; /* 0x08 */
1958 U16 ControllerDevHandle; /* 0x0A */
1959 U32 DiscoveryStatus; /* 0x0C */
1960 U32 Reserved; /* 0x10 */
1961 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1962 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1965 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1966 * one and check the value returned for NumPhys at runtime.
1968 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1969 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1972 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1974 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1975 U32 Reserved1; /* 0x08 */
1976 U8 NumPhys; /* 0x0C */
1977 U8 Reserved2; /* 0x0D */
1978 U16 Reserved3; /* 0x0E */
1979 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1980 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1981 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1982 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1984 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1986 /* values for SAS IO Unit Page 0 PortFlags */
1987 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1988 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1990 /* values for SAS IO Unit Page 0 PhyFlags */
1991 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1992 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1994 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1996 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1998 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1999 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2000 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2001 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2002 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2003 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2004 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2005 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2006 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2007 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2008 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2009 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2010 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2011 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2012 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2013 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2014 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2015 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2016 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2017 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2018 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2021 /* SAS IO Unit Page 1 */
2023 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
2026 U8 PortFlags; /* 0x01 */
2027 U8 PhyFlags; /* 0x02 */
2028 U8 MaxMinLinkRate; /* 0x03 */
2029 U32 ControllerPhyDeviceInfo; /* 0x04 */
2030 U16 MaxTargetPortConnectTime; /* 0x08 */
2031 U16 Reserved1; /* 0x0A */
2032 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2033 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
2036 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2037 * one and check the value returned for NumPhys at runtime.
2039 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2040 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
2043 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
2045 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2046 U16 ControlFlags; /* 0x08 */
2047 U16 SASNarrowMaxQueueDepth; /* 0x0A */
2048 U16 AdditionalControlFlags; /* 0x0C */
2049 U16 SASWideMaxQueueDepth; /* 0x0E */
2050 U8 NumPhys; /* 0x10 */
2051 U8 SATAMaxQDepth; /* 0x11 */
2052 U8 ReportDeviceMissingDelay; /* 0x12 */
2053 U8 IODeviceMissingDelay; /* 0x13 */
2054 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
2055 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2056 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2057 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
2059 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2061 /* values for SAS IO Unit Page 1 ControlFlags */
2062 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2063 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2064 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2065 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2067 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2068 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2069 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2070 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2071 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2073 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2074 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2075 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2076 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2077 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2078 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2079 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2080 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2082 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2083 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2084 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2085 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2086 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2087 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2088 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2089 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2090 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2092 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2093 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2094 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2096 /* values for SAS IO Unit Page 1 PortFlags */
2097 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2099 /* values for SAS IO Unit Page 1 PhyFlags */
2100 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2101 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2103 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
2104 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2105 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2106 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2107 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2108 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2109 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2110 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2111 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2112 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2113 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2115 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2118 /* SAS IO Unit Page 4 */
2120 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2122 U8 MaxTargetSpinup; /* 0x00 */
2123 U8 SpinupDelay; /* 0x01 */
2124 U8 SpinupFlags; /* 0x02 */
2125 U8 Reserved1; /* 0x03 */
2126 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2127 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2129 /* defines for SAS IO Unit Page 4 SpinupFlags */
2130 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2134 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2135 * one and check the value returned for NumPhys at runtime.
2137 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2138 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2141 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2143 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2144 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2145 U32 Reserved1; /* 0x18 */
2146 U32 Reserved2; /* 0x1C */
2147 U32 Reserved3; /* 0x20 */
2148 U8 BootDeviceWaitTime; /* 0x24 */
2149 U8 Reserved4; /* 0x25 */
2150 U16 Reserved5; /* 0x26 */
2151 U8 NumPhys; /* 0x28 */
2152 U8 PEInitialSpinupDelay; /* 0x29 */
2153 U8 PEReplyDelay; /* 0x2A */
2154 U8 Flags; /* 0x2B */
2155 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2156 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2157 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2158 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2160 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2162 /* defines for Flags field */
2163 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2165 /* defines for PHY field */
2166 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2169 /* SAS IO Unit Page 5 */
2171 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2173 U8 ControlFlags; /* 0x00 */
2174 U8 PortWidthModGroup; /* 0x01 */
2175 U16 InactivityTimerExponent; /* 0x02 */
2176 U8 SATAPartialTimeout; /* 0x04 */
2177 U8 Reserved2; /* 0x05 */
2178 U8 SATASlumberTimeout; /* 0x06 */
2179 U8 Reserved3; /* 0x07 */
2180 U8 SASPartialTimeout; /* 0x08 */
2181 U8 Reserved4; /* 0x09 */
2182 U8 SASSlumberTimeout; /* 0x0A */
2183 U8 Reserved5; /* 0x0B */
2184 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2185 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2186 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2188 /* defines for ControlFlags field */
2189 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2190 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2191 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2192 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2194 /* defines for PortWidthModeGroup field */
2195 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2197 /* defines for InactivityTimerExponent field */
2198 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2199 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2200 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2201 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2202 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2203 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2204 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2205 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2207 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2208 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2209 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2210 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2211 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2212 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2213 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2214 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2217 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2218 * one and check the value returned for NumPhys at runtime.
2220 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2221 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2224 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2226 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2227 U8 NumPhys; /* 0x08 */
2228 U8 Reserved1; /* 0x09 */
2229 U16 Reserved2; /* 0x0A */
2230 U32 Reserved3; /* 0x0C */
2231 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2232 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2233 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2234 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2236 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2239 /* SAS IO Unit Page 6 */
2241 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2243 U8 CurrentStatus; /* 0x00 */
2244 U8 CurrentModulation; /* 0x01 */
2245 U8 CurrentUtilization; /* 0x02 */
2246 U8 Reserved1; /* 0x03 */
2247 U32 Reserved2; /* 0x04 */
2248 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2249 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2250 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2251 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2253 /* defines for CurrentStatus field */
2254 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2255 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2256 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2257 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2258 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2259 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2260 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2261 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2263 /* defines for CurrentModulation field */
2264 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2265 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2266 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2267 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2270 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2271 * one and check the value returned for NumGroups at runtime.
2273 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2274 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2277 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2279 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2280 U32 Reserved1; /* 0x08 */
2281 U32 Reserved2; /* 0x0C */
2282 U8 NumGroups; /* 0x10 */
2283 U8 Reserved3; /* 0x11 */
2284 U16 Reserved4; /* 0x12 */
2285 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2286 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2287 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2288 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2289 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2291 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2294 /* SAS IO Unit Page 7 */
2296 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2298 U8 Flags; /* 0x00 */
2299 U8 Reserved1; /* 0x01 */
2300 U16 Reserved2; /* 0x02 */
2301 U8 Threshold75Pct; /* 0x04 */
2302 U8 Threshold50Pct; /* 0x05 */
2303 U8 Threshold25Pct; /* 0x06 */
2304 U8 Reserved3; /* 0x07 */
2305 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2306 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2307 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2308 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2310 /* defines for Flags field */
2311 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2315 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2316 * one and check the value returned for NumGroups at runtime.
2318 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2319 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2322 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2324 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2325 U8 SamplingInterval; /* 0x08 */
2326 U8 WindowLength; /* 0x09 */
2327 U16 Reserved1; /* 0x0A */
2328 U32 Reserved2; /* 0x0C */
2329 U32 Reserved3; /* 0x10 */
2330 U8 NumGroups; /* 0x14 */
2331 U8 Reserved4; /* 0x15 */
2332 U16 Reserved5; /* 0x16 */
2333 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2334 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2335 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2336 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2337 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2339 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2342 /* SAS IO Unit Page 8 */
2344 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2346 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2347 U32 Reserved1; /* 0x08 */
2348 U32 PowerManagementCapabilities; /* 0x0C */
2349 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */
2350 U8 Reserved2; /* 0x11 */
2351 U16 Reserved3; /* 0x12 */
2352 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2353 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2354 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2356 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2358 /* defines for PowerManagementCapabilities field */
2359 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2360 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2361 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2362 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2363 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2364 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2365 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2366 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2367 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2368 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2370 /* defines for TxRxSleepStatus field */
2371 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2372 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2373 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2374 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2378 /* SAS IO Unit Page 16 */
2380 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16
2382 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2383 U64 TimeStamp; /* 0x08 */
2384 U32 Reserved1; /* 0x10 */
2385 U32 Reserved2; /* 0x14 */
2386 U32 FastPathPendedRequests; /* 0x18 */
2387 U32 FastPathUnPendedRequests; /* 0x1C */
2388 U32 FastPathHostRequestStarts; /* 0x20 */
2389 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2390 U32 FastPathHostCompletions; /* 0x28 */
2391 U32 FastPathFirmwareCompletions; /* 0x2C */
2392 U32 NonFastPathRequestStarts; /* 0x30 */
2393 U32 NonFastPathHostCompletions; /* 0x30 */
2394 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2395 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2396 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2398 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2401 /****************************************************************************
2402 * SAS Expander Config Pages
2403 ****************************************************************************/
2405 /* SAS Expander Page 0 */
2407 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2409 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2410 U8 PhysicalPort; /* 0x08 */
2411 U8 ReportGenLength; /* 0x09 */
2412 U16 EnclosureHandle; /* 0x0A */
2413 U64 SASAddress; /* 0x0C */
2414 U32 DiscoveryStatus; /* 0x14 */
2415 U16 DevHandle; /* 0x18 */
2416 U16 ParentDevHandle; /* 0x1A */
2417 U16 ExpanderChangeCount; /* 0x1C */
2418 U16 ExpanderRouteIndexes; /* 0x1E */
2419 U8 NumPhys; /* 0x20 */
2420 U8 SASLevel; /* 0x21 */
2421 U16 Flags; /* 0x22 */
2422 U16 STPBusInactivityTimeLimit; /* 0x24 */
2423 U16 STPMaxConnectTimeLimit; /* 0x26 */
2424 U16 STP_SMP_NexusLossTime; /* 0x28 */
2425 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2426 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2427 U16 ZoneLockInactivityLimit; /* 0x34 */
2428 U16 Reserved1; /* 0x36 */
2429 U8 TimeToReducedFunc; /* 0x38 */
2430 U8 InitialTimeToReducedFunc; /* 0x39 */
2431 U8 MaxReducedFuncTime; /* 0x3A */
2432 U8 Reserved2; /* 0x3B */
2433 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2434 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2436 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2438 /* values for SAS Expander Page 0 DiscoveryStatus field */
2439 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2440 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2441 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2442 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2443 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2444 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2445 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2446 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2447 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2448 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2449 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2450 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2451 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2452 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2453 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2454 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2455 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2456 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2457 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2458 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2460 /* values for SAS Expander Page 0 Flags field */
2461 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2462 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2463 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2464 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2465 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2466 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2467 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2468 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2469 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2470 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2471 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2474 /* SAS Expander Page 1 */
2476 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2478 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2479 U8 PhysicalPort; /* 0x08 */
2480 U8 Reserved1; /* 0x09 */
2481 U16 Reserved2; /* 0x0A */
2482 U8 NumPhys; /* 0x0C */
2484 U16 NumTableEntriesProgrammed; /* 0x0E */
2485 U8 ProgrammedLinkRate; /* 0x10 */
2486 U8 HwLinkRate; /* 0x11 */
2487 U16 AttachedDevHandle; /* 0x12 */
2488 U32 PhyInfo; /* 0x14 */
2489 U32 AttachedDeviceInfo; /* 0x18 */
2490 U16 ExpanderDevHandle; /* 0x1C */
2491 U8 ChangeCount; /* 0x1E */
2492 U8 NegotiatedLinkRate; /* 0x1F */
2493 U8 PhyIdentifier; /* 0x20 */
2494 U8 AttachedPhyIdentifier; /* 0x21 */
2495 U8 Reserved3; /* 0x22 */
2496 U8 DiscoveryInfo; /* 0x23 */
2497 U32 AttachedPhyInfo; /* 0x24 */
2498 U8 ZoneGroup; /* 0x28 */
2499 U8 SelfConfigStatus; /* 0x29 */
2500 U16 Reserved4; /* 0x2A */
2501 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2502 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2504 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2506 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2508 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2510 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2512 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2514 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2516 /* values for SAS Expander Page 1 DiscoveryInfo field */
2517 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2518 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2519 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2521 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2524 /****************************************************************************
2525 * SAS Device Config Pages
2526 ****************************************************************************/
2528 /* SAS Device Page 0 */
2530 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2532 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2533 U16 Slot; /* 0x08 */
2534 U16 EnclosureHandle; /* 0x0A */
2535 U64 SASAddress; /* 0x0C */
2536 U16 ParentDevHandle; /* 0x14 */
2537 U8 PhyNum; /* 0x16 */
2538 U8 AccessStatus; /* 0x17 */
2539 U16 DevHandle; /* 0x18 */
2540 U8 AttachedPhyIdentifier; /* 0x1A */
2541 U8 ZoneGroup; /* 0x1B */
2542 U32 DeviceInfo; /* 0x1C */
2543 U16 Flags; /* 0x20 */
2544 U8 PhysicalPort; /* 0x22 */
2545 U8 MaxPortConnections; /* 0x23 */
2546 U64 DeviceName; /* 0x24 */
2547 U8 PortGroups; /* 0x2C */
2548 U8 DmaGroup; /* 0x2D */
2549 U8 ControlGroup; /* 0x2E */
2550 U8 EnclosureLevel; /* 0x2F */
2551 U8 ConnectorName[4]; /* 0x30 */
2552 U32 Reserved3; /* 0x34 */
2553 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2554 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2556 #define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2558 /* values for SAS Device Page 0 AccessStatus field */
2559 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2560 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2561 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2562 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2563 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2564 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2565 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2566 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2567 /* specific values for SATA Init failures */
2568 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2569 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2570 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2571 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2572 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2573 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2574 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2575 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2576 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2577 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2578 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2580 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2582 /* values for SAS Device Page 0 Flags field */
2583 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2584 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2585 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2586 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2587 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2588 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2589 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2590 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2591 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2592 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2593 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2594 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2595 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2596 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2597 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2600 /* SAS Device Page 1 */
2602 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2604 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2605 U32 Reserved1; /* 0x08 */
2606 U64 SASAddress; /* 0x0C */
2607 U32 Reserved2; /* 0x14 */
2608 U16 DevHandle; /* 0x18 */
2609 U16 Reserved3; /* 0x1A */
2610 U8 InitialRegDeviceFIS[20];/* 0x1C */
2611 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2612 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2614 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2617 /****************************************************************************
2618 * SAS PHY Config Pages
2619 ****************************************************************************/
2621 /* SAS PHY Page 0 */
2623 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2625 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2626 U16 OwnerDevHandle; /* 0x08 */
2627 U16 Reserved1; /* 0x0A */
2628 U16 AttachedDevHandle; /* 0x0C */
2629 U8 AttachedPhyIdentifier; /* 0x0E */
2630 U8 Reserved2; /* 0x0F */
2631 U32 AttachedPhyInfo; /* 0x10 */
2632 U8 ProgrammedLinkRate; /* 0x14 */
2633 U8 HwLinkRate; /* 0x15 */
2634 U8 ChangeCount; /* 0x16 */
2635 U8 Flags; /* 0x17 */
2636 U32 PhyInfo; /* 0x18 */
2637 U8 NegotiatedLinkRate; /* 0x1C */
2638 U8 Reserved3; /* 0x1D */
2639 U16 Reserved4; /* 0x1E */
2640 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2641 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2643 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2645 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2647 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2649 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2651 /* values for SAS PHY Page 0 Flags field */
2652 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2654 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2656 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2659 /* SAS PHY Page 1 */
2661 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2663 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2664 U32 Reserved1; /* 0x08 */
2665 U32 InvalidDwordCount; /* 0x0C */
2666 U32 RunningDisparityErrorCount; /* 0x10 */
2667 U32 LossDwordSynchCount; /* 0x14 */
2668 U32 PhyResetProblemCount; /* 0x18 */
2669 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2670 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2672 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2675 /* SAS PHY Page 2 */
2677 typedef struct _MPI2_SASPHY2_PHY_EVENT
2679 U8 PhyEventCode; /* 0x00 */
2680 U8 Reserved1; /* 0x01 */
2681 U16 Reserved2; /* 0x02 */
2682 U32 PhyEventInfo; /* 0x04 */
2683 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2684 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2686 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2690 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2691 * one and check the value returned for NumPhyEvents at runtime.
2693 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2694 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2697 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2699 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2700 U32 Reserved1; /* 0x08 */
2701 U8 NumPhyEvents; /* 0x0C */
2702 U8 Reserved2; /* 0x0D */
2703 U16 Reserved3; /* 0x0E */
2704 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2705 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2706 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2708 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2711 /* SAS PHY Page 3 */
2713 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2715 U8 PhyEventCode; /* 0x00 */
2716 U8 Reserved1; /* 0x01 */
2717 U16 Reserved2; /* 0x02 */
2718 U8 CounterType; /* 0x04 */
2719 U8 ThresholdWindow; /* 0x05 */
2720 U8 TimeUnits; /* 0x06 */
2721 U8 Reserved3; /* 0x07 */
2722 U32 EventThreshold; /* 0x08 */
2723 U16 ThresholdFlags; /* 0x0C */
2724 U16 Reserved4; /* 0x0E */
2725 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2726 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2728 /* values for PhyEventCode field */
2729 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2730 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2731 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2732 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2733 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2734 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2735 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2736 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2737 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2738 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2739 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2740 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2741 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2742 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2743 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2744 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2745 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2746 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2747 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2748 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2749 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2750 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2751 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2752 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2753 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2754 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2755 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2756 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2757 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2758 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2759 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2760 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2761 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2762 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2763 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2764 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2765 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2767 /* values for the CounterType field */
2768 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2769 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2770 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2772 /* values for the TimeUnits field */
2773 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2774 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2775 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2776 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2778 /* values for the ThresholdFlags field */
2779 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2780 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2783 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2784 * one and check the value returned for NumPhyEvents at runtime.
2786 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2787 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2790 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2792 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2793 U32 Reserved1; /* 0x08 */
2794 U8 NumPhyEvents; /* 0x0C */
2795 U8 Reserved2; /* 0x0D */
2796 U16 Reserved3; /* 0x0E */
2797 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2798 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2799 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2801 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2804 /* SAS PHY Page 4 */
2806 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2808 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2809 U16 Reserved1; /* 0x08 */
2810 U8 Reserved2; /* 0x0A */
2811 U8 Flags; /* 0x0B */
2812 U8 InitialFrame[28]; /* 0x0C */
2813 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2814 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2816 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2818 /* values for the Flags field */
2819 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2820 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2825 /****************************************************************************
2826 * SAS Port Config Pages
2827 ****************************************************************************/
2829 /* SAS Port Page 0 */
2831 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2833 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2834 U8 PortNumber; /* 0x08 */
2835 U8 PhysicalPort; /* 0x09 */
2836 U8 PortWidth; /* 0x0A */
2837 U8 PhysicalPortWidth; /* 0x0B */
2838 U8 ZoneGroup; /* 0x0C */
2839 U8 Reserved1; /* 0x0D */
2840 U16 Reserved2; /* 0x0E */
2841 U64 SASAddress; /* 0x10 */
2842 U32 DeviceInfo; /* 0x18 */
2843 U32 Reserved3; /* 0x1C */
2844 U32 Reserved4; /* 0x20 */
2845 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2846 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2848 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2850 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2853 /****************************************************************************
2854 * SAS Enclosure Config Pages
2855 ****************************************************************************/
2857 /* SAS Enclosure Page 0 */
2859 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2861 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2862 U32 Reserved1; /* 0x08 */
2863 U64 EnclosureLogicalID; /* 0x0C */
2864 U16 Flags; /* 0x14 */
2865 U16 EnclosureHandle; /* 0x16 */
2866 U16 NumSlots; /* 0x18 */
2867 U16 StartSlot; /* 0x1A */
2868 U8 Reserved2; /* 0x1C */
2869 U8 EnclosureLevel; /* 0x1D */
2870 U16 SEPDevHandle; /* 0x1E */
2871 U32 Reserved3; /* 0x20 */
2872 U32 Reserved4; /* 0x24 */
2873 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2874 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2875 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2877 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
2879 /* values for SAS Enclosure Page 0 Flags field */
2880 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
2881 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2882 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2883 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2884 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2885 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2886 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2887 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2890 /****************************************************************************
2892 ****************************************************************************/
2897 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2898 * one and check the value returned for NumLogEntries at runtime.
2900 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2901 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2904 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2906 typedef struct _MPI2_LOG_0_ENTRY
2908 U64 TimeStamp; /* 0x00 */
2909 U32 Reserved1; /* 0x08 */
2910 U16 LogSequence; /* 0x0C */
2911 U16 LogEntryQualifier; /* 0x0E */
2912 U8 VP_ID; /* 0x10 */
2913 U8 VF_ID; /* 0x11 */
2914 U16 Reserved2; /* 0x12 */
2915 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2916 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2917 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2919 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2920 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2921 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2922 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2923 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2924 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2926 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2928 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2929 U32 Reserved1; /* 0x08 */
2930 U32 Reserved2; /* 0x0C */
2931 U16 NumLogEntries; /* 0x10 */
2932 U16 Reserved3; /* 0x12 */
2933 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2934 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2935 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2937 #define MPI2_LOG_0_PAGEVERSION (0x02)
2940 /****************************************************************************
2942 ****************************************************************************/
2947 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2948 * one and check the value returned for NumElements at runtime.
2950 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2951 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2954 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2956 U16 ElementFlags; /* 0x00 */
2957 U16 VolDevHandle; /* 0x02 */
2958 U8 HotSparePool; /* 0x04 */
2959 U8 PhysDiskNum; /* 0x05 */
2960 U16 PhysDiskDevHandle; /* 0x06 */
2961 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2962 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2963 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2965 /* values for the ElementFlags field */
2966 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2967 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2968 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2969 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2970 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2973 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2975 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2976 U8 NumHotSpares; /* 0x08 */
2977 U8 NumPhysDisks; /* 0x09 */
2978 U8 NumVolumes; /* 0x0A */
2979 U8 ConfigNum; /* 0x0B */
2980 U32 Flags; /* 0x0C */
2981 U8 ConfigGUID[24]; /* 0x10 */
2982 U32 Reserved1; /* 0x28 */
2983 U8 NumElements; /* 0x2C */
2984 U8 Reserved2; /* 0x2D */
2985 U16 Reserved3; /* 0x2E */
2986 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2987 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2988 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2989 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2991 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2993 /* values for RAID Configuration Page 0 Flags field */
2994 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2997 /****************************************************************************
2998 * Driver Persistent Mapping Config Pages
2999 ****************************************************************************/
3001 /* Driver Persistent Mapping Page 0 */
3003 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
3005 U64 PhysicalIdentifier; /* 0x00 */
3006 U16 MappingInformation; /* 0x08 */
3007 U16 DeviceIndex; /* 0x0A */
3008 U32 PhysicalBitsMapping; /* 0x0C */
3009 U32 Reserved1; /* 0x10 */
3010 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3011 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3012 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
3014 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
3016 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3017 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
3018 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3019 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3020 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
3022 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3024 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
3025 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3026 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3027 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3030 /****************************************************************************
3031 * Ethernet Config Pages
3032 ****************************************************************************/
3034 /* Ethernet Page 0 */
3036 /* IP address (union of IPv4 and IPv6) */
3037 typedef union _MPI2_ETHERNET_IP_ADDR
3041 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
3042 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
3044 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3046 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
3048 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3049 U8 NumInterfaces; /* 0x08 */
3050 U8 Reserved0; /* 0x09 */
3051 U16 Reserved1; /* 0x0A */
3052 U32 Status; /* 0x0C */
3053 U8 MediaState; /* 0x10 */
3054 U8 Reserved2; /* 0x11 */
3055 U16 Reserved3; /* 0x12 */
3056 U8 MacAddress[6]; /* 0x14 */
3057 U8 Reserved4; /* 0x1A */
3058 U8 Reserved5; /* 0x1B */
3059 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
3060 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
3061 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
3062 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
3063 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
3064 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
3065 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3066 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3067 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
3069 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3071 /* values for Ethernet Page 0 Status field */
3072 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3073 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3074 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3075 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3076 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3077 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3078 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3079 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3080 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3081 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3082 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3083 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3085 /* values for Ethernet Page 0 MediaState field */
3086 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3087 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3088 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3090 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3091 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3092 #define MPI2_ETHPG0_MS_10MBIT (0x01)
3093 #define MPI2_ETHPG0_MS_100MBIT (0x02)
3094 #define MPI2_ETHPG0_MS_1GBIT (0x03)
3097 /* Ethernet Page 1 */
3099 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
3101 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3102 U32 Reserved0; /* 0x08 */
3103 U32 Flags; /* 0x0C */
3104 U8 MediaState; /* 0x10 */
3105 U8 Reserved1; /* 0x11 */
3106 U16 Reserved2; /* 0x12 */
3107 U8 MacAddress[6]; /* 0x14 */
3108 U8 Reserved3; /* 0x1A */
3109 U8 Reserved4; /* 0x1B */
3110 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
3111 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
3112 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
3113 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
3114 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
3115 U32 Reserved5; /* 0x6C */
3116 U32 Reserved6; /* 0x70 */
3117 U32 Reserved7; /* 0x74 */
3118 U32 Reserved8; /* 0x78 */
3119 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3120 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3121 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3123 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3125 /* values for Ethernet Page 1 Flags field */
3126 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3127 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3128 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3129 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3130 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3131 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3132 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3133 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3134 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3136 /* values for Ethernet Page 1 MediaState field */
3137 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3138 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3139 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3141 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3142 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3143 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3144 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3145 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3148 /****************************************************************************
3149 * Extended Manufacturing Config Pages
3150 ****************************************************************************/
3153 * Generic structure to use for product-specific extended manufacturing pages
3154 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3158 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
3160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3161 U32 ProductSpecificInfo; /* 0x08 */
3162 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3163 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3164 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3166 /* PageVersion should be provided by product-specific code */
projects / FreeBSD / releng / 9.3.git / blob