2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/interrupt.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
51 #include <machine/vmparam.h>
54 #include <dev/ppbus/ppbconf.h>
55 #include <dev/ppbus/ppb_msq.h>
57 #include <dev/ppc/ppcvar.h>
58 #include <dev/ppc/ppcreg.h>
62 static void ppcintr(void *arg);
64 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
65 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
67 #define LOG_PPC(function, ppc, string) \
68 if (bootverbose) printf("%s: %s\n", function, string)
70 #if defined(__i386__) && defined(PC98)
71 #define PC98_IEEE_1284_DISABLE 0x100
72 #define PC98_IEEE_1284_PORT 0x140
75 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
77 devclass_t ppc_devclass;
78 const char ppc_driver_name[] = "ppc";
80 static char *ppc_models[] = {
81 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
82 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
83 "SMC FDC37C935", "PC87303", 0
86 /* list of available modes */
87 static char *ppc_avms[] = {
88 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
89 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
90 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
91 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
94 /* list of current executing modes
95 * Note that few modes do not actually exist.
97 static char *ppc_modes[] = {
98 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
99 "EPP", "EPP", "EPP", "ECP",
100 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
101 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
104 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
108 * BIOS printer list - used by BIOS probe.
110 #define BIOS_PPC_PORTS 0x408
111 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
112 #define BIOS_MAX_PPC 4
119 ppc_ecp_sync(device_t dev)
122 struct ppc_data *ppc = DEVTOSOFTC(dev);
124 PPC_ASSERT_LOCKED(ppc);
125 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
129 if ((r & 0xe0) != PPC_ECR_EPP)
132 for (i = 0; i < 100; i++) {
139 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
147 * Detect parallel port FIFO
150 ppc_detect_fifo(struct ppc_data *ppc)
153 char ctr_sav, ctr, cc;
157 ecr_sav = r_ecr(ppc);
158 ctr_sav = r_ctr(ppc);
160 /* enter ECP configuration mode, no interrupt, no DMA */
163 /* read PWord size - transfers in FIFO mode must be PWord aligned */
164 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
166 /* XXX 16 and 32 bits implementations not supported */
167 if (ppc->ppc_pword != PPC_PWORD_8) {
168 LOG_PPC(__func__, ppc, "PWord not supported");
172 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
174 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
176 /* enter ECP test mode, no interrupt, no DMA */
180 for (i=0; i<1024; i++) {
181 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
187 LOG_PPC(__func__, ppc, "can't flush FIFO");
191 /* enable interrupts, no DMA */
194 /* determine readIntrThreshold
195 * fill the FIFO until serviceIntr is set
197 for (i=0; i<1024; i++) {
198 w_fifo(ppc, (char)i);
199 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
200 /* readThreshold reached */
203 if (r_ecr(ppc) & PPC_FIFO_FULL) {
210 LOG_PPC(__func__, ppc, "can't fill FIFO");
214 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
215 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
216 w_ecr(ppc, 0xd0); /* enable interrupts */
218 /* determine writeIntrThreshold
219 * empty the FIFO until serviceIntr is set
221 for (i=ppc->ppc_fifo; i>0; i--) {
222 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
223 LOG_PPC(__func__, ppc, "invalid data in FIFO");
226 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
227 /* writeIntrThreshold reached */
228 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
230 /* if FIFO empty before the last byte, error */
231 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
232 LOG_PPC(__func__, ppc, "data lost in FIFO");
237 /* FIFO must be empty after the last byte */
238 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
239 LOG_PPC(__func__, ppc, "can't empty the FIFO");
256 ppc_detect_port(struct ppc_data *ppc)
259 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
261 if (r_dtr(ppc) != 0xaa)
268 * EPP timeout, according to the PC87332 manual
269 * Semantics of clearing EPP timeout bit.
270 * PC87332 - reading SPP_STR does it...
271 * SMC - write 1 to EPP timeout bit XXX
272 * Others - (?) write 0 to EPP timeout bit
275 ppc_reset_epp_timeout(struct ppc_data *ppc)
281 w_str(ppc, r & 0xfe);
287 ppc_check_epp_timeout(struct ppc_data *ppc)
289 ppc_reset_epp_timeout(ppc);
291 return (!(r_str(ppc) & TIMEOUT));
295 * Configure current operating mode
298 ppc_generic_setmode(struct ppc_data *ppc, int mode)
302 /* check if mode is available */
303 if (mode && !(ppc->ppc_avm & mode))
306 /* if ECP mode, configure ecr register */
307 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
308 /* return to byte mode (keeping direction bit),
309 * no interrupt, no DMA to be able to change to
312 w_ecr(ppc, PPC_ECR_RESET);
313 ecr = PPC_DISABLE_INTR;
317 else if (mode & PPB_ECP)
318 /* select ECP mode */
320 else if (mode & PPB_PS2)
321 /* select PS2 mode with ECP */
324 /* select COMPATIBLE/NIBBLE mode */
330 ppc->ppc_mode = mode;
336 * The ppc driver is free to choose options like FIFO or DMA
337 * if ECP mode is available.
339 * The 'RAW' option allows the upper drivers to force the ppc mode
340 * even with FIFO, DMA available.
343 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
347 /* check if mode is available */
348 if (mode && !(ppc->ppc_avm & mode))
351 /* if ECP mode, configure ecr register */
352 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
353 /* return to byte mode (keeping direction bit),
354 * no interrupt, no DMA to be able to change to
357 w_ecr(ppc, PPC_ECR_RESET);
358 ecr = PPC_DISABLE_INTR;
361 /* select EPP mode */
363 else if (mode & PPB_ECP)
364 /* select ECP mode */
366 else if (mode & PPB_PS2)
367 /* select PS2 mode with ECP */
370 /* select COMPATIBLE/NIBBLE mode */
376 ppc->ppc_mode = mode;
381 #ifdef PPC_PROBE_CHIPSET
385 * Probe for a Natsemi PC873xx-family part.
387 * References in this function are to the National Semiconductor
388 * PC87332 datasheet TL/C/11930, May 1995 revision.
390 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
391 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
392 static int pc873xx_irqtab[] = {5, 7, 5, 0};
394 static int pc873xx_regstab[] = {
395 PC873_FER, PC873_FAR, PC873_PTR,
396 PC873_FCR, PC873_PCR, PC873_PMC,
397 PC873_TUP, PC873_SID, PC873_PNP0,
398 PC873_PNP1, PC873_LPTBA, -1
401 static char *pc873xx_rnametab[] = {
402 "FER", "FAR", "PTR", "FCR", "PCR",
403 "PMC", "TUP", "SID", "PNP0", "PNP1",
408 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
410 static int index = 0;
412 int ptr, pcr, val, i;
414 while ((idport = pc873xx_basetab[index++])) {
416 /* XXX should check first to see if this location is already claimed */
419 * Pull the 873xx through the power-on ID cycle (2.2,1.).
420 * We can't use this to locate the chip as it may already have
421 * been used by the BIOS.
423 (void)inb(idport); (void)inb(idport);
424 (void)inb(idport); (void)inb(idport);
427 * Read the SID byte. Possible values are :
434 outb(idport, PC873_SID);
435 val = inb(idport + 1);
436 if ((val & 0xf0) == 0x10) {
437 ppc->ppc_model = NS_PC87332;
438 } else if ((val & 0xf8) == 0x70) {
439 ppc->ppc_model = NS_PC87306;
440 } else if ((val & 0xf8) == 0x50) {
441 ppc->ppc_model = NS_PC87334;
442 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
443 documentation, but probing
445 ppc->ppc_model = NS_PC87303;
447 if (bootverbose && (val != 0xff))
448 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
449 continue ; /* not recognised */
452 /* print registers */
455 for (i=0; pc873xx_regstab[i] != -1; i++) {
456 outb(idport, pc873xx_regstab[i]);
457 printf(" %s=0x%x", pc873xx_rnametab[i],
458 inb(idport + 1) & 0xff);
464 * We think we have one. Is it enabled and where we want it to be?
466 outb(idport, PC873_FER);
467 val = inb(idport + 1);
468 if (!(val & PC873_PPENABLE)) {
470 printf("PC873xx parallel port disabled\n");
473 outb(idport, PC873_FAR);
474 val = inb(idport + 1);
475 /* XXX we should create a driver instance for every port found */
476 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
478 /* First try to change the port address to that requested... */
480 switch (ppc->ppc_base) {
498 outb(idport, PC873_FAR);
499 outb(idport + 1, val);
500 outb(idport + 1, val);
502 /* Check for success by reading back the value we supposedly
503 wrote and comparing...*/
505 outb(idport, PC873_FAR);
506 val = inb(idport + 1) & 0x3;
508 /* If we fail, report the failure... */
510 if (pc873xx_porttab[val] != ppc->ppc_base) {
512 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
513 pc873xx_porttab[val], ppc->ppc_base);
518 outb(idport, PC873_PTR);
519 ptr = inb(idport + 1);
521 /* get irq settings */
522 if (ppc->ppc_base == 0x378)
523 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
525 irq = pc873xx_irqtab[val];
528 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
531 * Check if irq settings are correct
533 if (irq != ppc->ppc_irq) {
535 * If the chipset is not locked and base address is 0x378,
536 * we have another chance
538 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
539 if (ppc->ppc_irq == 7) {
540 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
541 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
543 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
544 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
547 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
550 printf("PC873xx sorry, can't change irq setting\n");
554 printf("PC873xx irq settings are correct\n");
557 outb(idport, PC873_PCR);
558 pcr = inb(idport + 1);
560 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
562 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
564 ppc->ppc_avm |= PPB_NIBBLE;
568 if (pcr & PC873_EPPEN) {
569 ppc->ppc_avm |= PPB_EPP;
574 if (pcr & PC873_EPP19)
575 ppc->ppc_epp = EPP_1_9;
577 ppc->ppc_epp = EPP_1_7;
579 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
580 outb(idport, PC873_PTR);
581 ptr = inb(idport + 1);
582 if (ptr & PC873_EPPRDIR)
583 printf(", Regular mode");
585 printf(", Automatic mode");
587 } else if (pcr & PC873_ECPEN) {
588 ppc->ppc_avm |= PPB_ECP;
592 if (pcr & PC873_ECPCLK) { /* XXX */
593 ppc->ppc_avm |= PPB_PS2;
598 outb(idport, PC873_PTR);
599 ptr = inb(idport + 1);
600 if (ptr & PC873_EXTENDED) {
601 ppc->ppc_avm |= PPB_SPP;
608 printf("PC873xx unlocked");
610 if (chipset_mode & PPB_ECP) {
611 if ((chipset_mode & PPB_EPP) && bootverbose)
612 printf(", ECP+EPP not supported");
615 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
616 outb(idport + 1, pcr);
617 outb(idport + 1, pcr);
622 } else if (chipset_mode & PPB_EPP) {
623 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
624 pcr |= (PC873_EPPEN | PC873_EPP19);
625 outb(idport + 1, pcr);
626 outb(idport + 1, pcr);
628 ppc->ppc_epp = EPP_1_9; /* XXX */
633 /* enable automatic direction turnover */
634 if (ppc->ppc_model == NS_PC87332) {
635 outb(idport, PC873_PTR);
636 ptr = inb(idport + 1);
637 ptr &= ~PC873_EPPRDIR;
638 outb(idport + 1, ptr);
639 outb(idport + 1, ptr);
642 printf(", Automatic mode");
645 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
646 outb(idport + 1, pcr);
647 outb(idport + 1, pcr);
649 /* configure extended bit in PTR */
650 outb(idport, PC873_PTR);
651 ptr = inb(idport + 1);
653 if (chipset_mode & PPB_PS2) {
654 ptr |= PC873_EXTENDED;
660 /* default to NIBBLE mode */
661 ptr &= ~PC873_EXTENDED;
666 outb(idport + 1, ptr);
667 outb(idport + 1, ptr);
670 ppc->ppc_avm = chipset_mode;
676 ppc->ppc_type = PPC_TYPE_GENERIC;
677 ppc_generic_setmode(ppc, chipset_mode);
679 return(chipset_mode);
685 * ppc_smc37c66xgt_detect
687 * SMC FDC37C66xGT configuration.
690 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
695 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
697 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
700 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
703 * Detection: enter configuration mode and read CRD register.
707 outb(csr, SMC665_iCODE);
708 outb(csr, SMC665_iCODE);
712 if (inb(cio) == 0x65) {
717 for (i = 0; i < 2; i++) {
719 outb(csr, SMC666_iCODE);
720 outb(csr, SMC666_iCODE);
724 if (inb(cio) == 0x66) {
729 /* Another chance, CSR may be hard-configured to be at 0x370 */
735 * If chipset not found, do not continue.
743 /* read the port's address: bits 0 and 1 of CR1 */
744 r = inb(cio) & SMC_CR1_ADDR;
745 if (port_address[(int)r] != ppc->ppc_base)
748 ppc->ppc_model = type;
751 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
752 * If SPP mode is detected, try to set ECP+EPP mode
757 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
761 printf(" CR4=0x%x", inb(cio) & 0xff);
768 /* autodetect mode */
770 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
771 if (type == SMC_37C666GT) {
772 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
774 printf(" configuration hardwired, supposing " \
778 if ((inb(cio) & SMC_CR1_MODE) == 0) {
779 /* already in extended parallel port mode, read CR4 */
781 r = (inb(cio) & SMC_CR4_EMODE);
785 ppc->ppc_avm |= PPB_SPP;
791 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
797 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
803 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
805 printf(" ECP+EPP SPP");
809 /* not an extended port mode */
810 ppc->ppc_avm |= PPB_SPP;
817 ppc->ppc_avm = chipset_mode;
819 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
820 if (type == SMC_37C666GT)
824 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
825 /* do not use ECP when the mode is not forced to */
826 outb(cio, r | SMC_CR1_MODE);
830 /* an extended mode is selected */
831 outb(cio, r & ~SMC_CR1_MODE);
833 /* read CR4 register and reset mode field */
835 r = inb(cio) & ~SMC_CR4_EMODE;
837 if (chipset_mode & PPB_ECP) {
838 if (chipset_mode & PPB_EPP) {
839 outb(cio, r | SMC_ECPEPP);
843 outb(cio, r | SMC_ECP);
849 outb(cio, r | SMC_EPPSPP);
854 ppc->ppc_avm = chipset_mode;
857 /* set FIFO threshold to 16 */
858 if (ppc->ppc_avm & PPB_ECP) {
869 if (ppc->ppc_avm & PPB_EPP) {
875 * Set the EPP protocol...
876 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
878 if (ppc->ppc_epp == EPP_1_9)
879 outb(cio, (r & ~SMC_CR4_EPPTYPE));
881 outb(cio, (r | SMC_CR4_EPPTYPE));
884 /* end config mode */
887 ppc->ppc_type = PPC_TYPE_SMCLIKE;
888 ppc_smclike_setmode(ppc, chipset_mode);
890 return (chipset_mode);
894 * SMC FDC37C935 configuration
895 * Found on many Alpha machines
898 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
904 outb(SMC935_CFG, 0x55); /* enter config mode */
905 outb(SMC935_CFG, 0x55);
908 outb(SMC935_IND, SMC935_ID); /* check device id */
909 if (inb(SMC935_DAT) == 0x2)
913 outb(SMC935_CFG, 0xaa); /* exit config mode */
917 ppc->ppc_model = type;
919 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
920 outb(SMC935_DAT, 3); /* which is logical device 3 */
922 /* set io port base */
923 outb(SMC935_IND, SMC935_PORTHI);
924 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
925 outb(SMC935_IND, SMC935_PORTLO);
926 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
929 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
931 ppc->ppc_avm = chipset_mode;
932 outb(SMC935_IND, SMC935_PPMODE);
933 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
935 /* SPP + EPP or just plain SPP */
936 if (chipset_mode & (PPB_SPP)) {
937 if (chipset_mode & PPB_EPP) {
938 if (ppc->ppc_epp == EPP_1_9) {
939 outb(SMC935_IND, SMC935_PPMODE);
940 outb(SMC935_DAT, SMC935_EPP19SPP);
942 if (ppc->ppc_epp == EPP_1_7) {
943 outb(SMC935_IND, SMC935_PPMODE);
944 outb(SMC935_DAT, SMC935_EPP17SPP);
947 outb(SMC935_IND, SMC935_PPMODE);
948 outb(SMC935_DAT, SMC935_SPP);
952 /* ECP + EPP or just plain ECP */
953 if (chipset_mode & PPB_ECP) {
954 if (chipset_mode & PPB_EPP) {
955 if (ppc->ppc_epp == EPP_1_9) {
956 outb(SMC935_IND, SMC935_PPMODE);
957 outb(SMC935_DAT, SMC935_ECPEPP19);
959 if (ppc->ppc_epp == EPP_1_7) {
960 outb(SMC935_IND, SMC935_PPMODE);
961 outb(SMC935_DAT, SMC935_ECPEPP17);
964 outb(SMC935_IND, SMC935_PPMODE);
965 outb(SMC935_DAT, SMC935_ECP);
970 outb(SMC935_CFG, 0xaa); /* exit config mode */
972 ppc->ppc_type = PPC_TYPE_SMCLIKE;
973 ppc_smclike_setmode(ppc, chipset_mode);
975 return (chipset_mode);
979 * Winbond W83877F stuff
981 * EFER: extended function enable register
982 * EFIR: extended function index register
983 * EFDR: extended function data register
985 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
986 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
988 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
989 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
990 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
991 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
994 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
997 unsigned char r, hefere, hefras;
999 for (i = 0; i < 4; i ++) {
1000 /* first try to enable configuration registers */
1001 efer = w83877f_efers[i];
1003 /* write the key to the EFER */
1004 for (j = 0; j < w83877f_keyiter[i]; j ++)
1005 outb (efer, w83877f_keys[i]);
1007 /* then check HEFERE and HEFRAS bits */
1009 hefere = inb(efdr) & WINB_HEFERE;
1012 hefras = inb(efdr) & WINB_HEFRAS;
1016 * 0 1 write 89h to 250h (power-on default)
1017 * 1 0 write 86h twice to 3f0h
1018 * 1 1 write 87h twice to 3f0h
1019 * 0 0 write 88h to 250h
1021 if ((hefere | hefras) == w83877f_hefs[i])
1025 return (-1); /* failed */
1028 /* check base port address - read from CR23 */
1030 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1033 /* read CHIP ID from CR9/bits0-3 */
1036 switch (inb(efdr) & WINB_CHIPID) {
1037 case WINB_W83877F_ID:
1038 ppc->ppc_model = WINB_W83877F;
1041 case WINB_W83877AF_ID:
1042 ppc->ppc_model = WINB_W83877AF;
1046 ppc->ppc_model = WINB_UNKNOWN;
1050 /* dump of registers */
1051 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1052 for (i = 0; i <= 0xd; i ++) {
1054 printf("0x%x ", inb(efdr));
1056 for (i = 0x10; i <= 0x17; i ++) {
1058 printf("0x%x ", inb(efdr));
1061 printf("0x%x ", inb(efdr));
1062 for (i = 0x20; i <= 0x29; i ++) {
1064 printf("0x%x ", inb(efdr));
1069 ppc->ppc_type = PPC_TYPE_GENERIC;
1071 if (!chipset_mode) {
1072 /* autodetect mode */
1076 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1080 r |= (inb(efdr) & WINB_PRTMODS2);
1085 device_printf(ppc->ppc_dev,
1086 "W83757 compatible mode\n");
1087 return (-1); /* generic or SMC-like */
1094 device_printf(ppc->ppc_dev,
1095 "not in parallel port mode\n");
1098 case (WINB_PARALLEL | WINB_EPP_SPP):
1099 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1101 device_printf(ppc->ppc_dev, "EPP SPP\n");
1104 case (WINB_PARALLEL | WINB_ECP):
1105 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1107 device_printf(ppc->ppc_dev, "ECP SPP\n");
1110 case (WINB_PARALLEL | WINB_ECP_EPP):
1111 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1112 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1115 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1118 printf("%s: unknown case (0x%x)!\n", __func__, r);
1124 /* select CR9 and set PRTMODS2 bit */
1126 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1128 /* select CR0 and reset PRTMODSx bits */
1130 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1132 if (chipset_mode & PPB_ECP) {
1133 if (chipset_mode & PPB_EPP) {
1134 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1136 device_printf(ppc->ppc_dev,
1139 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1142 outb(efdr, inb(efdr) | WINB_ECP);
1144 device_printf(ppc->ppc_dev, "ECP\n");
1147 /* select EPP_SPP otherwise */
1148 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1150 device_printf(ppc->ppc_dev, "EPP SPP\n");
1152 ppc->ppc_avm = chipset_mode;
1155 /* exit configuration mode */
1158 switch (ppc->ppc_type) {
1159 case PPC_TYPE_SMCLIKE:
1160 ppc_smclike_setmode(ppc, chipset_mode);
1163 ppc_generic_setmode(ppc, chipset_mode);
1167 return (chipset_mode);
1172 * ppc_generic_detect
1175 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1177 /* default to generic */
1178 ppc->ppc_type = PPC_TYPE_GENERIC;
1181 device_printf(ppc->ppc_dev, "SPP");
1183 /* first, check for ECP */
1184 w_ecr(ppc, PPC_ECR_PS2);
1185 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1186 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1190 /* search for SMC style ECP+EPP mode */
1191 w_ecr(ppc, PPC_ECR_EPP);
1194 /* try to reset EPP timeout bit */
1195 if (ppc_check_epp_timeout(ppc)) {
1196 ppc->ppc_dtm |= PPB_EPP;
1198 if (ppc->ppc_dtm & PPB_ECP) {
1199 /* SMC like chipset found */
1200 ppc->ppc_model = SMC_LIKE;
1201 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1210 /* restore to standard mode */
1211 w_ecr(ppc, PPC_ECR_STD);
1214 /* XXX try to detect NIBBLE and PS2 modes */
1215 ppc->ppc_dtm |= PPB_NIBBLE;
1218 ppc->ppc_avm = chipset_mode;
1220 ppc->ppc_avm = ppc->ppc_dtm;
1225 switch (ppc->ppc_type) {
1226 case PPC_TYPE_SMCLIKE:
1227 ppc_smclike_setmode(ppc, chipset_mode);
1230 ppc_generic_setmode(ppc, chipset_mode);
1234 return (chipset_mode);
1240 * mode is the mode suggested at boot
1243 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1245 #ifdef PPC_PROBE_CHIPSET
1248 /* list of supported chipsets */
1249 int (*chipset_detect[])(struct ppc_data *, int) = {
1251 ppc_smc37c66xgt_detect,
1253 ppc_smc37c935_detect,
1259 /* if can't find the port and mode not forced return error */
1260 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1261 return (EIO); /* failed, port not present */
1263 /* assume centronics compatible mode is supported */
1264 ppc->ppc_avm = PPB_COMPATIBLE;
1266 #ifdef PPC_PROBE_CHIPSET
1267 /* we have to differenciate available chipset modes,
1268 * chipset running modes and IEEE-1284 operating modes
1270 * after detection, the port must support running in compatible mode
1272 if (ppc->ppc_flags & 0x40) {
1274 printf("ppc: chipset forced to generic\n");
1277 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1279 #ifdef PPC_PROBE_CHIPSET
1281 for (i=0; chipset_detect[i] != NULL; i++) {
1282 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1283 ppc->ppc_mode = mode;
1290 /* configure/detect ECP FIFO */
1291 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1292 ppc_detect_fifo(ppc);
1298 * ppc_exec_microseq()
1300 * Execute a microsequence.
1301 * Microsequence mechanism is supposed to handle fast I/O operations.
1304 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1306 struct ppc_data *ppc = DEVTOSOFTC(dev);
1307 struct ppb_microseq *mi;
1314 register int accum = 0;
1315 register char *ptr = 0;
1317 struct ppb_microseq *stack = 0;
1319 /* microsequence registers are equivalent to PC-like port registers */
1321 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1322 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1324 #define INCR_PC (mi ++) /* increment program counter */
1326 PPC_ASSERT_LOCKED(ppc);
1329 switch (mi->opcode) {
1331 cc = r_reg(mi->arg[0].i, ppc);
1332 cc &= (char)mi->arg[2].i; /* clear mask */
1333 cc |= (char)mi->arg[1].i; /* assert mask */
1334 w_reg(mi->arg[0].i, ppc, cc);
1338 case MS_OP_RASSERT_P:
1342 if ((len = mi->arg[0].i) == MS_ACCUM) {
1343 accum = ppc->ppc_accum;
1344 for (; accum; accum--)
1345 w_reg(reg, ppc, *ptr++);
1346 ppc->ppc_accum = accum;
1348 for (i=0; i<len; i++)
1349 w_reg(reg, ppc, *ptr++);
1355 case MS_OP_RFETCH_P:
1357 mask = (char)mi->arg[2].i;
1360 if ((len = mi->arg[0].i) == MS_ACCUM) {
1361 accum = ppc->ppc_accum;
1362 for (; accum; accum--)
1363 *ptr++ = r_reg(reg, ppc) & mask;
1364 ppc->ppc_accum = accum;
1366 for (i=0; i<len; i++)
1367 *ptr++ = r_reg(reg, ppc) & mask;
1374 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1382 /* let's suppose the next instr. is the same */
1384 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1385 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1387 if (mi->opcode == MS_OP_DELAY) {
1388 DELAY(mi->arg[0].i);
1397 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1405 iter = mi->arg[1].i;
1406 p = (char *)mi->arg[2].p;
1408 /* XXX delay limited to 255 us */
1409 for (i=0; i<iter; i++) {
1410 w_reg(reg, ppc, *p++);
1411 DELAY((unsigned char)*p++);
1417 ppc->ppc_accum = mi->arg[0].i;
1422 if (--ppc->ppc_accum > 0)
1429 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1436 if ((cc & (char)mi->arg[0].i) == 0)
1443 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1451 * If the C call returns !0 then end the microseq.
1452 * The current state of ptr is passed to the C function
1454 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1461 ppc->ppc_ptr = (char *)mi->arg[0].p;
1467 panic("%s: too much calls", __func__);
1470 /* store the state of the actual
1475 /* jump to the new microsequence */
1476 mi = (struct ppb_microseq *)mi->arg[0].p;
1483 /* retrieve microseq and pc state before the call */
1486 /* reset the stack */
1489 /* XXX return code */
1497 /* can't return to ppb level during the execution
1498 * of a submicrosequence */
1500 panic("%s: can't return to ppb level",
1503 /* update pc for ppb level of execution */
1506 /* return to ppb level of execution */
1510 panic("%s: unknown microsequence opcode 0x%x",
1511 __func__, mi->opcode);
1521 struct ppc_data *ppc = arg;
1522 u_char ctr, ecr, str;
1525 * If we have any child interrupt handlers registered, let
1526 * them handle this interrupt.
1528 * XXX: If DMA is in progress should we just complete that w/o
1532 if (ppc->ppc_intr_hook != NULL &&
1533 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1542 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1543 printf("![%x/%x/%x]", ctr, ecr, str);
1546 /* don't use ecp mode with IRQENABLE set */
1547 if (ctr & IRQENABLE) {
1552 /* interrupts are generated by nFault signal
1553 * only in ECP mode */
1554 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1555 /* check if ppc driver has programmed the
1556 * nFault interrupt */
1557 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1559 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1560 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1562 /* shall be handled by underlying layers XXX */
1568 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1569 /* disable interrupts (should be done by hardware though) */
1570 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1571 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1574 /* check if DMA completed */
1575 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1580 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1583 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1587 ppc->ppc_dmadone(ppc);
1588 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1590 /* wakeup the waiting process */
1594 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1596 /* classic interrupt I/O */
1597 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1605 ppc_read(device_t dev, char *buf, int len, int mode)
1611 ppc_write(device_t dev, char *buf, int len, int how)
1617 ppc_reset_epp(device_t dev)
1619 struct ppc_data *ppc = DEVTOSOFTC(dev);
1621 PPC_ASSERT_LOCKED(ppc);
1622 ppc_reset_epp_timeout(ppc);
1628 ppc_setmode(device_t dev, int mode)
1630 struct ppc_data *ppc = DEVTOSOFTC(dev);
1632 PPC_ASSERT_LOCKED(ppc);
1633 switch (ppc->ppc_type) {
1634 case PPC_TYPE_SMCLIKE:
1635 return (ppc_smclike_setmode(ppc, mode));
1638 case PPC_TYPE_GENERIC:
1640 return (ppc_generic_setmode(ppc, mode));
1649 ppc_probe(device_t dev, int rid)
1652 static short next_bios_ppc = 0;
1654 unsigned int pc98_ieee_mode = 0x00;
1658 struct ppc_data *ppc;
1663 * Allocate the ppc_data structure.
1665 ppc = DEVTOSOFTC(dev);
1666 bzero(ppc, sizeof(struct ppc_data));
1668 ppc->rid_ioport = rid;
1670 /* retrieve ISA parameters */
1671 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1675 * If port not specified, use bios list.
1679 if (next_bios_ppc == 0) {
1680 /* Use default IEEE-1284 port of NEC PC-98x1 */
1681 port = PC98_IEEE_1284_PORT;
1685 "parallel port found at 0x%lx\n", port);
1688 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1689 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1690 port = *(BIOS_PORTS + next_bios_ppc++);
1693 "parallel port found at 0x%lx\n", port);
1695 device_printf(dev, "parallel port not found.\n");
1699 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1700 IO_LPTSIZE_EXTENDED);
1704 /* IO port is mandatory */
1706 /* Try "extended" IO port range...*/
1707 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1708 &ppc->rid_ioport, 0, ~0,
1709 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1711 if (ppc->res_ioport != 0) {
1713 device_printf(dev, "using extended I/O port range\n");
1715 /* Failed? If so, then try the "normal" IO port range... */
1716 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1717 &ppc->rid_ioport, 0, ~0,
1720 if (ppc->res_ioport != 0) {
1722 device_printf(dev, "using normal I/O port range\n");
1724 device_printf(dev, "cannot reserve I/O port range\n");
1729 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1731 ppc->ppc_flags = device_get_flags(dev);
1733 if (!(ppc->ppc_flags & 0x20)) {
1734 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1737 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1743 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1745 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1748 ppc->ppc_model = GENERIC;
1750 ppc->ppc_mode = PPB_COMPATIBLE;
1751 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1753 ppc->ppc_type = PPC_TYPE_GENERIC;
1755 #if defined(__i386__) && defined(PC98)
1757 * IEEE STD 1284 Function Check and Enable
1758 * for default IEEE-1284 port of NEC PC-98x1
1760 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1761 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1762 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1763 pc98_ieee_mode = tmp;
1764 if ((tmp & 0x10) == 0x10) {
1765 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1766 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1767 if ((tmp & 0x10) == 0x10)
1770 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1771 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1772 if ((tmp & 0x10) != 0x10)
1775 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1780 * Try to detect the chipset and its mode.
1782 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1788 #if defined(__i386__) && defined(PC98)
1789 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1790 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1791 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1794 if (ppc->res_irq != 0) {
1795 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1798 if (ppc->res_ioport != 0) {
1799 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1802 if (ppc->res_drq != 0) {
1803 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1810 ppc_attach(device_t dev)
1812 struct ppc_data *ppc = DEVTOSOFTC(dev);
1815 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1817 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1818 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1819 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1820 ppc_epp_protocol[ppc->ppc_epp] : "");
1823 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1824 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1827 /* default to the tty mask for registration */ /* XXX */
1828 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1829 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1832 "failed to register interrupt handler: %d\n",
1834 mtx_destroy(&ppc->ppc_lock);
1839 /* add ppbus as a child of this isa to parallel bridge */
1840 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1843 * Probe the ppbus and attach devices found.
1845 device_probe_and_attach(ppc->ppbus);
1851 ppc_detach(device_t dev)
1853 struct ppc_data *ppc = DEVTOSOFTC(dev);
1855 if (ppc->res_irq == 0) {
1859 /* detach & delete all children */
1860 device_delete_children(dev);
1862 if (ppc->res_irq != 0) {
1863 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1864 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1867 if (ppc->res_ioport != 0) {
1868 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1871 if (ppc->res_drq != 0) {
1872 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1876 mtx_destroy(&ppc->ppc_lock);
1882 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1884 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1886 PPC_ASSERT_LOCKED(ppc);
1889 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1892 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1895 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1898 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1901 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1904 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1907 return (r_dtr(ppc));
1909 return (r_str(ppc));
1911 return (r_ctr(ppc));
1913 return (r_epp_A(ppc));
1915 return (r_epp_D(ppc));
1917 return (r_ecr(ppc));
1919 return (r_fifo(ppc));
1942 panic("%s: unknown I/O operation", __func__);
1946 return (0); /* not significative */
1950 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1952 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1955 case PPC_IVAR_EPP_PROTO:
1956 PPC_ASSERT_LOCKED(ppc);
1957 *val = (u_long)ppc->ppc_epp;
1960 *val = (uintptr_t)&ppc->ppc_lock;
1970 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1972 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1975 case PPC_IVAR_INTR_HANDLER:
1976 PPC_ASSERT_LOCKED(ppc);
1977 if (dev != ppc->ppbus)
1980 ppc->ppc_intr_hook = NULL;
1983 if (ppc->ppc_intr_hook != NULL)
1985 ppc->ppc_intr_hook = (void *)val;
1986 ppc->ppc_intr_arg = device_get_softc(dev);
1996 * We allow child devices to allocate an IRQ resource at rid 0 for their
1997 * interrupt handlers.
2000 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
2001 u_long start, u_long end, u_long count, u_int flags)
2003 struct ppc_data *ppc = DEVTOSOFTC(bus);
2008 return (ppc->res_irq);
2015 ppc_release_resource(device_t bus, device_t child, int type, int rid,
2019 struct ppc_data *ppc = DEVTOSOFTC(bus);
2025 KASSERT(r == ppc->res_irq,
2026 ("ppc child IRQ resource mismatch"));
2034 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);