2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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25 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ECORE_HSI_ROCE__
33 #define __ECORE_HSI_ROCE__
34 /************************************************************************/
35 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */
36 /************************************************************************/
37 #include "ecore_hsi_rdma.h"
38 /************************************************************************/
39 /* Add include to common roce target for both eCore and protocol roce driver */
40 /************************************************************************/
41 #include "roce_common.h"
44 * The roce storm context of Mstorm
46 struct mstorm_roce_conn_st_ctx
48 struct regpair temp[6];
53 * The roce storm context of Mstorm
55 struct pstorm_roce_conn_st_ctx
57 struct regpair temp[16];
62 * The roce storm context of Ystorm
64 struct ystorm_roce_conn_st_ctx
66 struct regpair temp[2];
70 * The roce storm context of Xstorm
72 struct xstorm_roce_conn_st_ctx
74 struct regpair temp[24];
78 * The roce storm context of Tstorm
80 struct tstorm_roce_conn_st_ctx
82 struct regpair temp[30];
86 * The roce storm context of Ystorm
88 struct ustorm_roce_conn_st_ctx
90 struct regpair temp[12];
94 * roce connection context
96 struct roce_conn_context
98 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */;
99 struct regpair ystorm_st_padding[2] /* padding */;
100 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */;
101 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */;
102 struct regpair xstorm_st_padding[2] /* padding */;
103 struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
104 struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
105 struct timers_context timer_context /* timer context */;
106 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
107 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */;
108 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */;
109 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */;
110 struct regpair ustorm_st_padding[2] /* padding */;
115 * roce create qp requester ramrod data
117 struct roce_create_qp_req_ramrod_data
120 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
121 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
122 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
123 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
124 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
125 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
126 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
127 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
128 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
129 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
130 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
131 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
132 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
133 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
135 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
136 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
141 __le32 ack_timeout_val;
146 __le16 low_latency_phy_queue;
147 struct regpair sq_pbl_addr;
148 struct regpair orq_pbl_addr;
149 __le16 local_mac_addr[3] /* BE order */;
150 __le16 remote_mac_addr[3] /* BE order */;
152 __le16 udp_src_port /* Only relevant in RRoCE */;
153 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
154 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
155 struct regpair qp_handle_for_cqe;
156 struct regpair qp_handle_for_async;
157 u8 stats_counter_id /* Statistics counter ID to use */;
160 __le16 regular_latency_phy_queue;
166 * roce create qp responder ramrod data
168 struct roce_create_qp_resp_ramrod_data
171 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
172 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
173 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
174 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
175 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
176 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
177 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
178 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
179 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
180 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
181 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
182 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
183 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
186 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
188 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
190 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
191 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
196 u8 stats_counter_id /* Statistics counter ID to use */;
202 struct rdma_srq_id srq_id;
203 struct regpair rq_pbl_addr;
204 struct regpair irq_pbl_addr;
205 __le16 local_mac_addr[3] /* BE order */;
206 __le16 remote_mac_addr[3] /* BE order */;
208 __le16 udp_src_port /* Only relevant in RRoCE */;
209 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
210 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
211 struct regpair qp_handle_for_cqe;
212 struct regpair qp_handle_for_async;
213 __le16 low_latency_phy_queue;
216 __le16 regular_latency_phy_queue;
222 * RoCE destroy qp requester output params
224 struct roce_destroy_qp_req_output_params
227 __le32 cq_prod /* Completion producer value at destroy QP */;
232 * RoCE destroy qp requester ramrod data
234 struct roce_destroy_qp_req_ramrod_data
236 struct regpair output_params_addr;
241 * RoCE destroy qp responder output params
243 struct roce_destroy_qp_resp_output_params
245 __le32 num_invalidated_mw;
246 __le32 cq_prod /* Completion producer value at destroy QP */;
251 * RoCE destroy qp responder ramrod data
253 struct roce_destroy_qp_resp_ramrod_data
255 struct regpair output_params_addr;
260 * roce func init ramrod data
262 struct roce_events_stats
265 __le16 rnr_naks_sent;
266 __le32 retransmit_count;
267 __le32 icrc_error_count;
273 * ROCE slow path EQ cmd IDs
275 enum roce_event_opcode
277 ROCE_EVENT_CREATE_QP=11,
278 ROCE_EVENT_MODIFY_QP,
280 ROCE_EVENT_DESTROY_QP,
281 ROCE_EVENT_CREATE_UD_QP,
282 ROCE_EVENT_DESTROY_UD_QP,
283 MAX_ROCE_EVENT_OPCODE
288 * roce func init ramrod data
290 struct roce_init_func_params
292 u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */;
293 u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */;
294 u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */;
296 __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */;
301 * roce func init ramrod data
303 struct roce_init_func_ramrod_data
305 struct rdma_init_func_ramrod_data rdma;
306 struct roce_init_func_params roce;
311 * roce modify qp requester ramrod data
313 struct roce_modify_qp_req_ramrod_data
316 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
317 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
318 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
319 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
320 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
321 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
322 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
323 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
324 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
325 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
326 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
327 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
328 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
329 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
330 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
331 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
332 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
333 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
334 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
335 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
336 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
337 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
338 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
339 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
341 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
342 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
343 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
344 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
350 __le32 ack_timeout_val;
354 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
355 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
360 * roce modify qp responder ramrod data
362 struct roce_modify_qp_resp_ramrod_data
365 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
366 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
367 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
368 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
369 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
370 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
371 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
372 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
373 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
374 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
375 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
376 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
377 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
378 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
379 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
380 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
381 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
382 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
383 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
384 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
385 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
386 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
388 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
389 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
390 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
391 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
399 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
400 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
405 * RoCE query qp requester output params
407 struct roce_query_qp_req_output_params
409 __le32 psn /* send next psn */;
411 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
412 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
413 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
414 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
415 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
416 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
421 * RoCE query qp requester ramrod data
423 struct roce_query_qp_req_ramrod_data
425 struct regpair output_params_addr;
430 * RoCE query qp responder output params
432 struct roce_query_qp_resp_output_params
434 __le32 psn /* send next psn */;
436 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
437 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
438 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
439 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
444 * RoCE query qp responder ramrod data
446 struct roce_query_qp_resp_ramrod_data
448 struct regpair output_params_addr;
453 * ROCE ramrod command IDs
455 enum roce_ramrod_cmd_id
457 ROCE_RAMROD_CREATE_QP=11,
458 ROCE_RAMROD_MODIFY_QP,
459 ROCE_RAMROD_QUERY_QP,
460 ROCE_RAMROD_DESTROY_QP,
461 ROCE_RAMROD_CREATE_UD_QP,
462 ROCE_RAMROD_DESTROY_UD_QP,
463 MAX_ROCE_RAMROD_CMD_ID
471 struct e4_mstorm_roce_req_conn_ag_ctx
473 u8 byte0 /* cdu_validation */;
474 u8 byte1 /* state */;
476 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
477 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
478 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
479 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
480 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
481 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
482 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
483 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
484 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
485 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
487 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
488 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
489 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
490 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
491 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
492 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
493 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
494 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
495 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
496 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
497 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
498 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
499 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
500 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
501 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
502 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
503 __le16 word0 /* word0 */;
504 __le16 word1 /* word1 */;
505 __le32 reg0 /* reg0 */;
506 __le32 reg1 /* reg1 */;
510 struct e4_mstorm_roce_resp_conn_ag_ctx
512 u8 byte0 /* cdu_validation */;
513 u8 byte1 /* state */;
515 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
516 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
517 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
518 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
519 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
520 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
521 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
522 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
523 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
524 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
526 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
527 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
528 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
529 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
530 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
531 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
532 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
533 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
534 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
535 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
536 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
537 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
538 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
539 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
540 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
542 __le16 word0 /* word0 */;
543 __le16 word1 /* word1 */;
544 __le32 reg0 /* reg0 */;
545 __le32 reg1 /* reg1 */;
549 struct e4_tstorm_roce_req_conn_ag_ctx
551 u8 reserved0 /* cdu_validation */;
552 u8 state /* state */;
554 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
555 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
556 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */
557 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
558 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */
559 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
560 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
561 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
562 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */
563 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
564 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */
565 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
566 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */
567 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
569 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
570 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
571 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */
572 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
573 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
574 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
575 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
576 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
578 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
579 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
580 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */
581 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
582 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */
583 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
584 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */
585 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */
588 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
589 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */
590 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
591 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */
592 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
593 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
594 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
595 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */
596 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
597 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
598 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
600 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
601 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
602 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
603 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
604 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */
605 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */
607 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */
609 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */
611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */
613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
617 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
620 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
622 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */
628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
629 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
633 __le32 reg0 /* reg0 */;
634 __le32 snd_nxt_psn /* reg1 */;
635 __le32 snd_max_psn /* reg2 */;
636 __le32 orq_prod /* reg3 */;
637 __le32 reg4 /* reg4 */;
638 __le32 reg5 /* reg5 */;
639 __le32 reg6 /* reg6 */;
640 __le32 reg7 /* reg7 */;
641 __le32 reg8 /* reg8 */;
642 u8 tx_cqe_error_type /* byte2 */;
643 u8 orq_cache_idx /* byte3 */;
644 __le16 snd_sq_cons_th /* word0 */;
645 u8 byte4 /* byte4 */;
646 u8 byte5 /* byte5 */;
647 __le16 snd_sq_cons /* word1 */;
648 __le16 word2 /* conn_dpi */;
649 __le16 word3 /* word3 */;
650 __le32 reg9 /* reg9 */;
651 __le32 reg10 /* reg10 */;
655 struct e4_tstorm_roce_resp_conn_ag_ctx
657 u8 byte0 /* cdu_validation */;
658 u8 state /* state */;
660 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
661 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
662 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */
663 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
664 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
665 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
666 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
667 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
668 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */
669 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
670 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
671 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
672 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
673 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
675 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */
676 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
677 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */
678 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
679 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
680 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
681 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
682 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
684 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
685 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
686 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
687 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
688 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
689 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
690 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
691 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
693 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
694 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
695 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
696 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
697 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
698 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
699 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */
700 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
701 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */
702 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
703 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
704 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
706 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
707 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
708 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
709 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
710 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
711 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
712 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
714 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
721 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
725 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
726 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
727 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */
734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
735 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
738 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
739 __le32 psn_and_rxmit_id_echo /* reg0 */;
740 __le32 reg1 /* reg1 */;
741 __le32 reg2 /* reg2 */;
742 __le32 reg3 /* reg3 */;
743 __le32 reg4 /* reg4 */;
744 __le32 reg5 /* reg5 */;
745 __le32 reg6 /* reg6 */;
746 __le32 reg7 /* reg7 */;
747 __le32 reg8 /* reg8 */;
748 u8 tx_async_error_type /* byte2 */;
749 u8 byte3 /* byte3 */;
750 __le16 rq_cons /* word0 */;
751 u8 byte4 /* byte4 */;
752 u8 byte5 /* byte5 */;
753 __le16 rq_prod /* word1 */;
754 __le16 conn_dpi /* conn_dpi */;
755 __le16 irq_cons /* word3 */;
756 __le32 num_invlidated_mw /* reg9 */;
757 __le32 reg10 /* reg10 */;
761 struct e4_ustorm_roce_req_conn_ag_ctx
763 u8 byte0 /* cdu_validation */;
764 u8 byte1 /* state */;
766 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
767 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
768 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
769 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
770 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
771 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
772 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
773 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
774 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
775 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
777 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
778 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
779 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
780 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
781 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
782 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
783 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
784 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
786 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
787 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
788 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
789 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
790 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
791 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
792 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
793 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
794 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
795 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
796 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
797 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
798 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
799 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
800 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
801 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
803 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
804 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
805 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
806 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
807 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
808 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
809 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
810 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
811 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
812 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
813 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
814 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
815 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
816 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
817 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
819 u8 byte2 /* byte2 */;
820 u8 byte3 /* byte3 */;
821 __le16 word0 /* conn_dpi */;
822 __le16 word1 /* word1 */;
823 __le32 reg0 /* reg0 */;
824 __le32 reg1 /* reg1 */;
825 __le32 reg2 /* reg2 */;
826 __le32 reg3 /* reg3 */;
827 __le16 word2 /* word2 */;
828 __le16 word3 /* word3 */;
832 struct e4_ustorm_roce_resp_conn_ag_ctx
834 u8 byte0 /* cdu_validation */;
835 u8 byte1 /* state */;
837 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
838 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
839 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
840 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
841 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
842 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
843 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
844 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
845 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
846 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
848 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
849 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
850 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
851 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
852 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
853 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
854 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
855 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
857 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
858 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
859 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
860 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
861 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
862 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
863 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
864 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
865 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
866 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
867 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
868 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
869 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
870 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
871 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
872 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
874 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
875 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
876 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
877 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
878 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
879 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
880 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
881 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
882 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
883 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
884 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
885 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
886 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
887 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
888 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
890 u8 byte2 /* byte2 */;
891 u8 byte3 /* byte3 */;
892 __le16 word0 /* conn_dpi */;
893 __le16 word1 /* word1 */;
894 __le32 reg0 /* reg0 */;
895 __le32 reg1 /* reg1 */;
896 __le32 reg2 /* reg2 */;
897 __le32 reg3 /* reg3 */;
898 __le16 word2 /* word2 */;
899 __le16 word3 /* word3 */;
903 struct e4_xstorm_roce_req_conn_ag_ctx
905 u8 reserved0 /* cdu_validation */;
906 u8 state /* state */;
908 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
909 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
910 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
911 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
912 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
913 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
914 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
915 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
916 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
917 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */
938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */
952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */
954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */
956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */
974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
994 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
996 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
1000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
1002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */
1003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
1004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */
1005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
1006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */
1007 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
1008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
1009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
1010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1011 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
1012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
1015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1016 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
1017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1018 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
1019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1020 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
1021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
1023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */
1024 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
1025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
1027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
1028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
1029 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
1032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1033 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
1034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
1035 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
1036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
1037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
1038 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
1039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
1040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1041 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
1044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
1046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
1049 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1050 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
1051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1052 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
1053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
1055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
1057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1058 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
1059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */
1060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
1061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
1064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
1066 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */
1067 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
1068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
1069 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
1070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */
1075 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
1076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
1078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */
1079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
1080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */
1081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
1083 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
1084 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
1085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
1086 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
1087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
1088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
1090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1092 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
1094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */
1101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
1102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
1104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
1106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
1107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
1108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
1109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
1111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
1112 u8 byte2 /* byte2 */;
1113 __le16 physical_q0 /* physical_q0 */;
1114 __le16 word1 /* physical_q1 */;
1115 __le16 sq_cmp_cons /* physical_q2 */;
1116 __le16 sq_cons /* word3 */;
1117 __le16 sq_prod /* word4 */;
1118 __le16 word5 /* word5 */;
1119 __le16 conn_dpi /* conn_dpi */;
1120 u8 byte3 /* byte3 */;
1121 u8 byte4 /* byte4 */;
1122 u8 byte5 /* byte5 */;
1123 u8 byte6 /* byte6 */;
1124 __le32 lsn /* reg0 */;
1125 __le32 ssn /* reg1 */;
1126 __le32 snd_una_psn /* reg2 */;
1127 __le32 snd_nxt_psn /* reg3 */;
1128 __le32 reg4 /* reg4 */;
1129 __le32 orq_cons_th /* cf_array0 */;
1130 __le32 orq_cons /* cf_array1 */;
1134 struct e4_xstorm_roce_resp_conn_ag_ctx
1136 u8 reserved0 /* cdu_validation */;
1137 u8 state /* state */;
1139 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1140 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1141 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
1142 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
1143 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
1144 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
1145 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1146 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
1148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
1149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
1150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
1151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
1152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
1153 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
1154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
1156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
1157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
1158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
1159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
1160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
1161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
1162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
1164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
1166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
1167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
1168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */
1169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
1170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
1173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
1175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
1177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
1179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
1182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */
1183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
1184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */
1185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
1186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */
1187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
1188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
1189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
1193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
1195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
1197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
1200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
1202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
1204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
1206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
1209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
1210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
1211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
1212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
1213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
1214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
1215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
1216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
1218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
1219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
1220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
1221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
1222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1224 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
1226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
1229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
1231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
1233 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */
1234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
1235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */
1236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
1237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */
1238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
1239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
1240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
1241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1242 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
1243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1244 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
1246 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
1248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1249 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
1250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1251 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
1252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1253 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
1254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
1255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
1256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
1258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
1259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
1260 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1261 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
1263 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
1265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
1266 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
1267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
1268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
1269 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
1270 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
1271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
1275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
1277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1278 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
1280 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
1282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1283 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
1284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
1286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1287 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
1288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
1290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
1292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
1295 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
1297 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
1298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
1299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */
1300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
1301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1304 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
1306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
1307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
1309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
1310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
1311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
1312 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
1314 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
1315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
1316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
1317 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
1318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
1319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
1321 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
1325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1331 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
1332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
1333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
1335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
1336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
1337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
1338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
1339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
1340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
1341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
1342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
1343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
1344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
1345 u8 byte2 /* byte2 */;
1346 __le16 physical_q0 /* physical_q0 */;
1347 __le16 word1 /* physical_q1 */;
1348 __le16 irq_prod /* physical_q2 */;
1349 __le16 word3 /* word3 */;
1350 __le16 word4 /* word4 */;
1351 __le16 e5_reserved1 /* word5 */;
1352 __le16 irq_cons /* conn_dpi */;
1353 u8 rxmit_opcode /* byte3 */;
1354 u8 byte4 /* byte4 */;
1355 u8 byte5 /* byte5 */;
1356 u8 byte6 /* byte6 */;
1357 __le32 rxmit_psn_and_id /* reg0 */;
1358 __le32 rxmit_bytes_length /* reg1 */;
1359 __le32 psn /* reg2 */;
1360 __le32 reg3 /* reg3 */;
1361 __le32 reg4 /* reg4 */;
1362 __le32 reg5 /* cf_array0 */;
1363 __le32 msn_and_syndrome /* cf_array1 */;
1367 struct e4_ystorm_roce_req_conn_ag_ctx
1369 u8 byte0 /* cdu_validation */;
1370 u8 byte1 /* state */;
1372 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1373 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
1374 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1375 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
1376 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1377 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
1378 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1379 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
1380 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1381 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
1383 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1384 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
1385 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1386 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
1387 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1388 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
1389 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1390 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
1391 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1392 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
1393 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1394 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
1395 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1396 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
1397 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1398 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
1399 u8 byte2 /* byte2 */;
1400 u8 byte3 /* byte3 */;
1401 __le16 word0 /* word0 */;
1402 __le32 reg0 /* reg0 */;
1403 __le32 reg1 /* reg1 */;
1404 __le16 word1 /* word1 */;
1405 __le16 word2 /* word2 */;
1406 __le16 word3 /* word3 */;
1407 __le16 word4 /* word4 */;
1408 __le32 reg2 /* reg2 */;
1409 __le32 reg3 /* reg3 */;
1413 struct e4_ystorm_roce_resp_conn_ag_ctx
1415 u8 byte0 /* cdu_validation */;
1416 u8 byte1 /* state */;
1418 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1419 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
1420 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1421 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
1422 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1423 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
1424 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1425 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
1426 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1427 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
1429 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1430 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
1431 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1432 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
1433 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1434 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
1435 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1436 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
1437 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1438 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
1439 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1440 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
1441 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1442 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
1443 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1444 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
1445 u8 byte2 /* byte2 */;
1446 u8 byte3 /* byte3 */;
1447 __le16 word0 /* word0 */;
1448 __le32 reg0 /* reg0 */;
1449 __le32 reg1 /* reg1 */;
1450 __le16 word1 /* word1 */;
1451 __le16 word2 /* word2 */;
1452 __le16 word3 /* word3 */;
1453 __le16 word4 /* word4 */;
1454 __le32 reg2 /* reg2 */;
1455 __le32 reg3 /* reg3 */;
1459 struct E5XstormRoceConnAgCtxDqExtLdPart
1461 u8 reserved0 /* cdu_validation */;
1462 u8 state_and_core_id /* state_and_core_id */;
1464 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1465 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1466 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */
1467 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1468 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */
1469 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1470 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1471 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1472 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */
1473 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1474 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */
1475 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1476 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */
1477 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1478 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */
1479 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1481 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */
1482 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1483 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */
1484 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1485 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */
1486 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
1487 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */
1488 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1489 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */
1490 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1491 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */
1492 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1493 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK 0x1 /* bit14 */
1494 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT 6
1495 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */
1496 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
1498 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */
1499 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1500 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */
1501 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1502 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */
1503 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1504 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */
1505 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1507 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK 0x3 /* cf4 */
1508 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT 0
1509 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK 0x3 /* cf5 */
1510 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT 2
1511 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK 0x3 /* cf6 */
1512 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT 4
1513 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
1514 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
1516 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */
1517 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1518 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */
1519 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1520 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */
1521 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1522 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */
1523 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1525 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */
1526 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1527 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */
1528 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1529 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK 0x3 /* cf14 */
1530 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT 4
1531 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */
1532 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1534 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */
1535 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
1536 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */
1537 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
1538 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */
1539 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
1540 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */
1541 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
1543 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */
1544 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
1545 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */
1546 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
1547 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */
1548 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1549 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */
1550 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1551 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */
1552 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1554 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */
1555 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1556 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */
1557 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1558 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */
1559 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT 2
1560 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */
1561 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT 3
1562 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */
1563 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT 4
1564 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
1565 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
1566 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */
1567 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1568 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */
1569 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1571 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */
1572 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1573 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */
1574 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1575 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */
1576 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1577 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */
1578 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1579 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */
1580 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT 4
1581 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */
1582 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1583 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */
1584 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
1585 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */
1586 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
1588 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */
1589 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
1590 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */
1591 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
1592 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */
1593 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
1594 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */
1595 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
1596 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1597 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1598 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */
1599 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
1600 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */
1601 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
1602 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */
1603 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
1605 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */
1606 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
1607 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */
1608 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
1609 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */
1610 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
1611 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */
1612 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1613 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */
1614 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1615 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */
1616 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5
1617 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */
1618 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1619 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */
1620 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1622 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK 0x1 /* rule10en */
1623 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT 0
1624 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */
1625 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1626 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */
1627 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1628 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */
1629 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1630 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */
1631 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT 4
1632 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */
1633 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1634 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */
1635 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT 6
1636 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */
1637 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT 7
1639 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */
1640 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1641 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */
1642 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1643 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */
1644 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1645 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */
1646 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1647 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */
1648 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1649 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */
1650 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1651 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */
1652 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1653 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */
1654 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1656 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK 0x1 /* bit16 */
1657 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT 0
1658 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */
1659 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
1660 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */
1661 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
1662 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */
1663 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
1664 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
1665 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1666 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */
1667 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
1668 u8 byte2 /* byte2 */;
1669 __le16 physical_q0 /* physical_q0 */;
1670 __le16 word1 /* physical_q1 */;
1671 __le16 sq_cmp_cons /* physical_q2 */;
1672 __le16 sq_cons /* word3 */;
1673 __le16 sq_prod /* word4 */;
1674 __le16 word5 /* word5 */;
1675 __le16 conn_dpi /* conn_dpi */;
1676 u8 byte3 /* byte3 */;
1677 u8 byte4 /* byte4 */;
1678 u8 byte5 /* byte5 */;
1679 u8 byte6 /* byte6 */;
1680 __le32 lsn /* reg0 */;
1681 __le32 ssn /* reg1 */;
1682 __le32 snd_una_psn /* reg2 */;
1683 __le32 snd_nxt_psn /* reg3 */;
1684 __le32 reg4 /* reg4 */;
1685 __le32 orq_cons_th /* cf_array0 */;
1686 __le32 orq_cons /* cf_array1 */;
1688 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK 0x1 /* bit22 */
1689 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT 0
1690 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK 0x1 /* bit23 */
1691 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT 1
1692 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK 0x1 /* bit24 */
1693 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT 2
1694 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK 0x3 /* cf24 */
1695 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT 3
1696 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK 0x1 /* cf24en */
1697 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT 5
1698 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK 0x1 /* rule26en */
1699 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT 6
1700 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK 0x1 /* rule27en */
1701 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT 7
1702 u8 byte7 /* byte7 */;
1703 __le16 word7 /* word7 */;
1704 __le16 word8 /* word8 */;
1705 __le16 word9 /* word9 */;
1706 __le16 word10 /* word10 */;
1707 __le16 tx_rdma_edpm_usg_cnt /* word11 */;
1708 __le32 reg7 /* reg7 */;
1709 __le32 reg8 /* reg8 */;
1710 __le32 reg9 /* reg9 */;
1711 u8 byte8 /* byte8 */;
1712 u8 byte9 /* byte9 */;
1713 u8 byte10 /* byte10 */;
1714 u8 byte11 /* byte11 */;
1715 u8 byte12 /* byte12 */;
1716 u8 byte13 /* byte13 */;
1717 u8 byte14 /* byte14 */;
1718 u8 byte15 /* byte15 */;
1719 __le32 reg10 /* reg10 */;
1720 __le32 reg11 /* reg11 */;
1721 __le32 reg12 /* reg12 */;
1722 __le32 reg13 /* reg13 */;
1726 struct e5_mstorm_roce_req_conn_ag_ctx
1728 u8 byte0 /* cdu_validation */;
1729 u8 byte1 /* state_and_core_id */;
1731 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1732 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
1733 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1734 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
1735 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1736 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
1737 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1738 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
1739 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1740 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
1742 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1743 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
1744 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1745 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
1746 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1747 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
1748 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1749 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
1750 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1751 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
1752 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1753 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
1754 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1755 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
1756 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1757 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
1758 __le16 word0 /* word0 */;
1759 __le16 word1 /* word1 */;
1760 __le32 reg0 /* reg0 */;
1761 __le32 reg1 /* reg1 */;
1765 struct e5_mstorm_roce_resp_conn_ag_ctx
1767 u8 byte0 /* cdu_validation */;
1768 u8 byte1 /* state_and_core_id */;
1770 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1771 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
1772 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1773 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
1774 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1775 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
1776 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1777 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
1778 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1779 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
1781 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1782 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
1783 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1784 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
1785 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1786 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
1787 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1788 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
1789 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1790 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
1791 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1792 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
1793 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1794 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
1795 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1796 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
1797 __le16 word0 /* word0 */;
1798 __le16 word1 /* word1 */;
1799 __le32 reg0 /* reg0 */;
1800 __le32 reg1 /* reg1 */;
1804 struct e5_tstorm_roce_req_conn_ag_ctx
1806 u8 reserved0 /* cdu_validation */;
1807 u8 state_and_core_id /* state_and_core_id */;
1809 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1810 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1811 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */
1812 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
1813 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */
1814 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
1815 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1816 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
1817 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */
1818 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
1819 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */
1820 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
1821 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */
1822 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
1824 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1825 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
1826 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */
1827 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
1828 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */
1829 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
1830 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1831 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1833 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1834 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1835 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */
1836 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
1837 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */
1838 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
1839 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */
1840 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
1842 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */
1843 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
1844 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */
1845 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
1846 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */
1847 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
1848 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1849 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
1850 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */
1851 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
1852 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1853 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1855 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1856 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1857 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1858 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1859 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */
1860 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
1861 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */
1862 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
1863 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */
1864 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
1865 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */
1866 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
1867 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */
1868 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
1869 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1870 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
1872 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1873 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
1874 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1875 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
1876 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1877 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
1878 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1879 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
1880 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1881 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
1882 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */
1883 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
1884 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1885 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
1886 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1887 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
1889 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
1890 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1891 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
1892 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1893 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
1894 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1895 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
1896 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
1897 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
1898 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
1899 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
1900 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
1901 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
1902 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
1903 u8 tx_cqe_error_type /* byte2 */;
1904 __le16 snd_sq_cons_th /* word0 */;
1905 __le32 reg0 /* reg0 */;
1906 __le32 snd_nxt_psn /* reg1 */;
1907 __le32 snd_max_psn /* reg2 */;
1908 __le32 orq_prod /* reg3 */;
1909 __le32 reg4 /* reg4 */;
1910 __le32 reg5 /* reg5 */;
1911 __le32 reg6 /* reg6 */;
1912 __le32 reg7 /* reg7 */;
1913 __le32 reg8 /* reg8 */;
1914 u8 orq_cache_idx /* byte3 */;
1915 u8 byte4 /* byte4 */;
1916 u8 byte5 /* byte5 */;
1917 u8 e4_reserved8 /* byte6 */;
1918 __le16 snd_sq_cons /* word1 */;
1919 __le16 word2 /* conn_dpi */;
1920 __le32 reg9 /* reg9 */;
1921 __le16 word3 /* word3 */;
1922 __le16 e4_reserved9 /* word4 */;
1926 struct e5_tstorm_roce_resp_conn_ag_ctx
1928 u8 byte0 /* cdu_validation */;
1929 u8 state_and_core_id /* state_and_core_id */;
1931 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1932 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1933 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1934 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
1935 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
1936 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
1937 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
1938 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
1939 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */
1940 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
1941 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
1942 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
1943 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1944 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
1946 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */
1947 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
1948 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */
1949 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
1950 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1951 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
1952 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */
1953 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
1955 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */
1956 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
1957 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1958 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
1959 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1960 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
1961 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1962 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
1964 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1965 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
1966 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1967 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
1968 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1969 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
1970 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */
1971 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
1972 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */
1973 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
1974 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1975 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
1977 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */
1978 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
1979 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */
1980 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1981 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1982 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
1983 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1984 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
1985 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1986 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
1987 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1988 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
1989 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1990 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
1991 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1992 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
1994 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1995 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
1996 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1997 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
1998 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1999 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
2000 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2001 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
2002 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2003 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
2004 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */
2005 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
2006 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2007 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
2008 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2009 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
2011 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
2012 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
2013 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
2014 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
2015 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
2016 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
2017 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
2018 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3
2019 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
2020 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5
2021 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
2022 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6
2023 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
2024 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7
2025 u8 tx_async_error_type /* byte2 */;
2026 __le16 rq_cons /* word0 */;
2027 __le32 psn_and_rxmit_id_echo /* reg0 */;
2028 __le32 reg1 /* reg1 */;
2029 __le32 reg2 /* reg2 */;
2030 __le32 reg3 /* reg3 */;
2031 __le32 reg4 /* reg4 */;
2032 __le32 reg5 /* reg5 */;
2033 __le32 reg6 /* reg6 */;
2034 __le32 reg7 /* reg7 */;
2035 __le32 reg8 /* reg8 */;
2036 u8 byte3 /* byte3 */;
2037 u8 byte4 /* byte4 */;
2038 u8 byte5 /* byte5 */;
2039 u8 e4_reserved8 /* byte6 */;
2040 __le16 rq_prod /* word1 */;
2041 __le16 conn_dpi /* conn_dpi */;
2042 __le32 num_invlidated_mw /* reg9 */;
2043 __le16 irq_cons /* word3 */;
2044 __le16 e4_reserved9 /* word4 */;
2048 struct e5_ustorm_roce_req_conn_ag_ctx
2050 u8 byte0 /* cdu_validation */;
2051 u8 byte1 /* state_and_core_id */;
2053 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2054 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
2055 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2056 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
2057 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2058 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
2059 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2060 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
2061 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2062 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
2064 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2065 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
2066 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2067 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
2068 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2069 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
2070 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2071 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
2073 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2074 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
2075 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2076 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
2077 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2078 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
2079 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2080 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
2081 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2082 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
2083 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2084 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
2085 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2086 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
2087 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2088 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
2090 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2091 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
2092 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2093 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
2094 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2095 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
2096 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2097 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
2098 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2099 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
2100 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2101 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
2102 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2103 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
2104 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2105 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
2107 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
2108 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
2109 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
2110 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
2111 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
2112 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
2113 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
2114 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
2115 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
2116 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
2117 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
2118 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
2119 u8 byte2 /* byte2 */;
2120 __le16 word0 /* conn_dpi */;
2121 __le16 word1 /* word1 */;
2122 __le32 reg0 /* reg0 */;
2123 __le32 reg1 /* reg1 */;
2124 __le32 reg2 /* reg2 */;
2125 __le32 reg3 /* reg3 */;
2126 __le16 word2 /* word2 */;
2127 __le16 word3 /* word3 */;
2131 struct e5_ustorm_roce_resp_conn_ag_ctx
2133 u8 byte0 /* cdu_validation */;
2134 u8 byte1 /* state_and_core_id */;
2136 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2137 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
2138 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2139 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
2140 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2141 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
2142 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2143 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
2144 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2145 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
2147 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2148 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
2149 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
2150 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
2151 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
2152 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
2153 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
2154 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
2156 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2157 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
2158 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2159 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
2160 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2161 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
2162 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2163 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
2164 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
2165 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
2166 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
2167 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
2168 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
2169 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
2170 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2171 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
2173 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2174 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
2175 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2176 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
2177 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2178 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
2179 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2180 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
2181 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2182 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
2183 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2184 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
2185 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2186 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
2187 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
2188 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
2190 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
2191 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
2192 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
2193 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
2194 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
2195 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
2196 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
2197 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
2198 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
2199 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
2200 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
2201 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
2202 u8 byte2 /* byte2 */;
2203 __le16 word0 /* conn_dpi */;
2204 __le16 word1 /* word1 */;
2205 __le32 reg0 /* reg0 */;
2206 __le32 reg1 /* reg1 */;
2207 __le32 reg2 /* reg2 */;
2208 __le32 reg3 /* reg3 */;
2209 __le16 word2 /* word2 */;
2210 __le16 word3 /* word3 */;
2214 struct e5_xstorm_roce_req_conn_ag_ctx
2216 u8 reserved0 /* cdu_validation */;
2217 u8 state_and_core_id /* state_and_core_id */;
2219 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
2220 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2221 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
2222 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
2223 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
2224 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
2225 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
2226 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2227 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2228 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
2229 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
2230 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
2231 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2232 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
2233 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2234 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
2236 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2237 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
2238 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2239 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
2240 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
2241 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
2242 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2243 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
2244 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2245 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
2246 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2247 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
2248 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */
2249 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
2250 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
2251 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
2253 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2254 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
2255 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2256 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
2257 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2258 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
2259 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2260 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
2262 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */
2263 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
2264 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */
2265 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
2266 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */
2267 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
2268 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
2269 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
2271 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2272 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
2273 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2274 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
2275 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2276 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
2277 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2278 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
2280 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2281 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
2282 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2283 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
2284 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */
2285 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
2286 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2287 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
2289 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
2290 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
2291 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
2292 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
2293 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
2294 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
2295 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
2296 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
2298 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
2299 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
2300 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
2301 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
2302 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2303 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2304 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2305 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
2306 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2307 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
2309 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2310 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
2311 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2312 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
2313 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */
2314 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
2315 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */
2316 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
2317 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */
2318 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
2319 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
2320 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
2321 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2322 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
2323 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2324 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
2326 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2327 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
2328 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2329 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
2330 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2331 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
2332 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2333 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
2334 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */
2335 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
2336 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2337 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
2338 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
2339 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
2340 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
2341 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
2343 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
2344 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
2345 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
2346 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
2347 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
2348 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
2349 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
2350 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
2351 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2352 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2353 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
2354 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
2355 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2356 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
2357 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2358 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
2360 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2361 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
2362 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2363 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
2364 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2365 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
2366 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2367 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
2368 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2369 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
2370 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */
2371 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
2372 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2373 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2374 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2375 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
2377 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */
2378 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
2379 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
2380 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
2381 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2382 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2383 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2384 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2385 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */
2386 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
2387 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2388 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
2389 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */
2390 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
2391 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */
2392 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
2394 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2395 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
2396 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2397 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
2398 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2399 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2400 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2401 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2402 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2403 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2404 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2405 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2406 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2407 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2408 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2409 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2411 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */
2412 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
2413 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
2414 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
2415 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
2416 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
2417 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */
2418 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
2419 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */
2420 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2421 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
2422 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
2423 u8 byte2 /* byte2 */;
2424 __le16 physical_q0 /* physical_q0 */;
2425 __le16 word1 /* physical_q1 */;
2426 __le16 sq_cmp_cons /* physical_q2 */;
2427 __le16 sq_cons /* word3 */;
2428 __le16 sq_prod /* word4 */;
2429 __le16 word5 /* word5 */;
2430 __le16 conn_dpi /* conn_dpi */;
2431 u8 byte3 /* byte3 */;
2432 u8 byte4 /* byte4 */;
2433 u8 byte5 /* byte5 */;
2434 u8 byte6 /* byte6 */;
2435 __le32 lsn /* reg0 */;
2436 __le32 ssn /* reg1 */;
2437 __le32 snd_una_psn /* reg2 */;
2438 __le32 snd_nxt_psn /* reg3 */;
2439 __le32 reg4 /* reg4 */;
2440 __le32 orq_cons_th /* cf_array0 */;
2441 __le32 orq_cons /* cf_array1 */;
2445 struct e5_xstorm_roce_resp_conn_ag_ctx
2447 u8 reserved0 /* cdu_validation */;
2448 u8 state_and_core_id /* state_and_core_id */;
2450 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
2451 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2452 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
2453 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
2454 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
2455 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
2456 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
2457 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2458 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
2459 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
2460 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
2461 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
2462 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
2463 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
2464 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
2465 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
2467 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
2468 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
2469 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
2470 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
2471 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */
2472 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
2473 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
2474 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
2475 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
2476 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
2477 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
2478 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
2479 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */
2480 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
2481 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */
2482 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
2484 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
2485 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
2486 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
2487 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
2488 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
2489 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
2490 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
2491 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
2493 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */
2494 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
2495 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */
2496 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
2497 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */
2498 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
2499 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */
2500 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
2502 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
2503 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
2504 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
2505 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
2506 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
2507 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
2508 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
2509 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
2511 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2512 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
2513 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2514 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
2515 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2516 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
2517 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2518 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
2520 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */
2521 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
2522 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
2523 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
2524 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
2525 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
2526 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */
2527 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
2529 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */
2530 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
2531 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */
2532 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
2533 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2534 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2535 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2536 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
2537 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2538 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
2540 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2541 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
2542 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
2543 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
2544 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */
2545 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
2546 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */
2547 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
2548 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */
2549 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
2550 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */
2551 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
2552 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
2553 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
2554 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
2555 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
2557 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
2558 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
2559 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
2560 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
2561 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
2562 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
2563 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
2564 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
2565 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
2566 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
2567 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
2568 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
2569 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
2570 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
2571 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
2572 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
2574 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
2575 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
2576 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */
2577 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
2578 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */
2579 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
2580 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */
2581 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
2582 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
2583 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2584 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
2585 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
2586 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2587 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
2588 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2589 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
2591 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2592 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
2593 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2594 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
2595 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2596 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
2597 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
2598 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
2599 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
2600 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
2601 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
2602 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
2603 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
2604 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2605 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
2606 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
2608 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
2609 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
2610 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */
2611 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
2612 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
2613 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2614 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
2615 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2616 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
2617 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
2618 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
2619 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
2620 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
2621 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
2622 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
2623 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
2625 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
2626 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
2627 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
2628 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
2629 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
2630 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2631 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
2632 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2633 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
2634 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2635 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
2636 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2637 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
2638 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2639 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
2640 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2642 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
2643 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
2644 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
2645 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
2646 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
2647 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
2648 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
2649 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
2650 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
2651 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
2652 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
2653 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
2654 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
2655 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
2656 u8 byte2 /* byte2 */;
2657 __le16 physical_q0 /* physical_q0 */;
2658 __le16 word1 /* physical_q1 */;
2659 __le16 irq_prod /* physical_q2 */;
2660 __le16 word3 /* word3 */;
2661 __le16 word4 /* word4 */;
2662 __le16 ack_cons /* word5 */;
2663 __le16 irq_cons /* conn_dpi */;
2664 u8 rxmit_opcode /* byte3 */;
2665 u8 byte4 /* byte4 */;
2666 u8 byte5 /* byte5 */;
2667 u8 byte6 /* byte6 */;
2668 __le32 rxmit_psn_and_id /* reg0 */;
2669 __le32 rxmit_bytes_length /* reg1 */;
2670 __le32 psn /* reg2 */;
2671 __le32 reg3 /* reg3 */;
2672 __le32 reg4 /* reg4 */;
2673 __le32 reg5 /* cf_array0 */;
2674 __le32 msn_and_syndrome /* cf_array1 */;
2678 struct e5_ystorm_roce_req_conn_ag_ctx
2680 u8 byte0 /* cdu_validation */;
2681 u8 byte1 /* state_and_core_id */;
2683 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2684 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
2685 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2686 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
2687 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2688 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
2689 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2690 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
2691 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2692 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
2694 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2695 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
2696 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2697 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
2698 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2699 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
2700 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2701 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
2702 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2703 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
2704 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2705 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
2706 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2707 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
2708 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2709 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
2710 u8 byte2 /* byte2 */;
2711 u8 byte3 /* byte3 */;
2712 __le16 word0 /* word0 */;
2713 __le32 reg0 /* reg0 */;
2714 __le32 reg1 /* reg1 */;
2715 __le16 word1 /* word1 */;
2716 __le16 word2 /* word2 */;
2717 __le16 word3 /* word3 */;
2718 __le16 word4 /* word4 */;
2719 __le32 reg2 /* reg2 */;
2720 __le32 reg3 /* reg3 */;
2724 struct e5_ystorm_roce_resp_conn_ag_ctx
2726 u8 byte0 /* cdu_validation */;
2727 u8 byte1 /* state_and_core_id */;
2729 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2730 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
2731 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2732 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
2733 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2734 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
2735 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2736 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
2737 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2738 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
2740 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2741 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
2742 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2743 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
2744 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2745 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
2746 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2747 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
2748 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2749 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
2750 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2751 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
2752 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2753 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
2754 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2755 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
2756 u8 byte2 /* byte2 */;
2757 u8 byte3 /* byte3 */;
2758 __le16 word0 /* word0 */;
2759 __le32 reg0 /* reg0 */;
2760 __le32 reg1 /* reg1 */;
2761 __le16 word1 /* word1 */;
2762 __le16 word2 /* word2 */;
2763 __le16 word3 /* word3 */;
2764 __le16 word4 /* word4 */;
2765 __le32 reg2 /* reg2 */;
2766 __le32 reg3 /* reg3 */;
2771 * Roce doorbell data
2775 PLAIN_ROCE /* RoCE v1 */,
2776 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */,
2777 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */,
2781 #endif /* __ECORE_HSI_ROCE__ */