2 * Copyright 2006-2009 Solarflare Communications Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
39 #define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
41 #ifndef EFSYS_MEM_IS_NULL
42 #define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL)
45 typedef enum efx_family_e {
52 extern __checkReturn int
56 __out efx_family_t *efp);
58 extern __checkReturn int
60 __in efsys_bar_t *esbp,
61 __out efx_family_t *efp);
63 #define EFX_PCI_VENID_SFC 0x1924
64 #define EFX_PCI_DEVID_FALCON 0x0710
65 #define EFX_PCI_DEVID_BETHPAGE 0x0803
66 #define EFX_PCI_DEVID_SIENA 0x0813
67 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
91 typedef struct efx_nic_s efx_nic_t;
93 extern __checkReturn int
95 __in efx_family_t family,
96 __in efsys_identifier_t *esip,
97 __in efsys_bar_t *esbp,
98 __in efsys_lock_t *eslp,
99 __deref_out efx_nic_t **enpp);
101 extern __checkReturn int
103 __in efx_nic_t *enp);
105 #if EFSYS_OPT_PCIE_TUNE
107 extern __checkReturn int
110 unsigned int nlanes);
112 extern __checkReturn int
113 efx_nic_pcie_extended_sync(
114 __in efx_nic_t *enp);
116 #endif /* EFSYS_OPT_PCIE_TUNE */
118 extern __checkReturn int
120 __in efx_nic_t *enp);
122 extern __checkReturn int
124 __in efx_nic_t *enp);
128 extern __checkReturn int
129 efx_nic_register_test(
130 __in efx_nic_t *enp);
132 #endif /* EFSYS_OPT_DIAG */
136 __in efx_nic_t *enp);
140 __in efx_nic_t *enp);
144 __in efx_nic_t *enp);
148 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
150 typedef enum efx_mcdi_exception_e {
151 EFX_MCDI_EXCEPTION_MC_REBOOT,
152 EFX_MCDI_EXCEPTION_MC_BADASSERT,
153 } efx_mcdi_exception_t;
155 typedef struct efx_mcdi_transport_s {
157 void (*emt_execute)(void *, efx_mcdi_req_t *);
158 void (*emt_ev_cpl)(void *);
159 void (*emt_exception)(void *, efx_mcdi_exception_t);
160 } efx_mcdi_transport_t;
162 extern __checkReturn int
165 __in const efx_mcdi_transport_t *mtp);
167 extern __checkReturn int
169 __in efx_nic_t *enp);
172 efx_mcdi_request_start(
174 __in efx_mcdi_req_t *emrp,
175 __in boolean_t ev_cpl);
177 extern __checkReturn boolean_t
178 efx_mcdi_request_poll(
179 __in efx_nic_t *enp);
181 extern __checkReturn boolean_t
182 efx_mcdi_request_abort(
183 __in efx_nic_t *enp);
187 __in efx_nic_t *enp);
189 #endif /* EFSYS_OPT_MCDI */
193 #define EFX_NINTR_FALCON 64
194 #define EFX_NINTR_SIENA 1024
196 typedef enum efx_intr_type_e {
197 EFX_INTR_INVALID = 0,
203 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
205 extern __checkReturn int
208 __in efx_intr_type_t type,
209 __in efsys_mem_t *esmp);
213 __in efx_nic_t *enp);
217 __in efx_nic_t *enp);
220 efx_intr_disable_unlocked(
221 __in efx_nic_t *enp);
223 #define EFX_INTR_NEVQS 32
225 extern __checkReturn int
228 __in unsigned int level);
231 efx_intr_status_line(
233 __out boolean_t *fatalp,
234 __out uint32_t *maskp);
237 efx_intr_status_message(
239 __in unsigned int message,
240 __out boolean_t *fatalp);
244 __in efx_nic_t *enp);
248 __in efx_nic_t *enp);
252 #if EFSYS_OPT_MAC_STATS
254 /* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */
255 typedef enum efx_mac_stat_e {
258 EFX_MAC_RX_UNICST_PKTS,
259 EFX_MAC_RX_MULTICST_PKTS,
260 EFX_MAC_RX_BRDCST_PKTS,
261 EFX_MAC_RX_PAUSE_PKTS,
262 EFX_MAC_RX_LE_64_PKTS,
263 EFX_MAC_RX_65_TO_127_PKTS,
264 EFX_MAC_RX_128_TO_255_PKTS,
265 EFX_MAC_RX_256_TO_511_PKTS,
266 EFX_MAC_RX_512_TO_1023_PKTS,
267 EFX_MAC_RX_1024_TO_15XX_PKTS,
268 EFX_MAC_RX_GE_15XX_PKTS,
270 EFX_MAC_RX_FCS_ERRORS,
271 EFX_MAC_RX_DROP_EVENTS,
272 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
273 EFX_MAC_RX_SYMBOL_ERRORS,
274 EFX_MAC_RX_ALIGN_ERRORS,
275 EFX_MAC_RX_INTERNAL_ERRORS,
276 EFX_MAC_RX_JABBER_PKTS,
277 EFX_MAC_RX_LANE0_CHAR_ERR,
278 EFX_MAC_RX_LANE1_CHAR_ERR,
279 EFX_MAC_RX_LANE2_CHAR_ERR,
280 EFX_MAC_RX_LANE3_CHAR_ERR,
281 EFX_MAC_RX_LANE0_DISP_ERR,
282 EFX_MAC_RX_LANE1_DISP_ERR,
283 EFX_MAC_RX_LANE2_DISP_ERR,
284 EFX_MAC_RX_LANE3_DISP_ERR,
285 EFX_MAC_RX_MATCH_FAULT,
286 EFX_MAC_RX_NODESC_DROP_CNT,
289 EFX_MAC_TX_UNICST_PKTS,
290 EFX_MAC_TX_MULTICST_PKTS,
291 EFX_MAC_TX_BRDCST_PKTS,
292 EFX_MAC_TX_PAUSE_PKTS,
293 EFX_MAC_TX_LE_64_PKTS,
294 EFX_MAC_TX_65_TO_127_PKTS,
295 EFX_MAC_TX_128_TO_255_PKTS,
296 EFX_MAC_TX_256_TO_511_PKTS,
297 EFX_MAC_TX_512_TO_1023_PKTS,
298 EFX_MAC_TX_1024_TO_15XX_PKTS,
299 EFX_MAC_TX_GE_15XX_PKTS,
301 EFX_MAC_TX_SGL_COL_PKTS,
302 EFX_MAC_TX_MULT_COL_PKTS,
303 EFX_MAC_TX_EX_COL_PKTS,
304 EFX_MAC_TX_LATE_COL_PKTS,
306 EFX_MAC_TX_EX_DEF_PKTS,
310 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
312 #endif /* EFSYS_OPT_MAC_STATS */
314 typedef enum efx_link_mode_e {
315 EFX_LINK_UNKNOWN = 0,
327 #define EFX_MAC_SDU_MAX 9202
329 #define EFX_MAC_PDU(_sdu) \
334 + /* bug16011 */ 16), \
337 #define EFX_MAC_PDU_MIN 60
338 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
340 extern __checkReturn int
345 extern __checkReturn int
350 extern __checkReturn int
353 __in boolean_t unicst,
354 __in boolean_t brdcst);
356 extern __checkReturn int
359 __in boolean_t enabled);
361 extern __checkReturn int
364 __out boolean_t *mac_upp);
366 #define EFX_FCNTL_RESPOND 0x00000001
367 #define EFX_FCNTL_GENERATE 0x00000002
369 extern __checkReturn int
372 __in unsigned int fcntl,
373 __in boolean_t autoneg);
378 __out unsigned int *fcntl_wantedp,
379 __out unsigned int *fcntl_linkp);
381 #define EFX_MAC_HASH_BITS (1 << 8)
383 extern __checkReturn int
386 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
388 #if EFSYS_OPT_MAC_STATS
392 extern __checkReturn const char __cs *
395 __in unsigned int id);
397 #endif /* EFSYS_OPT_NAMES */
399 #define EFX_MAC_STATS_SIZE 0x400
402 * Upload mac statistics supported by the hardware into the given buffer.
404 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
407 * The hardware will only DMA statistics that it understands (of course).
408 * Drivers should not make any assumptions about which statistics are
409 * supported, especially when the statistics are generated by firmware.
411 * Thus, drivers should zero this buffer before use, so that not-understood
412 * statistics read back as zero.
414 extern __checkReturn int
415 efx_mac_stats_upload(
417 __in efsys_mem_t *esmp);
419 extern __checkReturn int
420 efx_mac_stats_periodic(
422 __in efsys_mem_t *esmp,
423 __in uint16_t period_ms,
424 __in boolean_t events);
426 extern __checkReturn int
427 efx_mac_stats_update(
429 __in efsys_mem_t *esmp,
430 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
431 __out_opt uint32_t *generationp);
433 #endif /* EFSYS_OPT_MAC_STATS */
437 typedef enum efx_mon_type_e {
448 extern const char __cs *
450 __in efx_nic_t *enp);
452 #endif /* EFSYS_OPT_NAMES */
454 extern __checkReturn int
456 __in efx_nic_t *enp);
458 #if EFSYS_OPT_MON_STATS
460 #define EFX_MON_STATS_SIZE 0x100
462 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 16a14e61aa4f8d80 */
463 typedef enum efx_mon_stat_e {
470 EFX_MON_STAT_EXT_TEMP,
471 EFX_MON_STAT_INT_TEMP,
474 EFX_MON_STAT_INT_COOLING,
475 EFX_MON_STAT_EXT_COOLING,
483 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
485 typedef enum efx_mon_stat_state_e {
486 EFX_MON_STAT_STATE_OK = 0,
487 EFX_MON_STAT_STATE_WARNING = 1,
488 EFX_MON_STAT_STATE_FATAL = 2,
489 EFX_MON_STAT_STATE_BROKEN = 3,
490 } efx_mon_stat_state_t;
492 typedef struct efx_mon_stat_value_t {
495 } efx_mon_stat_value_t;
499 extern const char __cs *
502 __in efx_mon_stat_t id);
504 #endif /* EFSYS_OPT_NAMES */
506 extern __checkReturn int
507 efx_mon_stats_update(
509 __in efsys_mem_t *esmp,
510 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
512 #endif /* EFSYS_OPT_MON_STATS */
516 __in efx_nic_t *enp);
520 #define PMA_PMD_MMD 1
525 #define CL22EXT_MMD 29
527 #define MAXMMD ((1 << 5) - 1)
530 #define EFX_PHY_NULL 0x0
531 #define EFX_PHY_TXC43128 0x1
532 #define EFX_PHY_SFX7101 0x3
533 #define EFX_PHY_QT2022C2 0x4
534 #define EFX_PHY_SFT9001A 0x8
535 #define EFX_PHY_QT2025C 0x9
536 #define EFX_PHY_SFT9001B 0xa
537 #define EFX_PHY_QLX111V 0xc
539 extern __checkReturn int
541 __in efx_nic_t *enp);
543 #if EFSYS_OPT_PHY_LED_CONTROL
545 typedef enum efx_phy_led_mode_e {
546 EFX_PHY_LED_DEFAULT = 0,
551 } efx_phy_led_mode_t;
553 extern __checkReturn int
556 __in efx_phy_led_mode_t mode);
558 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
560 extern __checkReturn int
562 __in efx_nic_t *enp);
564 #if EFSYS_OPT_LOOPBACK
566 typedef enum efx_loopback_type_e {
567 EFX_LOOPBACK_OFF = 0,
568 EFX_LOOPBACK_DATA = 1,
569 EFX_LOOPBACK_GMAC = 2,
570 EFX_LOOPBACK_XGMII = 3,
571 EFX_LOOPBACK_XGXS = 4,
572 EFX_LOOPBACK_XAUI = 5,
573 EFX_LOOPBACK_GMII = 6,
574 EFX_LOOPBACK_SGMII = 7,
575 EFX_LOOPBACK_XGBR = 8,
576 EFX_LOOPBACK_XFI = 9,
577 EFX_LOOPBACK_XAUI_FAR = 10,
578 EFX_LOOPBACK_GMII_FAR = 11,
579 EFX_LOOPBACK_SGMII_FAR = 12,
580 EFX_LOOPBACK_XFI_FAR = 13,
581 EFX_LOOPBACK_GPHY = 14,
582 EFX_LOOPBACK_PHY_XS = 15,
583 EFX_LOOPBACK_PCS = 16,
584 EFX_LOOPBACK_PMA_PMD = 17,
586 } efx_loopback_type_t;
588 #define EFX_LOOPBACK_MAC_MASK \
589 ((1 << EFX_LOOPBACK_DATA) | \
590 (1 << EFX_LOOPBACK_GMAC) | \
591 (1 << EFX_LOOPBACK_XGMII) | \
592 (1 << EFX_LOOPBACK_XGXS) | \
593 (1 << EFX_LOOPBACK_XAUI) | \
594 (1 << EFX_LOOPBACK_GMII) | \
595 (1 << EFX_LOOPBACK_SGMII) | \
596 (1 << EFX_LOOPBACK_XGBR) | \
597 (1 << EFX_LOOPBACK_XFI) | \
598 (1 << EFX_LOOPBACK_XAUI_FAR) | \
599 (1 << EFX_LOOPBACK_GMII_FAR) | \
600 (1 << EFX_LOOPBACK_SGMII_FAR) | \
601 (1 << EFX_LOOPBACK_XFI_FAR))
603 #define EFX_LOOPBACK_MASK \
604 ((1 << EFX_LOOPBACK_NTYPES) - 1)
606 extern __checkReturn int
607 efx_port_loopback_set(
609 __in efx_link_mode_t link_mode,
610 __in efx_loopback_type_t type);
614 extern __checkReturn const char __cs *
615 efx_loopback_type_name(
617 __in efx_loopback_type_t type);
619 #endif /* EFSYS_OPT_NAMES */
621 #endif /* EFSYS_OPT_LOOPBACK */
623 extern __checkReturn int
626 __out efx_link_mode_t *link_modep);
630 __in efx_nic_t *enp);
632 typedef enum efx_phy_cap_type_e {
633 EFX_PHY_CAP_INVALID = 0,
640 EFX_PHY_CAP_10000FDX,
645 } efx_phy_cap_type_t;
648 #define EFX_PHY_CAP_CURRENT 0x00000000
649 #define EFX_PHY_CAP_DEFAULT 0x00000001
650 #define EFX_PHY_CAP_PERM 0x00000002
656 __out uint32_t *maskp);
658 extern __checkReturn int
666 __out uint32_t *maskp);
668 extern __checkReturn int
671 __out uint32_t *ouip);
673 typedef enum efx_phy_media_type_e {
674 EFX_PHY_MEDIA_INVALID = 0,
679 EFX_PHY_MEDIA_SFP_PLUS,
680 EFX_PHY_MEDIA_BASE_T,
682 } efx_phy_media_type_t;
684 /* Get the type of medium currently used. If the board has ports for
685 * modules, a module is present, and we recognise the media type of
686 * the module, then this will be the media type of the module.
687 * Otherwise it will be the media type of the port.
690 efx_phy_media_type_get(
692 __out efx_phy_media_type_t *typep);
694 #if EFSYS_OPT_PHY_STATS
696 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
697 typedef enum efx_phy_stat_e {
699 EFX_PHY_STAT_PMA_PMD_LINK_UP,
700 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
701 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
702 EFX_PHY_STAT_PMA_PMD_REV_A,
703 EFX_PHY_STAT_PMA_PMD_REV_B,
704 EFX_PHY_STAT_PMA_PMD_REV_C,
705 EFX_PHY_STAT_PMA_PMD_REV_D,
706 EFX_PHY_STAT_PCS_LINK_UP,
707 EFX_PHY_STAT_PCS_RX_FAULT,
708 EFX_PHY_STAT_PCS_TX_FAULT,
709 EFX_PHY_STAT_PCS_BER,
710 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
711 EFX_PHY_STAT_PHY_XS_LINK_UP,
712 EFX_PHY_STAT_PHY_XS_RX_FAULT,
713 EFX_PHY_STAT_PHY_XS_TX_FAULT,
714 EFX_PHY_STAT_PHY_XS_ALIGN,
715 EFX_PHY_STAT_PHY_XS_SYNC_A,
716 EFX_PHY_STAT_PHY_XS_SYNC_B,
717 EFX_PHY_STAT_PHY_XS_SYNC_C,
718 EFX_PHY_STAT_PHY_XS_SYNC_D,
719 EFX_PHY_STAT_AN_LINK_UP,
720 EFX_PHY_STAT_AN_MASTER,
721 EFX_PHY_STAT_AN_LOCAL_RX_OK,
722 EFX_PHY_STAT_AN_REMOTE_RX_OK,
723 EFX_PHY_STAT_CL22EXT_LINK_UP,
728 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
729 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
730 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
731 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
732 EFX_PHY_STAT_AN_COMPLETE,
733 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
734 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
735 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
736 EFX_PHY_STAT_PCS_FW_VERSION_0,
737 EFX_PHY_STAT_PCS_FW_VERSION_1,
738 EFX_PHY_STAT_PCS_FW_VERSION_2,
739 EFX_PHY_STAT_PCS_FW_VERSION_3,
740 EFX_PHY_STAT_PCS_FW_BUILD_YY,
741 EFX_PHY_STAT_PCS_FW_BUILD_MM,
742 EFX_PHY_STAT_PCS_FW_BUILD_DD,
743 EFX_PHY_STAT_PCS_OP_MODE,
747 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
751 extern const char __cs *
754 __in efx_phy_stat_t stat);
756 #endif /* EFSYS_OPT_NAMES */
758 #define EFX_PHY_STATS_SIZE 0x100
760 extern __checkReturn int
761 efx_phy_stats_update(
763 __in efsys_mem_t *esmp,
764 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat);
766 #endif /* EFSYS_OPT_PHY_STATS */
768 #if EFSYS_OPT_PHY_PROPS
772 extern const char __cs *
775 __in unsigned int id);
777 #endif /* EFSYS_OPT_NAMES */
779 #define EFX_PHY_PROP_DEFAULT 0x00000001
781 extern __checkReturn int
784 __in unsigned int id,
786 __out uint32_t *valp);
788 extern __checkReturn int
791 __in unsigned int id,
794 #endif /* EFSYS_OPT_PHY_PROPS */
796 #if EFSYS_OPT_PHY_BIST
798 typedef enum efx_phy_bist_type_e {
799 EFX_PHY_BIST_TYPE_UNKNOWN,
800 EFX_PHY_BIST_TYPE_NORMAL,
801 EFX_PHY_BIST_TYPE_CABLE_SHORT,
802 EFX_PHY_BIST_TYPE_CABLE_LONG,
803 EFX_PHY_BIST_TYPE_NTYPES,
804 } efx_phy_bist_type_t;
806 typedef enum efx_phy_bist_result_e {
807 EFX_PHY_BIST_RESULT_UNKNOWN,
808 EFX_PHY_BIST_RESULT_RUNNING,
809 EFX_PHY_BIST_RESULT_PASSED,
810 EFX_PHY_BIST_RESULT_FAILED,
811 } efx_phy_bist_result_t;
813 typedef enum efx_phy_cable_status_e {
814 EFX_PHY_CABLE_STATUS_OK,
815 EFX_PHY_CABLE_STATUS_INVALID,
816 EFX_PHY_CABLE_STATUS_OPEN,
817 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
818 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
819 EFX_PHY_CABLE_STATUS_BUSY,
820 } efx_phy_cable_status_t;
822 typedef enum efx_phy_bist_value_e {
823 EFX_PHY_BIST_CABLE_LENGTH_A,
824 EFX_PHY_BIST_CABLE_LENGTH_B,
825 EFX_PHY_BIST_CABLE_LENGTH_C,
826 EFX_PHY_BIST_CABLE_LENGTH_D,
827 EFX_PHY_BIST_CABLE_STATUS_A,
828 EFX_PHY_BIST_CABLE_STATUS_B,
829 EFX_PHY_BIST_CABLE_STATUS_C,
830 EFX_PHY_BIST_CABLE_STATUS_D,
831 EFX_PHY_BIST_FAULT_CODE,
832 EFX_PHY_BIST_NVALUES,
833 } efx_phy_bist_value_t;
835 extern __checkReturn int
838 __in efx_phy_bist_type_t type);
840 extern __checkReturn int
843 __in efx_phy_bist_type_t type,
844 __out efx_phy_bist_result_t *resultp,
845 __out_opt uint32_t *value_maskp,
846 __out_ecount_opt(count) unsigned long *valuesp,
852 __in efx_phy_bist_type_t type);
854 #endif /* EFSYS_OPT_PHY_BIST */
856 #define EFX_FEATURE_IPV6 0x00000001
857 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
858 #define EFX_FEATURE_LINK_EVENTS 0x00000004
859 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
860 #define EFX_FEATURE_WOL 0x00000010
861 #define EFX_FEATURE_MCDI 0x00000020
862 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
863 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
865 typedef struct efx_nic_cfg_s {
866 uint32_t enc_board_type;
867 uint32_t enc_phy_type;
869 char enc_phy_name[21];
871 char enc_phy_revision[21];
872 efx_mon_type_t enc_mon_type;
873 #if EFSYS_OPT_MON_STATS
874 uint32_t enc_mon_stat_mask;
876 unsigned int enc_features;
877 uint8_t enc_mac_addr[6];
879 uint32_t enc_evq_limit;
880 uint32_t enc_txq_limit;
881 uint32_t enc_rxq_limit;
882 uint32_t enc_buftbl_limit;
883 uint32_t enc_evq_moderation_max;
884 #if EFSYS_OPT_LOOPBACK
885 uint32_t enc_loopback_types[EFX_LINK_NMODES];
886 #endif /* EFSYS_OPT_LOOPBACK */
887 #if EFSYS_OPT_PHY_FLAGS
888 uint32_t enc_phy_flags_mask;
889 #endif /* EFSYS_OPT_PHY_FLAGS */
890 #if EFSYS_OPT_PHY_LED_CONTROL
891 uint32_t enc_led_mask;
892 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
893 #if EFSYS_OPT_PHY_STATS
894 uint64_t enc_phy_stat_mask;
895 #endif /* EFSYS_OPT_PHY_STATS */
896 #if EFSYS_OPT_PHY_PROPS
897 unsigned int enc_phy_nprops;
898 #endif /* EFSYS_OPT_PHY_PROPS */
900 uint8_t enc_siena_channel;
901 #if EFSYS_OPT_PHY_STATS
902 uint32_t enc_siena_phy_stat_mask;
903 #endif /* EFSYS_OPT_PHY_STATS */
904 #if EFSYS_OPT_MON_STATS
905 uint32_t enc_siena_mon_stat_mask;
906 #endif /* EFSYS_OPT_MON_STATS */
907 #endif /* EFSYS_OPT_SIENA */
908 #if EFSYS_OPT_PHY_BIST
909 uint32_t enc_bist_mask;
910 #endif /* EFSYS_OPT_PHY_BIST */
913 extern const efx_nic_cfg_t *
915 __in efx_nic_t *enp);
919 typedef enum efx_vpd_tag_e {
926 typedef uint16_t efx_vpd_keyword_t;
928 typedef struct efx_vpd_value_s {
929 efx_vpd_tag_t evv_tag;
930 efx_vpd_keyword_t evv_keyword;
932 uint8_t evv_value[0x100];
936 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
938 extern __checkReturn int
940 __in efx_nic_t *enp);
942 extern __checkReturn int
945 __out size_t *sizep);
947 extern __checkReturn int
950 __out_bcount(size) caddr_t data,
953 extern __checkReturn int
956 __in_bcount(size) caddr_t data,
959 extern __checkReturn int
962 __in_bcount(size) caddr_t data,
965 extern __checkReturn int
968 __in_bcount(size) caddr_t data,
970 __inout efx_vpd_value_t *evvp);
972 extern __checkReturn int
975 __inout_bcount(size) caddr_t data,
977 __in efx_vpd_value_t *evvp);
979 extern __checkReturn int
982 __inout_bcount(size) caddr_t data,
984 __out efx_vpd_value_t *evvp,
985 __inout unsigned int *contp);
987 extern __checkReturn int
990 __in_bcount(size) caddr_t data,
995 __in efx_nic_t *enp);
997 #endif /* EFSYS_OPT_VPD */
1003 typedef enum efx_nvram_type_e {
1004 EFX_NVRAM_INVALID = 0,
1006 EFX_NVRAM_BOOTROM_CFG,
1007 EFX_NVRAM_MC_FIRMWARE,
1008 EFX_NVRAM_MC_GOLDEN,
1014 extern __checkReturn int
1016 __in efx_nic_t *enp);
1020 extern __checkReturn int
1022 __in efx_nic_t *enp);
1024 #endif /* EFSYS_OPT_DIAG */
1026 extern __checkReturn int
1028 __in efx_nic_t *enp,
1029 __in efx_nvram_type_t type,
1030 __out size_t *sizep);
1032 extern __checkReturn int
1034 __in efx_nic_t *enp,
1035 __in efx_nvram_type_t type,
1036 __out_opt size_t *pref_chunkp);
1039 efx_nvram_rw_finish(
1040 __in efx_nic_t *enp,
1041 __in efx_nvram_type_t type);
1043 extern __checkReturn int
1044 efx_nvram_get_version(
1045 __in efx_nic_t *enp,
1046 __in efx_nvram_type_t type,
1047 __out uint32_t *subtypep,
1048 __out_ecount(4) uint16_t version[4]);
1050 extern __checkReturn int
1051 efx_nvram_read_chunk(
1052 __in efx_nic_t *enp,
1053 __in efx_nvram_type_t type,
1054 __in unsigned int offset,
1055 __out_bcount(size) caddr_t data,
1058 extern __checkReturn int
1059 efx_nvram_set_version(
1060 __in efx_nic_t *enp,
1061 __in efx_nvram_type_t type,
1062 __out uint16_t version[4]);
1064 extern __checkReturn int
1066 __in efx_nic_t *enp,
1067 __in efx_nvram_type_t type);
1069 extern __checkReturn int
1070 efx_nvram_write_chunk(
1071 __in efx_nic_t *enp,
1072 __in efx_nvram_type_t type,
1073 __in unsigned int offset,
1074 __in_bcount(size) caddr_t data,
1079 __in efx_nic_t *enp);
1081 #endif /* EFSYS_OPT_NVRAM */
1083 #if EFSYS_OPT_BOOTCFG
1087 __in efx_nic_t *enp,
1088 __out_bcount(size) caddr_t data,
1093 __in efx_nic_t *enp,
1094 __in_bcount(size) caddr_t data,
1097 #endif /* EFSYS_OPT_BOOTCFG */
1101 typedef enum efx_wol_type_e {
1102 EFX_WOL_TYPE_INVALID,
1104 EFX_WOL_TYPE_BITMAP,
1109 typedef enum efx_lightsout_offload_type_e {
1110 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1111 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1112 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1113 } efx_lightsout_offload_type_t;
1115 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1116 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1118 typedef union efx_wol_param_u {
1120 uint8_t mac_addr[6];
1123 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1124 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1129 typedef union efx_lightsout_offload_param_u {
1131 uint8_t mac_addr[6];
1135 uint8_t mac_addr[6];
1136 uint32_t solicited_node[4];
1139 } efx_lightsout_offload_param_t;
1141 extern __checkReturn int
1143 __in efx_nic_t *enp);
1145 extern __checkReturn int
1146 efx_wol_filter_clear(
1147 __in efx_nic_t *enp);
1149 extern __checkReturn int
1151 __in efx_nic_t *enp,
1152 __in efx_wol_type_t type,
1153 __in efx_wol_param_t *paramp,
1154 __out uint32_t *filter_idp);
1156 extern __checkReturn int
1157 efx_wol_filter_remove(
1158 __in efx_nic_t *enp,
1159 __in uint32_t filter_id);
1161 extern __checkReturn int
1162 efx_lightsout_offload_add(
1163 __in efx_nic_t *enp,
1164 __in efx_lightsout_offload_type_t type,
1165 __in efx_lightsout_offload_param_t *paramp,
1166 __out uint32_t *filter_idp);
1168 extern __checkReturn int
1169 efx_lightsout_offload_remove(
1170 __in efx_nic_t *enp,
1171 __in efx_lightsout_offload_type_t type,
1172 __in uint32_t filter_id);
1176 __in efx_nic_t *enp);
1178 #endif /* EFSYS_OPT_WOL */
1182 typedef enum efx_pattern_type_t {
1183 EFX_PATTERN_BYTE_INCREMENT = 0,
1184 EFX_PATTERN_ALL_THE_SAME,
1185 EFX_PATTERN_BIT_ALTERNATE,
1186 EFX_PATTERN_BYTE_ALTERNATE,
1187 EFX_PATTERN_BYTE_CHANGING,
1188 EFX_PATTERN_BIT_SWEEP,
1190 } efx_pattern_type_t;
1193 (*efx_sram_pattern_fn_t)(
1195 __in boolean_t negate,
1196 __out efx_qword_t *eqp);
1198 extern __checkReturn int
1200 __in efx_nic_t *enp,
1201 __in efx_pattern_type_t type);
1203 #endif /* EFSYS_OPT_DIAG */
1205 extern __checkReturn int
1206 efx_sram_buf_tbl_set(
1207 __in efx_nic_t *enp,
1209 __in efsys_mem_t *esmp,
1213 efx_sram_buf_tbl_clear(
1214 __in efx_nic_t *enp,
1218 #define EFX_BUF_TBL_SIZE 0x20000
1220 #define EFX_BUF_SIZE 4096
1224 typedef struct efx_evq_s efx_evq_t;
1226 #if EFSYS_OPT_QSTATS
1228 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */
1229 typedef enum efx_ev_qstat_e {
1236 EV_RX_PAUSE_FRM_ERR,
1237 EV_RX_BUF_OWNER_ID_ERR,
1238 EV_RX_IPV4_HDR_CHKSUM_ERR,
1239 EV_RX_TCP_UDP_CHKSUM_ERR,
1243 EV_RX_MCAST_HASH_MATCH,
1260 EV_GLOBAL_RX_RECOVERY,
1262 EV_DRIVER_SRM_UPD_DONE,
1263 EV_DRIVER_TX_DESCQ_FLS_DONE,
1264 EV_DRIVER_RX_DESCQ_FLS_DONE,
1265 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1266 EV_DRIVER_RX_DSC_ERROR,
1267 EV_DRIVER_TX_DSC_ERROR,
1273 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1275 #endif /* EFSYS_OPT_QSTATS */
1277 extern __checkReturn int
1279 __in efx_nic_t *enp);
1283 __in efx_nic_t *enp);
1285 #define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min))
1287 #define EFX_EVQ_MAXNEVS 32768
1288 #define EFX_EVQ_MINNEVS 512
1290 #define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS)
1292 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1293 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1295 extern __checkReturn int
1297 __in efx_nic_t *enp,
1298 __in unsigned int index,
1299 __in efsys_mem_t *esmp,
1302 __deref_out efx_evq_t **eepp);
1306 __in efx_evq_t *eep,
1307 __in uint16_t data);
1309 typedef __checkReturn boolean_t
1310 (*efx_initialized_ev_t)(
1311 __in_opt void *arg);
1313 #define EFX_PKT_UNICAST 0x0004
1314 #define EFX_PKT_START 0x0008
1316 #define EFX_PKT_VLAN_TAGGED 0x0010
1317 #define EFX_CKSUM_TCPUDP 0x0020
1318 #define EFX_CKSUM_IPV4 0x0040
1319 #define EFX_PKT_CONT 0x0080
1321 #define EFX_CHECK_VLAN 0x0100
1322 #define EFX_PKT_TCP 0x0200
1323 #define EFX_PKT_UDP 0x0400
1324 #define EFX_PKT_IPV4 0x0800
1326 #define EFX_PKT_IPV6 0x1000
1327 #define EFX_ADDR_MISMATCH 0x4000
1328 #define EFX_DISCARD 0x8000
1330 #define EFX_EV_RX_NLABELS 32
1331 #define EFX_EV_TX_NLABELS 32
1333 typedef __checkReturn boolean_t
1336 __in uint32_t label,
1339 __in uint16_t flags);
1341 typedef __checkReturn boolean_t
1344 __in uint32_t label,
1347 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1348 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1349 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1350 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1351 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1352 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1354 typedef __checkReturn boolean_t
1355 (*efx_exception_ev_t)(
1357 __in uint32_t label,
1358 __in uint32_t data);
1360 typedef __checkReturn boolean_t
1361 (*efx_rxq_flush_done_ev_t)(
1363 __in uint32_t label);
1365 typedef __checkReturn boolean_t
1366 (*efx_rxq_flush_failed_ev_t)(
1368 __in uint32_t label);
1370 typedef __checkReturn boolean_t
1371 (*efx_txq_flush_done_ev_t)(
1373 __in uint32_t label);
1375 typedef __checkReturn boolean_t
1376 (*efx_software_ev_t)(
1378 __in uint16_t magic);
1380 typedef __checkReturn boolean_t
1383 __in uint32_t code);
1385 #define EFX_SRAM_CLEAR 0
1386 #define EFX_SRAM_UPDATE 1
1387 #define EFX_SRAM_ILLEGAL_CLEAR 2
1389 typedef __checkReturn boolean_t
1390 (*efx_wake_up_ev_t)(
1392 __in uint32_t label);
1394 typedef __checkReturn boolean_t
1397 __in uint32_t label);
1399 typedef __checkReturn boolean_t
1400 (*efx_link_change_ev_t)(
1402 __in efx_link_mode_t link_mode);
1404 #if EFSYS_OPT_MON_STATS
1406 typedef __checkReturn boolean_t
1407 (*efx_monitor_ev_t)(
1409 __in efx_mon_stat_t id,
1410 __in efx_mon_stat_value_t value);
1412 #endif /* EFSYS_OPT_MON_STATS */
1414 #if EFSYS_OPT_MAC_STATS
1416 typedef __checkReturn boolean_t
1417 (*efx_mac_stats_ev_t)(
1419 __in uint32_t generation
1422 #endif /* EFSYS_OPT_MAC_STATS */
1424 typedef struct efx_ev_callbacks_s {
1425 efx_initialized_ev_t eec_initialized;
1428 efx_exception_ev_t eec_exception;
1429 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1430 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1431 efx_txq_flush_done_ev_t eec_txq_flush_done;
1432 efx_software_ev_t eec_software;
1433 efx_sram_ev_t eec_sram;
1434 efx_wake_up_ev_t eec_wake_up;
1435 efx_timer_ev_t eec_timer;
1436 efx_link_change_ev_t eec_link_change;
1437 #if EFSYS_OPT_MON_STATS
1438 efx_monitor_ev_t eec_monitor;
1439 #endif /* EFSYS_OPT_MON_STATS */
1440 #if EFSYS_OPT_MAC_STATS
1441 efx_mac_stats_ev_t eec_mac_stats;
1442 #endif /* EFSYS_OPT_MON_STATS */
1443 } efx_ev_callbacks_t;
1445 extern __checkReturn boolean_t
1447 __in efx_evq_t *eep,
1448 __in unsigned int count);
1450 #if EFSYS_OPT_EV_PREFETCH
1454 __in efx_evq_t *eep,
1455 __in unsigned int count);
1457 #endif /* EFSYS_OPT_EV_PREFETCH */
1461 __in efx_evq_t *eep,
1462 __inout unsigned int *countp,
1463 __in const efx_ev_callbacks_t *eecp,
1464 __in_opt void *arg);
1466 extern __checkReturn int
1468 __in efx_evq_t *eep,
1469 __in unsigned int us);
1471 extern __checkReturn int
1473 __in efx_evq_t *eep,
1474 __in unsigned int count);
1476 #if EFSYS_OPT_QSTATS
1480 extern const char __cs *
1482 __in efx_nic_t *enp,
1483 __in unsigned int id);
1485 #endif /* EFSYS_OPT_NAMES */
1488 efx_ev_qstats_update(
1489 __in efx_evq_t *eep,
1490 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1492 #endif /* EFSYS_OPT_QSTATS */
1496 __in efx_evq_t *eep);
1500 typedef struct efx_rxq_s efx_rxq_t;
1502 extern __checkReturn int
1504 __in efx_nic_t *enp);
1508 __in efx_nic_t *enp);
1510 #if EFSYS_OPT_RX_HDR_SPLIT
1512 efx_rx_hdr_split_enable(
1513 __in efx_nic_t *enp,
1514 __in unsigned int hdr_buf_size,
1515 __in unsigned int pld_buf_size);
1517 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1519 #if EFSYS_OPT_RX_SCATTER
1521 efx_rx_scatter_enable(
1522 __in efx_nic_t *enp,
1523 __in unsigned int buf_size);
1524 #endif /* EFSYS_OPT_RX_SCATTER */
1526 #if EFSYS_OPT_RX_SCALE
1528 typedef enum efx_rx_hash_alg_e {
1529 EFX_RX_HASHALG_LFSR = 0,
1530 EFX_RX_HASHALG_TOEPLITZ
1531 } efx_rx_hash_alg_t;
1533 typedef enum efx_rx_hash_type_e {
1534 EFX_RX_HASH_IPV4 = 0,
1535 EFX_RX_HASH_TCPIPV4,
1537 EFX_RX_HASH_TCPIPV6,
1538 } efx_rx_hash_type_t;
1540 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1541 #define EFX_MAXRSS 64 /* RX indirection entry range */
1542 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1544 extern __checkReturn int
1545 efx_rx_scale_mode_set(
1546 __in efx_nic_t *enp,
1547 __in efx_rx_hash_alg_t alg,
1548 __in efx_rx_hash_type_t type,
1549 __in boolean_t insert);
1551 extern __checkReturn int
1552 efx_rx_scale_tbl_set(
1553 __in efx_nic_t *enp,
1554 __in_ecount(n) unsigned int *table,
1557 extern __checkReturn int
1558 efx_rx_scale_toeplitz_ipv4_key_set(
1559 __in efx_nic_t *enp,
1560 __in_ecount(n) uint8_t *key,
1563 extern __checkReturn int
1564 efx_rx_scale_toeplitz_ipv6_key_set(
1565 __in efx_nic_t *enp,
1566 __in_ecount(n) uint8_t *key,
1570 * The prefix is a byte array of one of the forms:
1572 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1573 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT
1574 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL
1578 * TT.TT.TT.TT is a 32-bit Toeplitz hash
1579 * LL.LL is a 16-bit LFSR hash
1581 * Hash values are in network (big-endian) byte order.
1584 #define EFX_RX_PREFIX_SIZE 16
1586 #define EFX_RX_HASH_VALUE(_func, _buffer) \
1587 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1588 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \
1589 ((uint32_t)(((_buffer)[12] << 24) | \
1590 ((_buffer)[13] << 16) | \
1591 ((_buffer)[14] << 8) | \
1594 #define EFX_RX_HASH_SIZE(_func) \
1595 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1596 sizeof (uint16_t) : \
1599 #endif /* EFSYS_OPT_RX_SCALE */
1601 #define EFX_RXQ_MAXNDESCS 4096
1602 #define EFX_RXQ_MINNDESCS 512
1604 #define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS)
1606 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1607 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1608 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1610 typedef enum efx_rxq_type_e {
1611 EFX_RXQ_TYPE_DEFAULT,
1612 EFX_RXQ_TYPE_SPLIT_HEADER,
1613 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1614 EFX_RXQ_TYPE_SCATTER,
1618 extern __checkReturn int
1620 __in efx_nic_t *enp,
1621 __in unsigned int index,
1622 __in unsigned int label,
1623 __in efx_rxq_type_t type,
1624 __in efsys_mem_t *esmp,
1627 __in efx_evq_t *eep,
1628 __deref_out efx_rxq_t **erpp);
1630 typedef struct efx_buffer_s {
1631 efsys_dma_addr_t eb_addr;
1638 __in efx_rxq_t *erp,
1639 __in_ecount(n) efsys_dma_addr_t *addrp,
1641 __in unsigned int n,
1642 __in unsigned int completed,
1643 __in unsigned int added);
1647 __in efx_rxq_t *erp,
1648 __in unsigned int added);
1652 __in efx_rxq_t *erp);
1656 __in efx_rxq_t *erp);
1660 __in efx_rxq_t *erp);
1664 typedef struct efx_txq_s efx_txq_t;
1666 #if EFSYS_OPT_QSTATS
1668 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */
1669 typedef enum efx_tx_qstat_e {
1675 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1677 #endif /* EFSYS_OPT_QSTATS */
1679 extern __checkReturn int
1681 __in efx_nic_t *enp);
1685 __in efx_nic_t *enp);
1687 #define EFX_TXQ_MAXNDESCS 4096
1688 #define EFX_TXQ_MINNDESCS 512
1690 #define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS)
1692 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1693 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1694 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1696 extern __checkReturn int
1698 __in efx_nic_t *enp,
1699 __in unsigned int index,
1700 __in unsigned int label,
1701 __in efsys_mem_t *esmp,
1704 __in uint16_t flags,
1705 __in efx_evq_t *eep,
1706 __deref_out efx_txq_t **etpp);
1708 extern __checkReturn int
1710 __in efx_txq_t *etp,
1711 __in_ecount(n) efx_buffer_t *eb,
1712 __in unsigned int n,
1713 __in unsigned int completed,
1714 __inout unsigned int *addedp);
1718 __in efx_txq_t *etp,
1719 __in unsigned int added);
1723 __in efx_txq_t *etp);
1727 __in efx_txq_t *etp);
1729 #if EFSYS_OPT_QSTATS
1733 extern const char __cs *
1735 __in efx_nic_t *etp,
1736 __in unsigned int id);
1738 #endif /* EFSYS_OPT_NAMES */
1741 efx_tx_qstats_update(
1742 __in efx_txq_t *etp,
1743 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1745 #endif /* EFSYS_OPT_QSTATS */
1749 __in efx_txq_t *etp);
1754 #if EFSYS_OPT_FILTER
1756 typedef enum efx_filter_flag_e {
1757 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
1758 * multiple queues */
1759 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
1760 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides
1761 * any matching IP filter */
1762 } efx_filter_flag_t;
1764 typedef struct efx_filter_spec_s {
1767 uint16_t efs_dmaq_id;
1768 uint32_t efs_dword[3];
1769 } efx_filter_spec_t;
1771 extern __checkReturn int
1773 __in efx_nic_t *enp);
1777 __in efx_nic_t *enp);
1779 extern __checkReturn int
1780 efx_rx_filter_insert(
1781 __in efx_rxq_t *erp,
1782 __inout efx_filter_spec_t *spec);
1784 extern __checkReturn int
1785 efx_rx_filter_remove(
1786 __in efx_rxq_t *erp,
1787 __inout efx_filter_spec_t *spec);
1791 __in efx_nic_t *enp);
1794 efx_filter_spec_rx_ipv4_tcp_full(
1795 __inout efx_filter_spec_t *spec,
1796 __in unsigned int flags,
1797 __in uint32_t src_ip,
1798 __in uint16_t src_tcp,
1799 __in uint32_t dest_ip,
1800 __in uint16_t dest_tcp);
1803 efx_filter_spec_rx_ipv4_tcp_wild(
1804 __inout efx_filter_spec_t *spec,
1805 __in unsigned int flags,
1806 __in uint32_t dest_ip,
1807 __in uint16_t dest_tcp);
1810 efx_filter_spec_rx_ipv4_udp_full(
1811 __inout efx_filter_spec_t *spec,
1812 __in unsigned int flags,
1813 __in uint32_t src_ip,
1814 __in uint16_t src_udp,
1815 __in uint32_t dest_ip,
1816 __in uint16_t dest_udp);
1819 efx_filter_spec_rx_ipv4_udp_wild(
1820 __inout efx_filter_spec_t *spec,
1821 __in unsigned int flags,
1822 __in uint32_t dest_ip,
1823 __in uint16_t dest_udp);
1826 efx_filter_spec_rx_mac_full(
1827 __inout efx_filter_spec_t *spec,
1828 __in unsigned int flags,
1829 __in uint16_t vlan_id,
1830 __in uint8_t *dest_mac);
1833 efx_filter_spec_rx_mac_wild(
1834 __inout efx_filter_spec_t *spec,
1835 __in unsigned int flags,
1836 __in uint8_t *dest_mac);
1839 extern __checkReturn int
1840 efx_tx_filter_insert(
1841 __in efx_txq_t *etp,
1842 __inout efx_filter_spec_t *spec);
1844 extern __checkReturn int
1845 efx_tx_filter_remove(
1846 __in efx_txq_t *etp,
1847 __inout efx_filter_spec_t *spec);
1850 efx_filter_spec_tx_ipv4_tcp_full(
1851 __inout efx_filter_spec_t *spec,
1852 __in uint32_t src_ip,
1853 __in uint16_t src_tcp,
1854 __in uint32_t dest_ip,
1855 __in uint16_t dest_tcp);
1858 efx_filter_spec_tx_ipv4_tcp_wild(
1859 __inout efx_filter_spec_t *spec,
1860 __in uint32_t src_ip,
1861 __in uint16_t src_tcp);
1864 efx_filter_spec_tx_ipv4_udp_full(
1865 __inout efx_filter_spec_t *spec,
1866 __in uint32_t src_ip,
1867 __in uint16_t src_udp,
1868 __in uint32_t dest_ip,
1869 __in uint16_t dest_udp);
1872 efx_filter_spec_tx_ipv4_udp_wild(
1873 __inout efx_filter_spec_t *spec,
1874 __in uint32_t src_ip,
1875 __in uint16_t src_udp);
1878 efx_filter_spec_tx_mac_full(
1879 __inout efx_filter_spec_t *spec,
1880 __in uint16_t vlan_id,
1881 __in uint8_t *src_mac);
1884 efx_filter_spec_tx_mac_wild(
1885 __inout efx_filter_spec_t *spec,
1886 __in uint8_t *src_mac);
1888 #endif /* EFSYS_OPT_FILTER */
1895 #endif /* _SYS_EFX_H */