2 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Constants, pretty much FreeBSD specific.
36 /* Number of playback / recording channel */
37 #define ATI_IXP_NPCHAN 1
38 #define ATI_IXP_NRCHAN 1
39 #define ATI_IXP_NCHANS (ATI_IXP_NPCHAN + ATI_IXP_NRCHAN)
42 * Maximum segments/descriptors is 256, but 2 for
43 * each channel should be more than enough for us.
45 #define ATI_IXP_DMA_CHSEGS 2
46 #define ATI_IXP_DMA_CHSEGS_MIN 2
47 #define ATI_IXP_DMA_CHSEGS_MAX 256
49 #define ATI_VENDOR_ID 0x1002 /* ATI Technologies */
51 #define ATI_IXP_200_ID 0x4341
52 #define ATI_IXP_300_ID 0x4361
53 #define ATI_IXP_400_ID 0x4370
54 #define ATI_IXP_SB600_ID 0x4382
56 #define ATI_IXP_BASE_RATE 48000
59 * Register definitions for ATI IXP
61 * References: ALSA snd-atiixp.c , OpenBSD/NetBSD auixp-*.h
64 #define ATI_IXP_CODECS 3
66 #define ATI_REG_ISR 0x00 /* interrupt source */
67 #define ATI_REG_ISR_IN_XRUN (1U<<0)
68 #define ATI_REG_ISR_IN_STATUS (1U<<1)
69 #define ATI_REG_ISR_OUT_XRUN (1U<<2)
70 #define ATI_REG_ISR_OUT_STATUS (1U<<3)
71 #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
72 #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
73 #define ATI_REG_ISR_PHYS_INTR (1U<<8)
74 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
75 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
76 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
77 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
78 #define ATI_REG_ISR_NEW_FRAME (1U<<13)
80 #define ATI_REG_IER 0x04 /* interrupt enable */
81 #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
82 #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
83 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
84 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
85 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
86 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
87 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
88 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
89 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
90 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
91 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
92 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO) */
93 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
95 #define ATI_REG_CMD 0x08 /* command */
96 #define ATI_REG_CMD_POWERDOWN (1U<<0)
97 #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
98 #define ATI_REG_CMD_SEND_EN (1U<<2)
99 #define ATI_REG_CMD_STATUS_MEM (1U<<3)
100 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
101 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
102 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
103 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
104 #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
105 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
106 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
107 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
108 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
109 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
110 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
111 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
112 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
113 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
114 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
115 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
116 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
117 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
118 #define ATI_REG_CMD_PACKED_DIS (1U<<24)
119 #define ATI_REG_CMD_BURST_EN (1U<<25)
120 #define ATI_REG_CMD_PANIC_EN (1U<<26)
121 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
122 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
123 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
124 #define ATI_REG_CMD_AC_SYNC (1U<<30)
125 #define ATI_REG_CMD_AC_RESET (1U<<31)
127 #define ATI_REG_PHYS_OUT_ADDR 0x0c
128 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
129 #define ATI_REG_PHYS_OUT_RW (1U<<2)
130 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
131 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
132 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
134 #define ATI_REG_PHYS_IN_ADDR 0x10
135 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
136 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
137 #define ATI_REG_PHYS_IN_DATA_SHIFT 16
139 #define ATI_REG_SLOTREQ 0x14
141 #define ATI_REG_COUNTER 0x18
142 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
143 #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
145 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
147 #define ATI_REG_IN_DMA_LINKPTR 0x20
148 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
149 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
150 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
151 #define ATI_REG_IN_DMA_DT_SIZE 0x30
153 #define ATI_REG_OUT_DMA_SLOT 0x34
154 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
155 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
156 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
157 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
159 #define ATI_REG_OUT_DMA_LINKPTR 0x38
160 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
161 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
162 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
163 #define ATI_REG_OUT_DMA_DT_SIZE 0x48
165 #define ATI_REG_SPDF_CMD 0x4c
166 #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
167 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
168 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
170 #define ATI_REG_SPDF_DMA_LINKPTR 0x50
171 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
172 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
173 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
174 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
176 #define ATI_REG_MODEM_MIRROR 0x7c
177 #define ATI_REG_AUDIO_MIRROR 0x80
179 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
180 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
182 #define ATI_REG_FIFO_FLUSH 0x88
183 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
184 #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
187 #define ATI_REG_LINKPTR_EN (1U<<0)
189 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
190 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
191 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
192 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
193 #define ATI_REG_DMA_STATE (7U<<26)
195 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
197 /* codec detection constant indicating the interrupt flags */
198 #define ALL_CODECS_NOT_READY \
199 (ATI_REG_ISR_CODEC0_NOT_READY | ATI_REG_ISR_CODEC1_NOT_READY |\
200 ATI_REG_ISR_CODEC2_NOT_READY)
201 #define CODEC_CHECK_BITS (ALL_CODECS_NOT_READY|ATI_REG_ISR_NEW_FRAME)