2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <cg@freebsd.org>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
46 * Hardware volume controller was implemented by
47 * John Baldwin <jhb@freebsd.org>.
50 #ifdef HAVE_KERNEL_OPTION_HEADERS
54 #include <dev/sound/pcm/sound.h>
55 #include <dev/sound/pcm/ac97.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
59 #include <dev/sound/pci/maestro_reg.h>
61 SND_DECLARE_FILE("$FreeBSD$");
64 * PCI IDs of supported chips:
66 * MAESTRO-1 0x01001285
67 * MAESTRO-2 0x1968125d
68 * MAESTRO-2E 0x1978125d
71 #define MAESTRO_1_PCI_ID 0x01001285
72 #define MAESTRO_2_PCI_ID 0x1968125d
73 #define MAESTRO_2E_PCI_ID 0x1978125d
75 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
76 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
79 # if AGG_MAXPLAYCH > 4
81 # define AGG_MAXPLAYCH 4
84 # define AGG_MAXPLAYCH 4
87 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
91 #if __FreeBSD_version < 500000
92 # define critical_enter() disable_intr()
93 # define critical_exit() enable_intr()
97 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
101 /* -----------------------------
106 struct agg_info *parent;
108 /* FreeBSD newpcm related */
109 struct pcm_channel *channel;
110 struct snd_dbuf *buffer;
113 bus_addr_t phys; /* channel buffer physical address */
114 bus_addr_t base; /* channel buffer segment base */
115 u_int32_t blklen; /* DMA block length in WORDs */
116 u_int32_t buflen; /* channel buffer length in WORDs */
120 unsigned qs16 : 1; /* quantum size is 16bit */
121 unsigned us : 1; /* in unsigned format */
126 struct agg_info *parent;
128 /* FreeBSD newpcm related */
129 struct pcm_channel *channel;
130 struct snd_dbuf *buffer;
133 bus_addr_t phys; /* channel buffer physical address */
134 bus_addr_t base; /* channel buffer segment base */
135 u_int32_t blklen; /* DMA block length in WORDs */
136 u_int32_t buflen; /* channel buffer length in WORDs */
141 int16_t *src; /* stereo peer buffer */
142 int16_t *sink; /* channel buffer pointer */
143 volatile u_int32_t hwptr; /* ready point in 16bit sample */
147 /* FreeBSD newbus related */
150 /* I wonder whether bus_space_* are in common in *BSD... */
151 struct resource *reg;
154 bus_space_handle_t sh;
156 struct resource *irq;
160 bus_dma_tag_t buf_dmat;
161 bus_dma_tag_t stat_dmat;
163 /* FreeBSD SMPng related */
164 struct mtx lock; /* mutual exclusion */
165 /* FreeBSD newpcm related */
166 struct ac97_info *codec;
169 u_int8_t *stat; /* status buffer pointer */
170 bus_addr_t phys; /* status buffer physical address */
171 unsigned int bufsz; /* channel buffer size in bytes */
173 volatile u_int active;
174 struct agg_chinfo pch[AGG_MAXPLAYCH];
175 struct agg_rchinfo rch;
176 volatile u_int8_t curpwr; /* current power status: D[0-3] */
180 /* -----------------------------
183 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
184 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
185 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
187 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
189 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
191 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
192 device_get_sysctl_*() as discussed on multimedia@ in msg-id
193 <861wujij2q.fsf@xps.des.no> */
194 static SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
195 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
196 &powerstate_active, 0, "The Dx power state when active (0-1)");
197 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
198 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
199 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
201 "The Dx power state prior to the first use (0-2)");
204 /* -----------------------------
208 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
211 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
212 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
215 static int agg_rdcodec(struct agg_info*, int);
216 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
218 static void ringbus_setdest(struct agg_info*, int, int);
220 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
221 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
222 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
223 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
224 static void wp_settimer(struct agg_info*, u_int);
225 static void wp_starttimer(struct agg_info*);
226 static void wp_stoptimer(struct agg_info*);
229 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
231 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
233 static u_int16_t wc_rdchctl(struct agg_info*, int);
235 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
237 static void agg_stopclock(struct agg_info*, int part, int st);
239 static void agg_initcodec(struct agg_info*);
240 static void agg_init(struct agg_info*);
241 static void agg_power(struct agg_info*, int);
243 static void aggch_start_dac(struct agg_chinfo*);
244 static void aggch_stop_dac(struct agg_chinfo*);
245 static void aggch_start_adc(struct agg_rchinfo*);
246 static void aggch_stop_adc(struct agg_rchinfo*);
247 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
248 static void aggch_feed_adc_mono(struct agg_rchinfo*);
250 #ifdef AGG_JITTER_CORRECTION
251 static void suppress_jitter(struct agg_chinfo*);
252 static void suppress_rec_jitter(struct agg_rchinfo*);
255 static void set_timer(struct agg_info*);
257 static void agg_intr(void *);
258 static int agg_probe(device_t);
259 static int agg_attach(device_t);
260 static int agg_detach(device_t);
261 static int agg_suspend(device_t);
262 static int agg_resume(device_t);
263 static int agg_shutdown(device_t);
265 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*);
266 static void dma_free(bus_dma_tag_t, void *);
269 /* -----------------------------
274 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
275 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
278 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
282 timo = msec * hz / 1000;
285 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
292 static __inline u_int32_t
293 agg_rd(struct agg_info *sc, int regno, int size)
297 return bus_space_read_1(sc->st, sc->sh, regno);
299 return bus_space_read_2(sc->st, sc->sh, regno);
301 return bus_space_read_4(sc->st, sc->sh, regno);
303 return ~(u_int32_t)0;
308 #define AGG_RD(sc, regno, size) \
309 bus_space_read_##size( \
310 ((struct agg_info*)(sc))->st, \
311 ((struct agg_info*)(sc))->sh, (regno))
315 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
319 bus_space_write_1(sc->st, sc->sh, regno, data);
322 bus_space_write_2(sc->st, sc->sh, regno, data);
325 bus_space_write_4(sc->st, sc->sh, regno, data);
331 #define AGG_WR(sc, regno, data, size) \
332 bus_space_write_##size( \
333 ((struct agg_info*)(sc))->st, \
334 ((struct agg_info*)(sc))->sh, (regno), (data))
336 /* -------------------------------------------------------------------- */
341 agg_codec_wait4idle(struct agg_info *ess)
345 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
348 DELAY(2); /* 20.8us / 13 */
355 agg_rdcodec(struct agg_info *ess, int regno)
359 /* We have to wait for a SAFE time to write addr/data */
360 if (agg_codec_wait4idle(ess)) {
361 /* Timed out. No read performed. */
362 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
366 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
367 /*DELAY(21); * AC97 cycle = 20.8usec */
369 /* Wait for data retrieve */
370 if (!agg_codec_wait4idle(ess)) {
371 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
373 /* Timed out. No read performed. */
374 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
382 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
384 /* We have to wait for a SAFE time to write addr/data */
385 if (agg_codec_wait4idle(ess)) {
386 /* Timed out. Abort writing. */
387 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
391 AGG_WR(ess, PORT_CODEC_REG, data, 2);
392 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
394 /* Wait for write completion */
395 if (agg_codec_wait4idle(ess)) {
397 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
405 ringbus_setdest(struct agg_info *ess, int src, int dest)
409 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
410 data &= ~(0xfU << src);
411 data |= (0xfU & dest) << src;
412 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
415 /* -------------------------------------------------------------------- */
420 wp_rdreg(struct agg_info *ess, u_int16_t reg)
422 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
423 return AGG_RD(ess, PORT_DSP_DATA, 2);
427 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
429 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
430 AGG_WR(ess, PORT_DSP_DATA, data, 2);
434 wp_wait_data(struct agg_info *ess, u_int16_t data)
438 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
442 AGG_WR(ess, PORT_DSP_DATA, data, 2);
449 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
451 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
452 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
453 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
454 return wp_rdreg(ess, WPREG_DATA_PORT);
458 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
460 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
461 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
462 wp_wrreg(ess, WPREG_DATA_PORT, data);
463 if (wp_wait_data(ess, data) != 0)
464 device_printf(ess->dev,
465 "wp_wrapu() write timed out.\n");
467 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
472 apu_setparam(struct agg_info *ess, int apuch,
473 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
475 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
476 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
477 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
478 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
479 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
480 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
481 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
482 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
483 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
484 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
485 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
486 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
490 wp_settimer(struct agg_info *ess, u_int divide)
494 RANGE(divide, 2, 32 << 7);
496 for (; divide > 32; divide >>= 1) {
501 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
504 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
505 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
506 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
507 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
511 wp_starttimer(struct agg_info *ess)
513 AGG_WR(ess, PORT_INT_STAT, 1, 2);
514 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
515 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
516 wp_wrreg(ess, WPREG_TIMER_START, 1);
520 wp_stoptimer(struct agg_info *ess)
522 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
523 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
524 AGG_WR(ess, PORT_INT_STAT, 1, 2);
525 wp_wrreg(ess, WPREG_TIMER_START, 0);
528 /* -------------------------------------------------------------------- */
534 wc_rdreg(struct agg_info *ess, u_int16_t reg)
536 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
537 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
542 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
544 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
545 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
550 wc_rdchctl(struct agg_info *ess, int ch)
552 return wc_rdreg(ess, ch << 3);
557 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
559 wc_wrreg(ess, ch << 3, data);
562 /* -------------------------------------------------------------------- */
564 /* Power management */
566 agg_stopclock(struct agg_info *ess, int part, int st)
570 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
572 if (st == PCI_POWERSTATE_D1)
573 data &= ~(1 << part);
576 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
577 data |= (0x10000 << part);
579 data &= ~(0x10000 << part);
580 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
585 /* -----------------------------
590 agg_initcodec(struct agg_info* ess)
594 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
595 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
596 DELAY(104); /* 20.8us * (4 + 1) */
598 /* XXX - 2nd codec should be looked at. */
599 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
601 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
604 if (agg_rdcodec(ess, 0) < 0) {
605 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
608 /* Try cold reset. */
609 device_printf(ess->dev, "will perform cold reset.\n");
610 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
611 if (pci_read_config(ess->dev, 0x58, 2) & 1)
613 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
614 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
615 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
616 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
618 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
620 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
621 agg_sleep(ess, "agginicd", 500);
622 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
623 DELAY(84); /* 20.8us * 4 */
624 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
630 agg_init(struct agg_info* ess)
634 /* Setup PCI config registers. */
636 /* Disable all legacy emulations. */
637 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
638 data |= LEGACY_DISABLED;
639 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
641 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
642 * Enable posted write.
643 * Prefer PCI timing rather than that of ISA.
645 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
647 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
648 data &= ~MAESTRO_SWAP_LR;
649 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
651 /* Turn off unused parts if necessary. */
652 /* consult CONF_MAESTRO. */
653 if (data & MAESTRO_SPDIF)
654 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
656 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
657 if (data & MAESTRO_HWVOL)
658 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
660 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
662 /* parts that never be used */
663 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
664 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
665 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
666 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
667 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
668 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
669 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
671 /* parts that will be used only when play/recording */
672 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
674 /* parts that should always be turned on */
675 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
676 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
677 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
678 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
680 /* Reset direct sound. */
681 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
683 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
685 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
687 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
690 /* Enable hardware volume control interruption. */
691 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
692 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
694 /* Setup Wave Processor. */
696 /* Enable WaveCache, set DMA base address. */
697 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
698 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
699 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
701 AGG_WR(ess, PORT_WAVCACHE_CTRL,
702 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
704 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
705 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
707 /* Setup Codec/Ringbus. */
709 AGG_WR(ess, PORT_RINGBUS_CTRL,
710 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
712 wp_wrreg(ess, 0x08, 0xB004);
713 wp_wrreg(ess, 0x09, 0x001B);
714 wp_wrreg(ess, 0x0A, 0x8000);
715 wp_wrreg(ess, 0x0B, 0x3F37);
716 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
717 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
718 ringbus_setdest(ess, RINGBUS_SRC_ADC,
719 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
720 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
721 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
723 /* Enable S/PDIF if necessary. */
724 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
725 /* XXX - why not use device flags? */
726 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
727 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
729 /* Setup ASSP. Needed for Dell Inspiron 7500? */
730 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
731 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
732 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
736 * There seems to be speciality with NEC systems.
738 switch (pci_get_subvendor(ess->dev)
739 | (pci_get_subdevice(ess->dev) << 16)) {
742 /* Matthew Braithwaite <matt@braithwaite.net> reported that
743 * NEC Versa LX doesn't need GPIO operation. */
744 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
745 AGG_WR(ess, PORT_GPIO_DIR,
746 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
747 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
752 /* Deals power state transition. Must be called with softc->lock held. */
754 agg_power(struct agg_info *ess, int status)
758 lastpwr = ess->curpwr;
759 if (lastpwr == status)
763 case PCI_POWERSTATE_D0:
764 case PCI_POWERSTATE_D1:
766 case PCI_POWERSTATE_D2:
767 pci_set_powerstate(ess->dev, status);
768 /* Turn on PCM-related parts. */
769 agg_wrcodec(ess, AC97_REG_POWER, 0);
772 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
773 device_printf(ess->dev,
774 "warning: codec not ready.\n");
776 AGG_WR(ess, PORT_RINGBUS_CTRL,
777 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
778 & ~RINGBUS_CTRL_ACLINK_ENABLED)
779 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
781 AGG_WR(ess, PORT_RINGBUS_CTRL,
782 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
783 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
785 case PCI_POWERSTATE_D3:
787 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
791 case PCI_POWERSTATE_D0:
792 case PCI_POWERSTATE_D1:
793 pci_set_powerstate(ess->dev, status);
797 case PCI_POWERSTATE_D2:
799 case PCI_POWERSTATE_D3:
801 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
805 case PCI_POWERSTATE_D0:
806 case PCI_POWERSTATE_D1:
807 /* Turn off PCM-related parts. */
808 AGG_WR(ess, PORT_RINGBUS_CTRL,
809 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
810 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
812 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
816 pci_set_powerstate(ess->dev, status);
818 case PCI_POWERSTATE_D3:
819 /* Entirely power down. */
820 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
822 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
824 if (lastpwr != PCI_POWERSTATE_D2)
826 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
827 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
828 pci_set_powerstate(ess->dev, status);
831 /* Invalid power state; let it ignored. */
836 ess->curpwr = status;
839 /* -------------------------------------------------------------------- */
841 /* Channel controller. */
844 aggch_start_dac(struct agg_chinfo *ch)
848 u_int16_t size, apuch, wtbar, wcreg, aputype;
853 wpwa = (ch->phys - ch->base) >> 1;
854 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
855 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
857 apuch = (ch->num << 1) | 32;
858 pan = PAN_RIGHT - PAN_FRONT;
861 wcreg |= WAVCACHE_CHCTL_STEREO;
863 aputype = APUTYPE_16BITSTEREO;
868 aputype = APUTYPE_8BITSTEREO;
872 aputype = APUTYPE_16BITLINEAR;
874 aputype = APUTYPE_8BITLINEAR;
879 wcreg |= WAVCACHE_CHCTL_U8;
882 wtbar = (wtbar >> 1) + 4;
884 dv = (((speed % 48000) << 16) + 24000) / 48000
885 + ((speed / 48000) << 16);
887 agg_lock(ch->parent);
888 agg_power(ch->parent, powerstate_active);
890 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
891 ch->base >> WAVCACHE_BASEADDR_SHIFT);
892 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
893 ch->base >> WAVCACHE_BASEADDR_SHIFT);
895 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
896 ch->base >> WAVCACHE_BASEADDR_SHIFT);
897 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
898 ch->base >> WAVCACHE_BASEADDR_SHIFT);
900 wc_wrchctl(ch->parent, apuch, wcreg);
901 wc_wrchctl(ch->parent, apuch + 1, wcreg);
903 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
906 wpwa |= (WPWA_STEREO >> 1);
907 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
910 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
911 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
912 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
913 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
916 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
917 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
920 /* to mark that this channel is ready for intr. */
921 ch->parent->active |= (1 << ch->num);
923 set_timer(ch->parent);
924 wp_starttimer(ch->parent);
925 agg_unlock(ch->parent);
929 aggch_stop_dac(struct agg_chinfo *ch)
931 agg_lock(ch->parent);
933 /* to mark that this channel no longer needs further intrs. */
934 ch->parent->active &= ~(1 << ch->num);
936 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
937 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
938 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
939 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
941 if (ch->parent->active) {
942 set_timer(ch->parent);
943 wp_starttimer(ch->parent);
945 wp_stoptimer(ch->parent);
946 agg_power(ch->parent, powerstate_idle);
948 agg_unlock(ch->parent);
952 aggch_start_adc(struct agg_rchinfo *ch)
954 bus_addr_t wpwa, wpwa2;
955 u_int16_t wcreg, wcreg2;
959 /* speed > 48000 not cared */
960 dv = ((ch->speed << 16) + 24000) / 48000;
962 /* RATECONV doesn't seem to like dv == 0x10000. */
967 wpwa = (ch->srcphys - ch->base) >> 1;
968 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
969 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
970 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
971 pan = PAN_LEFT - PAN_FRONT;
973 wpwa = (ch->phys - ch->base) >> 1;
974 wpwa2 = (ch->srcphys - ch->base) >> 1;
975 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
976 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
980 agg_lock(ch->parent);
983 agg_power(ch->parent, powerstate_active);
985 /* Invalidate WaveCache. */
986 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
987 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
988 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
989 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
991 /* Load APU registers. */
992 /* APU #0 : Sample rate converter for left/center. */
993 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
994 ch->buflen >> ch->stereo, 0, dv);
995 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
996 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
998 /* APU #1 : Sample rate converter for right. */
999 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
1000 ch->buflen >> ch->stereo, 0, dv);
1001 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
1002 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
1004 /* APU #2 : Input mixer for left. */
1005 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1006 ch->parent->bufsz >> 2, pan, 0x10000);
1007 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1008 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1009 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1011 /* APU #3 : Input mixer for right. */
1012 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1013 ch->parent->bufsz >> 2, -pan, 0x10000);
1014 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1015 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1016 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1018 /* to mark this channel ready for intr. */
1019 ch->parent->active |= (1 << ch->parent->playchns);
1023 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1024 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1025 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1026 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1027 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1028 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1029 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1030 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1033 set_timer(ch->parent);
1034 wp_starttimer(ch->parent);
1035 agg_unlock(ch->parent);
1039 aggch_stop_adc(struct agg_rchinfo *ch)
1043 agg_lock(ch->parent);
1045 /* to mark that this channel no longer needs further intrs. */
1046 ch->parent->active &= ~(1 << ch->parent->playchns);
1048 for (apuch = 0; apuch < 4; apuch++)
1049 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1050 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1052 if (ch->parent->active) {
1053 set_timer(ch->parent);
1054 wp_starttimer(ch->parent);
1056 wp_stoptimer(ch->parent);
1057 agg_power(ch->parent, powerstate_idle);
1059 agg_unlock(ch->parent);
1063 * Feed from L/R channel of ADC to destination with stereo interleaving.
1064 * This function expects n not overwrapping the buffer boundary.
1065 * Note that n is measured in sample unit.
1067 * XXX - this function works in 16bit stereo format only.
1070 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1074 for (end = l + n; l < end; ) {
1081 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1086 agg_lock(ch->parent);
1087 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1088 agg_unlock(ch->parent);
1089 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1091 src2 = ch->src + ch->parent->bufsz/4;
1094 interleave(ch->src + last, src2 + last,
1095 ch->sink + 2*last, ch->buflen/2 - last);
1096 interleave(ch->src, src2,
1098 } else if (cur > last)
1099 interleave(ch->src + last, src2 + last,
1100 ch->sink + 2*last, cur - last);
1105 * Feed from R channel of ADC and mixdown to destination L/center.
1106 * This function expects n not overwrapping the buffer boundary.
1107 * Note that n is measured in sample unit.
1109 * XXX - this function works in 16bit monoral format only.
1112 mixdown(int16_t *src, int16_t *dest, unsigned n)
1116 for (end = dest + n; dest < end; dest++)
1117 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1121 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1125 agg_lock(ch->parent);
1126 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1127 agg_unlock(ch->parent);
1128 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1132 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1133 mixdown(ch->src, ch->sink, cur);
1134 } else if (cur > last)
1135 mixdown(ch->src + last, ch->sink + last, cur - last);
1139 #ifdef AGG_JITTER_CORRECTION
1141 * Stereo jitter suppressor.
1142 * Sometimes playback pointers differ in stereo-paired channels.
1143 * Calling this routine within intr fixes the problem.
1146 suppress_jitter(struct agg_chinfo *ch)
1149 int cp1, cp2, diff /*, halfsize*/ ;
1151 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1152 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1153 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1155 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1156 if (diff > 1 /* && diff < halfsize*/ )
1157 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1163 suppress_rec_jitter(struct agg_rchinfo *ch)
1165 int cp1, cp2, diff /*, halfsize*/ ;
1167 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1168 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1169 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1170 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1172 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1173 if (diff > 1 /* && diff < halfsize*/ )
1174 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1180 calc_timer_div(struct agg_chinfo *ch)
1187 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1192 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1193 + speed - 1) / speed;
1197 calc_timer_div_rch(struct agg_rchinfo *ch)
1204 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1208 return (48000 * (ch->blklen << (!ch->stereo))
1209 + speed - 1) / speed;
1213 set_timer(struct agg_info *ess)
1216 u_int dv = 32 << 7, newdv;
1218 for (i = 0; i < ess->playchns; i++)
1219 if ((ess->active & (1 << i)) &&
1220 (dv > (newdv = calc_timer_div(ess->pch + i))))
1222 if ((ess->active & (1 << i)) &&
1223 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1226 wp_settimer(ess, dv);
1230 /* -----------------------------
1234 /* AC97 mixer interface. */
1237 agg_ac97_init(kobj_t obj, void *sc)
1239 struct agg_info *ess = sc;
1241 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1245 agg_ac97_read(kobj_t obj, void *sc, int regno)
1247 struct agg_info *ess = sc;
1250 /* XXX sound locking violation: agg_lock(ess); */
1251 ret = agg_rdcodec(ess, regno);
1252 /* agg_unlock(ess); */
1257 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1259 struct agg_info *ess = sc;
1262 /* XXX sound locking violation: agg_lock(ess); */
1263 ret = agg_wrcodec(ess, regno, data);
1264 /* agg_unlock(ess); */
1269 static kobj_method_t agg_ac97_methods[] = {
1270 KOBJMETHOD(ac97_init, agg_ac97_init),
1271 KOBJMETHOD(ac97_read, agg_ac97_read),
1272 KOBJMETHOD(ac97_write, agg_ac97_write),
1275 AC97_DECLARE(agg_ac97);
1278 /* -------------------------------------------------------------------- */
1280 /* Playback channel. */
1283 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1284 struct pcm_channel *c, int dir)
1286 struct agg_info *ess = devinfo;
1287 struct agg_chinfo *ch;
1288 bus_addr_t physaddr;
1291 KASSERT((dir == PCMDIR_PLAY),
1292 ("aggpch_init() called for RECORDING channel!"));
1293 ch = ess->pch + ess->playchns;
1298 ch->num = ess->playchns;
1300 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr);
1303 ch->phys = physaddr;
1304 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1306 sndbuf_setup(b, p, ess->bufsz);
1307 ch->blklen = sndbuf_getblksz(b) / 2;
1308 ch->buflen = sndbuf_getsize(b) / 2;
1315 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1317 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1321 /* sort pchs by phys address */
1322 for (i = 0; i < n; i++) {
1323 for (j = 0; j < i; j++)
1324 if (chans[i].phys < pchs[j]->phys) {
1325 for (k = i; k > j; k--)
1326 pchs[k] = pchs[k - 1];
1329 pchs[j] = chans + i;
1332 /* use new base register if next buffer can not be addressed
1333 via current base. */
1334 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1335 base = pchs[0]->base;
1336 for (k = 1, i = 1; i < n; i++) {
1337 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1338 /* not addressable: assign new base */
1339 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1341 pchs[i]->base = base;
1346 printf("Total of %d bases are assigned.\n", k);
1347 for (i = 0; i < n; i++) {
1348 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1349 i, (long long)chans[i].phys,
1350 (long long)(chans[i].phys -
1351 chans[i].base) >> 1);
1357 aggpch_free(kobj_t obj, void *data)
1359 struct agg_chinfo *ch = data;
1360 struct agg_info *ess = ch->parent;
1362 /* free up buffer - called after channel stopped */
1363 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer));
1365 /* return 0 if ok */
1370 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1372 struct agg_chinfo *ch = data;
1374 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1376 ch->stereo = ch->qs16 = ch->us = 0;
1377 if (AFMT_CHANNEL(format) > 1)
1380 if (format & AFMT_U8 || format & AFMT_S8) {
1381 if (format & AFMT_U8)
1389 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1392 ((struct agg_chinfo*)data)->speed = speed;
1398 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1400 struct agg_chinfo *ch = data;
1403 /* try to keep at least 20msec DMA space */
1404 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1405 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1407 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1408 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1409 blkcnt = sndbuf_getblkcnt(ch->buffer);
1410 blocksize = sndbuf_getblksz(ch->buffer);
1412 sndbuf_setblkcnt(ch->buffer, blkcnt);
1413 sndbuf_setblksz(ch->buffer, blocksize);
1416 ch->blklen = blocksize / 2;
1417 ch->buflen = blkcnt * blocksize / 2;
1422 aggpch_trigger(kobj_t obj, void *data, int go)
1424 struct agg_chinfo *ch = data;
1427 case PCMTRIG_EMLDMAWR:
1430 aggch_start_dac(ch);
1441 aggpch_getptr(kobj_t obj, void *data)
1443 struct agg_chinfo *ch = data;
1446 agg_lock(ch->parent);
1447 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1448 agg_unlock(ch->parent);
1450 return ch->qs16 && ch->stereo
1451 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1452 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1455 static struct pcmchan_caps *
1456 aggpch_getcaps(kobj_t obj, void *data)
1458 static u_int32_t playfmt[] = {
1459 SND_FORMAT(AFMT_U8, 1, 0),
1460 SND_FORMAT(AFMT_U8, 2, 0),
1461 SND_FORMAT(AFMT_S8, 1, 0),
1462 SND_FORMAT(AFMT_S8, 2, 0),
1463 SND_FORMAT(AFMT_S16_LE, 1, 0),
1464 SND_FORMAT(AFMT_S16_LE, 2, 0),
1467 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1473 static kobj_method_t aggpch_methods[] = {
1474 KOBJMETHOD(channel_init, aggpch_init),
1475 KOBJMETHOD(channel_free, aggpch_free),
1476 KOBJMETHOD(channel_setformat, aggpch_setformat),
1477 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1478 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1479 KOBJMETHOD(channel_trigger, aggpch_trigger),
1480 KOBJMETHOD(channel_getptr, aggpch_getptr),
1481 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1484 CHANNEL_DECLARE(aggpch);
1487 /* -------------------------------------------------------------------- */
1489 /* Recording channel. */
1492 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1493 struct pcm_channel *c, int dir)
1495 struct agg_info *ess = devinfo;
1496 struct agg_rchinfo *ch;
1499 KASSERT((dir == PCMDIR_REC),
1500 ("aggrch_init() called for PLAYBACK channel!"));
1507 /* Uses the bottom-half of the status buffer. */
1508 p = ess->stat + ess->bufsz;
1509 ch->phys = ess->phys + ess->bufsz;
1510 ch->base = ess->phys;
1511 ch->src = (int16_t *)(p + ess->bufsz);
1512 ch->srcphys = ch->phys + ess->bufsz;
1513 ch->sink = (int16_t *)p;
1515 sndbuf_setup(b, p, ess->bufsz);
1516 ch->blklen = sndbuf_getblksz(b) / 2;
1517 ch->buflen = sndbuf_getsize(b) / 2;
1523 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1525 struct agg_rchinfo *ch = data;
1527 if (!(format & AFMT_S16_LE))
1529 if (AFMT_CHANNEL(format) > 1)
1537 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1540 ((struct agg_rchinfo*)data)->speed = speed;
1546 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1548 struct agg_rchinfo *ch = data;
1551 /* try to keep at least 20msec DMA space */
1552 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1553 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1555 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1556 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1557 blkcnt = sndbuf_getblkcnt(ch->buffer);
1558 blocksize = sndbuf_getblksz(ch->buffer);
1560 sndbuf_setblkcnt(ch->buffer, blkcnt);
1561 sndbuf_setblksz(ch->buffer, blocksize);
1564 ch->blklen = blocksize / 2;
1565 ch->buflen = blkcnt * blocksize / 2;
1570 aggrch_trigger(kobj_t obj, void *sc, int go)
1572 struct agg_rchinfo *ch = sc;
1575 case PCMTRIG_EMLDMARD:
1577 aggch_feed_adc_stereo(ch);
1579 aggch_feed_adc_mono(ch);
1582 aggch_start_adc(ch);
1593 aggrch_getptr(kobj_t obj, void *sc)
1595 struct agg_rchinfo *ch = sc;
1597 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1600 static struct pcmchan_caps *
1601 aggrch_getcaps(kobj_t obj, void *sc)
1603 static u_int32_t recfmt[] = {
1604 SND_FORMAT(AFMT_S16_LE, 1, 0),
1605 SND_FORMAT(AFMT_S16_LE, 2, 0),
1608 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1613 static kobj_method_t aggrch_methods[] = {
1614 KOBJMETHOD(channel_init, aggrch_init),
1615 /* channel_free: no-op */
1616 KOBJMETHOD(channel_setformat, aggrch_setformat),
1617 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1618 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1619 KOBJMETHOD(channel_trigger, aggrch_trigger),
1620 KOBJMETHOD(channel_getptr, aggrch_getptr),
1621 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1624 CHANNEL_DECLARE(aggrch);
1627 /* -----------------------------
1634 struct agg_info* ess = sc;
1635 register u_int8_t status;
1639 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1643 /* Acknowledge intr. */
1644 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1646 if (status & HOSTINT_STAT_DSOUND) {
1647 #ifdef AGG_JITTER_CORRECTION
1650 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1651 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1652 #ifdef AGG_JITTER_CORRECTION
1653 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1654 if (ess->active & m)
1655 suppress_jitter(ess->pch + i);
1657 if (ess->active & m)
1658 suppress_rec_jitter(&ess->rch);
1661 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1662 if (ess->active & m) {
1663 if (ess->curpwr <= PCI_POWERSTATE_D1)
1664 chn_intr(ess->pch[i].channel);
1671 if ((ess->active & m)
1672 && ess->curpwr <= PCI_POWERSTATE_D1)
1673 chn_intr(ess->rch.channel);
1675 #ifdef AGG_JITTER_CORRECTION
1681 if (status & HOSTINT_STAT_HWVOL) {
1682 register u_int8_t event;
1685 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1686 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1691 mixer_hwvol_step(ess->dev, 1, 1);
1694 mixer_hwvol_step(ess->dev, -1, -1);
1699 if (event & HWVOL_MUTE) {
1700 mixer_hwvol_mute(ess->dev);
1703 device_printf(ess->dev,
1704 "%s: unknown HWVOL event 0x%x\n",
1705 device_get_nameunit(ess->dev), event);
1711 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1713 bus_addr_t *phys = arg;
1715 *phys = error? 0 : segs->ds_addr;
1718 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1719 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1725 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys)
1730 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, &map))
1732 if (bus_dmamap_load(dmat, map, buf, sz, setmap, phys, 0)
1734 bus_dmamem_free(dmat, buf, map);
1741 dma_free(bus_dma_tag_t dmat, void *buf)
1743 bus_dmamem_free(dmat, buf, NULL);
1747 agg_probe(device_t dev)
1751 switch (pci_get_devid(dev)) {
1752 case MAESTRO_1_PCI_ID:
1753 s = "ESS Technology Maestro-1";
1756 case MAESTRO_2_PCI_ID:
1757 s = "ESS Technology Maestro-2";
1760 case MAESTRO_2E_PCI_ID:
1761 s = "ESS Technology Maestro-2E";
1765 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1766 device_set_desc(dev, s);
1767 return BUS_PROBE_DEFAULT;
1773 agg_attach(device_t dev)
1775 struct agg_info *ess = NULL;
1777 int regid = PCIR_BAR(0);
1778 struct resource *reg = NULL;
1779 struct ac97_info *codec = NULL;
1781 struct resource *irq = NULL;
1783 char status[SND_STATUSLEN];
1786 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1789 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1790 MTX_DEF | MTX_RECURSE);
1791 if (!mtx_initialized(&ess->lock)) {
1792 device_printf(dev, "failed to create a mutex.\n");
1797 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1798 "dac", &dacn) == 0) {
1801 else if (dacn > AGG_MAXPLAYCH)
1802 dacn = AGG_MAXPLAYCH;
1804 dacn = AGG_MAXPLAYCH;
1806 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1807 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1808 /*align */ 4, 1 << (16+1),
1809 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1810 /*filter*/ NULL, NULL,
1811 /*size */ ess->bufsz, 1, 0x3ffff,
1813 #if __FreeBSD_version >= 501102
1814 /*lock */ busdma_lock_mutex, &Giant,
1816 &ess->buf_dmat) != 0) {
1817 device_printf(dev, "unable to create dma tag\n");
1822 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1823 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1825 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1826 /*filter*/ NULL, NULL,
1827 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1829 #if __FreeBSD_version >= 501102
1830 /*lock */ busdma_lock_mutex, &Giant,
1832 &ess->stat_dmat) != 0) {
1833 device_printf(dev, "unable to create dma tag\n");
1838 /* Allocate the room for brain-damaging status buffer. */
1839 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys);
1840 if (ess->stat == NULL) {
1841 device_printf(dev, "cannot allocate status buffer\n");
1846 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1847 (long long)ess->phys);
1849 /* State D0-uninitialized. */
1850 ess->curpwr = PCI_POWERSTATE_D3;
1851 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1853 pci_enable_busmaster(dev);
1855 /* Allocate resources. */
1856 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id, RF_ACTIVE);
1860 ess->st = rman_get_bustag(reg);
1861 ess->sh = rman_get_bushandle(reg);
1863 device_printf(dev, "unable to map register space\n");
1867 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1868 RF_ACTIVE | RF_SHAREABLE);
1873 device_printf(dev, "unable to map interrupt\n");
1878 /* Setup resources. */
1879 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1880 device_printf(dev, "unable to setup interrupt\n");
1886 /* Transition from D0-uninitialized to D0. */
1888 agg_power(ess, PCI_POWERSTATE_D0);
1889 if (agg_rdcodec(ess, 0) == 0x80) {
1890 /* XXX - TODO: PT101 */
1892 device_printf(dev, "PT101 codec detected!\n");
1897 codec = AC97_CREATE(dev, ess, agg_ac97);
1898 if (codec == NULL) {
1899 device_printf(dev, "failed to create AC97 codec softc!\n");
1903 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1904 device_printf(dev, "mixer initialization failed!\n");
1910 ret = pcm_register(dev, ess, dacn, 1);
1914 mixer_hwvol_init(dev);
1916 agg_power(ess, powerstate_init);
1918 for (data = 0; data < dacn; data++)
1919 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1920 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1921 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1923 snprintf(status, SND_STATUSLEN,
1924 "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d",
1925 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1926 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1927 pcm_setstatus(dev, status);
1933 ac97_destroy(codec);
1935 bus_teardown_intr(dev, irq, ih);
1937 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1939 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1941 if (ess->stat != NULL)
1942 dma_free(ess->stat_dmat, ess->stat);
1943 if (ess->stat_dmat != NULL)
1944 bus_dma_tag_destroy(ess->stat_dmat);
1945 if (ess->buf_dmat != NULL)
1946 bus_dma_tag_destroy(ess->buf_dmat);
1947 if (mtx_initialized(&ess->lock))
1948 mtx_destroy(&ess->lock);
1949 free(ess, M_DEVBUF);
1956 agg_detach(device_t dev)
1958 struct agg_info *ess = pcm_getdevinfo(dev);
1962 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1963 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1967 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1973 r = pcm_unregister(dev);
1975 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1980 agg_power(ess, PCI_POWERSTATE_D3);
1983 bus_teardown_intr(dev, ess->irq, ess->ih);
1984 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1985 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1986 dma_free(ess->stat_dmat, ess->stat);
1987 bus_dma_tag_destroy(ess->stat_dmat);
1988 bus_dma_tag_destroy(ess->buf_dmat);
1989 mtx_destroy(&ess->lock);
1990 free(ess, M_DEVBUF);
1995 agg_suspend(device_t dev)
1997 struct agg_info *ess = pcm_getdevinfo(dev);
1999 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
2001 agg_power(ess, PCI_POWERSTATE_D3);
2008 agg_resume(device_t dev)
2011 struct agg_info *ess = pcm_getdevinfo(dev);
2013 for (i = 0; i < ess->playchns; i++)
2014 if (ess->active & (1 << i))
2015 aggch_start_dac(ess->pch + i);
2016 if (ess->active & (1 << i))
2017 aggch_start_adc(&ess->rch);
2021 agg_power(ess, powerstate_init);
2024 if (mixer_reinit(dev)) {
2025 device_printf(dev, "unable to reinitialize the mixer\n");
2033 agg_shutdown(device_t dev)
2035 struct agg_info *ess = pcm_getdevinfo(dev);
2038 agg_power(ess, PCI_POWERSTATE_D3);
2045 static device_method_t agg_methods[] = {
2046 DEVMETHOD(device_probe, agg_probe),
2047 DEVMETHOD(device_attach, agg_attach),
2048 DEVMETHOD(device_detach, agg_detach),
2049 DEVMETHOD(device_suspend, agg_suspend),
2050 DEVMETHOD(device_resume, agg_resume),
2051 DEVMETHOD(device_shutdown, agg_shutdown),
2056 static driver_t agg_driver = {
2062 /*static devclass_t pcm_devclass;*/
2064 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2065 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2066 MODULE_VERSION(snd_maestro, 1);