2 * Copyright (c) 2012 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
40 #include <machine/bus.h>
41 #include <machine/fdt.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_cpu.h>
45 #include <dev/uart/uart_bus.h>
46 #include <dev/uart/uart_dev_imx.h>
49 #include <arm/freescale/imx/imx_ccmvar.h>
52 * Low-level UART interface.
54 static int imx_uart_probe(struct uart_bas *bas);
55 static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
56 static void imx_uart_term(struct uart_bas *bas);
57 static void imx_uart_putc(struct uart_bas *bas, int);
58 static int imx_uart_rxready(struct uart_bas *bas);
59 static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
61 static struct uart_ops uart_imx_uart_ops = {
62 .probe = imx_uart_probe,
63 .init = imx_uart_init,
64 .term = imx_uart_term,
65 .putc = imx_uart_putc,
66 .rxready = imx_uart_rxready,
67 .getc = imx_uart_getc,
70 #if 0 /* Handy when debugging. */
72 dumpregs(struct uart_bas *bas, const char * msg)
77 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x "
78 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n",
80 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),
81 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),
82 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));
87 imx_uart_probe(struct uart_bas *bas)
94 imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
95 int stopbits, int parity)
97 uint32_t baseclk, reg;
99 /* Enable the device and the RX/TX channels. */
100 SET(bas, REG(UCR1), FLD(UCR1, UARTEN));
101 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));
109 ENA(bas, UCR2, STPB);
111 DIS(bas, UCR2, STPB);
114 case UART_PARITY_ODD:
115 DIS(bas, UCR2, PROE);
116 ENA(bas, UCR2, PREN);
118 case UART_PARITY_EVEN:
119 ENA(bas, UCR2, PROE);
120 ENA(bas, UCR2, PREN);
122 case UART_PARITY_MARK:
123 case UART_PARITY_SPACE:
124 /* FALLTHROUGH: Hardware doesn't support mark/space. */
125 case UART_PARITY_NONE:
127 DIS(bas, UCR2, PREN);
132 * The hardware has an extremely flexible baud clock: it allows setting
133 * both the numerator and denominator of the divider, as well as a
134 * separate pre-divider. We simplify the problem of coming up with a
135 * workable pair of numbers by assuming a pre-divider and numerator of
136 * one because our base clock is so fast we can reach virtually any
137 * reasonable speed with a simple divisor. The numerator value actually
138 * includes the 16x over-sampling (so a value of 16 means divide by 1);
139 * the register value is the numerator-1, so we have a hard-coded 15.
140 * Note that a quirk of the hardware requires that both UBIR and UBMR be
141 * set back to back in order for the change to take effect.
144 baseclk = imx_ccm_uart_hz();
145 reg = GETREG(bas, REG(UFCR));
146 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;
147 SETREG(bas, REG(UFCR), reg);
148 SETREG(bas, REG(UBIR), 15);
149 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);
154 imx_uart_term(struct uart_bas *bas)
160 imx_uart_putc(struct uart_bas *bas, int c)
163 while (!(IS(bas, USR2, TXFE)))
165 SETREG(bas, REG(UTXD), c);
169 imx_uart_rxready(struct uart_bas *bas)
172 return ((IS(bas, USR2, RDR)) ? 1 : 0);
176 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
181 while (!(IS(bas, USR2, RDR)))
184 c = GETREG(bas, REG(URXD));
187 if (c & FLD(URXD, BRK)) {
196 * High-level UART interface.
198 struct imx_uart_softc {
199 struct uart_softc base;
202 static int imx_uart_bus_attach(struct uart_softc *);
203 static int imx_uart_bus_detach(struct uart_softc *);
204 static int imx_uart_bus_flush(struct uart_softc *, int);
205 static int imx_uart_bus_getsig(struct uart_softc *);
206 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
207 static int imx_uart_bus_ipend(struct uart_softc *);
208 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
209 static int imx_uart_bus_probe(struct uart_softc *);
210 static int imx_uart_bus_receive(struct uart_softc *);
211 static int imx_uart_bus_setsig(struct uart_softc *, int);
212 static int imx_uart_bus_transmit(struct uart_softc *);
213 static void imx_uart_bus_grab(struct uart_softc *);
214 static void imx_uart_bus_ungrab(struct uart_softc *);
216 static kobj_method_t imx_uart_methods[] = {
217 KOBJMETHOD(uart_attach, imx_uart_bus_attach),
218 KOBJMETHOD(uart_detach, imx_uart_bus_detach),
219 KOBJMETHOD(uart_flush, imx_uart_bus_flush),
220 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
221 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
222 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
223 KOBJMETHOD(uart_param, imx_uart_bus_param),
224 KOBJMETHOD(uart_probe, imx_uart_bus_probe),
225 KOBJMETHOD(uart_receive, imx_uart_bus_receive),
226 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
227 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
228 KOBJMETHOD(uart_grab, imx_uart_bus_grab),
229 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab),
233 struct uart_class uart_imx_class = {
236 sizeof(struct imx_uart_softc),
237 .uc_ops = &uart_imx_uart_ops,
239 .uc_rclk = 24000000 /* TODO: get value from CCM */
242 #define SIGCHG(c, i, s, d) \
244 i |= (i & s) ? s : s | d; \
246 i = (i & s) ? (i & ~s) | d : i; \
250 imx_uart_bus_attach(struct uart_softc *sc)
252 struct uart_bas *bas;
253 struct uart_devinfo *di;
256 if (sc->sc_sysdev != NULL) {
258 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
261 imx_uart_init(bas, 115200, 8, 1, 0);
264 (void)imx_uart_bus_getsig(sc);
266 ENA(bas, UCR4, DREN);
267 DIS(bas, UCR1, RRDYEN);
268 DIS(bas, UCR1, IDEN);
269 DIS(bas, UCR3, RXDSEN);
270 DIS(bas, UCR2, ATEN);
271 DIS(bas, UCR1, TXMPTYEN);
272 DIS(bas, UCR1, TRDYEN);
273 DIS(bas, UCR4, TCEN);
274 DIS(bas, UCR4, OREN);
275 ENA(bas, UCR4, BKEN);
276 DIS(bas, UCR4, WKEN);
277 DIS(bas, UCR1, ADEN);
278 DIS(bas, UCR3, ACIEN);
279 DIS(bas, UCR2, ESCI);
280 DIS(bas, UCR4, ENIRI);
281 DIS(bas, UCR3, AIRINTEN);
282 DIS(bas, UCR3, AWAKEN);
283 DIS(bas, UCR3, FRAERREN);
284 DIS(bas, UCR3, PARERREN);
285 DIS(bas, UCR1, RTSDEN);
286 DIS(bas, UCR2, RTSEN);
287 DIS(bas, UCR3, DTREN);
290 DIS(bas, UCR3, DTRDEN);
291 ENA(bas, UCR2, IRTS);
292 ENA(bas, UCR3, RXDMUXSEL);
294 /* ACK all interrupts */
295 SETREG(bas, REG(USR1), 0xffff);
296 SETREG(bas, REG(USR2), 0xffff);
301 imx_uart_bus_detach(struct uart_softc *sc)
304 SETREG(&sc->sc_bas, REG(UCR4), 0);
310 imx_uart_bus_flush(struct uart_softc *sc, int what)
318 imx_uart_bus_getsig(struct uart_softc *sc)
320 uint32_t new, old, sig;
326 uart_lock(sc->sc_hwmtx);
327 bes = GETREG(&sc->sc_bas, REG(USR2));
328 uart_unlock(sc->sc_hwmtx);
329 /* XXX: chip can show delta */
330 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
331 new = sig & ~SER_MASK_DELTA;
332 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
338 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
340 struct uart_bas *bas;
345 uart_lock(sc->sc_hwmtx);
347 case UART_IOCTL_BREAK:
350 case UART_IOCTL_BAUD:
352 *(int*)data = 115200;
358 uart_unlock(sc->sc_hwmtx);
364 imx_uart_bus_ipend(struct uart_softc *sc)
366 struct uart_bas *bas;
374 uart_lock(sc->sc_hwmtx);
376 /* Read pending interrupts */
377 usr1 = GETREG(bas, REG(USR1));
378 usr2 = GETREG(bas, REG(USR2));
380 SETREG(bas, REG(USR1), usr1);
381 SETREG(bas, REG(USR2), usr2);
383 ucr1 = GETREG(bas, REG(UCR1));
384 ucr4 = GETREG(bas, REG(UCR4));
386 if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) {
387 DIS(bas, UCR1, TXMPTYEN);
389 ipend |= SER_INT_TXIDLE;
391 if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) {
392 DIS(bas, UCR4, DREN);
393 /* Wow, new char on input */
394 ipend |= SER_INT_RXREADY;
396 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
397 ipend |= SER_INT_BREAK;
399 uart_unlock(sc->sc_hwmtx);
405 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
406 int stopbits, int parity)
409 uart_lock(sc->sc_hwmtx);
410 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
411 uart_unlock(sc->sc_hwmtx);
416 imx_uart_bus_probe(struct uart_softc *sc)
420 error = imx_uart_probe(&sc->sc_bas);
427 device_set_desc(sc->sc_dev, "Freescale i.MX UART");
432 imx_uart_bus_receive(struct uart_softc *sc)
434 struct uart_bas *bas;
438 uart_lock(sc->sc_hwmtx);
440 /* Read while we have anything in FIFO */
441 while (IS(bas, USR2, RDR)) {
442 if (uart_rx_full(sc)) {
443 /* No space left in input buffer */
444 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
448 xc = GETREG(bas, REG(URXD));
450 /* We have valid char */
451 if (xc & FLD(URXD, CHARRDY))
452 out = xc & 0x000000ff;
454 if (xc & FLD(URXD, FRMERR))
455 out |= UART_STAT_FRAMERR;
456 if (xc & FLD(URXD, PRERR))
457 out |= UART_STAT_PARERR;
458 if (xc & FLD(URXD, OVRRUN))
459 out |= UART_STAT_OVERRUN;
460 if (xc & FLD(URXD, BRK))
461 out |= UART_STAT_BREAK;
463 uart_rx_put(sc, out);
465 /* Reenable Data Ready interrupt */
466 ENA(bas, UCR4, DREN);
468 uart_unlock(sc->sc_hwmtx);
473 imx_uart_bus_setsig(struct uart_softc *sc, int sig)
480 imx_uart_bus_transmit(struct uart_softc *sc)
482 struct uart_bas *bas = &sc->sc_bas;
486 uart_lock(sc->sc_hwmtx);
489 for (i = 0; i < sc->sc_txdatasz; i++) {
490 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
494 /* Call me when ready */
495 ENA(bas, UCR1, TXMPTYEN);
497 uart_unlock(sc->sc_hwmtx);
503 imx_uart_bus_grab(struct uart_softc *sc)
505 struct uart_bas *bas = &sc->sc_bas;
508 uart_lock(sc->sc_hwmtx);
509 DIS(bas, UCR4, DREN);
510 uart_unlock(sc->sc_hwmtx);
514 imx_uart_bus_ungrab(struct uart_softc *sc)
516 struct uart_bas *bas = &sc->sc_bas;
519 uart_lock(sc->sc_hwmtx);
520 ENA(bas, UCR4, DREN);
521 uart_unlock(sc->sc_hwmtx);