3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
36 * NOTE: The current implementation only supports Device Side Mode!
39 #include <sys/stdint.h>
40 #include <sys/stddef.h>
41 #include <sys/param.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/condvar.h>
51 #include <sys/sysctl.h>
53 #include <sys/unistd.h>
54 #include <sys/callout.h>
55 #include <sys/malloc.h>
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
61 #define USB_DEBUG_VAR musbotgdebug
63 #include <dev/usb/usb_core.h>
64 #include <dev/usb/usb_debug.h>
65 #include <dev/usb/usb_busdma.h>
66 #include <dev/usb/usb_process.h>
67 #include <dev/usb/usb_transfer.h>
68 #include <dev/usb/usb_device.h>
69 #include <dev/usb/usb_hub.h>
70 #include <dev/usb/usb_util.h>
72 #include <dev/usb/usb_controller.h>
73 #include <dev/usb/usb_bus.h>
74 #include <dev/usb/controller/musb_otg.h>
76 #define MUSBOTG_INTR_ENDPT 1
78 #define MUSBOTG_BUS2SC(bus) \
79 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
80 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
82 #define MUSBOTG_PC2SC(pc) \
83 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
86 static int musbotgdebug = 0;
88 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
89 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
90 &musbotgdebug, 0, "Debug level");
97 struct usb_bus_methods musbotg_bus_methods;
98 struct usb_pipe_methods musbotg_device_bulk_methods;
99 struct usb_pipe_methods musbotg_device_ctrl_methods;
100 struct usb_pipe_methods musbotg_device_intr_methods;
101 struct usb_pipe_methods musbotg_device_isoc_methods;
103 /* Control transfers: Device mode */
104 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
105 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
106 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
107 static musbotg_cmd_t musbotg_dev_ctrl_status;
109 /* Control transfers: Host mode */
110 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
111 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
112 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
113 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
114 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
116 /* Bulk, Interrupt, Isochronous: Device mode */
117 static musbotg_cmd_t musbotg_dev_data_rx;
118 static musbotg_cmd_t musbotg_dev_data_tx;
120 /* Bulk, Interrupt, Isochronous: Host mode */
121 static musbotg_cmd_t musbotg_host_data_rx;
122 static musbotg_cmd_t musbotg_host_data_tx;
124 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
125 static void musbotg_do_poll(struct usb_bus *);
126 static void musbotg_standard_done(struct usb_xfer *);
127 static void musbotg_interrupt_poll(struct musbotg_softc *);
128 static void musbotg_root_intr(struct musbotg_softc *);
129 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td);
130 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
131 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
134 * Here is a configuration that the chip supports.
136 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
139 .max_in_frame_size = 64,/* fixed */
140 .max_out_frame_size = 64, /* fixed */
142 .support_control = 1,
147 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td)
154 /* In device mode each EP got its own channel */
155 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
156 musbotg_ep_int_set(sc, ep, 1);
161 * All control transactions go through EP0
164 if (sc->sc_channel_mask & (1 << 0))
166 sc->sc_channel_mask |= (1 << 0);
167 musbotg_ep_int_set(sc, ep, 1);
171 for (ch = 1; ch < MUSB2_EP_MAX; ch++) {
172 if (!(sc->sc_channel_mask & (1 << ch))) {
173 sc->sc_channel_mask |= (1 << ch);
174 musbotg_ep_int_set(sc, ch, 1);
179 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
185 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
188 DPRINTFN(1, "ep_no=%d\n", td->channel);
190 if (sc->sc_mode == MUSB2_DEVICE_MODE)
195 if (td->channel == -1)
198 musbotg_ep_int_set(sc, td->channel, 0);
199 sc->sc_channel_mask &= ~(1 << td->channel);
205 musbotg_get_hw_ep_profile(struct usb_device *udev,
206 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
208 struct musbotg_softc *sc;
210 sc = MUSBOTG_BUS2SC(udev->bus);
213 /* control endpoint */
214 *ppf = musbotg_ep_profile;
215 } else if (ep_addr <= sc->sc_ep_max) {
216 /* other endpoints */
217 *ppf = sc->sc_hw_ep_profile + ep_addr;
224 musbotg_clocks_on(struct musbotg_softc *sc)
226 if (sc->sc_flags.clocks_off &&
227 sc->sc_flags.port_powered) {
231 if (sc->sc_clocks_on) {
232 (sc->sc_clocks_on) (sc->sc_clocks_arg);
234 sc->sc_flags.clocks_off = 0;
236 /* XXX enable Transceiver */
241 musbotg_clocks_off(struct musbotg_softc *sc)
243 if (!sc->sc_flags.clocks_off) {
247 /* XXX disable Transceiver */
249 if (sc->sc_clocks_off) {
250 (sc->sc_clocks_off) (sc->sc_clocks_arg);
252 sc->sc_flags.clocks_off = 1;
257 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
261 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
263 temp |= MUSB2_MASK_SOFTC;
265 temp &= ~MUSB2_MASK_SOFTC;
267 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
271 musbotg_pull_up(struct musbotg_softc *sc)
273 /* pullup D+, if possible */
275 if (!sc->sc_flags.d_pulled_up &&
276 sc->sc_flags.port_powered) {
277 sc->sc_flags.d_pulled_up = 1;
278 musbotg_pull_common(sc, 1);
283 musbotg_pull_down(struct musbotg_softc *sc)
285 /* pulldown D+, if possible */
287 if (sc->sc_flags.d_pulled_up) {
288 sc->sc_flags.d_pulled_up = 0;
289 musbotg_pull_common(sc, 0);
294 musbotg_suspend_host(struct musbotg_softc *sc)
298 if (sc->sc_flags.status_suspend) {
302 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
303 temp |= MUSB2_MASK_SUSPMODE;
304 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
305 sc->sc_flags.status_suspend = 1;
309 musbotg_wakeup_host(struct musbotg_softc *sc)
313 if (!(sc->sc_flags.status_suspend)) {
317 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
318 temp &= ~MUSB2_MASK_SUSPMODE;
319 temp |= MUSB2_MASK_RESUME;
320 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
322 /* wait 20 milliseconds */
323 /* Wait for reset to complete. */
324 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
326 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
327 temp &= ~MUSB2_MASK_RESUME;
328 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
330 sc->sc_flags.status_suspend = 0;
334 musbotg_wakeup_peer(struct musbotg_softc *sc)
338 if (!(sc->sc_flags.status_suspend)) {
342 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
343 temp |= MUSB2_MASK_RESUME;
344 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
346 /* wait 8 milliseconds */
347 /* Wait for reset to complete. */
348 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
350 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
351 temp &= ~MUSB2_MASK_RESUME;
352 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
356 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
358 DPRINTFN(4, "addr=%d\n", addr);
360 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
364 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
366 struct musbotg_softc *sc;
367 struct usb_device_request req;
371 /* get pointer to softc */
372 sc = MUSBOTG_PC2SC(td->pc);
374 if (td->channel == -1)
375 td->channel = musbotg_channel_alloc(sc, td);
377 /* EP0 is busy, wait */
378 if (td->channel == -1)
381 DPRINTFN(1, "ep_no=%d\n", td->channel);
383 /* select endpoint 0 */
384 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
386 /* read out FIFO status */
387 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
389 DPRINTFN(4, "csr=0x%02x\n", csr);
392 * NOTE: If DATAEND is set we should not call the
393 * callback, hence the status stage is not complete.
395 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
396 /* do not stall at this point */
398 /* wait for interrupt */
399 DPRINTFN(0, "CSR0 DATAEND\n");
403 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
404 /* clear SENTSTALL */
405 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
406 /* get latest status */
407 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
408 /* update EP0 state */
411 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
413 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
414 MUSB2_MASK_CSR0L_SETUPEND_CLR);
415 /* get latest status */
416 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
417 /* update EP0 state */
420 if (sc->sc_ep0_busy) {
421 DPRINTFN(0, "EP0 BUSY\n");
424 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
427 /* clear did stall flag */
429 /* get the packet byte count */
430 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
432 /* verify data length */
433 if (count != td->remainder) {
434 DPRINTFN(0, "Invalid SETUP packet "
435 "length, %d bytes\n", count);
436 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
437 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
440 if (count != sizeof(req)) {
441 DPRINTFN(0, "Unsupported SETUP packet "
442 "length, %d bytes\n", count);
443 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
444 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
448 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
449 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
451 /* copy data into real buffer */
452 usbd_copy_in(td->pc, 0, &req, sizeof(req));
454 td->offset = sizeof(req);
457 /* set pending command */
458 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
460 /* we need set stall or dataend after this */
463 /* sneak peek the set address */
464 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
465 (req.bRequest == UR_SET_ADDRESS)) {
466 sc->sc_dv_addr = req.wValue[0] & 0x7F;
468 sc->sc_dv_addr = 0xFF;
471 musbotg_channel_free(sc, td);
472 return (0); /* complete */
475 /* abort any ongoing transfer */
476 if (!td->did_stall) {
477 DPRINTFN(4, "stalling\n");
478 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
479 MUSB2_MASK_CSR0L_SENDSTALL);
482 return (1); /* not complete */
486 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
488 struct musbotg_softc *sc;
489 struct usb_device_request req;
492 /* get pointer to softc */
493 sc = MUSBOTG_PC2SC(td->pc);
495 if (td->channel == -1)
496 td->channel = musbotg_channel_alloc(sc, td);
498 /* EP0 is busy, wait */
499 if (td->channel == -1)
502 DPRINTFN(1, "ep_no=%d\n", td->channel);
504 /* select endpoint 0 */
505 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
507 /* read out FIFO status */
508 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
509 DPRINTFN(4, "csr=0x%02x\n", csr);
511 /* Not ready yet yet */
512 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
516 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
517 MUSB2_MASK_CSR0L_ERROR))
519 /* Clear status bit */
520 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
521 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
525 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
526 DPRINTFN(1, "NAK timeout\n");
528 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
529 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
530 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
531 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
532 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
533 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
534 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
535 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
537 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
541 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
548 musbotg_channel_free(sc, td);
552 /* Fifo is not empty and there is no NAK timeout */
553 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
556 /* check if we are complete */
557 if (td->remainder == 0) {
558 /* we are complete */
559 musbotg_channel_free(sc, td);
563 /* copy data into real buffer */
564 usbd_copy_out(td->pc, 0, &req, sizeof(req));
567 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
568 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
570 /* update offset and remainder */
571 td->offset += sizeof(req);
572 td->remainder -= sizeof(req);
575 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
576 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
577 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
578 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
579 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
583 MUSB2_MASK_CSR0L_TXPKTRDY |
584 MUSB2_MASK_CSR0L_SETUPPKT);
586 /* Just to be consistent, not used above */
587 td->transaction_started = 1;
589 return (1); /* in progress */
592 /* Control endpoint only data handling functions (RX/TX/SYNC) */
595 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
597 struct usb_page_search buf_res;
598 struct musbotg_softc *sc;
603 /* get pointer to softc */
604 sc = MUSBOTG_PC2SC(td->pc);
606 /* select endpoint 0 */
607 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
609 /* check if a command is pending */
610 if (sc->sc_ep0_cmd) {
611 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
614 /* read out FIFO status */
615 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
617 DPRINTFN(4, "csr=0x%02x\n", csr);
621 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
622 MUSB2_MASK_CSR0L_SENTSTALL)) {
623 if (td->remainder == 0) {
625 * We are actually complete and have
626 * received the next SETUP
628 DPRINTFN(4, "faking complete\n");
629 return (0); /* complete */
632 * USB Host Aborted the transfer.
635 return (0); /* complete */
637 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
638 return (1); /* not complete */
640 /* get the packet byte count */
641 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
643 /* verify the packet byte count */
644 if (count != td->max_frame_size) {
645 if (count < td->max_frame_size) {
646 /* we have a short packet */
650 /* invalid USB packet */
652 return (0); /* we are complete */
655 /* verify the packet byte count */
656 if (count > td->remainder) {
657 /* invalid USB packet */
659 return (0); /* we are complete */
664 usbd_get_page(td->pc, td->offset, &buf_res);
666 /* get correct length */
667 if (buf_res.length > count) {
668 buf_res.length = count;
670 /* check for unaligned memory address */
671 if (USB_P2U(buf_res.buffer) & 3) {
676 /* receive data 4 bytes at a time */
677 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
678 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
683 /* receive data 1 byte at a time */
684 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
686 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
688 usbd_copy_in(td->pc, td->offset,
689 sc->sc_bounce_buf, count);
691 /* update offset and remainder */
693 td->remainder -= count;
696 /* check if we can optimise */
697 if (buf_res.length >= 4) {
699 /* receive data 4 bytes at a time */
700 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
701 MUSB2_REG_EPFIFO(0), buf_res.buffer,
704 temp = buf_res.length & ~3;
706 /* update counters */
709 td->remainder -= temp;
713 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
714 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
716 /* update counters */
717 count -= buf_res.length;
718 td->offset += buf_res.length;
719 td->remainder -= buf_res.length;
722 /* check if we are complete */
723 if ((td->remainder == 0) || got_short) {
725 /* we are complete */
726 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
729 /* else need to receive a zero length packet */
731 /* write command - need more data */
732 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
733 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
734 return (1); /* not complete */
738 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
740 struct usb_page_search buf_res;
741 struct musbotg_softc *sc;
745 /* get pointer to softc */
746 sc = MUSBOTG_PC2SC(td->pc);
748 /* select endpoint 0 */
749 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
751 /* check if a command is pending */
752 if (sc->sc_ep0_cmd) {
753 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
756 /* read out FIFO status */
757 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
759 DPRINTFN(4, "csr=0x%02x\n", csr);
761 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
762 MUSB2_MASK_CSR0L_SENTSTALL)) {
764 * The current transfer was aborted
768 return (0); /* complete */
770 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
771 return (1); /* not complete */
773 count = td->max_frame_size;
774 if (td->remainder < count) {
775 /* we have a short packet */
777 count = td->remainder;
782 usbd_get_page(td->pc, td->offset, &buf_res);
784 /* get correct length */
785 if (buf_res.length > count) {
786 buf_res.length = count;
788 /* check for unaligned memory address */
789 if (USB_P2U(buf_res.buffer) & 3) {
791 usbd_copy_out(td->pc, td->offset,
792 sc->sc_bounce_buf, count);
797 /* transmit data 4 bytes at a time */
798 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
799 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
804 /* receive data 1 byte at a time */
805 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
807 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
809 /* update offset and remainder */
811 td->remainder -= count;
814 /* check if we can optimise */
815 if (buf_res.length >= 4) {
817 /* transmit data 4 bytes at a time */
818 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
819 MUSB2_REG_EPFIFO(0), buf_res.buffer,
822 temp = buf_res.length & ~3;
824 /* update counters */
827 td->remainder -= temp;
831 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
832 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
834 /* update counters */
835 count -= buf_res.length;
836 td->offset += buf_res.length;
837 td->remainder -= buf_res.length;
840 /* check remainder */
841 if (td->remainder == 0) {
843 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
844 return (0); /* complete */
846 /* else we need to transmit a short packet */
849 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
850 MUSB2_MASK_CSR0L_TXPKTRDY);
852 return (1); /* not complete */
856 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
858 struct usb_page_search buf_res;
859 struct musbotg_softc *sc;
864 /* get pointer to softc */
865 sc = MUSBOTG_PC2SC(td->pc);
867 if (td->channel == -1)
868 td->channel = musbotg_channel_alloc(sc, td);
870 /* EP0 is busy, wait */
871 if (td->channel == -1)
874 DPRINTFN(1, "ep_no=%d\n", td->channel);
876 /* select endpoint 0 */
877 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
879 /* read out FIFO status */
880 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
882 DPRINTFN(4, "csr=0x%02x\n", csr);
885 if (!td->transaction_started) {
886 td->transaction_started = 1;
888 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
890 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
892 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
893 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
894 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
896 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
897 MUSB2_MASK_CSR0L_REQPKT);
902 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
903 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
904 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
906 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
913 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
914 MUSB2_MASK_CSR0L_ERROR))
916 /* Clear status bit */
917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
918 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
923 musbotg_channel_free(sc, td);
924 return (0); /* we are complete */
927 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
928 return (1); /* not yet */
930 /* get the packet byte count */
931 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
933 /* verify the packet byte count */
934 if (count != td->max_frame_size) {
935 if (count < td->max_frame_size) {
936 /* we have a short packet */
940 /* invalid USB packet */
942 musbotg_channel_free(sc, td);
943 return (0); /* we are complete */
946 /* verify the packet byte count */
947 if (count > td->remainder) {
948 /* invalid USB packet */
950 musbotg_channel_free(sc, td);
951 return (0); /* we are complete */
956 usbd_get_page(td->pc, td->offset, &buf_res);
958 /* get correct length */
959 if (buf_res.length > count) {
960 buf_res.length = count;
962 /* check for unaligned memory address */
963 if (USB_P2U(buf_res.buffer) & 3) {
968 /* receive data 4 bytes at a time */
969 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
970 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
975 /* receive data 1 byte at a time */
976 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
978 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
980 usbd_copy_in(td->pc, td->offset,
981 sc->sc_bounce_buf, count);
983 /* update offset and remainder */
985 td->remainder -= count;
988 /* check if we can optimise */
989 if (buf_res.length >= 4) {
991 /* receive data 4 bytes at a time */
992 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
993 MUSB2_REG_EPFIFO(0), buf_res.buffer,
996 temp = buf_res.length & ~3;
998 /* update counters */
1001 td->remainder -= temp;
1005 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1006 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1008 /* update counters */
1009 count -= buf_res.length;
1010 td->offset += buf_res.length;
1011 td->remainder -= buf_res.length;
1014 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1015 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1017 /* check if we are complete */
1018 if ((td->remainder == 0) || got_short) {
1019 if (td->short_pkt) {
1020 /* we are complete */
1022 musbotg_channel_free(sc, td);
1025 /* else need to receive a zero length packet */
1028 td->transaction_started = 1;
1029 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1030 MUSB2_MASK_CSR0L_REQPKT);
1032 return (1); /* not complete */
1036 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1038 struct usb_page_search buf_res;
1039 struct musbotg_softc *sc;
1043 /* get pointer to softc */
1044 sc = MUSBOTG_PC2SC(td->pc);
1046 if (td->channel == -1)
1047 td->channel = musbotg_channel_alloc(sc, td);
1050 if (td->channel == -1)
1053 DPRINTFN(1, "ep_no=%d\n", td->channel);
1055 /* select endpoint */
1056 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1058 /* read out FIFO status */
1059 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1060 DPRINTFN(4, "csr=0x%02x\n", csr);
1062 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1063 MUSB2_MASK_CSR0L_ERROR)) {
1064 /* clear status bits */
1065 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1069 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1071 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1072 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1073 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1074 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1075 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1076 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1077 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1078 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1079 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1084 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1085 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1092 musbotg_channel_free(sc, td);
1093 return (0); /* complete */
1097 * Wait while FIFO is empty.
1098 * Do not flush it because it will cause transactions
1099 * with size more then packet size. It might upset
1102 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1105 /* Packet still being processed */
1106 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1109 if (td->transaction_started) {
1110 /* check remainder */
1111 if (td->remainder == 0) {
1112 if (td->short_pkt) {
1113 musbotg_channel_free(sc, td);
1114 return (0); /* complete */
1116 /* else we need to transmit a short packet */
1119 /* We're not complete - more transactions required */
1120 td->transaction_started = 0;
1123 /* check for short packet */
1124 count = td->max_frame_size;
1125 if (td->remainder < count) {
1126 /* we have a short packet */
1128 count = td->remainder;
1134 usbd_get_page(td->pc, td->offset, &buf_res);
1136 /* get correct length */
1137 if (buf_res.length > count) {
1138 buf_res.length = count;
1140 /* check for unaligned memory address */
1141 if (USB_P2U(buf_res.buffer) & 3) {
1143 usbd_copy_out(td->pc, td->offset,
1144 sc->sc_bounce_buf, count);
1149 /* transmit data 4 bytes at a time */
1150 bus_space_write_multi_4(sc->sc_io_tag,
1151 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1152 sc->sc_bounce_buf, temp / 4);
1156 /* receive data 1 byte at a time */
1157 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1158 MUSB2_REG_EPFIFO(0),
1159 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1161 /* update offset and remainder */
1162 td->offset += count;
1163 td->remainder -= count;
1166 /* check if we can optimise */
1167 if (buf_res.length >= 4) {
1169 /* transmit data 4 bytes at a time */
1170 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1171 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1172 buf_res.length / 4);
1174 temp = buf_res.length & ~3;
1176 /* update counters */
1179 td->remainder -= temp;
1183 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1184 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1187 /* update counters */
1188 count -= buf_res.length;
1189 td->offset += buf_res.length;
1190 td->remainder -= buf_res.length;
1193 /* Function address */
1194 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1195 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1196 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1197 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1199 /* TX NAK timeout */
1200 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1203 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1204 MUSB2_MASK_CSR0L_TXPKTRDY);
1206 td->transaction_started = 1;
1208 return (1); /* not complete */
1212 musbotg_dev_ctrl_status(struct musbotg_td *td)
1214 struct musbotg_softc *sc;
1217 /* get pointer to softc */
1218 sc = MUSBOTG_PC2SC(td->pc);
1220 /* select endpoint 0 */
1221 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1223 if (sc->sc_ep0_busy) {
1224 sc->sc_ep0_busy = 0;
1225 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1226 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1229 /* read out FIFO status */
1230 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1232 DPRINTFN(4, "csr=0x%02x\n", csr);
1234 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1235 /* wait for interrupt */
1236 return (1); /* not complete */
1238 if (sc->sc_dv_addr != 0xFF) {
1239 /* write function address */
1240 musbotg_set_address(sc, sc->sc_dv_addr);
1243 musbotg_channel_free(sc, td);
1244 return (0); /* complete */
1248 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1250 struct musbotg_softc *sc;
1253 /* get pointer to softc */
1254 sc = MUSBOTG_PC2SC(td->pc);
1256 if (td->channel == -1)
1257 td->channel = musbotg_channel_alloc(sc, td);
1259 /* EP0 is busy, wait */
1260 if (td->channel == -1)
1263 DPRINTFN(1, "ep_no=%d\n", td->channel);
1265 /* select endpoint 0 */
1266 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1268 if (!td->transaction_started) {
1269 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1272 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1273 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1274 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1276 /* RX NAK timeout */
1277 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1279 td->transaction_started = 1;
1282 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1283 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1284 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1287 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1288 MUSB2_MASK_CSR0L_STATUSPKT |
1289 MUSB2_MASK_CSR0L_REQPKT);
1291 return (1); /* Just started */
1295 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1297 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1299 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1300 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1301 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1302 musbotg_channel_free(sc, td);
1303 return (0); /* complete */
1306 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1307 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1308 MUSB2_MASK_CSR0L_REQPKT);
1309 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1311 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1312 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1317 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1318 MUSB2_MASK_CSR0L_ERROR))
1320 /* Clear status bit */
1321 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1322 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1327 musbotg_channel_free(sc, td);
1331 return (1); /* Not ready yet */
1335 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1337 struct musbotg_softc *sc;
1340 /* get pointer to softc */
1341 sc = MUSBOTG_PC2SC(td->pc);
1343 if (td->channel == -1)
1344 td->channel = musbotg_channel_alloc(sc, td);
1346 /* EP0 is busy, wait */
1347 if (td->channel == -1)
1350 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1351 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1353 /* select endpoint 0 */
1354 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1356 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1357 DPRINTFN(4, "csr=0x%02x\n", csr);
1360 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1364 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1365 MUSB2_MASK_CSR0L_ERROR))
1367 /* Clear status bit */
1368 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1369 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1371 musbotg_channel_free(sc, td);
1372 return (0); /* complete */
1375 if (td->transaction_started) {
1376 musbotg_channel_free(sc, td);
1377 return (0); /* complete */
1380 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1382 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1383 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1384 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1385 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1387 /* TX NAK timeout */
1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1390 td->transaction_started = 1;
1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1394 MUSB2_MASK_CSR0L_STATUSPKT |
1395 MUSB2_MASK_CSR0L_TXPKTRDY);
1397 return (1); /* wait for interrupt */
1401 musbotg_dev_data_rx(struct musbotg_td *td)
1403 struct usb_page_search buf_res;
1404 struct musbotg_softc *sc;
1410 to = 8; /* don't loop forever! */
1413 /* get pointer to softc */
1414 sc = MUSBOTG_PC2SC(td->pc);
1416 if (td->channel == -1)
1417 td->channel = musbotg_channel_alloc(sc, td);
1419 /* EP0 is busy, wait */
1420 if (td->channel == -1)
1423 /* select endpoint */
1424 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1427 /* read out FIFO status */
1428 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1430 DPRINTFN(4, "csr=0x%02x\n", csr);
1433 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1434 /* make sure we don't clear "RXPKTRDY" */
1435 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1436 MUSB2_MASK_CSRL_RXPKTRDY);
1440 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1441 return (1); /* not complete */
1443 /* get the packet byte count */
1444 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1446 DPRINTFN(4, "count=0x%04x\n", count);
1449 * Check for short or invalid packet:
1451 if (count != td->max_frame_size) {
1452 if (count < td->max_frame_size) {
1453 /* we have a short packet */
1457 /* invalid USB packet */
1459 musbotg_channel_free(sc, td);
1460 return (0); /* we are complete */
1463 /* verify the packet byte count */
1464 if (count > td->remainder) {
1465 /* invalid USB packet */
1467 musbotg_channel_free(sc, td);
1468 return (0); /* we are complete */
1473 usbd_get_page(td->pc, td->offset, &buf_res);
1475 /* get correct length */
1476 if (buf_res.length > count) {
1477 buf_res.length = count;
1479 /* check for unaligned memory address */
1480 if (USB_P2U(buf_res.buffer) & 3) {
1485 /* receive data 4 bytes at a time */
1486 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1487 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1492 /* receive data 1 byte at a time */
1493 bus_space_read_multi_1(sc->sc_io_tag,
1494 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1495 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1497 usbd_copy_in(td->pc, td->offset,
1498 sc->sc_bounce_buf, count);
1500 /* update offset and remainder */
1501 td->offset += count;
1502 td->remainder -= count;
1505 /* check if we can optimise */
1506 if (buf_res.length >= 4) {
1508 /* receive data 4 bytes at a time */
1509 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1510 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1511 buf_res.length / 4);
1513 temp = buf_res.length & ~3;
1515 /* update counters */
1518 td->remainder -= temp;
1522 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1523 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1526 /* update counters */
1527 count -= buf_res.length;
1528 td->offset += buf_res.length;
1529 td->remainder -= buf_res.length;
1532 /* clear status bits */
1533 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1535 /* check if we are complete */
1536 if ((td->remainder == 0) || got_short) {
1537 if (td->short_pkt) {
1538 /* we are complete */
1539 musbotg_channel_free(sc, td);
1542 /* else need to receive a zero length packet */
1547 return (1); /* not complete */
1551 musbotg_dev_data_tx(struct musbotg_td *td)
1553 struct usb_page_search buf_res;
1554 struct musbotg_softc *sc;
1559 to = 8; /* don't loop forever! */
1561 /* get pointer to softc */
1562 sc = MUSBOTG_PC2SC(td->pc);
1564 if (td->channel == -1)
1565 td->channel = musbotg_channel_alloc(sc, td);
1567 /* EP0 is busy, wait */
1568 if (td->channel == -1)
1571 /* select endpoint */
1572 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1576 /* read out FIFO status */
1577 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1579 DPRINTFN(4, "csr=0x%02x\n", csr);
1581 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1582 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1583 /* clear status bits */
1584 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1586 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1587 return (1); /* not complete */
1589 /* check for short packet */
1590 count = td->max_frame_size;
1591 if (td->remainder < count) {
1592 /* we have a short packet */
1594 count = td->remainder;
1599 usbd_get_page(td->pc, td->offset, &buf_res);
1601 /* get correct length */
1602 if (buf_res.length > count) {
1603 buf_res.length = count;
1605 /* check for unaligned memory address */
1606 if (USB_P2U(buf_res.buffer) & 3) {
1608 usbd_copy_out(td->pc, td->offset,
1609 sc->sc_bounce_buf, count);
1614 /* transmit data 4 bytes at a time */
1615 bus_space_write_multi_4(sc->sc_io_tag,
1616 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1617 sc->sc_bounce_buf, temp / 4);
1621 /* receive data 1 byte at a time */
1622 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1623 MUSB2_REG_EPFIFO(td->channel),
1624 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1626 /* update offset and remainder */
1627 td->offset += count;
1628 td->remainder -= count;
1631 /* check if we can optimise */
1632 if (buf_res.length >= 4) {
1634 /* transmit data 4 bytes at a time */
1635 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1636 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1637 buf_res.length / 4);
1639 temp = buf_res.length & ~3;
1641 /* update counters */
1644 td->remainder -= temp;
1648 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1649 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1652 /* update counters */
1653 count -= buf_res.length;
1654 td->offset += buf_res.length;
1655 td->remainder -= buf_res.length;
1658 /* Max packet size */
1659 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1662 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1663 MUSB2_MASK_CSRL_TXPKTRDY);
1665 /* check remainder */
1666 if (td->remainder == 0) {
1667 if (td->short_pkt) {
1668 musbotg_channel_free(sc, td);
1669 return (0); /* complete */
1671 /* else we need to transmit a short packet */
1676 return (1); /* not complete */
1680 musbotg_host_data_rx(struct musbotg_td *td)
1682 struct usb_page_search buf_res;
1683 struct musbotg_softc *sc;
1689 /* get pointer to softc */
1690 sc = MUSBOTG_PC2SC(td->pc);
1692 if (td->channel == -1)
1693 td->channel = musbotg_channel_alloc(sc, td);
1696 if (td->channel == -1)
1699 DPRINTFN(1, "ep_no=%d\n", td->channel);
1701 to = 8; /* don't loop forever! */
1704 /* select endpoint */
1705 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1708 /* read out FIFO status */
1709 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1710 DPRINTFN(4, "csr=0x%02x\n", csr);
1712 if (!td->transaction_started) {
1713 /* Function address */
1714 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1717 /* SPLIT transaction */
1718 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1720 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1723 /* RX NAK timeout */
1724 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1725 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1727 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1729 /* Protocol, speed, device endpoint */
1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1732 /* Max packet size */
1733 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1736 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1737 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1739 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1741 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1743 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1745 /* Set data toggle */
1746 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1749 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1750 MUSB2_MASK_CSRL_RXREQPKT);
1752 td->transaction_started = 1;
1756 /* clear NAK timeout */
1757 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1758 DPRINTFN(4, "NAK Timeout\n");
1759 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1760 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1761 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1763 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1764 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1770 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1771 DPRINTFN(4, "RXERROR\n");
1775 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1776 DPRINTFN(4, "RXSTALL\n");
1781 musbotg_channel_free(sc, td);
1782 return (0); /* we are complete */
1785 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1786 /* No data available yet */
1791 /* get the packet byte count */
1792 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1793 DPRINTFN(4, "count=0x%04x\n", count);
1796 * Check for short or invalid packet:
1798 if (count != td->max_frame_size) {
1799 if (count < td->max_frame_size) {
1800 /* we have a short packet */
1804 /* invalid USB packet */
1806 musbotg_channel_free(sc, td);
1807 return (0); /* we are complete */
1811 /* verify the packet byte count */
1812 if (count > td->remainder) {
1813 /* invalid USB packet */
1815 musbotg_channel_free(sc, td);
1816 return (0); /* we are complete */
1822 usbd_get_page(td->pc, td->offset, &buf_res);
1824 /* get correct length */
1825 if (buf_res.length > count) {
1826 buf_res.length = count;
1828 /* check for unaligned memory address */
1829 if (USB_P2U(buf_res.buffer) & 3) {
1834 /* receive data 4 bytes at a time */
1835 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1836 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1841 /* receive data 1 byte at a time */
1842 bus_space_read_multi_1(sc->sc_io_tag,
1843 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1844 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1846 usbd_copy_in(td->pc, td->offset,
1847 sc->sc_bounce_buf, count);
1849 /* update offset and remainder */
1850 td->offset += count;
1851 td->remainder -= count;
1854 /* check if we can optimise */
1855 if (buf_res.length >= 4) {
1857 /* receive data 4 bytes at a time */
1858 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1859 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1860 buf_res.length / 4);
1862 temp = buf_res.length & ~3;
1864 /* update counters */
1867 td->remainder -= temp;
1871 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1872 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1875 /* update counters */
1876 count -= buf_res.length;
1877 td->offset += buf_res.length;
1878 td->remainder -= buf_res.length;
1881 /* clear status bits */
1882 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1884 /* check if we are complete */
1885 if ((td->remainder == 0) || got_short) {
1886 if (td->short_pkt) {
1887 /* we are complete */
1888 musbotg_channel_free(sc, td);
1891 /* else need to receive a zero length packet */
1894 /* Reset transaction state and restart */
1895 td->transaction_started = 0;
1900 return (1); /* not complete */
1904 musbotg_host_data_tx(struct musbotg_td *td)
1906 struct usb_page_search buf_res;
1907 struct musbotg_softc *sc;
1911 /* get pointer to softc */
1912 sc = MUSBOTG_PC2SC(td->pc);
1914 if (td->channel == -1)
1915 td->channel = musbotg_channel_alloc(sc, td);
1918 if (td->channel == -1)
1921 DPRINTFN(1, "ep_no=%d\n", td->channel);
1923 /* select endpoint */
1924 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1926 /* read out FIFO status */
1927 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1928 DPRINTFN(4, "csr=0x%02x\n", csr);
1930 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1931 MUSB2_MASK_CSRL_TXERROR)) {
1932 /* clear status bits */
1933 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1935 musbotg_channel_free(sc, td);
1936 return (0); /* complete */
1939 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1941 * Flush TX FIFO before clearing NAK TO
1943 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1944 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1945 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1946 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1947 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1948 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1949 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1950 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1954 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1958 musbotg_channel_free(sc, td);
1959 return (0); /* complete */
1963 * Wait while FIFO is empty.
1964 * Do not flush it because it will cause transactions
1965 * with size more then packet size. It might upset
1968 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1971 /* Packet still being processed */
1972 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1975 if (td->transaction_started) {
1976 /* check remainder */
1977 if (td->remainder == 0) {
1978 if (td->short_pkt) {
1979 musbotg_channel_free(sc, td);
1980 return (0); /* complete */
1982 /* else we need to transmit a short packet */
1985 /* We're not complete - more transactions required */
1986 td->transaction_started = 0;
1989 /* check for short packet */
1990 count = td->max_frame_size;
1991 if (td->remainder < count) {
1992 /* we have a short packet */
1994 count = td->remainder;
2000 usbd_get_page(td->pc, td->offset, &buf_res);
2002 /* get correct length */
2003 if (buf_res.length > count) {
2004 buf_res.length = count;
2006 /* check for unaligned memory address */
2007 if (USB_P2U(buf_res.buffer) & 3) {
2009 usbd_copy_out(td->pc, td->offset,
2010 sc->sc_bounce_buf, count);
2015 /* transmit data 4 bytes at a time */
2016 bus_space_write_multi_4(sc->sc_io_tag,
2017 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2018 sc->sc_bounce_buf, temp / 4);
2022 /* receive data 1 byte at a time */
2023 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2024 MUSB2_REG_EPFIFO(td->channel),
2025 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2027 /* update offset and remainder */
2028 td->offset += count;
2029 td->remainder -= count;
2032 /* check if we can optimise */
2033 if (buf_res.length >= 4) {
2035 /* transmit data 4 bytes at a time */
2036 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2037 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2038 buf_res.length / 4);
2040 temp = buf_res.length & ~3;
2042 /* update counters */
2045 td->remainder -= temp;
2049 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2050 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2053 /* update counters */
2054 count -= buf_res.length;
2055 td->offset += buf_res.length;
2056 td->remainder -= buf_res.length;
2059 /* Function address */
2060 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2063 /* SPLIT transaction */
2064 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2066 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2069 /* TX NAK timeout */
2070 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2071 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2073 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2075 /* Protocol, speed, device endpoint */
2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2078 /* Max packet size */
2079 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2081 if (!td->transaction_started) {
2082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2083 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2085 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2087 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2089 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2091 /* Set data toggle */
2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2096 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2097 MUSB2_MASK_CSRL_TXPKTRDY);
2099 /* Update Data Toggle */
2101 td->transaction_started = 1;
2103 return (1); /* not complete */
2107 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2109 struct musbotg_softc *sc;
2110 struct musbotg_td *td;
2113 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2115 td = xfer->td_transfer_cache;
2118 if ((td->func) (td)) {
2119 /* operation in progress */
2123 if (((void *)td) == xfer->td_transfer_last) {
2128 } else if (td->remainder > 0) {
2130 * We had a short transfer. If there is no alternate
2131 * next, stop processing !
2133 if (!td->alt_next) {
2138 * Fetch the next transfer descriptor and transfer
2139 * some flags to the next transfer descriptor
2142 xfer->td_transfer_cache = td;
2145 return (1); /* not complete */
2147 /* compute all actual lengths */
2148 musbotg_standard_done(xfer);
2150 return (0); /* complete */
2154 musbotg_interrupt_poll(struct musbotg_softc *sc)
2156 struct usb_xfer *xfer;
2159 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2160 if (!musbotg_xfer_do_fifo(xfer)) {
2161 /* queue has been modified */
2168 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2170 DPRINTFN(4, "vbus = %u\n", is_on);
2172 USB_BUS_LOCK(&sc->sc_bus);
2174 if (!sc->sc_flags.status_vbus) {
2175 sc->sc_flags.status_vbus = 1;
2177 /* complete root HUB interrupt endpoint */
2178 musbotg_root_intr(sc);
2181 if (sc->sc_flags.status_vbus) {
2182 sc->sc_flags.status_vbus = 0;
2183 sc->sc_flags.status_bus_reset = 0;
2184 sc->sc_flags.status_suspend = 0;
2185 sc->sc_flags.change_suspend = 0;
2186 sc->sc_flags.change_connect = 1;
2188 /* complete root HUB interrupt endpoint */
2189 musbotg_root_intr(sc);
2193 USB_BUS_UNLOCK(&sc->sc_bus);
2197 musbotg_connect_interrupt(struct musbotg_softc *sc)
2199 USB_BUS_LOCK(&sc->sc_bus);
2200 sc->sc_flags.change_connect = 1;
2202 /* complete root HUB interrupt endpoint */
2203 musbotg_root_intr(sc);
2204 USB_BUS_UNLOCK(&sc->sc_bus);
2208 musbotg_interrupt(struct musbotg_softc *sc,
2209 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2217 USB_BUS_LOCK(&sc->sc_bus);
2221 /* read all interrupt registers */
2222 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2224 /* read all FIFO interrupts */
2225 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2226 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2227 rx_status |= rxstat;
2228 tx_status |= txstat;
2231 /* Clear platform flags after first time */
2236 /* check for any bus state change interrupts */
2238 if (usb_status & (MUSB2_MASK_IRESET |
2239 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2240 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) {
2242 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2244 if (usb_status & MUSB2_MASK_IRESET) {
2246 /* set correct state */
2247 sc->sc_flags.status_bus_reset = 1;
2248 sc->sc_flags.status_suspend = 0;
2249 sc->sc_flags.change_suspend = 0;
2250 sc->sc_flags.change_connect = 1;
2252 /* determine line speed */
2253 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2254 if (temp & MUSB2_MASK_HSMODE)
2255 sc->sc_flags.status_high_speed = 1;
2257 sc->sc_flags.status_high_speed = 0;
2260 * After reset all interrupts are on and we need to
2263 temp = MUSB2_MASK_IRESET;
2264 /* disable resume interrupt */
2265 temp &= ~MUSB2_MASK_IRESUME;
2266 /* enable suspend interrupt */
2267 temp |= MUSB2_MASK_ISUSP;
2268 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2269 /* disable TX and RX interrupts */
2270 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2271 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2274 * If RXRSM and RXSUSP is set at the same time we interpret
2275 * that like RESUME. Resume is set when there is at least 3
2276 * milliseconds of inactivity on the USB BUS.
2278 if (usb_status & MUSB2_MASK_IRESUME) {
2279 if (sc->sc_flags.status_suspend) {
2280 sc->sc_flags.status_suspend = 0;
2281 sc->sc_flags.change_suspend = 1;
2283 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2284 /* disable resume interrupt */
2285 temp &= ~MUSB2_MASK_IRESUME;
2286 /* enable suspend interrupt */
2287 temp |= MUSB2_MASK_ISUSP;
2288 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2290 } else if (usb_status & MUSB2_MASK_ISUSP) {
2291 if (!sc->sc_flags.status_suspend) {
2292 sc->sc_flags.status_suspend = 1;
2293 sc->sc_flags.change_suspend = 1;
2295 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2296 /* disable suspend interrupt */
2297 temp &= ~MUSB2_MASK_ISUSP;
2298 /* enable resume interrupt */
2299 temp |= MUSB2_MASK_IRESUME;
2300 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2304 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2305 sc->sc_flags.change_connect = 1;
2308 * Host Mode: There is no IRESET so assume bus is
2309 * always in reset state once device is connected.
2311 if (sc->sc_mode == MUSB2_HOST_MODE) {
2312 if (usb_status & MUSB2_MASK_ICONN)
2313 sc->sc_flags.status_bus_reset = 1;
2314 if (usb_status & MUSB2_MASK_IDISC)
2315 sc->sc_flags.status_bus_reset = 0;
2318 /* complete root HUB interrupt endpoint */
2319 musbotg_root_intr(sc);
2321 /* check for any endpoint interrupts */
2323 if (rx_status || tx_status) {
2324 DPRINTFN(4, "real endpoint interrupt "
2325 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2327 /* poll one time regardless of FIFO status */
2329 musbotg_interrupt_poll(sc);
2334 USB_BUS_UNLOCK(&sc->sc_bus);
2338 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2340 struct musbotg_td *td;
2342 /* get current Transfer Descriptor */
2346 /* prepare for next TD */
2347 temp->td_next = td->obj_next;
2349 /* fill out the Transfer Descriptor */
2350 td->func = temp->func;
2352 td->offset = temp->offset;
2353 td->remainder = temp->len;
2355 td->transaction_started = 0;
2356 td->did_stall = temp->did_stall;
2357 td->short_pkt = temp->short_pkt;
2358 td->alt_next = temp->setup_alt_next;
2359 td->channel = temp->channel;
2360 td->dev_addr = temp->dev_addr;
2361 td->haddr = temp->haddr;
2362 td->hport = temp->hport;
2363 td->transfer_type = temp->transfer_type;
2367 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2369 struct musbotg_std_temp temp;
2370 struct musbotg_softc *sc;
2371 struct musbotg_td *td;
2375 enum usb_dev_speed speed;
2379 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2380 xfer->address, UE_GET_ADDR(xfer->endpointno),
2381 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2383 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2384 ep_no = (xfer->endpointno & UE_ADDR);
2386 temp.max_frame_size = xfer->max_frame_size;
2388 td = xfer->td_start[0];
2389 xfer->td_transfer_first = td;
2390 xfer->td_transfer_cache = td;
2393 dev_addr = xfer->address;
2395 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2399 temp.td_next = xfer->td_start[0];
2401 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
2402 temp.did_stall = !xfer->flags_int.control_stall;
2404 temp.dev_addr = dev_addr;
2405 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2406 temp.hport = xfer->xroot->udev->hs_port_no;
2408 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2409 speed = usbd_get_speed(xfer->xroot->udev);
2413 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2415 case USB_SPEED_FULL:
2416 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2418 case USB_SPEED_HIGH:
2419 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2422 temp.transfer_type = 0;
2423 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2427 switch (xfer_type) {
2429 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2431 case UE_ISOCHRONOUS:
2432 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2435 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2438 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2441 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2446 temp.transfer_type |= ep_no;
2447 td->toggle = xfer->endpoint->toggle_next;
2450 /* check if we should prepend a setup message */
2452 if (xfer->flags_int.control_xfr) {
2453 if (xfer->flags_int.control_hdr) {
2455 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2456 temp.func = &musbotg_dev_ctrl_setup_rx;
2458 temp.func = &musbotg_host_ctrl_setup_tx;
2460 temp.len = xfer->frlengths[0];
2461 temp.pc = xfer->frbuffers + 0;
2462 temp.short_pkt = temp.len ? 1 : 0;
2464 musbotg_setup_standard_chain_sub(&temp);
2473 if (x != xfer->nframes) {
2474 if (xfer->endpointno & UE_DIR_IN)
2477 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2481 if (xfer->flags_int.control_xfr)
2482 temp.func = &musbotg_host_ctrl_data_tx;
2484 temp.func = &musbotg_host_data_tx;
2486 if (xfer->flags_int.control_xfr)
2487 temp.func = &musbotg_host_ctrl_data_rx;
2489 temp.func = &musbotg_host_data_rx;
2494 if (xfer->flags_int.control_xfr)
2495 temp.func = &musbotg_dev_ctrl_data_tx;
2497 temp.func = &musbotg_dev_data_tx;
2499 if (xfer->flags_int.control_xfr)
2500 temp.func = &musbotg_dev_ctrl_data_rx;
2502 temp.func = &musbotg_dev_data_rx;
2506 /* setup "pc" pointer */
2507 temp.pc = xfer->frbuffers + x;
2509 while (x != xfer->nframes) {
2511 /* DATA0 / DATA1 message */
2513 temp.len = xfer->frlengths[x];
2517 if (x == xfer->nframes) {
2518 if (xfer->flags_int.control_xfr) {
2519 if (xfer->flags_int.control_act) {
2520 temp.setup_alt_next = 0;
2523 temp.setup_alt_next = 0;
2526 if (temp.len == 0) {
2528 /* make sure that we send an USB packet */
2534 if (xfer->flags_int.isochronous_xfr) {
2535 /* isochronous data transfer */
2536 /* don't force short */
2539 /* regular data transfer */
2540 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2544 musbotg_setup_standard_chain_sub(&temp);
2546 if (xfer->flags_int.isochronous_xfr) {
2547 temp.offset += temp.len;
2549 /* get next Page Cache pointer */
2550 temp.pc = xfer->frbuffers + x;
2554 /* check for control transfer */
2555 if (xfer->flags_int.control_xfr) {
2557 /* always setup a valid "pc" pointer for status and sync */
2558 temp.pc = xfer->frbuffers + 0;
2561 temp.setup_alt_next = 0;
2563 /* check if we should append a status stage */
2564 if (!xfer->flags_int.control_act) {
2566 * Send a DATA1 message and invert the current
2567 * endpoint direction.
2569 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2570 temp.func = &musbotg_dev_ctrl_status;
2572 if (xfer->endpointno & UE_DIR_IN)
2573 temp.func = musbotg_host_ctrl_status_tx;
2575 temp.func = musbotg_host_ctrl_status_rx;
2577 musbotg_setup_standard_chain_sub(&temp);
2580 /* must have at least one frame! */
2582 xfer->td_transfer_last = td;
2586 musbotg_timeout(void *arg)
2588 struct usb_xfer *xfer = arg;
2590 DPRINTFN(1, "xfer=%p\n", xfer);
2592 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2594 /* transfer is transferred */
2595 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2599 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2604 * Only enable the endpoint interrupt when we are
2605 * actually waiting for data, hence we are dealing
2606 * with level triggered interrupts !
2608 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2614 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2616 temp |= MUSB2_MASK_EPINT(0);
2618 temp &= ~MUSB2_MASK_EPINT(0);
2620 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2622 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2624 temp |= MUSB2_MASK_EPINT(channel);
2626 temp &= ~MUSB2_MASK_EPINT(channel);
2627 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2629 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2631 temp |= MUSB2_MASK_EPINT(channel);
2633 temp &= ~MUSB2_MASK_EPINT(channel);
2634 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2637 if (sc->sc_ep_int_set)
2638 sc->sc_ep_int_set(sc, channel, on);
2642 musbotg_start_standard_chain(struct usb_xfer *xfer)
2647 if (musbotg_xfer_do_fifo(xfer)) {
2649 DPRINTFN(14, "enabled interrupts on endpoint\n");
2651 /* put transfer on interrupt queue */
2652 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2654 /* start timeout, if any */
2655 if (xfer->timeout != 0) {
2656 usbd_transfer_timeout_ms(xfer,
2657 &musbotg_timeout, xfer->timeout);
2663 musbotg_root_intr(struct musbotg_softc *sc)
2667 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2670 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2672 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2673 sizeof(sc->sc_hub_idata));
2677 musbotg_standard_done_sub(struct usb_xfer *xfer)
2679 struct musbotg_td *td;
2685 td = xfer->td_transfer_cache;
2688 len = td->remainder;
2690 xfer->endpoint->toggle_next = td->toggle;
2692 if (xfer->aframes != xfer->nframes) {
2694 * Verify the length and subtract
2695 * the remainder from "frlengths[]":
2697 if (len > xfer->frlengths[xfer->aframes]) {
2700 xfer->frlengths[xfer->aframes] -= len;
2703 /* Check for transfer error */
2705 /* the transfer is finished */
2710 /* Check for short transfer */
2712 if (xfer->flags_int.short_frames_ok) {
2713 /* follow alt next */
2720 /* the transfer is finished */
2728 /* this USB frame is complete */
2734 /* update transfer cache */
2736 xfer->td_transfer_cache = td;
2739 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2743 musbotg_standard_done(struct usb_xfer *xfer)
2745 usb_error_t err = 0;
2747 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2748 xfer, xfer->endpoint);
2752 xfer->td_transfer_cache = xfer->td_transfer_first;
2754 if (xfer->flags_int.control_xfr) {
2756 if (xfer->flags_int.control_hdr) {
2758 err = musbotg_standard_done_sub(xfer);
2762 if (xfer->td_transfer_cache == NULL) {
2766 while (xfer->aframes != xfer->nframes) {
2768 err = musbotg_standard_done_sub(xfer);
2771 if (xfer->td_transfer_cache == NULL) {
2776 if (xfer->flags_int.control_xfr &&
2777 !xfer->flags_int.control_act) {
2779 err = musbotg_standard_done_sub(xfer);
2782 musbotg_device_done(xfer, err);
2785 /*------------------------------------------------------------------------*
2786 * musbotg_device_done
2788 * NOTE: this function can be called more than one time on the
2789 * same USB transfer!
2790 *------------------------------------------------------------------------*/
2792 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2794 struct musbotg_td *td;
2795 struct musbotg_softc *sc;
2797 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2799 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2800 xfer, xfer->endpoint, error);
2802 DPRINTFN(14, "disabled interrupts on endpoint\n");
2804 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2805 td = xfer->td_transfer_cache;
2807 if (td && (td->channel != -1))
2808 musbotg_channel_free(sc, td);
2810 /* dequeue transfer and start next transfer */
2811 usbd_transfer_done(xfer, error);
2815 musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
2816 struct usb_endpoint *ep, uint8_t *did_stall)
2818 struct musbotg_softc *sc;
2821 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2823 DPRINTFN(4, "endpoint=%p\n", ep);
2826 /* cancel any ongoing transfers */
2827 musbotg_device_done(xfer, USB_ERR_STALLED);
2829 /* set FORCESTALL */
2830 sc = MUSBOTG_BUS2SC(udev->bus);
2832 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2834 /* select endpoint */
2835 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2837 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2838 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2839 MUSB2_MASK_CSRL_TXSENDSTALL);
2841 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2842 MUSB2_MASK_CSRL_RXSENDSTALL);
2847 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2848 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2854 if (ep_type == UE_CONTROL) {
2855 /* clearing stall is not needed */
2858 /* select endpoint */
2859 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2861 /* compute max frame size */
2862 mps = wMaxPacket & 0x7FF;
2863 switch ((wMaxPacket >> 11) & 3) {
2874 if (ep_dir == UE_DIR_IN) {
2878 /* Configure endpoint */
2881 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2882 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2883 MUSB2_MASK_CSRH_TXMODE | temp);
2885 case UE_ISOCHRONOUS:
2886 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2887 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2888 MUSB2_MASK_CSRH_TXMODE |
2889 MUSB2_MASK_CSRH_TXISO | temp);
2892 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2893 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2894 MUSB2_MASK_CSRH_TXMODE | temp);
2900 /* Need to flush twice in case of double bufring */
2901 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2902 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2903 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2904 MUSB2_MASK_CSRL_TXFFLUSH);
2905 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2906 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2908 MUSB2_MASK_CSRL_TXFFLUSH);
2909 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2912 /* reset data toggle */
2913 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2914 MUSB2_MASK_CSRL_TXDT_CLR);
2915 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2916 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2918 /* set double/single buffering */
2919 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2920 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2921 max_in_frame_size / 2)) {
2923 temp &= ~(1 << ep_no);
2926 temp |= (1 << ep_no);
2928 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2930 /* clear sent stall */
2931 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2932 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2933 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2939 /* Configure endpoint */
2942 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2943 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2944 MUSB2_MASK_CSRH_RXNYET | temp);
2946 case UE_ISOCHRONOUS:
2947 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2948 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2949 MUSB2_MASK_CSRH_RXNYET |
2950 MUSB2_MASK_CSRH_RXISO | temp);
2953 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2954 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2960 /* Need to flush twice in case of double bufring */
2961 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2962 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2963 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2964 MUSB2_MASK_CSRL_RXFFLUSH);
2965 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2966 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2967 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2968 MUSB2_MASK_CSRL_RXFFLUSH);
2969 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2972 /* reset data toggle */
2973 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2974 MUSB2_MASK_CSRL_RXDT_CLR);
2975 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2976 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2978 /* set double/single buffering */
2979 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2980 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2981 max_out_frame_size / 2)) {
2983 temp &= ~(1 << ep_no);
2986 temp |= (1 << ep_no);
2988 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
2990 /* clear sent stall */
2991 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
2992 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2998 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3000 struct musbotg_softc *sc;
3001 struct usb_endpoint_descriptor *ed;
3003 DPRINTFN(4, "endpoint=%p\n", ep);
3005 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3008 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3013 sc = MUSBOTG_BUS2SC(udev->bus);
3015 /* get endpoint descriptor */
3018 /* reset endpoint */
3019 musbotg_clear_stall_sub(sc,
3020 UGETW(ed->wMaxPacketSize),
3021 (ed->bEndpointAddress & UE_ADDR),
3022 (ed->bmAttributes & UE_XFERTYPE),
3023 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3027 musbotg_init(struct musbotg_softc *sc)
3029 struct usb_hw_ep_profile *pf;
3039 DPRINTFN(1, "start\n");
3041 /* set up the bus structure */
3042 sc->sc_bus.usbrev = USB_REV_2_0;
3043 sc->sc_bus.methods = &musbotg_bus_methods;
3045 USB_BUS_LOCK(&sc->sc_bus);
3047 /* turn on clocks */
3049 if (sc->sc_clocks_on) {
3050 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3053 /* wait a little for things to stabilise */
3054 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3056 /* disable all interrupts */
3058 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3059 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3061 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3062 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3063 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3065 /* disable pullup */
3067 musbotg_pull_common(sc, 0);
3069 /* wait a little bit (10ms) */
3070 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3073 /* disable double packet buffering */
3074 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3075 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3077 /* enable HighSpeed and ISO Update flags */
3079 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3080 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3082 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3083 /* clear Session bit, if set */
3084 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3085 temp &= ~MUSB2_MASK_SESS;
3086 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3088 /* Enter session for Host mode */
3089 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3090 temp |= MUSB2_MASK_SESS;
3091 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3094 /* wait a little for things to stabilise */
3095 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3097 DPRINTF("DEVCTL=0x%02x\n", temp);
3099 /* disable testmode */
3101 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3103 /* set default value */
3105 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3107 /* select endpoint index 0 */
3109 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3111 /* read out number of endpoints */
3114 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3117 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3119 /* these numbers exclude the control endpoint */
3121 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3123 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3124 if (sc->sc_ep_max == 0) {
3125 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3127 /* read out configuration data */
3129 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3131 DPRINTFN(2, "Config Data: 0x%02x\n",
3134 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3137 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3138 "assuming 16Kbytes of FIFO RAM\n");
3141 DPRINTFN(2, "HW version: 0x%04x\n",
3142 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3144 /* initialise endpoint profiles */
3148 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3149 pf = sc->sc_hw_ep_profile + temp;
3151 /* select endpoint */
3152 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3154 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3155 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3156 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3158 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3159 temp, ftx, frx, dynfifo);
3162 if (frx && (temp <= nrx)) {
3165 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3166 MUSB2_VAL_FIFOSZ_4096 |
3168 } else if (temp < 8) {
3170 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3171 MUSB2_VAL_FIFOSZ_512 |
3174 frx = 7; /* 128 bytes */
3175 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3176 MUSB2_VAL_FIFOSZ_128);
3179 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3182 offset += (1 << frx);
3184 if (ftx && (temp <= ntx)) {
3187 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3188 MUSB2_VAL_FIFOSZ_4096 |
3190 } else if (temp < 8) {
3192 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3193 MUSB2_VAL_FIFOSZ_512 |
3196 ftx = 7; /* 128 bytes */
3197 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3198 MUSB2_VAL_FIFOSZ_128);
3201 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3204 offset += (1 << ftx);
3208 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3209 pf->max_in_frame_size = 1 << ftx;
3210 pf->max_out_frame_size = 1 << frx;
3211 pf->is_simplex = 0; /* duplex */
3212 pf->support_multi_buffer = 1;
3213 pf->support_bulk = 1;
3214 pf->support_interrupt = 1;
3215 pf->support_isochronous = 1;
3217 pf->support_out = 1;
3218 } else if (frx && (temp <= nrx)) {
3219 pf->max_out_frame_size = 1 << frx;
3220 pf->is_simplex = 1; /* simplex */
3221 pf->support_multi_buffer = 1;
3222 pf->support_bulk = 1;
3223 pf->support_interrupt = 1;
3224 pf->support_isochronous = 1;
3225 pf->support_out = 1;
3226 } else if (ftx && (temp <= ntx)) {
3227 pf->max_in_frame_size = 1 << ftx;
3228 pf->is_simplex = 1; /* simplex */
3229 pf->support_multi_buffer = 1;
3230 pf->support_bulk = 1;
3231 pf->support_interrupt = 1;
3232 pf->support_isochronous = 1;
3237 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3239 /* turn on default interrupts */
3241 if (sc->sc_mode == MUSB2_HOST_MODE)
3242 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3244 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3247 musbotg_clocks_off(sc);
3249 USB_BUS_UNLOCK(&sc->sc_bus);
3251 /* catch any lost interrupts */
3253 musbotg_do_poll(&sc->sc_bus);
3255 return (0); /* success */
3259 musbotg_uninit(struct musbotg_softc *sc)
3261 USB_BUS_LOCK(&sc->sc_bus);
3263 /* disable all interrupts */
3264 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3265 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3266 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3268 sc->sc_flags.port_powered = 0;
3269 sc->sc_flags.status_vbus = 0;
3270 sc->sc_flags.status_bus_reset = 0;
3271 sc->sc_flags.status_suspend = 0;
3272 sc->sc_flags.change_suspend = 0;
3273 sc->sc_flags.change_connect = 1;
3275 musbotg_pull_down(sc);
3276 musbotg_clocks_off(sc);
3277 USB_BUS_UNLOCK(&sc->sc_bus);
3281 musbotg_suspend(struct musbotg_softc *sc)
3287 musbotg_resume(struct musbotg_softc *sc)
3293 musbotg_do_poll(struct usb_bus *bus)
3295 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3297 USB_BUS_LOCK(&sc->sc_bus);
3298 musbotg_interrupt_poll(sc);
3299 USB_BUS_UNLOCK(&sc->sc_bus);
3302 /*------------------------------------------------------------------------*
3303 * musbotg bulk support
3304 *------------------------------------------------------------------------*/
3306 musbotg_device_bulk_open(struct usb_xfer *xfer)
3312 musbotg_device_bulk_close(struct usb_xfer *xfer)
3314 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3318 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3324 musbotg_device_bulk_start(struct usb_xfer *xfer)
3327 musbotg_setup_standard_chain(xfer);
3328 musbotg_start_standard_chain(xfer);
3331 struct usb_pipe_methods musbotg_device_bulk_methods =
3333 .open = musbotg_device_bulk_open,
3334 .close = musbotg_device_bulk_close,
3335 .enter = musbotg_device_bulk_enter,
3336 .start = musbotg_device_bulk_start,
3339 /*------------------------------------------------------------------------*
3340 * musbotg control support
3341 *------------------------------------------------------------------------*/
3343 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3349 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3351 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3355 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3361 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3364 musbotg_setup_standard_chain(xfer);
3365 musbotg_start_standard_chain(xfer);
3368 struct usb_pipe_methods musbotg_device_ctrl_methods =
3370 .open = musbotg_device_ctrl_open,
3371 .close = musbotg_device_ctrl_close,
3372 .enter = musbotg_device_ctrl_enter,
3373 .start = musbotg_device_ctrl_start,
3376 /*------------------------------------------------------------------------*
3377 * musbotg interrupt support
3378 *------------------------------------------------------------------------*/
3380 musbotg_device_intr_open(struct usb_xfer *xfer)
3386 musbotg_device_intr_close(struct usb_xfer *xfer)
3388 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3392 musbotg_device_intr_enter(struct usb_xfer *xfer)
3398 musbotg_device_intr_start(struct usb_xfer *xfer)
3401 musbotg_setup_standard_chain(xfer);
3402 musbotg_start_standard_chain(xfer);
3405 struct usb_pipe_methods musbotg_device_intr_methods =
3407 .open = musbotg_device_intr_open,
3408 .close = musbotg_device_intr_close,
3409 .enter = musbotg_device_intr_enter,
3410 .start = musbotg_device_intr_start,
3413 /*------------------------------------------------------------------------*
3414 * musbotg full speed isochronous support
3415 *------------------------------------------------------------------------*/
3417 musbotg_device_isoc_open(struct usb_xfer *xfer)
3423 musbotg_device_isoc_close(struct usb_xfer *xfer)
3425 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3429 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3431 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3436 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3437 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3439 /* get the current frame index */
3441 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3444 * check if the frame index is within the window where the frames
3447 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3449 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3450 fs_frames = (xfer->nframes + 7) / 8;
3452 fs_frames = xfer->nframes;
3455 if ((xfer->endpoint->is_synced == 0) ||
3456 (temp < fs_frames)) {
3458 * If there is data underflow or the pipe queue is
3459 * empty we schedule the transfer a few frames ahead
3460 * of the current frame position. Else two isochronous
3461 * transfers might overlap.
3463 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3464 xfer->endpoint->is_synced = 1;
3465 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3468 * compute how many milliseconds the insertion is ahead of the
3469 * current frame position:
3471 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3474 * pre-compute when the isochronous transfer will be finished:
3476 xfer->isoc_time_complete =
3477 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3480 /* compute frame number for next insertion */
3481 xfer->endpoint->isoc_next += fs_frames;
3484 musbotg_setup_standard_chain(xfer);
3488 musbotg_device_isoc_start(struct usb_xfer *xfer)
3490 /* start TD chain */
3491 musbotg_start_standard_chain(xfer);
3494 struct usb_pipe_methods musbotg_device_isoc_methods =
3496 .open = musbotg_device_isoc_open,
3497 .close = musbotg_device_isoc_close,
3498 .enter = musbotg_device_isoc_enter,
3499 .start = musbotg_device_isoc_start,
3502 /*------------------------------------------------------------------------*
3503 * musbotg root control support
3504 *------------------------------------------------------------------------*
3505 * Simulate a hardware HUB by handling all the necessary requests.
3506 *------------------------------------------------------------------------*/
3508 static const struct usb_device_descriptor musbotg_devd = {
3509 .bLength = sizeof(struct usb_device_descriptor),
3510 .bDescriptorType = UDESC_DEVICE,
3511 .bcdUSB = {0x00, 0x02},
3512 .bDeviceClass = UDCLASS_HUB,
3513 .bDeviceSubClass = UDSUBCLASS_HUB,
3514 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3515 .bMaxPacketSize = 64,
3516 .bcdDevice = {0x00, 0x01},
3519 .bNumConfigurations = 1,
3522 static const struct usb_device_qualifier musbotg_odevd = {
3523 .bLength = sizeof(struct usb_device_qualifier),
3524 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3525 .bcdUSB = {0x00, 0x02},
3526 .bDeviceClass = UDCLASS_HUB,
3527 .bDeviceSubClass = UDSUBCLASS_HUB,
3528 .bDeviceProtocol = UDPROTO_FSHUB,
3529 .bMaxPacketSize0 = 0,
3530 .bNumConfigurations = 0,
3533 static const struct musbotg_config_desc musbotg_confd = {
3535 .bLength = sizeof(struct usb_config_descriptor),
3536 .bDescriptorType = UDESC_CONFIG,
3537 .wTotalLength[0] = sizeof(musbotg_confd),
3539 .bConfigurationValue = 1,
3540 .iConfiguration = 0,
3541 .bmAttributes = UC_SELF_POWERED,
3545 .bLength = sizeof(struct usb_interface_descriptor),
3546 .bDescriptorType = UDESC_INTERFACE,
3548 .bInterfaceClass = UICLASS_HUB,
3549 .bInterfaceSubClass = UISUBCLASS_HUB,
3550 .bInterfaceProtocol = 0,
3553 .bLength = sizeof(struct usb_endpoint_descriptor),
3554 .bDescriptorType = UDESC_ENDPOINT,
3555 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3556 .bmAttributes = UE_INTERRUPT,
3557 .wMaxPacketSize[0] = 8,
3562 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3564 static const struct usb_hub_descriptor_min musbotg_hubd = {
3565 .bDescLength = sizeof(musbotg_hubd),
3566 .bDescriptorType = UDESC_HUB,
3568 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3569 .bPwrOn2PwrGood = 50,
3570 .bHubContrCurrent = 0,
3571 .DeviceRemovable = {0}, /* port is removable */
3574 #define STRING_LANG \
3575 0x09, 0x04, /* American English */
3577 #define STRING_VENDOR \
3578 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \
3579 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0
3581 #define STRING_PRODUCT \
3582 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \
3583 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
3586 USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab);
3587 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3588 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3591 musbotg_roothub_exec(struct usb_device *udev,
3592 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3594 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3602 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3605 ptr = (const void *)&sc->sc_hub_temp;
3609 value = UGETW(req->wValue);
3610 index = UGETW(req->wIndex);
3612 /* demultiplex the control request */
3614 switch (req->bmRequestType) {
3615 case UT_READ_DEVICE:
3616 switch (req->bRequest) {
3617 case UR_GET_DESCRIPTOR:
3618 goto tr_handle_get_descriptor;
3620 goto tr_handle_get_config;
3622 goto tr_handle_get_status;
3628 case UT_WRITE_DEVICE:
3629 switch (req->bRequest) {
3630 case UR_SET_ADDRESS:
3631 goto tr_handle_set_address;
3633 goto tr_handle_set_config;
3634 case UR_CLEAR_FEATURE:
3635 goto tr_valid; /* nop */
3636 case UR_SET_DESCRIPTOR:
3637 goto tr_valid; /* nop */
3638 case UR_SET_FEATURE:
3644 case UT_WRITE_ENDPOINT:
3645 switch (req->bRequest) {
3646 case UR_CLEAR_FEATURE:
3647 switch (UGETW(req->wValue)) {
3648 case UF_ENDPOINT_HALT:
3649 goto tr_handle_clear_halt;
3650 case UF_DEVICE_REMOTE_WAKEUP:
3651 goto tr_handle_clear_wakeup;
3656 case UR_SET_FEATURE:
3657 switch (UGETW(req->wValue)) {
3658 case UF_ENDPOINT_HALT:
3659 goto tr_handle_set_halt;
3660 case UF_DEVICE_REMOTE_WAKEUP:
3661 goto tr_handle_set_wakeup;
3666 case UR_SYNCH_FRAME:
3667 goto tr_valid; /* nop */
3673 case UT_READ_ENDPOINT:
3674 switch (req->bRequest) {
3676 goto tr_handle_get_ep_status;
3682 case UT_WRITE_INTERFACE:
3683 switch (req->bRequest) {
3684 case UR_SET_INTERFACE:
3685 goto tr_handle_set_interface;
3686 case UR_CLEAR_FEATURE:
3687 goto tr_valid; /* nop */
3688 case UR_SET_FEATURE:
3694 case UT_READ_INTERFACE:
3695 switch (req->bRequest) {
3696 case UR_GET_INTERFACE:
3697 goto tr_handle_get_interface;
3699 goto tr_handle_get_iface_status;
3705 case UT_WRITE_CLASS_INTERFACE:
3706 case UT_WRITE_VENDOR_INTERFACE:
3710 case UT_READ_CLASS_INTERFACE:
3711 case UT_READ_VENDOR_INTERFACE:
3715 case UT_WRITE_CLASS_DEVICE:
3716 switch (req->bRequest) {
3717 case UR_CLEAR_FEATURE:
3719 case UR_SET_DESCRIPTOR:
3720 case UR_SET_FEATURE:
3727 case UT_WRITE_CLASS_OTHER:
3728 switch (req->bRequest) {
3729 case UR_CLEAR_FEATURE:
3730 goto tr_handle_clear_port_feature;
3731 case UR_SET_FEATURE:
3732 goto tr_handle_set_port_feature;
3733 case UR_CLEAR_TT_BUFFER:
3743 case UT_READ_CLASS_OTHER:
3744 switch (req->bRequest) {
3745 case UR_GET_TT_STATE:
3746 goto tr_handle_get_tt_state;
3748 goto tr_handle_get_port_status;
3754 case UT_READ_CLASS_DEVICE:
3755 switch (req->bRequest) {
3756 case UR_GET_DESCRIPTOR:
3757 goto tr_handle_get_class_descriptor;
3759 goto tr_handle_get_class_status;
3770 tr_handle_get_descriptor:
3771 switch (value >> 8) {
3776 len = sizeof(musbotg_devd);
3777 ptr = (const void *)&musbotg_devd;
3779 case UDESC_DEVICE_QUALIFIER:
3783 len = sizeof(musbotg_odevd);
3784 ptr = (const void *)&musbotg_odevd;
3790 len = sizeof(musbotg_confd);
3791 ptr = (const void *)&musbotg_confd;
3794 switch (value & 0xff) {
3795 case 0: /* Language table */
3796 len = sizeof(musbotg_langtab);
3797 ptr = (const void *)&musbotg_langtab;
3800 case 1: /* Vendor */
3801 len = sizeof(musbotg_vendor);
3802 ptr = (const void *)&musbotg_vendor;
3805 case 2: /* Product */
3806 len = sizeof(musbotg_product);
3807 ptr = (const void *)&musbotg_product;
3818 tr_handle_get_config:
3820 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3823 tr_handle_get_status:
3825 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3828 tr_handle_set_address:
3829 if (value & 0xFF00) {
3832 sc->sc_rt_addr = value;
3835 tr_handle_set_config:
3839 sc->sc_conf = value;
3842 tr_handle_get_interface:
3844 sc->sc_hub_temp.wValue[0] = 0;
3847 tr_handle_get_tt_state:
3848 tr_handle_get_class_status:
3849 tr_handle_get_iface_status:
3850 tr_handle_get_ep_status:
3852 USETW(sc->sc_hub_temp.wValue, 0);
3856 tr_handle_set_interface:
3857 tr_handle_set_wakeup:
3858 tr_handle_clear_wakeup:
3859 tr_handle_clear_halt:
3862 tr_handle_clear_port_feature:
3866 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3869 case UHF_PORT_SUSPEND:
3870 if (sc->sc_mode == MUSB2_HOST_MODE)
3871 musbotg_wakeup_host(sc);
3873 musbotg_wakeup_peer(sc);
3876 case UHF_PORT_ENABLE:
3877 sc->sc_flags.port_enabled = 0;
3880 case UHF_C_PORT_ENABLE:
3881 sc->sc_flags.change_enabled = 0;
3884 case UHF_C_PORT_OVER_CURRENT:
3885 sc->sc_flags.change_over_current = 0;
3888 case UHF_C_PORT_RESET:
3889 sc->sc_flags.change_reset = 0;
3893 case UHF_PORT_INDICATOR:
3897 case UHF_PORT_POWER:
3898 sc->sc_flags.port_powered = 0;
3899 musbotg_pull_down(sc);
3900 musbotg_clocks_off(sc);
3902 case UHF_C_PORT_CONNECTION:
3903 sc->sc_flags.change_connect = 0;
3905 case UHF_C_PORT_SUSPEND:
3906 sc->sc_flags.change_suspend = 0;
3909 err = USB_ERR_IOERROR;
3914 tr_handle_set_port_feature:
3918 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3921 case UHF_PORT_ENABLE:
3922 sc->sc_flags.port_enabled = 1;
3924 case UHF_PORT_SUSPEND:
3925 if (sc->sc_mode == MUSB2_HOST_MODE)
3926 musbotg_suspend_host(sc);
3929 case UHF_PORT_RESET:
3930 if (sc->sc_mode == MUSB2_HOST_MODE) {
3931 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3932 reg |= MUSB2_MASK_RESET;
3933 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3935 /* Wait for 20 msec */
3936 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3938 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3939 reg &= ~MUSB2_MASK_RESET;
3940 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3942 /* determine line speed */
3943 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3944 if (reg & MUSB2_MASK_HSMODE)
3945 sc->sc_flags.status_high_speed = 1;
3947 sc->sc_flags.status_high_speed = 0;
3949 sc->sc_flags.change_reset = 1;
3951 err = USB_ERR_IOERROR;
3955 case UHF_PORT_INDICATOR:
3958 case UHF_PORT_POWER:
3959 sc->sc_flags.port_powered = 1;
3962 err = USB_ERR_IOERROR;
3967 tr_handle_get_port_status:
3969 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3974 if (sc->sc_flags.status_vbus) {
3975 musbotg_clocks_on(sc);
3976 musbotg_pull_up(sc);
3978 musbotg_pull_down(sc);
3979 musbotg_clocks_off(sc);
3982 /* Select Device Side Mode */
3983 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3984 value = UPS_PORT_MODE_DEVICE;
3988 if (sc->sc_flags.status_high_speed) {
3989 value |= UPS_HIGH_SPEED;
3991 if (sc->sc_flags.port_powered) {
3992 value |= UPS_PORT_POWER;
3994 if (sc->sc_flags.port_enabled) {
3995 value |= UPS_PORT_ENABLED;
3998 if (sc->sc_flags.port_over_current)
3999 value |= UPS_OVERCURRENT_INDICATOR;
4001 if (sc->sc_flags.status_vbus &&
4002 sc->sc_flags.status_bus_reset) {
4003 value |= UPS_CURRENT_CONNECT_STATUS;
4005 if (sc->sc_flags.status_suspend) {
4006 value |= UPS_SUSPEND;
4008 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4012 if (sc->sc_flags.change_connect) {
4013 value |= UPS_C_CONNECT_STATUS;
4015 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4016 if (sc->sc_flags.status_vbus &&
4017 sc->sc_flags.status_bus_reset) {
4018 /* reset EP0 state */
4019 sc->sc_ep0_busy = 0;
4024 if (sc->sc_flags.change_suspend)
4025 value |= UPS_C_SUSPEND;
4026 if (sc->sc_flags.change_reset)
4027 value |= UPS_C_PORT_RESET;
4028 if (sc->sc_flags.change_over_current)
4029 value |= UPS_C_OVERCURRENT_INDICATOR;
4031 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4032 len = sizeof(sc->sc_hub_temp.ps);
4035 tr_handle_get_class_descriptor:
4039 ptr = (const void *)&musbotg_hubd;
4040 len = sizeof(musbotg_hubd);
4044 err = USB_ERR_STALLED;
4053 musbotg_xfer_setup(struct usb_setup_params *parm)
4055 struct musbotg_softc *sc;
4056 struct usb_xfer *xfer;
4062 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4063 xfer = parm->curr_xfer;
4066 * NOTE: This driver does not use any of the parameters that
4067 * are computed from the following values. Just set some
4068 * reasonable dummies:
4070 parm->hc_max_packet_size = 0x400;
4071 parm->hc_max_frame_size = 0xc00;
4073 if ((parm->methods == &musbotg_device_isoc_methods) ||
4074 (parm->methods == &musbotg_device_intr_methods))
4075 parm->hc_max_packet_count = 3;
4077 parm->hc_max_packet_count = 1;
4079 usbd_transfer_setup_sub(parm);
4082 * compute maximum number of TDs
4084 if (parm->methods == &musbotg_device_ctrl_methods) {
4086 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4088 } else if (parm->methods == &musbotg_device_bulk_methods) {
4090 ntd = xfer->nframes + 1 /* SYNC */ ;
4092 } else if (parm->methods == &musbotg_device_intr_methods) {
4094 ntd = xfer->nframes + 1 /* SYNC */ ;
4096 } else if (parm->methods == &musbotg_device_isoc_methods) {
4098 ntd = xfer->nframes + 1 /* SYNC */ ;
4106 * check if "usbd_transfer_setup_sub" set an error
4112 * allocate transfer descriptors
4116 ep_no = xfer->endpointno & UE_ADDR;
4119 * Check for a valid endpoint profile in USB device mode:
4121 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4122 const struct usb_hw_ep_profile *pf;
4124 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4127 /* should not happen */
4128 parm->err = USB_ERR_INVAL;
4134 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4136 for (n = 0; n != ntd; n++) {
4138 struct musbotg_td *td;
4142 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4145 td->max_frame_size = xfer->max_frame_size;
4146 td->reg_max_packet = xfer->max_packet_size |
4147 ((xfer->max_packet_count - 1) << 11);
4149 td->obj_next = last_obj;
4153 parm->size[0] += sizeof(*td);
4156 xfer->td_start[0] = last_obj;
4160 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4166 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4168 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4170 if (sc->sc_mode == MUSB2_HOST_MODE)
4171 *pus = 2000; /* microseconds */
4177 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4178 struct usb_endpoint *ep)
4180 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4182 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4184 edesc->bEndpointAddress, udev->flags.usb_mode,
4187 if (udev->device_index != sc->sc_rt_addr) {
4188 switch (edesc->bmAttributes & UE_XFERTYPE) {
4190 ep->methods = &musbotg_device_ctrl_methods;
4193 ep->methods = &musbotg_device_intr_methods;
4195 case UE_ISOCHRONOUS:
4196 ep->methods = &musbotg_device_isoc_methods;
4199 ep->methods = &musbotg_device_bulk_methods;
4209 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4211 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4214 case USB_HW_POWER_SUSPEND:
4215 musbotg_suspend(sc);
4217 case USB_HW_POWER_SHUTDOWN:
4220 case USB_HW_POWER_RESUME:
4228 struct usb_bus_methods musbotg_bus_methods =
4230 .endpoint_init = &musbotg_ep_init,
4231 .get_dma_delay = &musbotg_get_dma_delay,
4232 .xfer_setup = &musbotg_xfer_setup,
4233 .xfer_unsetup = &musbotg_xfer_unsetup,
4234 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4235 .set_stall = &musbotg_set_stall,
4236 .clear_stall = &musbotg_clear_stall,
4237 .roothub_exec = &musbotg_roothub_exec,
4238 .xfer_poll = &musbotg_do_poll,
4239 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,